CN109711057A - A kind of method and its system for proofing chip environment completeness - Google Patents
A kind of method and its system for proofing chip environment completeness Download PDFInfo
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- CN109711057A CN109711057A CN201811622261.1A CN201811622261A CN109711057A CN 109711057 A CN109711057 A CN 109711057A CN 201811622261 A CN201811622261 A CN 201811622261A CN 109711057 A CN109711057 A CN 109711057A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000012795 verification Methods 0.000 claims abstract description 41
- 238000003780 insertion Methods 0.000 claims abstract description 12
- 230000037431 insertion Effects 0.000 claims abstract description 12
- 230000008569 process Effects 0.000 claims description 8
- 238000005070 sampling Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000005284 excitation Effects 0.000 description 3
- 238000012550 audit Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
Abstract
The present invention relates to a kind of methods and its system for proofing chip environment completeness；Wherein, the method for proofing chip environment completeness, comprising the following steps: S1 creates covering group, includes at least one covering point in covering group；S2, will be in the execution code of covering point insertion verification environment concern；S3 is sampled and is collected to covering point coverage information；S4 shows covering point coverage information with corresponding eda tool；S5, judges whether covering point is covered to entirely；If so, into S7；If it is not, then entering S6；S6, carries out verification environment perfect, and returns to S3；S7, the complete signal of output environment.The artificial guarantee of previous verification environment completeness is become tool and presented automatically by the present invention, it appears more intuitive, also more convincingness, and accuracy rate is higher, it being capable of preferably meet demand.
Description
Technical field
The present invention relates to chip checking technical fields, more specifically refer to a kind of for proofing chip environment completeness
Method and its system.
Background technique
It can check whether design code is capped by code coverage during chip checking, be checked with function coverage
Whether design code function is capped；But often the same function can be there are many verifying scene to cover, so authenticated
Verifying scene abundant is needed in journey to support；One good verification environment usually contains verifying scene very abundant, these
Verifying scene is all that verifying personnel write and safeguard；But human factor is added, if none is quantitatively characterized, or do not have
There is a tool explicitly to express which verifying scene is performed, it is possible to miss important verifying scene；And or
It joined inspection comparison mechanism very abundant in person's verification environment, if none is quantitatively characterized or none tool
It explicitly expresses, it is possible to miss important checking mechanism；And these checking mechanisms are usually contained and are held to critical function
Whether row correctly checks that, if causing to check failure because verifying personnel's hand is misled, which will not ensure that correctly.
Currently, industry is there are no clear stipulaties verification environment, how this guarantees that completeness, unified way are all by verifying
Personnel oneself maintenance, is checked by other staff；But this method is fuzzy due to safeguarding, not enough rigorously, not can guarantee function
Point is sufficiently verified.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, a kind of side for proofing chip environment completeness is provided
Method and its system.
To achieve the above object, the present invention is used in lower technical solution:
A method of for proofing chip environment completeness, comprising the following steps:
S1 creates covering group, includes at least one covering point in covering group；
S2, will be in the execution code of covering point insertion verification environment concern；
S3 is sampled and is collected to covering point coverage information；
S4 shows covering point coverage information with corresponding eda tool；
S5, judges whether covering point is covered to entirely；If so, into S7；If it is not, then entering S6；
S6, carries out verification environment perfect, and returns to S3；
S7, the complete signal of output environment.
Its further technical solution are as follows: in the S1, the quantity of covering group is at least one.
Its further technical solution are as follows: the S1 includes:
S11 creates at least one covering group in the environment；
S12 includes at least one covering point in each covering group.
Its further technical solution are as follows: in the S3, in environment operational process, covering point coverage information is sampled
And collection.
Its further technical solution are as follows: in the S4, after environment executes, with corresponding eda tool to covering point
Coverage information is shown.
Its further technical solution are as follows: in the S6, check verification environment, verification environment is carried out perfect.
A kind of system for proofing chip environment completeness, including creating unit, insertion unit, sample collection unit,
Display unit, judging unit improve unit and output unit；
The creating unit includes at least one covering point in covering group for creating covering group；
The insertion unit, for that will cover in a little execution code of insertion verification environment concern；
The sample collection unit, for covering point coverage information to be sampled and collected；
The display unit, for being shown with corresponding eda tool to covering point coverage information；
The judging unit, for judging whether covering point is covered to entirely；
It is described to improve unit, it is perfect for being carried out to verification environment；
The output unit is used for the complete signal of output environment.
Its further technical solution are as follows: the quantity of covering group is at least one in the creating unit.
Its further technical solution are as follows: in the sample collection unit, covering point coverage information is sampled and collected
It is in environment operational process.
Its further technical solution are as follows: in the display unit, after environment executes, with corresponding eda tool
Covering point coverage information is shown；It is described to improve in unit, it checks verification environment, verification environment is carried out perfect.
Compared with the prior art, the invention has the advantages that: the artificial guarantee of previous verification environment completeness is become
Tool is presented automatically, it appears more intuitive, also more convincingness, and accuracy rate is higher, it being capable of preferably meet demand.
The invention will be further described in the following with reference to the drawings and specific embodiments.
Detailed description of the invention
Fig. 1 is a kind of method flow diagram for proofing chip environment completeness of the present invention；
Fig. 2 is a kind of system block diagram for proofing chip environment completeness of the present invention.
10 creating units 20 are inserted into unit
30 sample collection unit, 40 display unit
50 judging units 60 improve unit
70 output units
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention into
One step introduction and explanation, but not limited to this.
Such as Fig. 1 to specific embodiment shown in Fig. 2, wherein it is complete for proofing chip environment that the invention discloses one kind
The method of property, comprising the following steps:
S1 creates covering group, includes at least one covering point in covering group；
S2, will be in the execution code of covering point insertion verification environment concern；
S3 is sampled and is collected to covering point coverage information；
S4 shows covering point coverage information with corresponding eda tool；
S5, judges whether covering point is covered to entirely；If so, into S7；If it is not, then entering S6；
S6, carries out verification environment perfect, and returns to S3；
S7, the complete signal of output environment.
Wherein, in the S1, the quantity of covering group is at least one.
Further, the S1 includes:
S11 creates at least one covering group in the environment；
S12 includes at least one covering point in each covering group.
Wherein, in the S3, in environment operational process, covering point coverage information is sampled and is collected.
Wherein, in the S4, after environment executes, covering point coverage information is shown with corresponding eda tool
Show.
Wherein, it in the S6, checks verification environment, verification environment is carried out perfect.
The present invention is to be blended in verification environment using function coverage method and technology feature；Functional coverage point is added to not
With verifying scene in, by sampling and collecting, finally explicitly given expression to by eda tool these functional coverage points whether have by
It all covers, can be clearly seen which functional coverage point covers, which is not covered with；If since environment misses
Certain conditions are limited, or accidentally fall certain audit functions note, then the functional coverage point in this partial code will not yet
It can go to, these functional coverage points can be clearly seen as long as through eda tool and be not covered with, so as to check ring
The problem of completeness in border.
And the prior art needs verification environment construction multiple combinations scene could be to chip by taking certain chip checking as an example
Function point is sufficiently verified, and is verified personnel and is also considered these combined situations really when writing arbitrary excitation, still
Due to accidentally limiting certain conditions in debugging process, and forget to remove restrictive condition afterwards, to cause verification environment
A little combine scenes do not arrive at random in the environment, and since these belong to combination function point, so from the code coverage of design
Rate can not also check, this, which results in this kind of scenes function, cannot be guaranteed；For another example, there are many arbitration functions in verification environment
The inspection code of correctness, if accidentally fallen these codes note, or because modification environment causes these to check that code is basic
It is unreachable, then these audit functions also will be ineffective, so that the function point just not can guarantee correctness yet.From above two
It, just can only be by constantly artificial multiple if a example can be seen that without a kind of mechanism the completeness for checking verification environment
The method for looking into environment is easy to omit, and not rigorous enough, not can guarantee function point and is sufficiently verified.
There is not unified completeness standard also for current verification environment, verification environment is essentially all that manually check carries out
Guarantee and devise the present invention, the invention avoids manual review bring efficiency, preciseness problems, and do not have very high
Convincingness.The place insertion covering point that the invention neatly can need to pay close attention in the environment, and finally can be by eda tool
Easily, clearly, explicit to express, and have very much preciseness, so as to currently be tested according to display result judgement
Demonstrate,prove the completeness of environment.
As shown in Fig. 2, the invention also discloses a kind of system for proofing chip environment completeness, including creating unit
10, it is inserted into unit 20, sample collection unit 30, display unit 40, judging unit 50 improves unit 60 and output unit 70；
The creating unit 10 includes at least one covering point in covering group for creating covering group；
The insertion unit 20, for that will cover in a little execution code of insertion verification environment concern；
The sample collection unit 30, for covering point coverage information to be sampled and collected；
The display unit 40, for being shown with corresponding eda tool to covering point coverage information；
The judging unit 50, for judging whether covering point is covered to entirely；
It is described to improve unit 60, it is perfect for being carried out to verification environment；
The output unit 70 is used for the complete signal of output environment.
Wherein, the quantity of covering group is at least one in the creating unit 10.
Wherein, in the sample collection unit 30, sampling is carried out to covering point coverage information and collection is run in environment
In the process.
Wherein, in the display unit 40, after environment executes, with corresponding eda tool to covering point covering
Information is shown；It is described to improve in unit 60, it checks verification environment, verification environment is carried out perfect.
The present invention is used for verification environment for the technology of function coverage method is ingenious, by being inserted into each excitation scene
Functional coverage point, and these covering points are sampled in the process of implementation, it then collects, finally by eda tool by these function
The coverage rate that point can be covered explicitly is expressed.By this method, can clearly know which covering point either with or without reaching,
To clearly know corresponding excitation scene either with or without covering, finally it is able to guarantee verification environment completeness.Use this side
The artificial guarantee of previous verification environment completeness is become tool and presented automatically by method, it appears more intuitive, also more convincingness；
And the technology of the present invention can be used for any chip checking for supporting function coverage method.
It is above-mentioned that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand, but not
It represents embodiments of the present invention and is only limitted to this, any technology done according to the present invention extends or recreation, by of the invention
Protection.Protection scope of the present invention is subject to claims.
Claims (10)
1. a kind of method for proofing chip environment completeness, which comprises the following steps:
S1 creates covering group, includes at least one covering point in covering group；
S2, will be in the execution code of covering point insertion verification environment concern；
S3 is sampled and is collected to covering point coverage information；
S4 shows covering point coverage information with corresponding eda tool；
S5, judges whether covering point is covered to entirely；If so, into S7；If it is not, then entering S6；
S6, carries out verification environment perfect, and returns to S3；
S7, the complete signal of output environment.
2. a kind of method for proofing chip environment completeness according to claim 1, which is characterized in that the S1
In, the quantity of covering group is at least one.
3. a kind of method for proofing chip environment completeness according to claim 2, which is characterized in that the S1 packet
It includes:
S11 creates at least one covering group in the environment；
S12 includes at least one covering point in each covering group.
4. a kind of method for proofing chip environment completeness according to claim 1, which is characterized in that the S3
In, in environment operational process, covering point coverage information is sampled and collected.
5. a kind of method for proofing chip environment completeness according to claim 1, which is characterized in that the S4
In, after environment executes, covering point coverage information is shown with corresponding eda tool.
6. a kind of method for proofing chip environment completeness according to claim 1, which is characterized in that the S6
In, it checks verification environment, verification environment is carried out perfect.
7. a kind of system for proofing chip environment completeness, which is characterized in that including creating unit, be inserted into unit, sampling
Collector unit, display unit, judging unit improve unit and output unit；
The creating unit includes at least one covering point in covering group for creating covering group；
The insertion unit, for that will cover in a little execution code of insertion verification environment concern；
The sample collection unit, for covering point coverage information to be sampled and collected；
The display unit, for being shown with corresponding eda tool to covering point coverage information；
The judging unit, for judging whether covering point is covered to entirely；
It is described to improve unit, it is perfect for being carried out to verification environment；
The output unit is used for the complete signal of output environment.
8. a kind of system for proofing chip environment completeness according to claim 7, which is characterized in that the creation
The quantity of covering group is at least one in unit.
9. a kind of system for proofing chip environment completeness according to claim 7, which is characterized in that the sampling
In collector unit, sampling is carried out to covering point coverage information and collection is in environment operational process.
10. a kind of system for proofing chip environment completeness according to claim 7, which is characterized in that described aobvious
Show in unit, after environment executes, covering point coverage information is shown with corresponding eda tool；It is described perfect
In unit, checks verification environment, verification environment is carried out perfect.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811622261.1A CN109711057A (en) | 2018-12-28 | 2018-12-28 | A kind of method and its system for proofing chip environment completeness |
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| CN201811622261.1A CN109711057A (en) | 2018-12-28 | 2018-12-28 | A kind of method and its system for proofing chip environment completeness |
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| CN109711057A true CN109711057A (en) | 2019-05-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112596966A (en) * | 2020-12-17 | 2021-04-02 | 海光信息技术股份有限公司 | Chip verification method, device, equipment and storage medium |
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| CN104636521A (en) * | 2013-11-14 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Smart card chip security authentication method based on VMM and authentication environment platform |
| CN105302573A (en) * | 2015-11-20 | 2016-02-03 | 浪潮集团有限公司 | Method for establishing function point matching setting automation platform for function verification platform |
| JP2016081397A (en) * | 2014-10-20 | 2016-05-16 | 株式会社ソシオネクスト | Design verification support device and design verification support method |
| CN108108558A (en) * | 2017-12-21 | 2018-06-01 | 郑州云海信息技术有限公司 | A kind of method and system based on degree of covering statistical appraisal accidental validation quality |
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2018
- 2018-12-28 CN CN201811622261.1A patent/CN109711057A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104636521A (en) * | 2013-11-14 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Smart card chip security authentication method based on VMM and authentication environment platform |
| JP2016081397A (en) * | 2014-10-20 | 2016-05-16 | 株式会社ソシオネクスト | Design verification support device and design verification support method |
| CN105302573A (en) * | 2015-11-20 | 2016-02-03 | 浪潮集团有限公司 | Method for establishing function point matching setting automation platform for function verification platform |
| CN108108558A (en) * | 2017-12-21 | 2018-06-01 | 郑州云海信息技术有限公司 | A kind of method and system based on degree of covering statistical appraisal accidental validation quality |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112596966A (en) * | 2020-12-17 | 2021-04-02 | 海光信息技术股份有限公司 | Chip verification method, device, equipment and storage medium |
| CN112596966B (en) * | 2020-12-17 | 2022-11-01 | 海光信息技术股份有限公司 | Chip verification method, device, equipment and storage medium |
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Application publication date: 20190503 |