JP2016080929A - Active matrix display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix display device capable of reducing contrast failure or display unevenness at a point starting a display period while reducing the cost and undesired electric power consumption.SOLUTION: A timing control unit 53 in a timing controller 58 is configured so that an image display control signal 3 which is output to a source driver 56 is output first for a predetermined period of time from end point of a vertical blanking period Td. With this preceding output, voltage fluctuation of the analog power source Vs is caused to be generated during a vertical blanking period Td.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a configuration of an active matrix display device for image display, and can be suitably used for a liquid crystal display device employing a liquid crystal panel as a display panel.

A known liquid crystal display device, which is a kind of active matrix display device, receives an input signal and an input voltage and drives a liquid crystal display panel to realize image display.
The input signal includes a clock, image data, a synchronization signal, and the like. The timing controller receives the input signal, and a drive control signal, a clock, and display data are generated at a desired timing.
In the power supply circuit portion, a logic voltage, an analog voltage (output driving voltage), a gradation voltage, a gate ON voltage, a gate OFF voltage, a common voltage, and the like are generated from the input voltage.
A gate driver IC and a source driver IC are driven at a desired timing by an output signal (drive control signal, clock, display data) from the timing controller unit and each power supply voltage, and a pixel driving TFT (Thin Film Transistor: Thin Film) in the display panel is driven. A voltage corresponding to the display image is applied to the liquid crystal.

  The driving period of the liquid crystal display panel is divided into a data enable period (vertical display period) in which voltage is applied to the pixels and another vertical blanking period (vertical blanking period). From the vertical blanking period to the data enable period At the time of switching to, the light load state where the current consumption is small changes to the normal state where the current consumption is large, and the load greatly changes for the power supply circuit. As a result, a certain transition time is required until the voltage returns to a desired voltage due to the problem of the response of the power supply circuit, and a contrast failure and display unevenness due to a decrease in the write voltage may occur for several lines at the start of display writing. .

  As described above, the power supply voltage necessary for driving the liquid crystal display panel includes a logic voltage, an analog voltage, a gradation voltage, a gate ON voltage, a gate OFF voltage, a common voltage, and the like, and the logic voltage is for operation of ICs. The input voltage is used as it is or regulated by the power supply circuit. The analog voltage is a power source for charging the liquid crystal pixels, and has the highest power consumption among the necessary power sources.

  Generally, an analog voltage is generated by using a boost chopper circuit called a boost circuit (FIG. 8 of Patent Document 1). The gradation voltage is a reference potential of the voltage applied to the liquid crystal pixels, and determines the gradation characteristics of the display panel in combination with the source driver IC. Usually, it is often generated by resistance division of an analog voltage, but recently, a dedicated IC has been increasingly used.

  The gate ON voltage and the gate OFF voltage are voltages for turning on / off the pixel TFT in the liquid crystal display panel, and the power consumption is low, and since the gate ON voltage is a positive voltage, a booster circuit called a positive charge pump circuit, and a gate OFF voltage Since is a negative voltage, it is often composed of a step-down circuit called a negative charge pump circuit.

  The common voltage is a voltage for driving the counter electrode of the liquid crystal display panel, and is a liquid crystal reference potential in which the voltage applied to the liquid crystal pixel is determined by the potential difference between the gradation voltage and the output voltage (image signal) of the source driver IC determined from the data. . There are various common voltages, such as an amplifier circuit called a push-pull circuit (see FIG. 1 of Patent Document 2) or a simple amplifier circuit.

  The problem taken up here is related to poor display contrast and display unevenness due to the response of the analog voltage boost circuit to load fluctuations. The boost circuit is a circuit that boosts an input voltage by using energy generated in a coil by controlling ON / OFF of an FET (see paragraph 0047 of Patent Document 1). When load fluctuation occurs, the output voltage is kept constant by controlling the ON / OFF duty ratio in order to obtain a desired voltage. However, in the vertical blanking period, there is no writing to the liquid crystal pixels, and the current consumption is small while the output voltage is maintained, and the state that is called the discontinuous mode in which the current flowing through the coil disappears, and in some cases the switching operation is stopped. It becomes a state to do.

  When the state transitions from this state to the data enable period and writing into the liquid crystal pixel starts, current consumption increases rapidly and a voltage drop occurs. Therefore, the FET ON / OFF control is started again to restore the desired voltage, but it takes time to restore the desired voltage from a state where the current consumption is small. The voltage drop that occurs here affects the voltage applied to the liquid crystal pixels through fluctuations in the output of the source driver IC (hereinafter referred to as source output).

  Conventionally, the power supply circuit design has been dealt with by tuning peripheral component constants and the like, which increases the cost such as adding a capacitor or increasing the capacity (output capacitor C1 shown in FIG. 8 of Patent Document 1) to suppress fluctuations in the power supply. Countermeasures were necessary.

  The output voltage of the source driver IC is determined by the analog voltage and the gradation voltage Vref. For example, a gradation voltage generator as shown in FIG. 8 is used so that the influence of the voltage drop of the analog voltage does not affect the output voltage of the source driver IC. In some cases (gradation voltage generation means), a low-pass filter composed of a resistor and a capacitor is introduced to suppress voltage drop of the gradation voltage. In the case of the gradation voltage generation unit shown in FIG. 8, the output voltage of the low-pass filter is the maximum gradation voltage (Vref−Max) input to the source driver IC. The low-pass filter has a resistance Rf and a resistance Rf so that even if a voltage drop of the maximum gradation voltage (Vref−Max) occurs in the data enable period, the voltage drops below a predetermined voltage drop where display unevenness is not visually recognized at the upper part of the actual display screen. A capacitor Cf is set.

Further, as shown in FIG. 10, the analog voltage value Vsd, which is a power source for operating the internal driver circuit of the source driver IC, needs to maintain the minimum voltage value that does not hinder the output operation even if a voltage drop occurs. .
In other words, the minimum voltage value is a voltage value obtained by adding a potential difference between the analog voltage value required for the source driver IC and the maximum gradation voltage (Vref−Max) to the maximum gradation voltage (Vref−Max). It becomes. For this reason, it is necessary to set a sufficiently high value in consideration of the voltage drop as the set value of the analog voltage value.

JP 2010-66632 A (paragraph 0647, FIG. 8) JP-A-11-194320 (FIG. 1)

  In this way, the potential difference caused by the response to load fluctuations of the boost circuit of the power supply that generates the analog voltage must not exceed the minimum voltage value when the analog voltage is dropped, and the analog voltage setting value and maximum gradation It is necessary to ensure a sufficient voltage difference, which causes an increase in power consumption and increases the output capacitor, which increases costs.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an active matrix display device that can suppress a contrast failure at the start of data enable and can increase unnecessary power consumption and cost. And

  An active matrix display device according to the present invention includes a plurality of pixels arranged in a matrix, a plurality of image signal lines arranged in each column of the pixels, and a plurality of scanning signal lines arranged in each row of the pixels. A display panel, scanning signal line driving means for driving the scanning signal lines, image signal line driving means for supplying image signals for driving pixels to the image signal lines, and scanning with the image signal line driving means. Timing control means for driving and controlling the signal line driving means, and power supply means configured by a booster circuit for supplying an output driving voltage to the image signal line driving means and the gradation voltage generating means. The timing control means outputs an image display control signal output from the timing control means to the image signal line driving means over a predetermined period from the end of the vertical blanking period. Being configured to output the line voltage variation of the output driving voltage by said preceding output is equal to or occurring during the vertical blanking period.

  According to the present invention, it is possible to suppress contrast failure and display unevenness at the start of a display period due to responsiveness to load fluctuations of a boost circuit of a power supply that generates an analog voltage. In addition, unnecessary power consumption increase and cost reduction are possible.

It is a circuit block diagram of the liquid crystal display device which concerns on Embodiment 1 thru | or 4 of this invention. FIG. 2 is a timing diagram of an output voltage variation of an analog voltage and a DENA signal of a power supply circuit unit in FIG. 1. FIG. 3 is a timing diagram showing a relationship between a DENA signal and a latch pulse signal of a source driver IC, partially expanding before and after the start of a data enable period in FIG. 2. It is a block diagram which shows the structure of the timing control part which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the timing control part which concerns on Embodiment 2 of this invention. FIG. 10 is a timing diagram illustrating a relationship between a DENA signal, a source driver IC output waveform, and a consumption current of an analog voltage, partially enlarged before and after the start of a data enable period according to a third embodiment of the present invention. FIG. 10 is a timing diagram illustrating a relationship between a DENA signal, a source driver IC output inverted signal, and a consumption current of an analog voltage, partially enlarged before and after the start of a data enable period according to a fourth embodiment of the present invention. It is a circuit diagram which shows the low-pass filter of the gradation voltage generation part in a liquid crystal display device. It is a schematic diagram which shows the electric potential relationship of an analog voltage and a gradation voltage in the liquid crystal display device which concerns on Embodiment 1 thru | or 4 of this invention. It is a schematic diagram which shows the electric potential relationship of the analog voltage and gradation voltage in the conventional liquid crystal display device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In order to avoid redundant descriptions, the same reference numerals are given to elements having the same or corresponding functions in each drawing.

Embodiment 1 FIG.
<< Circuit configuration >>
FIG. 1 shows a circuit configuration of the liquid crystal display device 50 according to the first embodiment. A plurality of scanning signal lines 51, a plurality of image signal lines 52, and pixels 54 and TFTs 59 for driving the pixels 54 at the intersections thereof are matrixed. 1 shows a configuration of a liquid crystal panel 55 configured to sandwich a liquid crystal layer between a matrix TFT substrate formed in a shape and a counter substrate (not shown), and a peripheral circuit for driving the liquid crystal panel 55.
As an example, in the case of a color liquid crystal panel having an XGA (Extended Graphics Array) resolution composed of pixels of 768 rows × 1024 columns, 768 scanning signal lines 51 and 3072 image signal lines 52 (= 1024 columns × 3) (RGB dots)).
In FIG. 1, the scanning signal line 51 is the first wiring, the image signal line 52 is the leftmost wiring, the pixel 54 connected to them, the TFT 59 for driving it, and the common wiring 61. Other wirings, pixels, TFTs, and common wirings are omitted.

  As shown in FIG. 1, a source driver IC (corresponding to image signal line driving means; hereinafter referred to as S-IC) 56 that outputs image signals for driving a plurality of image signal lines 52 of the liquid crystal panel 55, A gate dry IC (corresponding to scanning signal line driving means, hereinafter referred to as G-IC) 57 for driving a plurality of scanning signal lines 51 is arranged, and a timing controller unit for controlling each of these drivers. (Timing control means; hereinafter referred to as T-CON) 58 is also arranged. Further, an input signal 2 given from the outside is inputted to the T-CON 58. The input signal 2 includes image data (hereinafter referred to as V-Data), a DENA signal indicating a period during which the V-Data is valid, and a clock serving as a reference for performing these processes (hereinafter referred to as CLK). Etc.

  Further, the power supply circuit unit 60 receives the external voltage 1 from the outside, and the S-IC voltage 5 (logic voltage, analog voltage, gradation voltage) and G-IC voltage 7 (logic voltage, gate ON voltage, gate). OFF voltage) and a common voltage 6 for the liquid crystal panel 55 are generated and supplied to each device.

  The T-CON 58 includes display data corresponding to the source driver control signal 3 (drive control signal) and the display luminance of the pixel as an image display control signal for driving and controlling the S-IC 56 in the timing control unit 53 incorporated therein. (Not shown) is generated. At the same time, the T-CON 58 also generates a gate driver control signal 4 for driving and controlling the G-IC 57 in the timing control unit 53.

  Note that the S-IC 56 applies a pixel writing voltage (image signal) to the corresponding plurality of image signal lines 52 in order to display video on the plurality of pixels 54. Therefore, the S-IC 56 integrates a plurality of drive circuits (not shown) connected to the image signal lines 52, respectively.

  Similarly, since the G-IC 57 drives a plurality of scanning signal lines 51, a plurality of circuits (not shown) for driving the scanning signal lines 51 are integrated. (In FIG. 1, the scanning signal line 51 is the first wiring, the image signal line 52 is the leftmost wiring, the pixel 54 connected to them, the TFT 59 for driving it, and the common wiring 61. Other wiring, pixels, TFTs, and common wiring are omitted.)

  The power supply circuit 60 generates a logic voltage Vdd, an analog voltage Vsd (output driving voltage), a gradation voltage Vref, a gate ON voltage Vgh, a gate OFF voltage Vgl, a common voltage 6 (Vcom voltage), and the like from the input voltage Vin. Here, the S-IC 56 is supplied with the power supply 5 for the source driver including the logic voltage Vdd, the analog voltage Vsd, and the gradation voltage Vref from the power supply circuit unit 60. The G-IC 57 is supplied with a gate driver power source 7 including a logic voltage Vdd, a gate ON voltage Vgh, and a gate OFF voltage Vgl from the power supply circuit unit 60. Further, the common voltage 6 (Vcom voltage) is supplied from the power supply circuit unit 60 to the counter electrode terminal (Vcom terminal) of the liquid crystal panel 55.

<< Operation timing >>
FIG. 2 is a schematic diagram showing the fluctuation of the analog voltage Vsd and the operation timing of the DENA signal during the operation of the power supply circuit unit 60 according to the first embodiment. 3, after the end of the vertical blanking period Tb of the DENA signal in FIG. 2, the start portion of the data enable period Td is expanded and the latch pulse signal LP input to the S-IC 56 and the consumption current Is of the analog voltage are added. It is a schematic diagram which shows an operation timing. The consumption current Is of the analog voltage is generated mainly by the S-IC 56 and is a current when the pixel voltage is written to the liquid crystal panel 55 by reversing the polarity every 1H. Here, the symbol “H” indicates a horizontal scanning period. Hereinafter, the horizontal scanning period is represented as “H”.

  In the first embodiment, within the vertical blanking period, as apparent from the waveform of the consumption current Is of the analog voltage shown in FIG. 3, a predetermined period from the end of the vertical blanking period (= data enable period start). In advance, the image signal line 52 equivalent to the data enable period is driven. Then, the analog voltage generation power supply circuit (hereinafter referred to as an analog power supply circuit) is set to an operation state equivalent to the subsequent data enable period. As a result, as is apparent from FIG. 2, the voltage fluctuation of the analog voltage Vsd occurs during the vertical blanking period Tb by the driving of the image signal line 52 by the preceding S-IC 56, and the data enable period Td starts. After that time, the voltage fluctuations converge and a stable analog voltage Vsd is obtained.

Thus, by setting the analog power supply circuit in the normal operation similar to the data enable period Td in advance, there is no large load fluctuation when the data enable period Td starts, and the gradation voltage Vref generated based on the analog voltage is also Since a desired potential can be maintained, display contrast failure and display unevenness can be prevented.
During the vertical blanking period, the G-IC 57 does not drive the scanning signal lines 51, and all the scanning signal lines 51 are held at the gate OFF voltage Vgl. Accordingly, all the TFTs 59 are turned off, no voltage is applied to the pixels 54, and display is not affected.

<< Operation of timing controller >>
4A is a block diagram showing the configuration of the source driver advance operation adding circuit unit 62 (shown by a broken line) in the timing control unit 53 shown by a one-dot chain line inside the T-CON 58 shown in FIG. is there. As shown in FIG. 4A, the source driver preceding operation addition circuit 62 includes an input signal determination circuit 63, a 1 horizontal period count circuit 64, a blanking period count / hold circuit 65, and a pseudo-DENA determination / generation circuit 66. Become.

  As shown in FIG. 3, in order to start driving the image signal line 52 equivalent to the data enable period Td at the end of the vertical blanking period Tb (that is, prior to the start of the data enable period Td), first, Specifically, in the T-CON 58 of the liquid crystal display device 50, it is necessary to discriminate between the data enable period Td and the vertical blanking period Tb of the input signal 2 in the source driver preceding operation addition circuit unit 62. In addition, it is necessary to hold how many minutes the vertical blanking period Tb is.

First, the source driver preceding operation addition circuit unit 62 determines the data enable period Td and the vertical blanking period Tb using the DENA signal (signal indicating the data valid period) of the input signal 2 and CLK.
The input signal discriminating circuit 63 to which DENA and CLK are input as shown in FIG. 4A starts from the rise of 1stDENA (first data valid signal after the end of the vertical blanking period) to LastDENA (last data in the data enable period). The period until the fall of the effective signal) is determined as the data enable period Td, the other period is set as the vertical blanking period Tb, and the blanking period determination signal 8 is set as one horizontal period counting circuit 64, blanking period counting / holding circuit 65, This is output to the pseudo-DENA discrimination / generation circuit 66.
As indicated by reference numeral 8 in FIG. 3, the signal timing has a waveform that is High in the vertical blanking period Tb and Low in the data enable period Td.

An example of a specific determination method for the vertical blanking period Tb will be described. Corresponding to the resolution of the liquid crystal display panel 55 (for example, 768 rows × 1024 columns for XGA), the number of pulses of the DENA signal in one frame is determined by a fixed value (768 for XGA in the example), so 1st DENA to DENA LastDENA can be easily discriminated by counting the rising edges. Also, 1st DENA can be defined as the first DENA after the DENA signal Low period lasts longer than a predetermined value, which can also be easily determined.
Alternatively, as another determination method, when the input signal 2 includes a vertical synchronization signal or a horizontal synchronization signal, the input signal 2 may be determined by using them together.

  Next, the counting of the vertical blanking period Tb in the blanking period counting / holding circuit 65 will be described. First, in the one horizontal period count circuit 64 shown in FIG. 4A, the next rising edge from the rising edge of the DENA signal using the DENA, the CLK, and the blanking period discrimination signal 8 input from the input signal discrimination circuit 63. Counts what CLK is 1H determined by the edge, and outputs one horizontal period count value 9 (number of clocks) to the blanking period count / holding circuit 65 and the pseudo-DENA discrimination / generation circuit 66 (the broken line indicates the output) Represents numeric data). Here, the blanking period discrimination signal 8 is used for initialization of count value and count operation / stop control. As an example, a typical 1H clock number of the input signal 2 for displaying the liquid crystal panel having the XGA resolution is about 1344 CLK.

The blanking period counting / holding circuit 65 counts how many vertical blanking periods Tb are based on one horizontal scanning period (number of clocks) as a reference (1H). As an example, a typical count number of the input signal 2 for displaying the liquid crystal panel having the XGA resolution is 38 (H).
Further, the blanking period count value 10 is held using the rising timing of 1stDENA as a trigger, and the blanking period count value 10 (for example, the count number 38) is output to the pseudo-DENA discrimination / generation circuit 66.

  The pseudo-DENA determination / generation circuit 66 completes the vertical blanking period Tb based on information of one horizontal period count value 9 (for example, 1344), the brab blanking period count value 10, CLK, and the blanking period determination signal 8. A blanking period output signal (pseudo DENA signal) 11 is generated and output so as to start source output several H before.

As a specific example, as shown in FIG. 4B, a first counter that counts a period corresponding to one horizontal period count value 9 using CLK as a count source in the pseudo-DENA determination / generation circuit 66; Using the count output (carry output) CY of the first counter as a count source, a second counter for down-counting from an initial value of 10 (for example, 38) is provided.
Further, if the count value CN of the second counter is equal to or less than the count value (for example, 8) for generating the blanking period output signal (pseudo DENA signal) 11, the pseudo DENA discrimination / generation circuit 66 counts CLK and Based on the output CY, a predetermined pseudo-DENA waveform corresponding to the resolution of the liquid crystal panel 55 (for example, 1024 columns) is repeatedly output. Here, the count output CY serves as a trigger for starting the output of the pseudo-DENA waveform. If the count value CN of the second counter is equal to or less than a predetermined value (8 as an example), the pseudo-DENA waveform is repeatedly output.

The pseudo DENA waveform has a length corresponding to one horizontal period count value 9 × clock cycle, and is composed of a predetermined pseudo horizontal blanking period and a pseudo horizontal data enable period.
The blanking period output signal (pseudo-DENA signal) 11 generated from the pseudo-DENA discriminating / generating circuit 66 configured as described above has a signal waveform of vertical blanking as shown by reference numeral 11 in FIGS. In the ranking period Tb, the output of the blanking period output signal (pseudo DENA signal) 11 is started from the number H before the end of the vertical blanking period Tb (8H before in the example of FIG. 3), and the start of the data enable period Td. End simultaneously (pseudo-DENA period).

  Next, as indicated by the symbol LP in FIG. 3, the timing control unit 53 in the T-CON 58 performs a logical OR between the blanking period output signal (pseudo DENA signal) 11 and the externally input DENA signal. Therefore, the internal DENA signal is generated, and the signal processing for generating the normal source driver control signal 3 based on the internal DENA signal is executed, so that the latch for the S-IC 56 can be obtained even during the vertical blanking period Tb. A pulse signal LP and an image signal line polarity signal POL (not shown) are generated and output to the S-IC 56.

  2 and 3, the drive voltage waveform of the image signal line 52 is not shown in the vertical blanking period Tb. However, since the liquid crystal panel 55 employs the TN mode as an example of the pixel configuration, The voltage for driving the image signal line 52 just before the end of the ranking period Tb (that is, prior to the start of the data enable period Td) is a black voltage having a large voltage amplitude. This black voltage corresponds to the maximum voltage for the liquid crystal display panel 55.

  Further, from what H before the start of the data enable period Td, the source output is determined by the setting in the T-CON 58. For example, when it is desired to start output from 8H before, as indicated by reference numeral 11 in FIG. 3, the blanking period output signal (pseudo DENA signal) 11 is generated when the count value CN of the second counter is 8 or less. Configure.

  Since the vertical blanking period Tb may differ by several H for each frame depending on the timing specification of the input signal 2, it is set in consideration of ensuring the necessary minimum period. The required minimum period is determined by the response characteristics of the analog power supply circuit, and generally a period of about 2H to 20H is required (for example, with respect to the vertical blanking period 38H).

<< Modification 1 >>
In the first embodiment described above, the blanking period count value 10 (holding value: unit H) is set to the same H number as an example of the initial value of the second counter, but the blanking period count value is used as this initial value. 10 (an example 38H) -8H is calculated inside the T-CON 58 and set as the initial value of the second counter, and the down-counting operation is executed during the vertical blanking period Tb of the next frame. The blanking period output signal (pseudo-DENA signal) 11 may be generated from 0 or later.

<< Modification 2 >>
Furthermore, instead of the pseudo-DENA generation circuit in the pseudo-DENA determination / generation circuit 66 shown in FIG. 4B, a pseudo-LP generation circuit is employed to generate a pseudo-LP signal, and the timing in the T-CON 58 is determined. It is also possible to perform a signal process of calculating a logical sum of the LP signal generated in the control unit 53 and the pseudo LP signal, generating a combined LP signal, and outputting the combined LP signal to the source driver IC.

<< Modification 3 >>
2 and 3, the drive voltage waveform of the image signal line 52 of the liquid crystal panel 55 is not shown, but just before the end of the vertical blanking period Tb (that is, prior to the start of the data enable period Td). When voltage application is started, the drive voltage can be switched depending on the liquid crystal mode employed by the liquid crystal panel 55. For example, if the display panel has a normally white pixel configuration such as the above-described TN mode, a black voltage is used. If the display panel has a normally black pixel configuration such as a VA mode or IPS mode, the white voltage is used. By driving the analog power supply circuit at a high load and increasing the output current, voltage drop at the start of the data enable period Td is suppressed. The switching method may be a setting pin of the T-CON 58 IC or a ROM data setting method for storing various setting information read into the T-CON 58.

<< Modification 4 >>
When voltage application to the image signal line 52 is started immediately before the end of the vertical blanking period Tb (that is, prior to the start of the data enable period Td), the applied voltage is set to a halftone voltage. In this way, the analog power supply circuit is driven with an intermediate load to increase the output current, and at least the boost circuit is shifted to the continuous mode, thereby suppressing a voltage drop at the start of the data enable period Td.

Embodiment 2. FIG.
When voltage application to the image signal line 52 is started just before the end of the vertical blanking period Tb (that is, prior to the start of the data enable period Td), the applied voltage is used as the first line display data 12 of the previous frame. .
FIG. 5 is a block diagram showing a configuration of a source driver preceding operation addition circuit unit 62 (shown by a broken line) in the timing control unit 53 shown by a one-dot chain line inside the T-CON 58 shown in FIG. As is clear from the figure, the second embodiment is different from the first embodiment in that V− is displayed on each pixel in the first row of the liquid crystal panel 55 in the source driver preceding operation adding circuit section 62. A line memory 67 for holding Data is added. In addition, the input signal discriminating circuit 63, the one horizontal period counting circuit 64, the blanking period counting / holding circuit 65, the pseudo-DENA discrimination / generation circuit 66, and the like are the same as those in the above-described first embodiment. Omitted.

  The line memory 67 receives CLK, DENA, and V-Data, takes in one row of image data, that is, V-Data of the first row in the 1st DENA period, and holds it for 1 frame period until the 1st DENA of the next frame is input. ing. The line memory 67 outputs the held blanking period output display data 12 to the timing control unit 53 shown in FIG. 1 at least during the vertical blanking period Tb (indicated by reference numeral 12 in FIG. 5). ) Further, during the vertical blanking period Tb, at least during the generation of the internal DENA signal, the timing control unit 53 converts the gradation data corresponding to the blanking period display data 12 in the first row held together with the source driver control signal 3 to S -Output to IC56.

When a still image is displayed on the liquid crystal panel 55, the change in V-Data in the first line between frames is small even when a moving image is displayed. Therefore, there is little difference between the current consumption during the internal DENA signal generation and the current consumption during the 1st DENA period.
Thus, by driving the power supply circuit that is generating the internal DENA signal with almost the same load as that of the first row, voltage drop at the start of the data enable period Td can be suppressed and pixel writing of the first row can be performed. Sufficient time can be secured.

Embodiment 3 FIG.
FIG. 6 shows the fluctuation waveform before and after the start of the data enable period Td, the operation timing of the DENA signal, and the S-IC output Sout (almost equivalent to the voltage applied to the pixel) during the operation of the power supply circuit unit 60 according to the third embodiment. ) It is a schematic diagram showing a relationship between a waveform and a consumption current Is of an analog voltage (output driving voltage). As shown in FIG. 6, when the voltage application to the image signal line 52 is started at the end of the vertical blanking period Tb (that is, prior to the start of the data enable period Td), the S-IC output Sout is lightly loaded. Gradually increase from (small amplitude) to heavy load (amplitude corresponding to normal display data).

  Here, when the liquid crystal panel 55 is a normally white liquid crystal panel such as a TN mode, the white voltage side is changed to the black voltage side. When the liquid crystal panel 55 is a normally black liquid crystal panel such as a VA mode or an IPS mode, the white voltage is applied from the black voltage side. Switch to the voltage side step by step.

As described above, the S-IC output Sout (image signal line drive output) is increased step by step for every 1H, and the generation of rush current is suppressed by suppressing the abrupt switching of the load. The voltage drop at the start of the data enable period Td, which is the original purpose, is suppressed.
In addition, it is possible to cope with various liquid crystal modes by enabling the T-CON 58 to set the number of steps and the voltage amplitude value to be used.

Embodiment 4 FIG.
FIG. 7 illustrates the fluctuation waveform before and after the start of the data enable period Td, the operation timing of the DENA signal, the S-IC image signal line polarity signal POL, and the analog voltage (during the operation of the power supply circuit unit 60 according to the fourth embodiment. It is a schematic diagram which shows the relationship of the consumption current Is of the voltage for output drive). As shown in FIG. 7, the image signal line polarity signal POL in the data enable period Td alternates between High and Low every 2H. As a result, for example, the applied voltage polarity of the pixel in the first row and the pixel in the second row adjacent thereto is the same polarity, and the applied voltage polarity of the pixel in the third row and the pixel in the fourth row adjacent thereto is also the same polarity. On the other hand, the applied voltage polarity of the pixels in the second row and the pixels in the third row adjacent thereto is so-called two-line inversion driving in which the polarities are opposite.

  As apparent from the waveform of the consumption current Is of the analog voltage shown in FIG. 7, in the case of 2-line inversion driving, the amplitude of the image signal line 52 increases at the timing when the positive / negative polarity of the pixel applied voltage alternates, and the image signal The charge / discharge current of the parasitic capacitance of the line 52 and the internal current of the S-IC 56 are increased, and the consumption current Is is increased.

  Further, in the fourth embodiment, when the drive of the image signal line 52 is started just before the end of the vertical blanking period Tb (that is, before the start of the data enable period Td), the output voltage inversion in the data enable period Td is reversed. 1H shorter than the timing (2H in this embodiment) is set as the inversion timing.

  As described above, during the generation of the internal DENA signal, the positive / negative alternating cycle of the output polarity of the S-IC 56 is made shorter than that of the data enable period Td, and the consumption of the current consumption Is is increased to stabilize the operation of the analog power supply circuit of the power supply circuit section 60. Is quickly achieved, and the voltage drop period of the analog voltage Vsd is shortened. As a result, voltage drop at the start of the data enable period Td is suppressed.

  In the liquid crystal display devices shown in the first to fourth embodiments, the voltage drop of the analog voltage starts from the vertical blanking period Tb as shown in FIG. 9, so that the voltage drop of the data enable period Td is reduced. The capacity of the output capacitor of the above-described analog power supply circuit and the low-pass filter unit capacitor Cf of the gradation voltage generation unit (gradation voltage generation unit) shown in FIG. 8 can be reduced, thereby suppressing unnecessary cost increase. be able to.

  Further, as shown in FIG. 9, the setting value of the analog voltage Vsd (output driving voltage) can be lowered from the conventional setting value indicated by the broken line to the setting value indicated by the solid line (downward arrow), and the maximum gradation The potential difference from the voltage (Vref−Max) can be set to the minimum necessary. As a result, power consumption of the analog voltage can be suppressed.

  In the first to fourth embodiments described above, a liquid crystal panel is adopted as an example of a display panel for displaying an image, and the embodiment thereof is shown. However, it is not necessary to designate and implement a display device. The display surface may be a so-called flat panel display having a flat shape, and can be employed in a liquid crystal display device, an organic EL display device, a MEMS (Micro Electro-Mechanical System) display, and the like.

3 Source driver control signal 4 Gate driver control signal 8 Blanking period determination signal 11 Blanking period output signal (pseudo DENA signal)
50 liquid crystal display device 51 scanning signal line 52 image signal line 53 timing control unit 54 pixel 55 liquid crystal panel 56 source driver IC (S-IC)
57 Gate Driver IC (G-IC)
58 Timing Controller (T-CON)
60 power supply circuit section 67 line memory V-Data image data DENA period in which image data is valid CLK clock Vsd analog voltage Vref gradation voltage Vref-Max maximum gradation voltage Td data enable period Tb vertical blanking period LP latch pulse signal POL Image signal line polarity signal Is Analog current consumption Sout S-IC output

Claims (8)

A display panel comprising a plurality of pixels arranged in a matrix, a plurality of image signal lines arranged in each column of the pixels, and a plurality of scanning signal lines arranged in each row of the pixels;
Scanning signal line driving means for driving the scanning signal line;
Image signal line driving means for supplying an image signal for driving the pixel to the image signal line;
Timing control means for driving and controlling the scanning signal line driving means and the image signal line driving means;
In an active matrix display device comprising: a power supply unit configured to include an image signal line driving unit and a gradation voltage generating unit, the power source unit being configured by a booster circuit;
The timing control unit is configured to output an image display control signal output from the timing control unit to the image signal line driving unit in advance for a predetermined period from the end of the vertical blanking period. As a result, the voltage variation of the output driving voltage occurs during the vertical blanking period. The image display control signal is classified into display data corresponding to the display luminance of the pixel and a drive control signal for controlling the input / output timing of the display data in the image signal line driving means,
The active matrix display device according to claim 1, wherein the display data for the preceding output corresponds to a maximum voltage for the display panel. The image display control signal is classified into display data corresponding to the display luminance of the pixel and a drive control signal for controlling the input / output timing of the display data in the image signal line driving means,
2. The active matrix display device according to claim 1, wherein the display data for the preceding output corresponds to a halftone voltage for the display panel. The image display control signal is classified into display data corresponding to the display luminance of the pixel and a drive control signal for controlling the input / output timing of the display data in the image signal line driving means,
A line memory for storing image data of the first row one frame before;
The active matrix display device according to claim 1, wherein the display data for the preceding output is generated based on the image data stored in the line memory. The image display control signal is classified into display data corresponding to the display luminance of the pixel and a drive control signal for controlling the input / output timing of the display data in the image signal line driving means,
2. The active matrix display device according to claim 1, wherein the display data for the preceding output can be selected according to a configuration of a pixel of the display panel. The image display control signal is classified into display data corresponding to the display luminance of the pixel and a drive control signal for controlling the input / output timing of the display data in the image signal line driving means,
2. The active matrix display device according to claim 1, wherein the display data for the preceding output is generated such that an output voltage for driving the image signal line of the image signal line driving unit is gradually increased.   7. The active matrix display device according to claim 1, wherein a positive / negative alternating cycle of output polarity of the image signal line driving means during the predetermined period is shorter than an alternating cycle in a display period. .   The active matrix display device according to any one of claims 1 to 7, wherein the predetermined period is a period corresponding to 2 to 20 times a horizontal scanning period.

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