JP2016076204A - データ記憶装置の性能を意識した電力キャッピング制御 - Google Patents
データ記憶装置の性能を意識した電力キャッピング制御 Download PDFInfo
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Abstract
【解決手段】データ記憶装置を示す。データ記憶装置は、データ記憶装置用の電力閾値を識別する記憶制御システムを含む。データ記憶装置は、データ記憶装置用の消費電力特性を判定し、データ記憶装置における少なくとも記憶トランザクション待ち行列の長さを調整して、データ記憶装置用の電力閾値未満として消費電力特性を設定するデータ記憶装置用の電力制御モードに入る。
【選択図】図1
Description
102、402、802 データ記憶装置
110、410、810 電力閾値
112、412、712 記憶媒体
114、414 記憶制御システム
116、416、716 待ち行列
120、420 ホストシステム
130、330、430 リンク
140、440 待ち行列の長さ
418、718 電力測定システム
424 プロセッサ
426 メモリ
428、804 ファイルシステム
702 ハードディスクドライブ
806 ブロック入出力スケジューラ
808 電力キャップブロック入出力インタフェース
812 電力キャッピングモニタ
814 性能モニタ
816 入出力実行制御器
818 ブロック入出力要求
901 通信トランシーバ
902 計算システム
903 処理システム
905 処理回路
906 メモリシステム
907 ソフトウェア
908 スループットモードモジュール
909 待ち時間モードモジュール
910 消費電力モジュール
911 ユーザインタフェースシステム
Claims (20)
- ホストシステムを動作させてデータ記憶装置の電力使用量を制御する方法であって、
前記データ記憶装置用の電力閾値を識別するステップと、
前記データ記憶装置用の消費電力特性を判定するステップと、
前記データ記憶装置用の電力制御モードに入り、前記データ記憶装置における少なくとも記憶トランザクション待ち行列の長さを応答可能に調整して、前記データ記憶装置用の前記電力閾値未満として前記消費電力特性を設定するステップと、
を含む方法。 - 前記消費電力特性を前記電力閾値未満に維持しながら、スループットをスループット閾値より上に増大させることに前記データ記憶装置用の最大の記憶トランザクション待ち行列の長さを専念させるステップをさらに含む、請求項1に記載の方法。
- 前記消費電力特性を前記電力閾値未満に維持しながら、待ち時間を待ち時間閾値未満に減少させるために前記記憶トランザクション待ち行列の長さを減少させるステップをさらに含む、請求項1に記載の方法。
- 前記実際の消費電力特性と前記目標消費電力特性との間の差に比例した前記記憶トランザクション待ち行列の長さを適応的に調整するステップをさらに含む、請求項1に記載の方法。
- 前記データ記憶装置における電力測定システムを利用して消費電力特性を測定するステップをさらに含む、請求項1に記載の方法。
- ホストシステムを用いて電力測定システムから消費電力特性を自動的および/または連続的に通信するステップをさらに含む、請求項1に記載の方法。
- サンプリングレートを設定するステップと、測定期間を設定するステップと、電力測定システム用の時間ベースの電力測定およびトランザクションベースの電力測定の中から選択するステップとのうちの少なくとも1つのステップをさらに含む、請求項1に記載の方法。
- ホストシステムによって前記データ記憶装置の前記電力測定システムの動作を制御するステップをさらに含む、請求項1に記載の方法。
- ホストシステムからの非同期要求に応じて前記データ記憶装置の記憶媒体上の所定の位置に識別子の組を書き込み、前記関連消費電力を測定するステップをさらに含む、請求項1に記載の方法。
- 記憶トランザクション待ち行列内で範囲をサイズ変更するステップをさらに含む、請求項1に記載の方法。
- データ記憶装置において消費電力を制御するホストシステムであって、
前記データ記憶装置の電力閾値を識別するように構成されている記憶制御システムと、
前記データ記憶装置の消費電力特性を監視するように構成されている電力測定システムと、
を含み、前記記憶制御システムが、前記データ記憶装置用の電力制御モードに入り、前記データ記憶装置における少なくとも記憶トランザクション待ち行列の長さを応答可能に調整して、前記データ記憶装置用の前記電力閾値未満として前記消費電力特性を設定するように構成される、ホストシステム。 - 前記消費電力特性を前記電力閾値未満に維持しながら、スループットをスループット閾値より上に増大させることに前記データ記憶装置用の最大の記憶トランザクション待ち行列の長さを専念させるようにさらに構成される、請求項11に記載のホストシステム。
- 前記消費電力特性を前記電力閾値未満に維持しながら、待ち時間を待ち時間閾値未満に減少させるために前記記憶トランザクション待ち行列の長さを減少させるようにさらに構成される、請求項11に記載のホストシステム。
- 前記実際の消費電力特性と前記目標消費電力特性との間の差に比例した前記記憶トランザクション待ち行列の長さを適応的に調整するようにさらに構成される、請求項11に記載のホストシステム。
- 電力測定システムをさらに含む、請求項11に記載のホストシステム。
- ホストシステムを用いて消費電力特性を自動的および/または連続的に通信するようにさらに構成される、請求項15に記載の電力測定システム。
- 設定可能なサンプリングレート、設定可能な測定期間、時間ベースの電力測定、およびトランザクションベースの電力測定のうちの少なくとも1つをさらに含む、請求項15に記載の電力測定システム。
- ホストシステムから制御コマンドを受信して制御コマンドに応答するようにさらに構成される、請求項15に記載の電力測定システム。
- ホストシステムからの非同期要求に応じて前記データ記憶装置の記憶媒体上の所定の位置に識別子の組を書き込み、前記関連消費電力を測定するようにさらに構成される、請求項11に記載のホストシステム。
- 記憶トランザクション待ち行列内で範囲をサイズ変更するようにさらに構成される、請求項11に記載のホストシステム。
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US14/493,304 US10146293B2 (en) | 2014-09-22 | 2014-09-22 | Performance-aware power capping control of data storage devices |
US14/493,304 | 2014-09-22 |
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EP (1) | EP2998830B8 (ja) |
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KR (1) | KR101831915B1 (ja) |
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EP2998830B1 (en) | 2019-08-07 |
CN105487814A (zh) | 2016-04-13 |
JP6162765B2 (ja) | 2017-07-12 |
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EP2998830A1 (en) | 2016-03-23 |
SG10201507858YA (en) | 2016-04-28 |
US10146293B2 (en) | 2018-12-04 |
KR20160034826A (ko) | 2016-03-30 |
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