WO2018068638A1 - 固态存储设备及其温度、功耗控制方法 - Google Patents

固态存储设备及其温度、功耗控制方法 Download PDF

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Publication number
WO2018068638A1
WO2018068638A1 PCT/CN2017/103578 CN2017103578W WO2018068638A1 WO 2018068638 A1 WO2018068638 A1 WO 2018068638A1 CN 2017103578 W CN2017103578 W CN 2017103578W WO 2018068638 A1 WO2018068638 A1 WO 2018068638A1
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Prior art keywords
power
value
state storage
storage device
credit
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PCT/CN2017/103578
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English (en)
French (fr)
Inventor
曹定尊
路向峰
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北京忆恒创源科技有限公司
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Priority claimed from CN201610887436.6A external-priority patent/CN107918522B/zh
Priority claimed from CN201610886067.9A external-priority patent/CN107919143B/zh
Application filed by 北京忆恒创源科技有限公司 filed Critical 北京忆恒创源科技有限公司
Publication of WO2018068638A1 publication Critical patent/WO2018068638A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Definitions

  • the present application relates to the field of solid state storage technologies, and in particular, to a solid state storage device and a control method thereof.
  • the solid state storage device 102 is coupled to the host for providing storage capabilities to the host.
  • the host and the solid-state storage device 102 can be coupled in various manners, including but not limited to, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface). , SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe, High Speed Peripheral Component Interconnect) NVMe (NVM Express, high speed nonvolatile storage), Ethernet, Fibre Channel, wireless communication network, etc. are connected to the host and solid state storage device 102.
  • SATA Serial Advanced Technology Attachment
  • SCSI Serial Attached SCSI
  • IDE Integrated Drive Electronics
  • USB Universal Serial Bus
  • PCIE Peripheral Component Interconnect Express
  • PCIe High Speed Peripheral Component Interconnect
  • NVMe High Speed nonvolatile storage
  • Ethernet Fibre Channel
  • Fibre Channel
  • the host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, and the like.
  • the storage device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.
  • NAND flash memory phase change memory
  • FeRAM Feroelectric RAM
  • MRAM Magnetic Random Access Memory
  • RRAM Resistive Random Access Memory
  • the interface 103 can be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, and the like.
  • Control component 104 is used to control data transfers between interface 103, NVM chip 105, and firmware memory 110, as well as for storage management, host logical address to flash physical address mapping, erase equalization, bad block management, and the like.
  • the control unit 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof.
  • the control unit 104 can be an FPGA (Field-programmable gate array) or an ASIC (Application Specific Integrated Circuit).
  • control component 104 may also include a processor or controller that executes software in the processor or controller to manipulate the hardware of the control component 104 to process IO (Input/Output) commands; the control component 104 It is also possible to couple to DRAM 110 and to access data of DRAM 110; the DRAM can store data for FTL tables and/or cached IO commands.
  • IO Input/Output
  • Control component 104 includes a flash interface controller (or flash channel controller) coupled to NVM chip 105 and issuing commands to NVM chip 105 in a manner consistent with the interface protocol of NVM chip 105 to operate the NVM chip 105, and receives a command execution result output from the NVM chip 105.
  • the interface protocol of the NVM chip 105 includes well-known interface protocols or standards such as "Toggle” and "ONFI".
  • a memory target is one or more Logic Units of a shared chip enable signal (CE, Chip Enable) within a NAND flash package.
  • Each logical unit has a LUN (Logic Unit Number).
  • One or more dies (Die) may be included in the NAND flash package.
  • the logic unit corresponds to a single die.
  • the logic unit can include a plurality of planes. Multiple planes within a logical unit can be accessed in parallel, while multiple logical units within a NAND flash chip can execute command and report states independently of each other.
  • the different energy consumed to access different operations of the NVM chip 105 corresponds to different power consumption.
  • the power state of the solid state storage device is defined in the NVMe protocol (see Table 1). A variety of power states are defined in Table 1, and each power state has a different maximum power consumption.
  • the operating temperature of the solid state storage device also needs to be effectively controlled. Temperatures that are too high or too low can affect the operation of the electronics. The temperature is affected by factors such as the power consumption of the solid-state storage device and the heat dissipation capability of the environment. The temperature of the solid state storage device is too high or too low to affect the operation of the electronic device.
  • Solid-state storage devices that conform to the NVMe protocol need to implement multiple power states. To achieve the power state required by the NVMe protocol, the temperature and power consumption of the solid state storage device needs to be controlled within a specified value or range.
  • the purpose of the application is to provide a solid state storage device and a control method thereof. Used to control the power and temperature of solid state storage devices.
  • a control method of a first solid state storage device comprising the steps of: step S1, measuring a current temperature value; and step S2, according to a current temperature value and a target temperature value Poorly, updating the value of the power quota pool; step S3, in response to the operation of accessing the NVM chip, applying a power quota from the power quota pool; step S4, performing an operation of accessing the NVM chip according to the applied power quota; step S5, responding The execution of the operation of accessing the NVM chip is completed, and the power amount is returned.
  • a control method of the second solid-state storage device if the current temperature value is greater than the target temperature value, the rated power pool is lowered. Value; if the current temperature value is less than the target temperature value, increase the value of the power quota pool.
  • control method of the second solid-state storage device of the first aspect of the present application there is provided a control method of the third solid-state storage device according to the first aspect of the present application, the amount of the power account pool being reduced or increased, proportional to the current The difference between the temperature value and the target temperature value.
  • the control method of the fourth solid-state storage device according to the first aspect of the present application is provided, and the power quota pool is acquired according to the difference between the current temperature value and the target temperature value. A decrease in the value or an increase in the amount.
  • a control method of a fifth solid-state storage device further comprising: measuring a current power value, if current If the power value is greater than the target power value, the value of the rated power pool is lowered; if the current power value is less than the target power value, the value of the power quota pool is increased.
  • step S4 in response to the power quota application being successful, step S4 is performed.
  • a control method of the seventh solid-state storage device according to the first aspect of the present application is provided, and step S2 is periodically performed.
  • a control method of an eighth solid-state storage device according to the first aspect of the present application, according to a difference between a current temperature value and a target temperature value
  • the value of the updated power quota pool includes: determining whether the solid state storage device is currently in a power unrestricted mode; if yes, setting a power available quota of the power quota pool to a maximum value, and updating the value of the power credit pool.
  • a control method of a ninth solid-state storage device if the solid-state storage device is currently not in power unlimited Mode; determining whether the period of obtaining the temperature value is reached; if yes, reading the current temperature value, and updating the power of the power quota pool according to the difference between the current temperature value and the target temperature value, and updating the value of the power quota pool.
  • control method of a tenth solid-state storage device in response to occurrence of a burst of access to the NVM chip Operation, lower the target power value.
  • the operation of the burst accessing the NVM chip includes, at a unit time A read, write, or erase operation that exceeds a first threshold, or a total amount of the three operations exceeds a second threshold.
  • the operation of the burst accessing the NVM chip refers to accessing in a unit time
  • the increment of operation of the NVM chip exceeds a third threshold.
  • a control method of a thirteenth solid-state storage device comprising a plurality of command queues
  • the operation of accessing the NVM chip in a command queue accesses a logical unit corresponding to the command queue.
  • control method of the thirteenth solid-state storage device of the first aspect of the present application there is provided a control method of the fourteenth solid-state storage device according to the first aspect of the present application, if the value of the power credit pool is insufficiently allocated to the plurality of access NVMs The operation of the chip distributes the credit value in turn to the operation of accessing the NVM chip in different command queues.
  • control method of the fifteenth solid-state storage device performing a read operation, a program operation, or a wipe
  • the amount of credit required for the operation is different.
  • the control method of the solid-state storage device of the present application controls the temperature and power of the solid-state storage device, and the power consumption management of the solid-state storage device is more reasonable, and the usage times and service life of the solid-state storage device are prolonged.
  • a control method of a first solid-state storage device comprising the steps of: measuring a current power value, and updating a power quota according to a difference between a current power value and a target power value
  • the power of the pool can be used; the current temperature value is measured; according to the difference between the current temperature value and the target temperature value, the second power available quota of the power quota pool is calculated; if the second power available credit is less than the power of the power quota pool, Using the credit, the power usage credit of the power credit pool is updated with the second power available credit.
  • a control method of a second solid-state storage device in response to the operation of accessing the NVM chip, requesting power from the power quota pool The amount of power; the operation of accessing the NVM chip is performed according to the applied power amount; and the power amount is returned in response to the completion of the operation of accessing the NVM chip.
  • control method of a third solid-state storage device in response to the occurrence of a burst of access to the NVM chip Operation, lower the target power value.
  • the operation of the burst accessing the NVM chip includes: memory per unit time A read operation, a write operation, or an erase operation exceeding the first threshold, or the total amount of the three operations exceeds the second threshold.
  • the operation of the burst accessing the NVM chip refers to accessing the NVM in a unit time.
  • the increment of the operation of the chip exceeds a third threshold.
  • a control method of a sixth solid-state storage device comprising a plurality of command queues, one The operation of accessing the NVM chip in the command queue accesses the logical unit corresponding to the command queue.
  • control method of the sixth solid-state storage device of the second aspect of the present application there is provided a control method of a seventh solid-state storage device according to the second aspect of the present application, if the value of the power credit pool is insufficiently allocated to a plurality of accessing NVM chips Operation, the quota value is alternately assigned to the operation of accessing the NVM chip in different command queues.
  • control method of an eighth solid-state storage device including read operation, programming Operation or erase operation.
  • the control method of the solid-state storage device of the present application controls the temperature and power of the solid-state storage device, and the power consumption management of the solid-state storage device is more reasonable, and the usage times and service life of the solid-state storage device are prolonged.
  • a first solid state storage device comprising: an NVM chip, a control management system, a power sensor and a temperature sensor, an NVM chip and a control management system coupling, a power sensor and a temperature
  • the sensors are coupled to a control management system; the power sensor is used to measure the current power value of the solid state storage device; the temperature sensor is used to measure the current temperature value of the solid state storage device; and the control management system is used for the solid state storage device measured by the power sensor The current power value, the current temperature value of the solid state storage device measured by the temperature sensor, schedules access to the NVM chip.
  • a second solid-state storage device comprising: a power control unit, a power quota pool and a power credit manager, and a power quota pool Separably coupled to a power amount manager and a power control unit, the power amount manager is coupled to the NVM chip, and the power control unit is coupled to the power sensor and the temperature sensor, wherein the power control unit is configured to use the current temperature value and the target temperature value, While satisfying the target power value, the current temperature value is controlled below the target temperature value; the value of the power quota pool is set according to the current power value and the target power value; the power quota manager is used to apply for the credit to the power quota pool, and the access is allowed to be performed.
  • the third solid-state storage device according to the third aspect of the present application is provided, and when the power quota manager fails to apply for the credit amount pool, the operation of suspending access to the NVM chip is continued until The application quota to the power quota pool was successful.
  • the power control unit is further configured to identify a burst access operation of the NVM chip, and adjust Low target power value.
  • the solid-state storage device of the present application controls the temperature and power of the solid-state storage device, and manages the power consumption of the solid-state storage device more reasonably, thereby prolonging the usage times and service life of the solid-state storage device.
  • a power control method for a first solid-state storage device comprising the steps of: Step S1, requesting a power quota from a power quota pool in response to an operation of accessing an NVM chip; Step S2: Perform an operation of accessing the NVM chip according to the applied power quota; and step S3, returning the power quota to the power quota pool in response to the completion of the operation of accessing the NVM chip.
  • the power control method of the second solid-state storage device is provided, further comprising: step R1: acquiring the current power of the solid-state storage device Value; step R2, updating the value of the power quota pool according to the difference between the current power value and the target power value.
  • the slave power quota pool application The power quota further includes: in response to the power quota application being successful, performing step S2.
  • the slave power quota pool application The power quota further includes tentatively processing the operation of accessing the NVM chip in response to the failure of the power quota application until the power quota application is successful.
  • a power control method of a fifth solid-state storage device which performs step R2 periodically.
  • a power control method of a sixth solid-state storage device in step R2, according to current power
  • the difference between the value and the target power value, and the value of the updated power quota pool includes: determining whether the solid state storage device is currently in a power unrestricted mode; if yes, setting the power quota of the power quota pool to a maximum value, and updating the power quota The value of the pool.
  • a power control method of a seventh solid-state storage device according to a current power value and a target power
  • the value of the updated value pool includes: if the current power value is greater than the target power value, the value of the power quota pool is lowered; if the current power value is less than the target power value, the value of the power quota pool is increased.
  • the power control method of the eighth solid-state storage device According to the power control method of the seventh solid-state storage device of the fourth aspect of the present application, there is provided the power control method of the eighth solid-state storage device according to the fourth aspect of the present application, the amount of the power account pool being reduced or increased, It is proportional to the difference between the current power value and the target power value.
  • a power control method of a ninth solid-state storage device according to the fourth aspect of the present application, further comprising:
  • the target power value is turned down in response to the operation of the burst accessing the NVM chip.
  • the operation of the burst accessing the NVM chip includes: There is a read operation, a write operation, or an erase operation exceeding the first threshold in a unit time, or the total amount of the three operations exceeds the second threshold.
  • the operation of the burst accessing the NVM chip refers to the unit The increment of access to the NVM chip during the time exceeds a third threshold.
  • the solid-state storage device including Command queues, access to the NVM chip in a command queue access to the logical unit corresponding to the command queue.
  • the power control method of the thirteenth solid-state storage device according to the fourth aspect of the present application is provided, if the value of the power account pool is insufficiently allocated to the The operation of accessing the NVM chip distributes the credit value in turn to the operation of accessing the NVM chip in different command queues.
  • a power control method of a fourteenth solid-state storage device includes read, program, or erase operations.
  • a power control method of a fourteenth solid-state storage device of a fourth aspect of the present application there is provided a power control method of a fifteenth solid-state storage device according to the fourth aspect of the present application, performing a read operation, a program operation, or an erase operation The amount of credit required is different.
  • the power control method of the solid-state storage device of the present application controls the power of the solid-state storage device, and the power consumption management of the solid-state storage device is more reasonable, and the usage times and service life of the solid-state storage device are prolonged.
  • a first solid state storage device comprising: an NVM chip, a power management system and a power sensor, an NVM chip and a power management system coupling, a power sensor and a power management system Phase coupling; a power sensor for measuring a current power value of the solid state storage device; and a power management system for scheduling access to the NVM chip by the current power value of the solid state storage device measured by the power sensor.
  • a second solid-state storage device comprising: a power control unit, a power credit pool, and a power credit manager, a power quota
  • the pool is coupled to the power amount manager and the power control unit, the power amount manager is coupled to the NVM chip, and the power control unit is coupled to the power sensor, wherein the power control unit is configured to set the power according to the current power value and the target power value.
  • the value of the quota pool; the power quota manager is used to apply for a quota to the power quota pool, allows access to the operation of the NVM chip, and returns the credit to the power credit pool after the operation is completed.
  • the third solid-state storage device provides the credit value in the power quota pool when the power quota manager fails to apply for the credit amount pool to the power quota pool.
  • the operation of the NVM chip is suspended until the amount of the power quota pool is successfully applied.
  • the power control unit is further configured to identify a burst access operation of the NVM chip, and Turn down the target power value.
  • the power control method of the solid-state storage device of the present application controls the power of the solid-state storage device, and the power consumption management of the solid-state storage device is more reasonable, and the usage times and service life of the solid-state storage device are prolonged.
  • a power control apparatus for a first solid state storage device comprising: a power credit application module for responding to an operation of accessing an NVM chip from a power amount pool Applying a power quota; an execution module, configured to perform an operation of accessing the NVM chip according to the applied power quota; and a power amount returning module for returning the power quota to the power credit pool in response to completion of the operation of accessing the NVM chip.
  • the power acquisition module configured to acquire a current state of the solid-state storage device
  • the power value update module is configured to update the value of the power account pool according to the difference between the current power value and the target power value.
  • a power control apparatus for a third solid-state storage device in response to the power quota application module applying for a power quota Successfully, the execution module performs an operation to access the NVM chip.
  • a power control apparatus for a fourth solid-state storage device in response to the power quota application module applying for a power quota Failure, the execution module suspends processing of the operation of accessing the NVM chip until the power quota application module applies for the power quota successfully.
  • the power credit update module periodically Update the value of the power quota pool.
  • the power credit update module according to the current The difference between the power value and the target power value, and the value of the updated power quota pool includes: determining whether the solid state storage device is currently in a power unrestricted mode; if yes, setting the power quota of the power quota pool to a maximum value, and updating the power The value of the quota pool.
  • the power credit update module according to The difference between the current power value and the target power value, and the value of the updated power quota pool includes: if the current power value is greater than the target power value, reducing the value of the rated power pool; if the current power value is less than the target power value, increasing the rated power quota pool Value.
  • the power control device of the seventh solid-state storage device of the sixth aspect of the present application there is provided the power control device of the eighth solid-state storage device according to the sixth aspect of the present application, the amount of the power account pool being reduced or increased, It is proportional to the difference between the current power value and the target power value.
  • a power control device of a ninth solid-state storage device according to the sixth aspect of the present application, the power credit update module being responsive to the occurrence The operation of the NVM chip is suddenly accessed, and the target power value is lowered.
  • a power control device of a tenth solid-state storage device including a plurality of commands Queue, the access to the NVM chip in a command queue accesses the logical unit corresponding to the command queue.
  • the power control apparatus of the eleventh solid-state storage device of the sixth aspect of the present application if the value of the power credit pool is insufficiently allocated to the plurality of Accessing the operation of the NVM chip assigns the credit value in turn to the operation of accessing the NVM chip in different command queues.
  • the power control device of the solid-state storage device of the present application controls the power of the solid-state storage device, and the power consumption management of the solid-state storage device is more reasonable, and the usage times and service life of the solid-state storage device are prolonged.
  • a program comprising instructions that, when loaded into a storage device and executed on a storage device, cause the storage device to perform the first aspect, the second aspect according to the present application Or the method of the fourth aspect.
  • a computer readable storage medium having stored thereon a program including instructions that, when loaded into a storage device and executed on a storage device, cause the storage device to perform The method of the first, second or fourth aspect of the application.
  • FIG. 1 is a block diagram of a prior art solid state storage device
  • FIG. 2 is a block diagram of a power management system in accordance with an embodiment of the present application.
  • FIG. 3 is a block diagram of a power management system in accordance with yet another embodiment of the present application.
  • FIG. 4 is a flow chart of a power control process in accordance with yet another embodiment of the present application.
  • FIG. 5 is a flowchart of a power control process according to still another embodiment of the present application.
  • FIG. 6 is a block diagram of a power management system in accordance with yet another embodiment of the present application.
  • FIG. 7 is a block diagram of a power management system in accordance with yet another embodiment of the present application.
  • FIG. 8 is a block diagram of a power management system in accordance with another embodiment of the present application.
  • FIG. 9 is a flow chart of a temperature-power control process in accordance with another embodiment of the present application.
  • FIG. 10 is a flowchart of a temperature-power control process according to still another embodiment of the present application.
  • FIG. 11 is a block diagram of a power management system in accordance with another embodiment of the present application.
  • FIG. 12 is a flow chart of a temperature-power control process in accordance with yet another embodiment of the present application.
  • the power consumption of solid-state storage devices is mainly derived from the read, program, and erase operations of the NVM chip. Each operation consumes different amounts of energy. For example, in one configuration (clock frequency, physical page size, etc.), a single NVM read consumes approximately 90 mW (milliwatts), a single program operation consumes approximately 150 mW, and a single erase operation consumes approximately 180 mW.
  • a plurality of NVM chips may be included in the solid state storage device, and logical units (LUNs) of the NVM chip may be accessed in parallel, so that a read operation, a program operation, or an erase operation may be performed in parallel on a plurality of logical units of the solid state storage device. The number of operations performed in parallel on multiple logical units also directly affects the power consumption of the solid state storage device.
  • LUNs logical units
  • the required power consumption state is achieved by controlling the number of operations such as read operations, program operations, erase operations, etc. of the issued NVM chip.
  • the power management system 200 of the solid state storage device includes a power manager 210 and a power sensor 230.
  • the power manager 210 is coupled to the NVM chip 105 (see also FIG. 1) for controlling whether to transmit IO operations in the command queue 240 to the NVM chip 105 in accordance with the power control target.
  • the power sensor 230 detects or acquires the power of the solid state storage device, such as by detecting the current and/or voltage of the solid state storage device power supply. Power management system 200 also maintains target power 220.
  • Target power 220 indicates the upper power limit of the solid state storage device in the current power state.
  • power manager 210 obtains the current power of the solid state storage device from power sensor 230, as compared to the value indicated by target power 220. If the current power is less than the target power, the power manager 210 allows the IO operation in the command queue 240 to be sent to the NVM chip 105; if the current power is not less than the target power, the power manager 210 implements power control and disables the command queue 240. The IO operation is sent to the NVM chip 105.
  • the power manager 210 can be implemented by the control component 104 of the solid state storage device (see also FIG. 1) or by the CPU in the control component 104 by executing a program.
  • the power management system 300 includes a power control unit 320, a power credit pool 330, and a power credit manager 310.
  • the power credit manager 310 controls whether to access the NVM chip IO operations in the command queue 240 to the NVM chip 105 based on the power quota provided by the power credit pool 330.
  • the power credit manager 310 applies for a power quota from the power credit pool 330.
  • the power credit values required for different types of IO operations are different.
  • the power control unit 320 is coupled to the power sensor 230 to compare the current power provided by the power sensor 230 with the target power 220 to update the power credit value of the power credit pool 330. For example, when the current power is less than the target power 220, more power credits are provided to the power credit pool 330, and when the current power is greater than the target power, the value of the power credit pool 330 is reduced.
  • the power credit value of the power credit pool 330 determines the number of IO operations that can be concurrently run in the solid state storage device.
  • the power quota manager 310 When there is an IO operation to be sent to the NVM chip 105 in the command queue 240, the power quota manager 310 applies the power quota to the power quota pool 330, and returns the applied power amount to the power credit pool 330 after the IO operation is completed.
  • the power quota pool 330 has an initial credit value of 100, and each NVM chip read operation requires a credit value of three, and each NVM chip programming operation requires a credit value of 14, which requires each NVM chip erase operation.
  • the limit value is 15.
  • the power credit manager 310 applies a credit value of 3 to the power credit pool 330.
  • the credit value pool 330 has a credit value from 100 to 97.
  • the power credit manager 310 A credit of value 3 is returned to the power credit pool 330.
  • the solid state storage device can process 33 read operations, 7 program operations, or 6 erase operations in parallel.
  • the power credit manager 310 will suspend the IO operations in the processing command queue 240.
  • the power quota pool 330 has a power quota value of 7, and there is a programming operation in the command queue 240 that needs to be processed, and the required credit value is 14. Since the remaining credit value of the power credit pool 330 is less than 14, it indicates that the remaining credit value is insufficient to support the programming operation.
  • the power credit manager 310 is unable to obtain a credit value for the programming operation, thus tentatively processing the programming operation of the command queue 240 until a power credit value sufficient for the programming operation occurs in the power credit pool 330.
  • power credit manager 310 schedules read operations in command queue 240.
  • the read operation requires a credit value of 3, which is less than the remaining credit value 7 of the power credit pool 330, so the power credit manager 310 can obtain sufficient power quota for the read operation from the power credit pool 330 and send the read operation to the NVM chip. 105.
  • current power is periodically acquired from the power sensor 230, compared to the target power 220, and the power credit value of the power credit pool 330 is updated.
  • the process of controlling the power of the solid state storage device includes the power control unit 320 obtaining the current power value from the power sensor 230 and obtaining the target power 220.
  • the power control unit 320 updates the power credit value of the power credit pool 330 according to the difference between the current power value and the target power value.
  • the power credit manager 310 applies a power quota to the power credit pool 330.
  • the power levels required may vary for different types of IO operations.
  • the power credit application will succeed, and the power credit value of the power credit pool 330 correspondingly reduces the applied credit value.
  • the power credit manager 310 allows the IO operation to be sent to the NVM chip 105; if the power quota application is unsuccessful, the processing of the IO operation is temporarily stopped, and the power credit manager 310 continues to apply power for the IO operation. The amount is up until the power quota is applied successfully.
  • the power quota is returned to the power credit pool 330 in response to completion of the IO operation access to the NVM chip. In response to the return power quota, the value of the power credit pool 330 is increased by the returned credit value.
  • FIG. 5 is a flow chart of a power control process in accordance with yet another embodiment of the present application.
  • the process of controlling the power of the solid state storage device includes: the power control unit 320 determines whether the current power state is unrestricted, and in the power state with no power limit, sets the power of the power credit pool 330.
  • the credit limit can be used as the maximum value and the power credit value of the power credit pool 330 is updated.
  • the host can set the solid state storage device to an unrestricted power state.
  • power control unit 320 and power credit manager 310 still operate even in a power-unlimited power state.
  • the power control unit 320 updates the value of the power credit pool 330 based on the power available quota of the power credit pool 330.
  • the maximum power usage limit of the power credit pool 330 is 210
  • the current power available usage quota is 100
  • the current power credit value is 50 because a partial power credit value is requested to process the IO operation.
  • the current power credit value is increased by the same magnitude, ie from 50 to 160.
  • the host can also set the solid state storage device to a different power state.
  • Corresponding to each power state there is a respective target power 220.
  • the target power 220 is also specified by the host.
  • the current power value is periodically acquired from the power sensor 230 and the power credit value of the power credit pool 330 is periodically updated.
  • power control unit 320 reads the current power value from power sensor 230, at the beginning or end of the control cycle.
  • the power quota value of the power quota pool 330 is updated according to the power available quota of the power credit pool 320 according to the difference between the current power value and the target power 220.
  • the period of acquiring power and the control period may be the same or different. Reducing the period and/or control period of the acquired power helps to increase the sensitivity or accuracy of the power control.
  • the current power value is not acquired from the power sensor 230 during the period in which the power is acquired. Therefore, during the period in which the power is acquired, if the control period expires, the power control unit 320 calculates the power usable amount based on the power value obtained from the power sensor 230 last time.
  • the power control unit 320 updates the credit value of the power quota pool 330
  • the power credit value of the power credit pool 330 is decreased; if the current power value is less than the target power value, the power is increased.
  • the power quota value of the quota pool 330 is proportional to the difference between the current power value and the target power value.
  • power control unit 320 calculates an increment of the power usable amount based on the difference between the current power value and the target power value. For example, if the current power value is less than the target power value, the power available usage amount is increased; and if the current power value is greater than the target power value, the power available usage amount is decreased. And updating the power quota value of the power credit pool 330 according to the increment of the power available amount.
  • the power usable amount be P
  • P(t 0 ) is the power usable amount of the previous time (time t 0 )
  • P(t 1 ) is the power usable amount to be updated currently, so that the power amount is
  • the power quota value of the pool is P c
  • the value of the power quota pool is an indication of the amount actually owned by the power quota pool, then:
  • P m is the current power value obtained from the power sensor 230
  • P t is the target power 220
  • the power credit pool 330 maintains the power of the power credit pool 330 to use the credit P and the power credit value P c of the power credit pool 330.
  • the power control unit 320 reads the power usable credit P(t 0 ) from the power credit pool 330, and calculates P(t 1 ) by the formula ( 1 ); The usage quota P(t 1 ) is provided to the power credit pool 330.
  • the power credit pool 330 uses the difference P(t 1 ) based on the received power, using the difference between P(t 1 ) and P(t 0 ) as the increment of the power credit value P c .
  • the power control unit 320 reads the power usable credit P(t 0 ) from the power credit pool 330, and calculates P(t 1 ) by the formula ( 1 ), which will be P(t). 1 )
  • the difference from P(t 0 ) is supplied to the power credit pool 330.
  • the power credit pool 330 also obtains and records the updated power usable credit (P(t 1 )) by the difference.
  • the read, program, and erase operations accessing the NVM chip 105 are counted to identify bursts of IO operations.
  • the burst of the IO operation refers to a read operation, a write operation or an erase operation exceeding a threshold value in a unit time, or the total amount/weighted total of the three IO operations exceeds a threshold value, and may also refer to an IO operation in a unit time.
  • the increment exceeds the threshold.
  • different thresholds are assigned to each operation to identify bursts of IO operations.
  • power control unit 320 In response to identifying a burst of IO operations, reduces the value of target power 220, thereby inhibiting a substantial increase in solid state storage device power caused by a burst of large operations.
  • FIG. 6 is a block diagram of a power management system in accordance with yet another embodiment of the present application.
  • the power management system 600 shown in FIG. 6 is similar to the power management system 300 shown in FIG. 3, except that the power amount manager 610 also counts IO operations and provides read and write operations to the power control unit 620. And/or statistical results of the erase operation. Based on the statistical result of the IO operation, the power control unit 620 identifies the burst of the IO operation and modifies (reduces) the target power 220 in response to the burst of the IO operation.
  • the power management system is utilized to control the temperature of the solid state storage device to prevent the solid state storage device from operating at excessive temperatures. Temperature is a by-product of power consumption, thus controlling the heating of solid-state storage devices by managing the power consumption of solid-state storage devices.
  • FIG. 7 is a block diagram of a power management system including a power manager 710 and a temperature sensor 730 in accordance with yet another embodiment of the present application.
  • Power manager 710 is coupled to NVM chip 105 (see also Figure 1), It is used to control whether the IO operation of accessing the NVM chip in the command queue 240 is sent to the NVM chip 105 according to the temperature control target.
  • Temperature sensor 730 detects or acquires the temperature of the solid state storage device, such as by arranging temperature sensors at one or more locations of the solid state storage device.
  • Power management system 700 also maintains target temperature 720.
  • Target temperature 720 indicates an upper operating temperature limit for the solid state storage device.
  • power manager 710 obtains the current temperature of the solid state storage device from temperature sensor 730, as compared to the value indicated by target temperature 720. If the current temperature is less than the target temperature 720, the power manager 710 allows the IO operation in the command queue 240 to be sent to the NVM chip 105; if the current temperature is not less than the target temperature 720, the power manager 710 performs power control and disables the command queue 240 The IO operation in is sent to the NVM chip 105.
  • the power management system 800 includes a power control unit 820, a power credit pool 830, and a power credit manager 810.
  • the power amount manager 810 controls whether to transmit the IO operation of accessing the NVM chip in the command queue 240 to the NVM chip 105 according to the power quota provided by the power quota pool 830.
  • the power credit manager 810 applies for a power quota from the power credit pool 830.
  • the power control unit 820 is coupled to the temperature sensor 840, which compares the current temperature provided by the temperature sensor 840 with the target temperature 842 to update the power credit value of the power credit pool 830. For example, when the current temperature is less than the target temperature 842, more power credits are provided to the power credit pool 830, and when the current temperature is greater than the target temperature, the value of the power credit pool 830 is reduced.
  • the power quota manager 810 applies the power quota to the power quota pool 830, and returns the applied power amount to the power credit pool 830 after the IO operation is completed.
  • the power credit manager 810 When the power quota of the power credit pool 830 is exhausted, the power credit manager 810 will suspend the IO operations in the processing command queue 240.
  • the power control unit 820 is further coupled to the power sensor 850 to compare the current power provided by the power sensor 850 with the target power 852 to update the power credit value of the power credit pool 830. For example, when the current power is less than the target power 852, more power credits are provided to the power credit pool 830, and when the current power is greater than the target power 852, the value of the power credit pool 830 is reduced.
  • the power control unit 820 periodically acquires current power from the power sensor 850, compares it with the target power 852, and updates the power credit value of the power credit pool 830.
  • the power control unit 820 considers to increase the power credit value to the power credit pool 830 according to one of temperature or power, and according to the other of the temperature or power, it is considered that the power credit value of the power credit pool 830 is to be reduced. Then, the reduction of the power credit value is implemented, and the increase of the power credit value is not implemented to ensure the security of the solid-state storage device.
  • the host may set different target temperature values to the solid state storage device to adapt the solid state storage device to different working environments, such as a host with high heat dissipation capability or a host with high heat dissipation capability.
  • the process of controlling the temperature and power of the solid state storage device includes the power control unit 820 obtaining the current temperature value from the temperature sensor 840 and obtaining the target temperature 842.
  • the power control unit 820 updates the power credit value of the power credit pool 830 according to the difference between the current temperature value provided by the temperature sensor 840 and the target temperature value.
  • the power credit manager 810 applies to the power credit pool 830 for a power quota.
  • the power credit manager 810 allows the IO operation to be sent to the NVM chip 105; if the power quota application is unsuccessful, the processing of the IO operation is temporarily stopped, and the power credit manager 810 continues to apply power for the IO operation. The amount is up until the power quota is applied successfully.
  • the power credit is returned to the power credit pool 830 in response to completion of the operation of accessing the NVM chip. In response to the return power quota, the value of the power credit pool 830 increases the credited value.
  • the value of the updated power quota pool 830 is: if the current temperature value is greater than the target temperature value, the value of the rated power pool 830 is decreased; if the current temperature value is less than the target temperature value, Then the value of the power quota pool 830 is increased.
  • the value of the power account pool 830 is reduced or increased by a factor proportional to the current The difference between the temperature value and the target temperature value.
  • the decrease or increase in the value of the power credit pool 830 is obtained based on the difference between the current temperature value and the target temperature value.
  • the difference between the current temperature value and the target temperature value is integrated over time to obtain an increment of the power credit pool 830. If the temperature of the solid state storage device is lower than the target temperature value for a long time, the value of the power limit value 830 may be greatly increased.
  • the power credit value of the power credit pool 22 is periodically updated during power control of the solid state storage device.
  • FIG. 10 is a flow chart of a temperature-power control process in accordance with yet another embodiment of the present application.
  • the process of controlling the temperature and power of the solid state storage device includes: the power control unit 820 determines whether it is currently a power unlimited power state. In the power unlimited power state, the power quota of the power quota pool 830 is set to a maximum value, and the power credit value of the power credit pool 830 is updated.
  • the host can set the solid state storage device to a power unrestricted power state, and the host can also set the solid state storage device to other power states, with respective target temperatures 842 and/or target powers 852 corresponding to the respective power states.
  • target power 852 and/or target temperature 842 are also specified by the host.
  • the current temperature value is periodically acquired from the temperature sensor 840, and the power credit value of the power credit pool 830 is updated based on the power available for the temperature. For example, in response to a timer event or interrupt, or polling of a timer, power control unit 820 reads current temperature value from temperature sensor 840 at the beginning or end of the cycle of acquiring temperature, based on current temperature value and target temperature 842 The difference is calculated by calculating the temperature-based power usage quota and updating the power credit value of the power credit pool 830.
  • the power credit value of the power credit pool 830 is updated when the temperature-based power usable credit is less than the power-based power usable credit to avoid the power of the solid state storage device exceeding the target power. Wherein, based on the difference between the current power value and the target power 852, the power-based power usable amount is calculated.
  • the power credit value of the power credit pool 830 is updated in accordance with a smaller of the temperature-based power available credit and the power-based power available credit. If the smaller of the two increases, the power quota value of the power quota pool 830 is increased; if the smaller of the two decreases, the power credit value of the power quota pool 830 is decreased.
  • FIG. 11 is a block diagram of a power management system according to another embodiment of the present application.
  • the power management system 1100 shown in FIG. 11 is similar to the power management system 800 shown in FIG. 8 except that the power amount manager 1110 is multiple
  • the command queues, namely the command queue 240, the command queue 250, and the command queue 260 are controlled to control whether IO operations in the command queue 240, the command queue 250, and the command queue 260 to access the NVM chip are sent to the NVM chip 105.
  • the power credit manager 1110 also counts IO operations and provides statistical results of read operations, program operations, and/or erase operations to the power control unit 1120. Based on the statistical results of the IO operation, the power control unit 1120 identifies the burst of the IO operation and modifies (reduces) the target temperature 842 and the target power 852 in response to the burst of the IO operation.
  • the power quota manager 1110 selects one of the plurality of command queues and processes the IO operations of the selected command queue to prevent the IO operations in a certain command queue from waiting for processing for too long. For example, when the power credit value of the power credit pool 830 is insufficient to support simultaneous processing of multiple IO operations, the power credit manager 1110 in turn requests power quotas for IO operations in multiple command queues.
  • the process of controlling the temperature and power of the solid state storage device includes: the power control unit 1120 determines whether the power state is currently unrestricted, and in the power state with no power limit, Then, the power quota of the power quota pool 830 is set to a maximum value, and the power credit value of the power quota pool 830 is updated.
  • the host can set the solid state storage device to an unrestricted power state.
  • power control unit 1120 and power credit manager 1110 operate even in a power-unlimited power state.
  • the power control unit 1120 updates the power credit value of the power credit pool 830 according to the power available quota of the power credit pool 830.
  • the power control unit 1120 periodically acquires the current temperature value from the temperature sensor 840 and periodically updates the power credit value of the power credit pool 830. For example, in response to a timer event or interrupt, or based on polling of the timer, at the beginning or end of the cycle of acquiring the temperature, the power control unit 1120 reads the current temperature value from the temperature sensor 840 at the beginning of the control cycle or Based on the end The current temperature value and the target temperature 842 are used to update the power credit value of the power credit pool 830.
  • power control unit 1120 updates the read, program, and/or erase operations to access NVM chip 105 in command queue 240, command queue 250, and/or command queue 260. Statistics to identify if a burst of IO operations has occurred. In response to identifying a burst of IO operations, control unit 1120 lowers the target power value. In the case of an emergency without IO operation, the adjustment of the target power value is skipped.
  • the power control unit 1120 updates the power credit value of the power credit pool 830 based on the current power value and the target power value obtained from the power sensor 850, and/or the current temperature value and the target temperature value obtained from the temperature sensor 840. For example, the power-based power usable amount is calculated based on the difference between the current power value and the target power value, and the temperature-based power usable amount is calculated based on the difference between the current temperature value and the target temperature value.
  • the power credit value of the power credit pool 830 is updated based on a change in the temperature-based power available credit and the power-based power available credit.
  • the power control unit 1120 considers to increase the power quota value of the power credit pool 830 according to one of temperature or power, and according to the other of the temperature or power, it is considered that the power quota of the power credit pool 830 is to be reduced.
  • the value is implemented to reduce the power credit value without implementing an increase in the power credit value to ensure the security of the solid state storage device.
  • Embodiments of the present application control the temperature and power of the solid state storage device, manage the power consumption of the solid state storage device more reasonably, and improve the reliability and life of the solid state storage device.

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Abstract

提供了固态存储设备及其温度、功耗控制方法。固态存储设备的控制方法，包括如下步骤：响应于存在访问NVM芯片(105)的操作，从功率额度池(330)申请功率额度；根据申请到的功率额度，执行访问NVM芯片的操作；响应于访问NVM芯片(105)的操作的执行完成，向功率额度池(330)归还功率额度。

Description

固态存储设备及其温度、功耗控制方法 技术领域
本申请涉及固态存储技术领域，具体涉及一种固态存储设备及其控制方法。
背景技术
图1是现有技术的固态存储设备的框图。固态存储设备102同主机相耦合，用于为主机提供存储能力。主机同固态存储设备102之间可通过多种方式相耦合，耦合方式包括但不限于通过例如SATA(Serial Advanced Technology Attachment，串行高级技术附件)、SCSI(Small Computer System Interface，小型计算机系统接口)、SAS(Serial Attached SCSI，串行连接SCSI)、IDE(Integrated Drive Electronics，集成驱动器电子)、USB(Universal Serial Bus，通用串行总线)、PCIE(Peripheral Component Interconnect Express,PCIe，高速外围组件互联)、NVMe(NVM Express，高速非易失存储)、以太网、光纤通道、无线通信网络等连接主机与固态存储设备102。主机可以是能够通过上述方式同存储设备相通信的信息处理设备，例如，个人计算机、平板电脑、服务器、便携式计算机、网络交换机、路由器、蜂窝电话、个人数字助理等。存储设备102包括接口103、控制部件104、一个或多个NVM芯片105以及DRAM(Dynamic Random Access Memory，动态随机访问存储器)110。
NAND闪存、相变存储器、FeRAM(Ferroelectric RAM，铁电存储器)、MRAM(Magnetic Random Access Memory，磁阻存储器)、RRAM(Resistive Random Access Memory，阻变存储器)等是常见的NVM。
接口103可适配于通过例如SATA、IDE、USB、PCIE、NVMe、SAS、以太网、光纤通道等方式与主机交换数据。
控制部件104用于控制在接口103、NVM芯片105以及固件存储器110之间的数据传输，还用于存储管理、主机逻辑地址到闪存物理地址映射、擦除均衡、坏块管理等。控制部件104可通过软件、硬件、固件或其组合的多种方式实现，例如，控制部件104可以是FPGA(Field-programmable gate array，现场可编程门阵列)、ASIC(Application Specific Integrated Circuit，应用专用集成电路)或者其组合的形式；控制部件104也可以包括处理器或者控制器，在处理器或控制器中执行软件来操纵控制部件104的硬件来处理IO(Input/Output)命令；控制部件104还可以耦合到DRAM110，并可访问DRAM 110的数据；在DRAM可存储FTL表和/或缓存的IO命令的数据。
控制部件104包括闪存接口控制器(或称为闪存通道控制器)，闪存接口控制器耦合到NVM芯片105，并以遵循NVM芯片105的接口协议的方式向NVM芯片105发出命令，以操作NVM芯片105，并接收从NVM芯片105输出的命令执行结果。NVM芯片105的接口协议包括“Toggle”、“ONFI”等公知的接口协议或标准。
存储器目标(Target)是NAND闪存封装内的共享芯片使能信号(CE，Chip Enable)的一个或多个逻辑单元(Logic Unit)。每个逻辑单元具有逻辑单元号(LUN，Logic Unit Number)。NAND闪存封装内可包括一个或多个管芯(Die)。 典型地，逻辑单元对应于单一的管芯。逻辑单元可包括多个平面(Plane)。逻辑单元内的多个平面可以并行存取，而NAND闪存芯片内的多个逻辑单元可以彼此独立地执行命令和报告状态。
在固态存储设备中，访问NVM芯片105的不同操作所消耗的能量不同对应不同的功耗。NVMe协议中定义了固态存储设备的功耗状态(参看表1)。表1中定义了多种功耗状态，以及每种功耗状态具有不同的最大功耗。固态存储设备的工作温度也需要被有效的控制。温度过高或过低都会影响电子器件的工作。温度受固态存储设备的功耗、环境散热能力等因素影响。固态存储设备的温度温度过高或者过低都会影响电子器件的工作。
表1
功耗状态 最大功耗 进入延迟 退出延迟
0 25W 5μs 5μs
1 18W 5μs 7μs
2 18W 5μs 8μs
3 15W 20μs 15μs
4 10W 20μs 30μs
5 8W 20μs 50μs
6 5W 20μs 5000μs
发明内容
符合NVMe协议的固态存储设备需要实现多种功耗状态。为实现NVMe协议要求的功耗状态，需要将固态存储设备的温度和功耗控制在指定的值或范围内。本申请的目的在于提供一种固态存储设备及其控制方法。用于对固态存储设备的功率和温度进行控制。
根据本申请的第一方面，提供根据本申请第一方面的第一固态存储设备的控制方法，包括如下步骤：步骤S1、测量出当前温度值；步骤S2、依据当前温度值与目标温度值的差，更新功率额度池的值；步骤S3、响应于存在访问NVM芯片的操作，从功率额度池申请功率额度；步骤S4、根据申请到的功率额度，执行访问NVM芯片的操作；步骤S5、响应于访问NVM芯片的操作的执行完成，归还功率额度。
根据本申请的第一方面的第一固态存储设备的控制方法，提供了根据本申请第一方面的第二固态存储设备的控制方法，若当前温度值大于目标温度值，则降低额定功率池的值；若当前温度值小于目标温度值，则提高功率额度池的值。
根据本申请的第一方面的第二固态存储设备的控制方法，提供了根据本申请第一方面的第三固态存储设备的控制方法，功率额度池的值的降低或者提高的量，正比于当前温度值与目标温度值的差。
根据本申请的第一方面的第二固态存储设备的控制方法，提供了根据本申请第一方面的第四固态存储设备的控制方法，依据当前温度值与目标温度值的差，获取功率额度池的值的降低或者提高的量。
根据本申请的第一方面的第一至第四固态存储设备的控制方法之一，提供了根据本申请第一方面的第五固态存储设备的控制方法，还包括：测量当前功率值，若当前 功率值大于目标功率值，则降低额定功率池的值；若当前功率值小于目标功率值，则提高功率额度池的值。
根据本申请的第一方面的第一至第五固态存储设备的控制方法之一，提供了根据本申请第一方面的第六固态存储设备的控制方法，所述从功率额度池申请功率额度还包括：响应于功率额度申请成功，执行步骤S4。
根据本申请的第一方面的第一至第六固态存储设备的控制方法之一，提供了根据本申请第一方面的第七固态存储设备的控制方法，周期性地执行步骤S2。
根据本申请的第一方面的第一至第七固态存储设备的控制方法之一，提供了根据本申请第一方面的第八固态存储设备的控制方法，依据当前温度值与目标温度值的差，更新功率额度池的值包括：判断固态存储设备当前是否为功率无限制模式；若是，则将功率额度池的功率可使用额度设定为最大值，并更新功率额度池的值。
根据本申请的第一方面的第一至第八固态存储设备的控制方法之一，提供了根据本申请第一方面的第九固态存储设备的控制方法，若固态存储设备当前非处于功率无限制模式；则判断是否到了获取温度值的周期；若是，读取当前温度值，并依据当前温度值与目标温度值的差，更新功率额度池的功率可使用额度，并更新功率额度池的值。
根据本申请的第一方面的第一至第九固态存储设备的控制方法之一，提供了根据本申请第一方面的第十固态存储设备的控制方法，响应于出现突发的访问NVM芯片的操作，调低目标功率值。
根据本申请的第一方面的第十固态存储设备的控制方法，提供了根据本申请第一方面的第十一固态存储设备的控制方法，出现突发的访问NVM芯片的操作包括，在单位时间内存在超过第一阈值的读操作、写操作或擦除操作，或者三种操作的总量超过第二阈值。
根据本申请的第一方面的第十固态存储设备的控制方法，提供了根据本申请第一方面的第十二固态存储设备的控制方法，突发的访问NVM芯片的操作指在单位时间内访问NVM芯片的操作的增量超过第三阈值。
根据本申请的第一方面的第十至第十二固态存储设备的控制方法之一，提供了根据本申请第一方面的第十三固态存储设备的控制方法，固态存储设备包括多个命令队列，一个命令队列中的访问NVM芯片的操作访问与该命令队列对应的逻辑单元。
根据本申请的第一方面的第十三固态存储设备的控制方法，提供了根据本申请第一方面的第十四固态存储设备的控制方法，若功率额度池的值不够分配给多个访问NVM芯片的操作，将额度值轮流分配给不同命令队列中的访问NVM芯片的操作。
根据本申请的第一方面的第一至第十四固态存储设备的控制方法之一，提供了根据本申请第一方面的第十五固态存储设备的控制方法，执行读操作、编程操作或擦除操作所需的额度值不同。
本申请的固态存储设备的控制方法，使得固态存储设备的温度和功率得到控制，对固态存储设备的功耗管理更合理，延长了固态存储设备的使用次数和使用寿命。
根据本申请的第二方面，提供了根据本申请的第二方面的第一固态存储设备的控制方法，包括如下步骤：测量当前功率值，依据当前功率值与目标功率值的差，更新功率额度池的功率可使用额度；测量出当前温度值；依据当前温度值与目标温度值的差，计算功率额度池的第二功率可使用额度；若第二功率可使用额度小于功率额度池的功率可使用额度，用第二功率可使用额度更新功率额度池的功率可使用额度。
根据本申请的第二方面的第一固态存储设备的控制方法，提供了根据本申请第二方面的第二固态存储设备的控制方法，响应于存在访问NVM芯片的操作，从功率额度池申请功率额度；根据申请到的功率额度，执行访问NVM芯片的操作；响应于访问NVM芯片的操作的执行完成，归还功率额度。
根据本申请的第二方面的第一至第二固态存储设备的控制方法之一，提供了根据本申请第二方面的第三固态存储设备的控制方法，响应于出现突发的访问NVM芯片 的操作，调低目标功率值。
根据本申请的第二方面的第三固态存储设备的控制方法，提供了根据本申请第二方面的第四固态存储设备的控制方法，出现突发的访问NVM芯片的操作包括，在单位时间内存在超过第一阈值的读操作、写操作或擦除操作，或者三种操作的总量超过第二阈值。
根据本申请的第二方面的第三固态存储设备的控制方法，提供了根据本申请第二方面的第五固态存储设备的控制方法，突发的访问NVM芯片的操作指在单位时间内访问NVM芯片的操作的增量超过第三阈值。
根据本申请的第二方面的第三至第五固态存储设备的控制方法之一，提供了根据本申请第二方面的第六固态存储设备的控制方法，固态存储设备包括多个命令队列，一个命令队列中的访问NVM芯片的操作访问与该命令队列对应的逻辑单元。
根据本申请的第二方面的第六固态存储设备的控制方法，提供了根据本申请第二方面的第七固态存储设备的控制方法，若功率额度池的值不够分配给多个访问NVM芯片的操作，将额度值轮流分配给不同命令队列中的访问NVM芯片的操作。
根据本申请的第二方面的第一至第七固态存储设备的控制方法之一，提供了根据本申请第二方面的第八固态存储设备的控制方法，访问NVM芯片的操作包括读操作、编程操作或擦除操作。
根据本申请的第二方面的第八固态存储设备的控制方法，提供了根据本申请第二方面的第九固态存储设备的控制方法，执行读操作、编程操作或擦除操作所需的额度值不同。
本申请的固态存储设备的控制方法，使得固态存储设备的温度和功率得到控制，对固态存储设备的功耗管理更合理，延长了固态存储设备的使用次数和使用寿命。
根据本申请的第三方面，提供了根据本申请第三方面的第一固态存储设备，包括：NVM芯片、控制管理系统、功率传感器和温度传感器，NVM芯片和控制管理系统耦合，功率传感器与温度传感器均和控制管理系统相相耦合；功率传感器用于测量固态存储设备的当前功率值；温度传感器用于测量固态存储设备的当前温度值；控制管理系统用于通过功率传感器测量的固态存储设备的当前功率值，通过温度传感器测量的固态存储设备的当前温度值，调度访问NVM芯片的操作。
根据本申请的第三方面的第一固态存储设备，提供了根据本申请第三方面的第二固态存储设备，控制管理系统包括：功率控制单元、功率额度池和功率额度管理器，功率额度池分别和功率额度管理器、功率控制单元相耦合，功率额度管理器和NVM芯片相耦合，功率控制单元耦合到功率传感器以及温度传感器，其中，功率控制单元用于根据当前温度值及目标温度值，在满足目标功率值的同时，将当前温度值控制在目标温度值以下；根据当前功率值及目标功率值，设置功率额度池的值；功率额度管理器用于向功率额度池申请额度，允许执行访问NVM芯片的操作，并在操作执行完成后，向功率额度池归还额度。
根据本申请的第三方面的第二固态存储设备，提供了根据本申请第三方面的第三固态存储设备，功率额度管理器向功率额度池申请额度失败时，暂停访问NVM芯片的操作，直到向功率额度池申请额度成功。
根据本申请的第三方面的第一或第二固态存储设备，提供了根据本申请第三方面的第四固态存储设备，功率控制单元还用于识别突发的访问NVM芯片的操作，并调低目标功率值。
本申请的固态存储设备，使得固态存储设备的温度和功率得到控制，对固态存储设备的功耗管理更合理，延长了固态存储设备的使用次数和使用寿命。
根据本申请的第四方面，提供根据本申请第四方面的第一固态存储设备的功率控制方法，包括如下步骤：步骤S1、响应于存在访问NVM芯片的操作，从功率额度池申请功率额度；步骤S2、根据申请到的功率额度，执行访问NVM芯片的操作；步骤S3、响应于访问NVM芯片的操作的执行完成，向功率额度池归还功率额度。
根据本申请的第四方面的第一固态存储设备的功率控制方法，提供了根据本申请第四方面的第二固态存储设备的功率控制方法，还包括：步骤R1、获取固态存储设备的当前功率值；步骤R2、依据当前功率值与目标功率值的差，更新功率额度池的值。
根据本申请的第四方面的第一至第二固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第三固态存储设备的功率控制方法，所述从功率额度池申请功率额度还包括：响应于功率额度申请成功，执行步骤S2。
根据本申请的第四方面的第一至第二固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第四固态存储设备的功率控制方法，所述从功率额度池申请功率额度还包括，响应于功率额度申请失败，暂定对所述访问NVM芯片的操作的处理，直到功率额度申请成功。
根据本申请的第四方面的第一至第三固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第五固态存储设备的功率控制方法，周期性地执行步骤R2。
根据本申请的第四方面的第一至第三固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第六固态存储设备的功率控制方法，步骤R2中，依据当前功率值与目标功率值的差，更新功率额度池的值包括：判断固态存储设备当前是否为功率无限制模式；若是，则将功率额度池的功率可使用额度设定为最大值，并更新功率额度池的值。
根据本申请的第四方面的第一至第六固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第七固态存储设备的功率控制方法，依据当前功率值与目标功率值的差，更新功率额度池的值包括：若当前功率值大于目标功率值，则降低功率额度池的值；若当前功率值小于目标功率值，则提高功率额度池的值。
根据本申请的第四方面的第七固态存储设备的功率控制方法，提供了根据本申请的第四方面的第八固态存储设备的功率控制方法，功率额度池的值的降低或者提高的量，正比于当前功率值与目标功率值的差。
根据本申请的第四方面的第一至第八固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第九固态存储设备的功率控制方法，还包括：
响应于出现突发的访问NVM芯片的操作，调低目标功率值。
根据本申请的第四方面的第九固态存储设备的功率控制方法，提供了根据本申请的第四方面的第十固态存储设备的功率控制方法，出现突发的访问NVM芯片的操作包括：在单位时间内存在超过第一阈值的读操作、写操作或擦除操作，或者三种操作的总量超过第二阈值。
根据本申请的第四方面的第九固态存储设备的功率控制方法，提供了根据本申请的第四方面的第十一固态存储设备的功率控制方法，突发的访问NVM芯片的操作指在单位时间内访问NVM芯片的操作的增量超过第三阈值。
根据本申请的第四方面的第九至第十一固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第十二固态存储设备的功率控制方法，固态存储设备包括多个命令队列，一个命令队列中的访问NVM芯片的操作访问与该命令队列对应的逻辑单元。
根据本申请的第四方面的第十二固态存储设备的功率控制方法，提供了根据本申请的第四方面的第十三固态存储设备的功率控制方法，若功率额度池的值不够分配给多个访问NVM芯片的操作，将额度值轮流分配给不同命令队列中的访问NVM芯片的操作。
根据本申请的第四方面的第一至第十三固态存储设备的功率控制方法之一，提供了根据本申请的第四方面的第十四固态存储设备的功率控制方法，访问NVM芯片的操作包括读操作、编程操作或擦除操作。
根据本申请的第四方面的第十四固态存储设备的功率控制方法，提供了根据本申请的第四方面的第十五固态存储设备的功率控制方法，执行读操作、编程操作或擦除操作所需的额度值不同。
本申请的固态存储设备的功率控制方法，使得固态存储设备的功率得到控制，对固态存储设备的功耗管理更合理，延长了固态存储设备的使用次数和使用寿命。
根据本申请的第五方面，提供了根据本申请的第五方面的第一固态存储设备，包括：NVM芯片、功率管理系统和功率传感器，NVM芯片和功率管理系统耦合，功率传感器和功率管理系统相相耦合；功率传感器用于测量固态存储设备的当前功率值；功率管理系统用于通过功率传感器测量的固态存储设备的当前功率值，调度访问NVM芯片的操作。
根据本申请的第五方面的第一固态存储设备，提供了根据本申请的第五方面的第二固态存储设备，功率管理系统包括：功率控制单元、功率额度池和功率额度管理器，功率额度池分别和功率额度管理器、功率控制单元相耦合，功率额度管理器和NVM芯片相耦合，功率控制单元耦合到功率传感器，其中，功率控制单元用于根据当前功率值及目标功率值，设置功率额度池的值；功率额度管理器用于向功率额度池申请额度，允许执行访问NVM芯片的操作，并在操作执行完成后，向功率额度池归还额度。
根据本申请的第五方面的第二固态存储设备，提供了根据本申请的第五方面的第三固态存储设备，功率额度管理器向功率额度池申请额度失败时，功率额度池中的额度值用光时，暂停访问NVM芯片的操作，直到向功率额度池申请额度成功。
根据本申请的第五方面的第二或第三固态存储设备，提供了根据本申请的第五方面的第四固态存储设备，功率控制单元还用于识别突发的访问NVM芯片的操作，并调低目标功率值。
本申请的固态存储设备的功率控制方法，使得固态存储设备的功率得到控制，对固态存储设备的功耗管理更合理，延长了固态存储设备的使用次数和使用寿命。
根据本申请的第六方面，提供了根据本申请的第六方面的第一固态存储设备的功率控制装置，包括：功率额度申请模块，用于响应于存在访问NVM芯片的操作，从功率额度池申请功率额度；执行模块，用于根据申请到的功率额度，执行访问NVM芯片的操作；以及功率额度归还模块，用于响应于访问NVM芯片的操作的执行完成，向功率额度池归还功率额度。
根据本申请的第六方面的第一固态存储设备的功率控制装置，提供了根据本申请的第六方面的第二固态存储设备的功率控制装置，功率获取模块，用于获取固态存储设备的当前功率值；功率额度更新模块，用于依据当前功率值与目标功率值的差，更新功率额度池的值。
根据本申请的第六方面的第一或第二固态存储设备的功率控制装置，提供了根据本申请的第六方面的第三固态存储设备的功率控制装置，响应于功率额度申请模块申请功率额度成功，执行模块执行访问NVM芯片的操作。
根据本申请的第六方面的第一或第二固态存储设备的功率控制装置，提供了根据本申请的第六方面的第四固态存储设备的功率控制装置，响应于功率额度申请模块申请功率额度失败，执行模块暂停对所述访问NVM芯片的操作的处理，直到功率额度申请模块申请功率额度成功。
根据本申请的第六方面的第一至第三固固态存储设备的功率控制装置之一，提供了根据本申请的第六方面的第五固态存储设备的功率控制装置，功率额度更新模块周期性地更新功率额度池的值。
根据本申请的第六方面的第一至第三固固态存储设备的功率控制装置之一，提供了根据本申请的第六方面的第六固态存储设备的功率控制装置，功率额度更新模块依据当前功率值与目标功率值的差，更新功率额度池的值包括：判断固态存储设备当前是否为功率无限制模式；若是，则将功率额度池的功率可使用额度设定为最大值，并更新功率额度池的值。
根据本申请的第六方面的第一至第六固态存储设备的功率控制装置之一，提供了根据本申请的第六方面的第七固态存储设备的功率控制装置，功率额度更新模块依据 当前功率值与目标功率值的差，更新功率额度池的值包括：若当前功率值大于目标功率值，则降低额定功率池的值；若当前功率值小于目标功率值，则提高额定功率额度池的值。
根据本申请的第六方面的第七固态存储设备的功率控制装置，提供了根据本申请的第六方面的第八固态存储设备的功率控制装置，功率额度池的值的降低或者提高的量，正比于当前功率值与目标功率值的差。
根据本申请的第六方面的第一至第八固态存储设备的功率控制装置之一，提供了根据本申请的第六方面的第九固态存储设备的功率控制装置，功率额度更新模块响应于出现突发的访问NVM芯片的操作，调低目标功率值。
根据本申请的第六方面的第一至第九固态存储设备的功率控制装置之一，提供了根据本申请的第六方面的第十固态存储设备的功率控制装置，固态存储设备包括多个命令队列，一个命令队列中的访问NVM芯片的操作访问与该命令队列对应的逻辑单元。
根据本申请的第六方面的第十固态存储设备的功率控制装置，提供了根据本申请的第六方面的第十一固态存储设备的功率控制装置，若功率额度池的值不够分配给多个访问NVM芯片的操作，将额度值轮流分配给不同命令队列中的访问NVM芯片的操作。
本申请的固态存储设备的功率控制装置，使得固态存储设备的功率得到控制，对固态存储设备的功耗管理更合理，延长了固态存储设备的使用次数和使用寿命。
根据本申请的第七方面，提供一种包括指令的程序，当被载入存储设备并在存储设备上执行时，所述程序使所述存储设备执行根据本申请的第一方面、第二方面或第四方面的方法。
根据本申请的第八方面，提供一种计算机可读存储介质，其上存储了包括指令的程序，当被载入存储设备并在存储设备上执行时，所述程序使所述存储设备执行根据本申请的第一方面、第二方面或第四方面的方法。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1是现有技术的固态存储设备的框图；
图2是根据本申请实施例的功率管理系统的框图；
图3是根据本申请又一实施例的功率管理系统的框图；
图4是根据本申请又一实施例的功率控制过程的流程图；
图5是根据本申请又一实施例的功率控制过程的流程图；
图6是根据本申请又一实施例的功率管理系统的框图；
图7是根据本申请又一实施例的功率管理系统的框图；
图8是根据本申请另一实施例的功率管理系统的框图；
图9是根据本申请另一实施例的温度-功率控制过程的流程图；
图10根据本申请又一实施例的温度-功率控制过程的流程图；
图11是根据本申请另一实施例的功率管理系统的框图；以及
图12是根据本申请依然又一实施例的温度-功率控制过程的流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
固态存储设备的功耗主要来源于对NVM芯片进行读操作、编程操作与擦除操作。每种操作消耗的能量不同。例如，在一种配置(时钟频率、物理页大小等)下，单一NVM读操作的功耗约90mW(毫瓦)、单一编程操作的功耗约150mW，单一擦除操作的功耗约180mW。固态存储设备中可包括多个NVM芯片，而NVM芯片的逻辑单元(LUN)可以并行访问，因而在固态存储设备的多个逻辑单元上可并行执行读操作、编程操作或擦除操作。在多个逻辑单元上并行执行的操作数量，也直接影响了固态存储设备的功耗。
在根据本申请的实施例中，通过控制发出的NVM芯片的读操作、编程操作、擦除操作等操作的数量，来实现所需要的功耗状态。
实施例1
图2是根据本申请实施例1的功率管理系统的框图。固态存储设备在不同的功率状态下具有不同的目标功率值，如25瓦。如图2所示，固态存储设备的功率管理系统200包括功率管理器210与功率传感器230。功率管理器210耦合到NVM芯片105(也参看图1)，用于依据功耗控制目标控制是否将命令队列240中的访问NVM芯片的IO操作发送给NVM芯片105。功率传感器230检测或采集固态存储设备的功率，例如通过检测固态存储设备电源的电流和/或电压来得到功率值。功率管理系统200还维护目标功率220。目标功率220指示当前功率状态下固态存储设备的功率上限。在一个例子中，功率管理器210从功率传感器230获得固态存储设备的当前功率，与目标功率220指示的值相比较。若当前功率小于目标功率，功率管理器210允许将命令队列240中的IO操作发送给NVM芯片105；若当前功率不小于目标功率，功率管理器210实施功率控制，并禁止将命令队列240中的IO操作发送给NVM芯片105。功率管理器210可实现于固态存储设备的控制部件104(也参看图1)，或由控制部件104中的CPU通过执行程序来实现。
图3是根据本申请又一实施例的功率管理系统的框图。如图3所示，功率管理系统300包括：功率控制单元320、功率额度池330和功率额度管理器310。功率额度管理器310依据功率额度池330提供的功率额度，控制是否将命令队列240中的访问NVM芯片IO操作发送给NVM芯片105。响应于命令队列240中有待处理的访问NVM芯片105(也参看图1)的操作，功率额度管理器310从功率额度池330申请功率额度。不同类型的IO操作所需的功率额度值不同。
功率控制单元320耦合到功率传感器230，比较功率传感器230提供的当前功率与目标功率220，来更新功率额度池330的功率额度值。例如，在当前功率小于目标功率220时，向功率额度池330提供更多的功率额度，而在当前功率大于目标功率时，削减功率额度池330的值。功率额度池330的功率额度值决定了固态存储设备中可并发运行的IO操作的数量。在命令队列240中有要发送给NVM芯片105的IO操作时，功率额度管理器310向功率额度池330申请功率额度，IO操作完成后将申请的功率额度归还功率额度池330。
在一个例子中，功率额度池330的初始额度值为100，每条NVM芯片读操作需要的额度值为3，每条NVM芯片编程操作需要的额度值为14，每条NVM芯片擦除操作需要的额度值为15。在命令队列240中有读操作要处理时，功率额度管理器310向功率额度池330申请额度值3。响应于功率额度管理器310申请了额度值3，功率额度池330的额度值从100变为97。响应于该读命令执行完成，功率额度管理器310 将值为3的额度归还给功率额度池330。以功率额度池330的初始值为100为例，固态存储设备可以并行处理33条读操作，7条编程操作或6条擦除操作。
可选地，当功率额度池330的功率额度用光时，功率额度管理器310将暂停处理命令队列240中的IO操作。
例如，功率额度池330的功率额度值为7，而命令队列240中有编程操作需要处理，需要的额度值为14。由于功率额度池330的剩余额度值小于14，表明剩余额度值不够支持编程操作。功率额度管理器310无法得到对该编程操作的额度值，因而暂定对命令队列240的编程操作的处理，直到功率额度池330中出现了足够分配给编程操作的功率额度值。可选地，功率额度管理器310调度命令队列240中的读操作。读操作需要的额度值为3，小于功率额度池330的剩余额度值7，因而功率额度管理器310能够从功率额度池330获得足够用于读操作的功率额度，并将读操作发送给NVM芯片105。
可选地，在固态存储设备的功率控制的过程中，周期性地从功率传感器230获取当前功率，与目标功率220进行比较，并对功率额度池330的功率额度值进行更新。
图4是根据本申请又一实施例的功率控制过程的流程图。如图4所示，对固态存储设备的功率进行控制的过程包括：功率控制单元320从功率传感器230获得当前功率值，以及获得目标功率220。功率控制单元320依据当前功率值与目标功率值的差，更新功率额度池330的功率额度值。响应于访问NVM芯片的IO操作，功率额度管理器310向功率额度池330申请功率额度。对于不同类型的IO操作，需要的功率额度可能不同。一般地，若功率额度池330的功率额度值不小于IO操作所需的功率额度，则功率额度申请会成功，以及功率额度池330的功率额度值相应地减少被申请的额度值。若功率额度申请成功，功率额度管理器310允许将IO操作发送给NVM芯片105；若功率额度申请不成功，则暂时停止对该IO操作的处理，功率额度管理器310继续为该IO操作申请功率额度，直至功率额度申请成功。响应于访问NVM芯片的IO操作执行完成，向功率额度池330归还功率额度。响应于归还功率额度，功率额度池330的值增加被归还的额度值。
图5是根据本申请又一实施例的功率控制过程的流程图。如图5所示，对固态存储设备的功率进行控制的过程包括：功率控制单元320判断当前是否是功率无限制的功率状态，在功率无限制的功率状态下，则设置功率额度池330的功率可使用额度为最大值，并更新功率额度池330的功率额度值。主机可将固态存储设备设置为功率无限制的功率状态。在一个例子中，即使在功率无限制的功率状态下，功率控制单元320与功率额度管理器310依然工作。功率控制单元320依据功率额度池330的功率可使用额度，更新功率额度池330的值。例如，功率额度池330的功率可使用额度的最大值为210，当前的功率可使用额度为100，而由于部分功率额度值被申请来处理IO操作，当前功率额度值为50。那么响应于功率额度池330的可使用额度从当前值100被修改为最大值210，使当前功率额度值增加相同的幅度，即从50增加到160。
主机还可将固态存储设备设置为其他功率状态。对应于各功率状态，具有各自的目标功率220。可选地，目标功率220也由主机指定。
若不是在功率无限制的功率状态下，则周期性地从功率传感器230获取当前功率值，并周期性地更新功率额度池330的功率额度值。例如，响应于定时器事件或者中断，或者对定时器的轮询，在获取功率的周期开始或结束时，功率控制单元320从功率传感器230读取当前功率值，而在控制周期的开始或结束时依据当前功率值与目标功率220的差计算功率额度池320的功率可使用额度，更新功率额度池330的功率额度值。获取功率的周期与控制周期可以相同或不同。降低获取功率的周期和/或控制周期，有助于提高功率控制的灵敏度或精度。
作为举例，在获取功率的周期内，不从功率传感器230获取当前功率值。因而在获取功率的周期内，若控制周期到时，功率控制单元320依据上一次从功率传感器230获取的功率值计算功率可使用额度。
作为举例，功率控制单元320在更新功率额度池330的额度值时，若当前功率值大于目标功率值，则降低功率额度池330的功率额度值；若当前功率值小于目标功率值，则提高功率额度池330的功率额度值。功率额度池330的功率额度值增加或减少的量，正比于当前功率值与目标功率值的差。
在另一个例子中，功率控制单元320依据当前功率值与目标功率值的差，计算功率可使用额度的增量。例如，若当前功率值小于目标功率值，功率可使用额度增加；而若当前功率值大于目标功率值，功率可使用额度降低。以及依据功率可使用额度的增量，相应更新功率额度池330的功率额度值。
作为举例，令功率可使用额度为P，P(t0)是上一时刻(t0时刻)的功率可使用额度，而P(t1)是当前要更新的功率可使用额度，令功率额度池的功率额度值为Pc，功率额度池的值是功率额度池所实际拥有的额度的指示，则：
P(t1)＝P(t0)-f(Pm-Pt)   公式(1)
Pm是从功率传感器230获取的当前功率值，Pt是目标功率220，f表示函数，例如f(Pm-Pt)＝(Pm-Pt)*k，k为系数。
在申请功率额度(例如10)时，只有Pc大等于要申请的功率额度(例如，10)，才能申请成功，而当Pc小于10时，申请失败。
功率额度池330维护功率额度池330的功率可使用额度P和功率额度池330的功率额度值Pc。
为了更新功率额度值Pc，在一个例子中，功率控制单元320从功率额度池330读出功率可使用额度P(t0)，通过公式(1)计算得到P(t1)；将功率可使用额度P(t1)提供给功率额度池330。功率额度池330基于接收的功率可使用额度P(t1)，用P(t1)与P(t0)的差作为功率额度值Pc的增量。
作为更新功率额度值Pc的另一个例子，功率控制单元320从功率额度池330读出功率可使用额度P(t0)，通过公式(1)计算得到P(t1)，将P(t1)与P(t0)的差值提供给功率额度池330。而功率额度池330基于所接收的差值，更新功率额度池330的功率额度值(Pc＝Pc+(P(t1)-P(t0)))。以及功率额度池330还通过差值得到并记录更新后的功率可使用额度(P(t1)。
在申请额度时，若功率额度池330的功率额度值Pc不小于所申请的功率额度值credit，则额度申请成功，并更新功率额度池的功率额度值(Pc＝Pc–credit)。在释放额度时，更新功率额度池的功率额度值(Pc＝Pc+credit)，其中，credit为一条IO操作所需的功率额度值。
在根据本申请的另一个实施例中，对访问NVM芯片105的读操作、编程操作和擦除操作进行统计，来识别IO操作的突发。IO操作的突发是指在单位时间内存在超过阈值的读操作、写操作或擦除操作，或者三种IO操作的总量/加权总量超过阈值，还可以指在单位时间内IO操作的增量超过阈值。可选地，为每种操作指定不同的阈值来识别IO操作的突发。
响应于识别出IO操作的突发，功率控制单元320降低目标功率220的值，从而抑制突发大量操作造成的固态存储设备功率大幅上升。
图6是根据本申请又一实施例的功率管理系统的框图。如图6所示的功率管理系统600同图3中示出的功率管理系统300相似，区别在于功率额度管理器610还对IO操作进行统计，并向功率控制单元620提供对读操作、编程操作和/或擦除操作的统计结果。基于对IO操作的统计结果，功率控制单元620识别IO操作的突发，并响应于IO操作的突发，修改(降低)目标功率220。
根据本申请的依然又一个实施例，利用功率管理系统控制固态存储设备的温度，避免固态存储设备在过高的温度下工作。温度是功耗的副产品，因而通过管理固态存储设备的功耗来控制固态存储设备的发热。
图7是根据本申请又一实施例的功率管理系统的框图，功率管理系统700包括功率管理器710与温度传感器730。功率管理器710耦合到NVM芯片105(也参看图1)， 用于依据温度控制目标控制是否将命令队列240中的访问NVM芯片的IO操作发送给NVM芯片105。温度传感器730检测或采集固态存储设备的温度，例如通过布置固态存储设备的一个或多个位置的温度传感器来获取温度值。功率管理系统700还维护目标温度720。目标温度720指示固态存储设备的工作温度上限。
在一个例子中，功率管理器710从温度传感器730获得固态存储设备的当前温度，与目标温度720指示的值相比较。若当前温度小于目标温度720，功率管理器710允许将命令队列240中的IO操作发送给NVM芯片105；若当前温度不小于目标温度720，功率管理器710实施功率控制，并禁止将命令队列240中的IO操作发送给NVM芯片105。
图8是根据本申请另一实施例的功率管理系统的框图。如图8所示，功率管理系统800包括：功率控制单元820、功率额度池830和功率额度管理器810。功率额度管理器810依据功率额度池830提供的功率额度，控制是否将命令队列240中的访问NVM芯片的IO操作发送给NVM芯片105。响应于命令队列240中有待处理的访问NVM芯片105(也参看图1)的操作，功率额度管理器810从功率额度池830申请功率额度。
功率控制单元820耦合到温度传感器840，比较温度传感器840提供的当前温度与目标温度842，来更新功率额度池830的功率额度值。例如，在当前温度小于目标温度842时，向功率额度池830提供更多的功率额度，而在当前温度大于目标温度时，削减功率额度池830的值。在命令队列240中有要发送给NVM芯片105的IO操作时，功率额度管理器810向功率额度池830申请功率额度，IO操作完成后将申请的功率额度归还功率额度池830。
当功率额度池830的功率额度用光时，功率额度管理器810将暂停处理命令队列240中的IO操作。
进一步地，功率控制单元820还耦合到功率传感器850，比较功率传感器850提供的当前功率与目标功率852，来更新功率额度池830的功率额度值。例如，在当前功率小于目标功率852时，向功率额度池830提供更多的功率额度，而在当前功率大于目标功率852时，削减功率额度池830的值。
可选地，在固态存储设备的功率控制的过程中，功率控制单元820周期性地从功率传感器850获取当前功率，与目标功率852进行比较，并对功率额度池830的功率额度值进行更新。
依然进一步地，若功率控制单元820依据温度或功率之一，认为要向功率额度池830增加功率额度值，而依据温度或功率的另一者，认为要削减功率额度池830的功率额度值，则实施对功率额度值的削减，而不实施对功率额度值的增加，以保障固态存储设备的安全性。
可选地，主机可向固态存储设备设置不同的目标温度值，以使固态存储设备适应不同的工作环境，例如散热能力较强的主机或散热能力一般的主机。
图9是根据本申请另一实施例的温度-功率控制过程的流程图。如图9所示，对固态存储设备的温度和功率进行控制的过程包括：功率控制单元820从温度传感器840获得当前温度值，以及获得目标温度842。功率控制单元820依据温度传感器840提供的当前温度值与目标温度值的差，更新功率额度池830的功率额度值。响应于命令队列240中存在访问NVM芯片的IO操作，功率额度管理器810向功率额度池830申请功率额度。若功率额度申请成功，功率额度管理器810允许将IO操作发送给NVM芯片105；若功率额度申请不成功，则暂时停止对该IO操作的处理，功率额度管理器810继续为该IO操作申请功率额度，直至功率额度申请成功。响应于访问NVM芯片的操作执行完成，向功率额度池830归还功率额度。响应于归还功率额度，功率额度池830的值增加被归还的额度值。
可选地，依据当前温度值与目标温度值的差，更新功率额度池830的值为：若当前温度值大于目标温度值，降低额定功率池830的值；若当前温度值小于目标温度值，则提高功率额度池830的值。例如，功率额度池830的值降低或者提高的量正比于当前 温度值与目标温度值的差。在另一例子中，依据当前温度值与目标温度值的差，获取功率额度池830的值的降低或者提高的量。例如，将当前温度值与目标温度值的差对时间做积分，来获得功率额度池830的增量。使得若固态存储设备的温度长期低于目标温度值，可对功率额度值830的值有较大的增加。
可选地，在固态存储设备的功率控制的过程中，周期性地对功率额度池22的功率额度值进行更新。
图10根据本申请又一实施例的温度-功率控制过程的流程图。如图10所示，对固态存储设备的温度和功率进行控制的过程包括：功率控制单元820判断当前是否是功率无限制的功率状态。在功率无限制的功率状态下，则设置功率额度池830的功率可使用额度为最大值，并更新功率额度池830的功率额度值。主机可将固态存储设备设置为功率无限制的功率状态，主机还可将固态存储设备设置为其他功率状态，对应于各功率状态，具有各自的目标温度842和/或目标功率852。可选地，目标功率852和/或目标温度842也由主机指定。
若不是在功率无限制的功率状态，则周期性地从温度传感器840获取当前温度值，并基于温度的功率可使用额度，更新功率额度池830的功率额度值。例如，响应于定时器事件或者中断，或者对定时器的轮询，在获取温度的周期开始或结束时，功率控制单元820从温度传感器840读取当前温度值，依据当前温度值与目标温度842的差，计算基于温度的功率可使用额度，并更新功率额度池830的功率额度值。
进一步地，在基于温度的功率可使用额度小于基于功率的功率可使用额度时，才更新功率额度池830的功率额度值，以避免固态存储设备的功率超过目标功率。其中，依据当前功率值与目标功率852的差，计算基于功率的功率可使用额度。可选地，在控制周期的开始或结束，依据基于温度的功率可使用额度与基于功率的功率可使用额度二者中较小的一个来更新功率额度池830的功率额度值。若二者中较小的一个增高，则增加功率额度池830的功率额度值；若二者中较小的一个降低，则减少功率额度池830的功率额度值。
图11是根据本申请另一实施例的功率管理系统的框图，如图11所示的功率管理系统1100同图8中示出的功率管理系统800相似，区别在于功率额度管理器1110对多个命令队列，即命令队列240、命令队列250和命令队列260进行控制，控制是否将命令队列240、命令队列250和命令队列260中的访问NVM芯片的IO操作发送给NVM芯片105。功率额度管理器1110还对IO操作进行统计，并向功率控制单元1120提供读操作、编程操作和/或擦除操作的统计结果。基于IO操作的统计结果，功率控制单元1120识别IO操作的突发，并响应于IO操作的突发，修改(降低)目标温度842和目标功率852。
进一步地，功率额度管理器1110选择多个命令队列之一并处理选中的命令队列的IO操作，以避免某一命令队列中的IO操作等待处理的时间过长。例如，在功率额度池830的功率额度值不足以支持同时处理多个IO操作时，功率额度管理器1110轮流为多个命令队列中的IO操作申请功率额度。
图12是根据本申请依然又一实施例的温度-功率控制过程的流程图。如图12所示(也参看图11)，对固态存储设备的温度和功率进行控制的过程包括：功率控制单元1120判断当前是否是功率无限制的功率状态，在功率无限制的功率状态下，则设置功率额度池830的功率可使用额度为最大值，并更新功率额度池830的功率额度值。主机可将固态存储设备设置为功率无限制的功率状态。在一个例子中，即使在功率无限制的功率状态下，功率控制单元1120与功率额度管理器1110依然工作。功率控制单元1120依据功率额度池830的功率可使用额度，更新功率额度池830的功率额度值。
若不是在功率无限制的功率状态下，则功率控制单元1120周期性地从温度传感器840获取当前温度值，并周期性地更新功率额度池830的功率额度值。例如，响应于定时器事件或者中断，或者基于对定时器的轮询，在获取温度的周期开始或结束时，功率控制单元1120从温度传感器840读取当前温度值，而在控制周期的开始或结束时依据 当前温度值与目标温度842，来更新功率额度池830的功率额度值。
进一步地，在控制周期的开始或结束时，功率控制单元1120更新对在命令队列240、命令队列250和/或命令队列260中访问NVM芯片105的读操作、编程操作和/或擦除操作的统计，来识别是否出现IO操作的突发。响应于识别到IO操作的突发，控制单元1120调低目标功率值。而在没有出现IO操作的突发情况下，略过对目标功率值的调整。
功率控制单元1120根据从功率传感器850获得的当前功率值与目标功率值，和/或从温度传感器840获得的当前温度值与目标温度值，来更新功率额度池830的功率额度值。例如，基于当前功率值与目标功率值的差计算基于功率的功率可使用额度，以及基于当前温度值与目标温度值的差计算基于温度的功率可使用额度。并根据基于温度的功率可使用额度与基于功率的功率可使用额度二者中较小一个的变化，来更新功率额度池830的功率额度值。
在另一个例子中，若功率控制单元1120依据温度或功率之一，认为要增加功率额度池830的功率额度值，而依据温度或功率的另一者，认为要削减功率额度池830的功率额度值，则实施对功率额度值的削减，而不实施对功率额度值的增加，以保障固态存储设备的安全性。
本申请的实施例使得固态存储设备的温度和功率得到控制，对固态存储设备的功耗管理更合理，提升了固态存储设备的可靠性和寿命。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种固态存储设备的控制方法，其特征在于，包括如下步骤：
    响应于存在访问NVM芯片的操作，从功率额度池申请功率额度；
    根据申请到的功率额度，执行访问NVM芯片的操作；
    响应于访问NVM芯片的操作的执行完成，向功率额度池归还功率额度。
  2. 如权利要求1所述的固态存储设备的控制方法，其特征在于，还包括：
    测量出当前温度值；
    依据当前温度值与目标温度值的差，更新功率额度池的值。
  3. 如权利要求2所述的固态存储设备的控制方法，其特征在于，若当前温度值大于目标温度值，则降低额定功率池的值；若当前温度值小于目标温度值，则提高功率额度池的值。
  4. 如权利要求1-3任一项所述的固态存储设备的控制方法，其特征在于，依据当前温度值与目标温度值的差，更新功率额度池的值包括：
    判断固态存储设备当前是否为功率无限制模式；
    若是，则将功率额度池的功率可使用额度设定为最大值，并更新功率额度池的值。
  5. 根据权利要求1-4任一项所述的固态存储设备的控制方法，还包括：
    响应于从功率额度池申请功率额度失败，暂定对所述访问NVM芯片的操作的处理，直到功率额度申请成功。
  6. 一种固态存储设备的控制方法，其特征在于，包括如下步骤：
    测量当前功率值，依据当前功率值与目标功率值的差，更新功率额度池的功率可使用额度；
    测量出当前温度值；
    依据当前温度值与目标温度值的差，计算功率额度池的第二功率可使用额度；
    若第二功率可使用额度小于功率额度池的功率可使用额度，用第二功率可使用额度更新功率额度池的功率可使用额度。
  7. 根据权利要求6所述的固态存储设备的控制方法，其特征在于，还包 括：
    响应于存在访问NVM芯片的操作，从功率额度池申请功率额度；
    根据申请到的功率额度，执行访问NVM芯片的操作；
    响应于访问NVM芯片的操作的执行完成，归还功率额度。
  8. 如权利要求1-7任一项所述的固态存储设备的控制方法，其特征在于，响应于出现突发的访问NVM芯片的操作，调低目标功率值。
  9. 一种固态存储设备，其特征在于，包括：NVM芯片、控制管理器和温度传感器，NVM芯片和控制管理器耦合，温度传感器和控制管理系统相耦合；
    温度传感器用于测量固态存储设备的当前温度；
    控制管理器用于依据温度传感器测量的固态存储设备的当前温度与目标温度的差，调度访问NVM芯片的IO操作。
  10. 如权利要求9所述的固态存储设备，其特征在于，控制管理器包括：功率控制单元、功率额度池和功率额度管理器，功率额度池分别和功率额度管理器、功率控制单元相耦合，功率额度管理器和NVM芯片相耦合，功率控制单元耦合到温度传感器，其中，
    功率控制单元用于根据当前温度值及目标温度值，根据当前温度值及目标温度值，设置功率额度池的功率额度值；
    功率额度管理器用于向功率额度池申请功率额度，允许执行访问NVM芯片的操作，并在操作执行完成后，向功率额度池归还功率额度。
  11. 如权利要求9或10所述的固态存储设备，其特征在于，功率控制单元还用于识别突发的访问NVM芯片的IO操作，并调低目标功率值。
  12. 根据权利要求9-11之一所述的固态存储设备，还包括功率传感器，功率传感器用于测量固态存储设备的当前功率，并耦合到功率控制单元820；
    所述功率控制单元依据当前功率与目标功率的差计算基于功率的功率可使用额度，以及依据当前温度与目标温度的差计算基于温度的功率可使用额度，以及依据基于功率的功率可使用额度与基于温度的功率可使用额度中较小的一个更新功率额度池的功率额度值。
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