JP2016072499A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits deterioration in threshold voltage to achieve a favorable transistor operation.SOLUTION: A semiconductor device comprises a gate electrode 10, a first insulation film 210 (gate insulation film), an oxide semiconductor film 220, a second insulation film 230, a source electrode 13, source wiring 12, a drain electrode 15 and drain wiring 14. The first insulation film is arranged on the gate electrode. The oxide semiconductor film is arranged on the first insulation film. The second insulation film is arranged on the oxide semiconductor film. The source electrode is arranged in the second insulation film to be connected to the oxide semiconductor film. The source wiring is arranged on the second insulation film so as not to overlap a channel part to be connected to the source electrode. The drain electrode is arranged in the second insulation film to be connected to the oxide semiconductor film. The drain wiring is arranged on the second insulation film so as not to overlap the channel part to be connected to the drain electrode.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  A semiconductor device made of a compound semiconductor is expected to realize excellent characteristics not found in a semiconductor device made of silicon. In recent years, for example, indium (In), gallium (Ga), zinc (Zn) A thin film transistor (TFT) using an oxide semiconductor film such as InGaZnO, which is an oxide of) has been developed. It is known that this InGaZnO thin film transistor exhibits n-type conductivity, can be easily manufactured at a low temperature of 300 ° C. or less, has high carrier mobility, and low off-state current. Therefore, not only application to a liquid crystal panel but also use as a high-performance thin film transistor is expected in a silicon LSI.

In the manufacturing process of a silicon LSI, a process called hydrogen sintering or hydrogen sintering is widely used in order to improve the stability and reliability of silicon MOS transistor characteristics. Specifically, in the final process of the device formation process, heat treatment at 350 to 450 ° C. is performed in a forming gas (for example, N ₂ : H ₂ = 1: 1), and the dangling becomes an interface state at the silicon-insulating film interface. This is a step of terminating the ring bond with hydrogen. Therefore, in the case where an oxide semiconductor thin film transistor is included as a component of a silicon LSI, the number of carriers in the channel portion of the oxide semiconductor fluctuates due to the introduction of hydrogen in the hydrogen sintering process, thereby reducing the resistance of the film and the threshold of the thin film transistor. It may cause transistor malfunction such as voltage drop. In addition, in a structure having a film serving as a hydrogen barrier over the entire channel surface of an oxide semiconductor thin film transistor, hydrogen contained in the oxide semiconductor layer or the surrounding film does not diffuse outwardly in the manufacturing process. As a result, this also caused transistor operation failure such as lowering the resistance of the oxide semiconductor film and lowering the threshold value of the thin film transistor.

JP 2013-156363 A JP 2010-016163 A K. Nomura et al., “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, Vol. 432, Issue 7016, pp. 488-492, 2004. R. B. Fair and R. C. Sun “Threshold-voltage instability in MOSFET ’s due to channel hot-hole emission,” IEEE Transactions on Electron Devices, vol. ED-28, No. 1, pp. 83-94, 1981.

  An object of the present invention is to overcome the above-described problems and to provide a semiconductor device capable of satisfactory transistor operation as a silicon LSI component.

  The semiconductor device of the embodiment includes a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, a source wiring, a drain electrode, and a drain wiring. Yes. The first insulating film is disposed on the gate electrode. The oxide semiconductor film is disposed on the first insulating film. The second insulating film is disposed on the oxide semiconductor film. The source electrode is disposed in the second insulating film and connected to the oxide semiconductor film. The source wiring is disposed on the second insulating film so as not to overlap the channel portion, and is connected to the source electrode. The drain electrode is disposed in the second insulating film and connected to the oxide semiconductor film. The drain wiring is disposed on the second insulating film so as not to overlap the channel portion, and is connected to the drain electrode.

  A semiconductor device according to another embodiment includes a gate electrode, a first insulating film, a first oxide semiconductor film, a second insulating film, a source electrode, a source wiring, a drain electrode, and a drain wiring. And a second oxide semiconductor film. The first insulating film is disposed on the gate electrode. The first oxide semiconductor film is disposed on the first insulating film. The second insulating film is disposed on the oxide semiconductor film. The source electrode is disposed in the second insulating film and connected to the oxide semiconductor film. A source wiring is disposed on the second insulating film and connected to the source electrode. The drain electrode is disposed in the second insulating film and connected to the oxide semiconductor film. The drain wiring is disposed on the second insulating film and connected to the drain electrode. The second oxide semiconductor film is disposed on the channel portion independently of the source wiring and the drain wiring.

FIG. 1 is a cross-sectional view and a plan view showing the configuration of the semiconductor device according to the first embodiment. It is a figure which shows an example of distribution of the hydrogen concentration in the comparative example of 1st Embodiment. It is a figure which shows an example of distribution of the hydrogen concentration in 1st Embodiment. It is an example of the graph which shows distribution of the hydrogen concentration in 1st Embodiment and a comparative example. It is a flowchart figure which shows the principal part process of the manufacturing method of the semiconductor device in 1st Embodiment. It is process sectional drawing of the manufacturing method of the semiconductor device in 1st Embodiment. It is process sectional drawing of the manufacturing method of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the modification of the structure of the semiconductor device in 1st Embodiment. It is a figure which shows an example of the cross section of the multilayer wiring structure in 1st Embodiment. It is a figure which shows another example of the cross section of the multilayer wiring structure in 1st Embodiment. It is sectional drawing which shows the structure of the semiconductor device in 2nd Embodiment. It is a figure which shows an example of distribution of the hydrogen concentration in the reference example of 2nd Embodiment. It is a figure which shows an example of distribution of the hydrogen concentration in 2nd Embodiment. It is an example of the graph which shows distribution of the hydrogen concentration in 2nd Embodiment and a reference example.

  In the following embodiments, “provided on” means. In addition to the case of being provided in direct contact, the case where another layer or film is inserted between them is also included. Further, “provided facing” includes not only the case of being provided in direct contact with the top or bottom, but also the case of being provided with another layer or film interposed therebetween.

(First embodiment)
The first embodiment will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.

FIG. 1 is a cross-sectional view and a plan view showing the configuration of the semiconductor device according to the first embodiment. FIG. 1 illustrates an example of a bottom gate type (reverse stagger type) thin film transistor (TFT) using an oxide semiconductor film such as an InGaZnO film (IGZO film) as a semiconductor device. In FIG. 1, a gate electrode 10 is formed on the surface of an insulating film 200 formed on a substrate. The insulating film 200 is a film containing silicon oxide (SiO _x ) or silicon nitride (SiN _x ). As the gate electrode 10, for example, a metal film containing tungsten (W), molybdenum (Mo), copper (Cu), Ta (tantalum), or Al (aluminum) is used for the gate electrode 30. As the gate electrode 10, titanium nitride (TiN) or tantalum nitride (TaN) may be used. An aluminum alloy may be used for the gate electrode 10. The aluminum alloy has aluminum as a main component and hillock countermeasures are taken. Further, the side surface of the gate electrode 10 may be inclined with respect to the stacking direction. That is, the side surface of the gate electrode 10 may be tapered. By making the side surface of the gate electrode 10 tapered, the coverage with the insulating film 210 formed on the gate electrode 10 is enhanced. Leakage current can be suppressed by increasing the coverage. In the example of FIG. 1, the insulating film 200 is embedded so that the surface (upper surface) of the gate electrode 10 is formed at the same height as the upper surface of the insulating film 200. In the example of FIG. 1, for example, it is assumed that the gate electrode 10 is formed in the same layer as a predetermined wiring of a multilayer wiring layer. Therefore, other wiring layers, semiconductor elements, and the like may be formed on the substrate and the insulating film 200. However, the present invention is not limited to this configuration, and the gate electrode 10 may be formed on the insulating film 200.

A gate insulating film 210 (first insulating film) is disposed on the gate electrode 10. The gate insulating film 210 is formed on the gate electrode 10 and the insulating film 200. For example, the gate insulating film 210 is a film containing silicon oxide (SiO _x ), aluminum oxide (Al _x O _y ), silicon nitride (SiN _x ), or silicon oxynitride (SiO _x N _y ). As the gate insulating film 210, a stacked film of two or more films of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride may be used. An oxide semiconductor film 220 is disposed over the gate insulating film 210. An oxide semiconductor has a single crystal state, a polycrystalline state, an amorphous state, or the like. For example, the oxide semiconductor contains at least one of indium (In), gallium (Ga), and zinc (Zn). As the oxide semiconductor, a ternary metal oxide such as InGaZnO (hereinafter sometimes referred to as IGZO) is used. As the oxide semiconductor, for example, a binary metal oxide such as InGaO may be used. InGaWO or InGaSiO containing at least one of tungsten (W) and silicon (Si) may be used. The oxide semiconductor may be a quaternary metal oxide such as InSnGaZnO or InAlGaZnO containing at least one of tin (Sn) and aluminum (Al). In any case, the component ratio of a metal or a non-metal element as a main component is arbitrary.
Here, the InGaZn-based oxide is an oxide containing indium, gallium, and zinc as main components, and the component ratio of these metals is arbitrary. Moreover, you may contain metals other than indium, gallium, and zinc, or elements other than a metal. For example, when an InGaZnO film is used as the oxide semiconductor film 220, the resistance without an electric field is sufficiently high, and the off-state current can be sufficiently reduced. In addition, carrier mobility can be increased.

The oxide semiconductor layer 220 serves as a channel layer of the thin film transistor. In the case where the oxide semiconductor layer 220 is a layer containing IGZO, for example, the oxide semiconductor layer 220 has a composition ratio of IGZO, and targets IGZO4 that is In: Ga: Zn: O = 1: 1: 1: 4. It is formed by the sputtering method used.
An insulating film 230 (second insulating film) is provided over the oxide semiconductor film 220. The insulating film 230 is a film that protects the upper surface of the oxide semiconductor film 220. For example, the insulating film 230 is a film containing silicon oxide, Tetho (Ortho Ethyl Ortho Silicate: TEOS), aluminum oxide, or silicon nitride. As the insulating film 230, a stacked film of two or more films of silicon oxide, theos, aluminum oxide, and silicon nitride may be used.

  Further, the source electrode 13 is disposed in the insulating film 230 on one end side of the oxide semiconductor film 220 and is electrically connected to one end side of the oxide semiconductor film 220. The source electrode 13 is connected to the oxide semiconductor film 220 at a position at least partially overlapping one end of the gate electrode 10 in the gate length direction.

  Further, the drain electrode 15 is disposed in the insulating film 230 on the other end side of the oxide semiconductor film 220 and connected to the other end side of the oxide semiconductor film 220. The drain electrode 15 is electrically connected to the oxide semiconductor film 220 at a position at least partially overlapping with the other end of the gate electrode 10 in the gate length direction.

  The source electrode 13 and the drain electrode 15 are made of a metal material film. For example, a metal film containing molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al) is used. Molybdenum nitride (MoN), titanium nitride (TiN), or tantalum nitride (TaN) may be used. The source electrode 13 and the drain electrode 15 may be a laminated film of two or more films of these conductive materials. A film containing ITO (Indium Tin Oxide) or zinc oxide (ZnO) may be used. Or you may be comprised by the metal material film | membrane as a main material, and the barrier metal film which is not shown in figure which covers the side surface and bottom face of a metal material film | membrane.

  A source wiring 12 connected to the source electrode 13 is disposed on the insulating film 230. Similarly, the drain wiring 14 connected to the drain electrode 15 is disposed on the insulating film 230. The source wiring 12 is formed so as not to protrude to the channel region 16 side of the oxide semiconductor film 220. In other words, the source wiring 12 is disposed on the insulating film 230 so as not to overlap the channel portion (channel region 16) and is connected to the source electrode 13. Similarly, the drain wiring 14 is formed so as not to protrude to the channel region 16 side. In other words, the drain wiring 14 is disposed on the insulating film 230 so as not to overlap the channel portion (channel region 16), and is connected to the drain electrode 15. The source wiring 12 and the drain wiring 14 are made of a metal material film. For example, a metal film containing molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al) is used. Molybdenum nitride (MoN), titanium nitride (TiN), or tantalum nitride (TaN) may be used. The source wiring 12 and the drain wiring 14 may be a laminated film of two or more films of these conductive materials. A film containing ITO (Indium Tin Oxide) or zinc oxide (ZnO) may be used. Or you may be comprised by the metal material film | membrane as a main material, and the barrier metal film which is not shown in figure which covers the side surface and bottom face of a metal material film | membrane. Note that the source wiring 12 and the source electrode 13 may be formed of different materials or may be integrally formed of the same material. Similarly, the drain wiring 14 and the drain electrode 15 may be formed of different materials or may be integrally formed of the same material. Further, it is preferable that the source wiring 12 and the drain wiring 14 are formed of the same material at the same time without increasing the number of processing steps. Similarly, when the source electrode 13 and the drain electrode 15 are formed of the same material at the same time, it is preferable that the number of processing steps does not increase.

  Here, in the manufacturing process of the silicon LSI, in order to improve the stability of the characteristics of the silicon MOS transistor fabricated on the silicon substrate and to improve the reliability, the metal wiring forming process for the source wiring 12 and the drain wiring 14 is performed. Is completed, a hydrogen sintering process at 350 ° C. is performed in a forming gas (for example, N 2: H 2 = 1: 1). This is a step of terminating dangling bonds, which are interface states at the silicon-insulating film interface, with hydrogen. Such introduction of hydrogen can increase the hydrogen concentration in a partial region of the channel portion of the oxide semiconductor film 220, thereby reducing the resistance of the oxide semiconductor layer and causing a transistor operation failure of the thin film transistor.

FIG. 2 is a diagram illustrating an example of a hydrogen concentration distribution in the thin film transistor in the comparative example of the first embodiment. 2 (a) to 2 (d) show the state where hydrogen descends from the upper surface as monovalent hydrogen ions (H ⁺ ) and propagates by drift diffusion in the InGaZnO thin film transistor, as shown in TCAD (Technology Computer Aided Design). The result analyzed using is shown. Even in a situation where no bias voltage is applied to the electrode terminal, a potential distribution and an electric field distribution are generated due to the inherent work function of the constituent material and the dielectric constant. 2A to 2D, the comparative example shows a case where the metal wiring on the source (S) / drain (D) electrode has a fringe portion protruding to the channel region side. Yes. FIG. 2A shows the hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor in a transient state of hydrogen drift diffusion. FIG. 2B shows a hydrogen concentration distribution on the InGaZnO film plane of the InGaZnO thin film transistor in a transient state of hydrogen drift diffusion. FIG. 2C shows the hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor when the hydrogen drift diffusion reaches a steady state. FIG. 2D shows the distribution of hydrogen concentration on the InGaZnO film plane of the InGaZnO thin film transistor when hydrogen drift diffusion reaches a steady state. In any of FIGS. 2A to 2D, the hydrogen concentration in the channel region is not a uniform concentration but a concentration difference occurs, and the fringe portions of the source wiring and the drain wiring protruding to the channel region side are present. The hydrogen concentration in the InGaZnO film (oxide semiconductor film 220) is higher than the hydrogen concentration in the central portion of the channel region of the oxide semiconductor film 220 where the fringe portions of the source wiring and the drain wiring do not exist above. It is shown that.

FIG. 3 is a diagram illustrating an example of a hydrogen concentration distribution in the thin film transistor according to the first embodiment. Similar to FIG. 2, FIGS. 3 (a) to 3 (d) show the situation in which hydrogen descends from the top surface as monovalent hydrogen ions (H ⁺ ) and propagates by drift diffusion in the InGaZnO thin film transistor. It is the result analyzed using (Technology Computer Aided Design). 3A to 3D, in the first embodiment, as shown in FIG. 1, the metal wiring on the source (S) / drain (D) electrode protrudes to the channel region side. It is configured so that there is no. Other configurations are the same as those of the comparative example of FIG. FIG. 3A shows a hydrogen concentration distribution in a cross section of an InGaZnO thin film transistor in a transient state of hydrogen drift diffusion. FIG. 3B shows the hydrogen concentration distribution on the InGaZnO film plane of the InGaZnO thin film transistor in the transition state of hydrogen drift diffusion. FIG. 3C shows the hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor in the steady state of hydrogen drift diffusion. FIG. 3D shows the hydrogen concentration distribution on the InGaZnO film plane of the InGaZnO thin film transistor in the steady state of hydrogen drift diffusion. 3A to 3D, compared with the hydrogen concentration increased in the InGaZnO film (oxide semiconductor film 220) under the fringe portion of the source wiring and the drain wiring protruding to the channel region side in the comparative example. In any case, the hydrogen concentration is suppressed to be low.

  FIG. 4 is an example of a graph showing the hydrogen concentration distribution in the thin film transistor in the first embodiment and the comparative example. 4A shows the hydrogen concentration on the vertical axis and the position in the channel length direction on the horizontal axis, and the source wiring shown in FIGS. 2A and 2B in the transient state of hydrogen drift diffusion and Hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the configuration with the fringe portion of the drain wiring, and the InGaZnO film in the configuration without the fringe portions of the source wiring and the drain wiring shown in FIGS. The hydrogen concentration of (oxide semiconductor film 220) is shown. FIG. 4B shows the hydrogen concentration on the vertical axis and the position in the channel length direction on the horizontal axis, and the source wiring shown in FIGS. 2C and 2D in the steady state of hydrogen drift diffusion and Hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the configuration with the fringe portion of the drain wiring, and the InGaZnO film in the configuration without the fringe portions of the source wiring and the drain wiring shown in FIGS. The hydrogen concentration of (oxide semiconductor film 220) is shown. 4A and 4B, graph A shows the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the structure with the fringe portions of the source wiring and the drain wiring. Graph B shows the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the structure without the fringe portion of the source wiring and the drain wiring. 4A and 4B, in both cases, the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the configuration with the fringe portions of the source wiring and the drain wiring protruding to the channel region side is as follows. This shows that the hydrogen concentration in the InGaZnO film (oxide semiconductor film 220) without the fringe portion is higher not only in the region under the fringe portion but also in the center portion of the channel region.

  As described above, in the configuration with the fringe portion of the source wiring and the drain wiring protruding to the channel region side as in the comparative example, the hydrogen concentration in the channel region 16 of the oxide semiconductor film 220 has a hydrogen concentration in the region below the fringe portion. To rise. Therefore, the number of carriers in the channel portion of the oxide semiconductor film 220 and a decrease in resistance are caused, which causes a decrease in threshold voltage of the thin film transistor and a malfunction of the transistor.

  Therefore, in the first embodiment, as shown in FIG. 1, the source wiring 12 and the drain wiring 14 are formed so as not to protrude to the channel region 16 side. By eliminating the fringe portion of the metal wiring on the channel region 16 side, the amount of hydrogen that enters from above in the hydrogen sintering process can be reduced. With this configuration, as described above, an increase in the hydrogen concentration not only in the region under the fringe portion in the channel region 16 of the oxide semiconductor film 220 but also in the entire channel region can be suppressed.

  FIG. 5 is a flowchart showing main steps of the semiconductor device manufacturing method according to the first embodiment. In FIG. 5, the semiconductor device manufacturing method according to the first embodiment includes a gate electrode formation step (S102), a gate insulation film formation step (S104), an oxide semiconductor film formation step (S106), and an insulation film formation. A series of steps (S108), opening formation step (S112), electrode material film formation step (S114), planarization step (S116), wiring material film formation step (S118), and patterning step (S120). The process of is implemented.

  FIG. 6 is a process cross-sectional view of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 shows from the gate electrode formation step (S102) to the insulating film formation step (S108) in FIG. Subsequent steps will be described later.

In FIG. 6A, the gate electrode 10 is formed in the insulating film 200 as a gate electrode formation step (S102). Assuming that a thin film transistor (TFT) using an oxide semiconductor film is formed in a multilayer wiring layer, a part of the metal wiring in the multilayer wiring may be provided beside the transistor. In the example of FIG. 5A, the gate electrode 10 is embedded in an insulating film by a damascene process. For example, an opening (groove) for the gate electrode 10 is formed in the insulating film 200. Then, a gate electrode material is deposited on the insulating film 200 so as to fill the opening. After the deposition, excess gate electrode material protruding from the opening may be removed by chemical mechanical polishing (CMP). Through this process, the gate electrode 10 is formed. As a material of the gate electrode 10, for example, a metal film containing copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), or Al (aluminum) Etc. can be used. When Cu is used, a barrier metal film is formed on the side and bottom surfaces of the opening so as to prevent diffusion of Cu into the insulating film 200 and the like, and the inside of the opening is buried via the barrier metal film. What is necessary is just to form. For example, the insulating film 200 is a film containing silicon oxide (SiO _x ) or silicon nitride (SiN _x ) on a silicon substrate made of a silicon wafer. Although not shown here, the insulating film 200 may be formed with wiring, various elements, and the like.

  In the example of FIG. 5A, a buried structure by a damascene process is shown. However, the structure is not limited to this, and a gate electrode material is deposited on the insulating film 200 by a sputtering method or the like and then patterned by an etching method. Thus, the gate electrode 10 may be formed. Further, the side surface of the gate electrode 10 may be inclined with respect to the stacking direction. That is, the side surface of the gate electrode 10 may be tapered.

In FIG. 6B, as the gate insulating film formation step (S104), the gate insulating film 210 is formed with a film thickness of, for example, 2 to 50 nm on the gate electrode 10 by using a chemical vapor deposition (CVD) method. Here, for example, it is formed with a film thickness of 15 nm. For example, silicon oxide (SiO ₂ ), aluminum oxide (Al _x O _y ), silicon nitride (SiNx), silicon oxynitride (SiO _x N _y ), or the like is preferably used as the material of the gate insulating film 210. . As the gate insulating film 210, a stacked film of two or more films of silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride may be used. As a forming method, it is preferable to use a plasma CVD method or an atomic layer deposition (ALD) method or an atomic layer chemical vapor deposition (ALCVD) method.

In FIG. 6C, as the oxide semiconductor film formation step (S106), the oxide semiconductor film 220 is formed with a film thickness of, for example, 10 to 30 nm on the gate insulating film 210 by sputtering. Here, for example, it is formed with a film thickness of 30 nm. After that, the oxide semiconductor film 220 is patterned by an etching method so as to leave an active region, whereby the oxide semiconductor film 220 having a predetermined size is formed. The width of the oxide semiconductor film 220 in the gate length direction is preferably wider than that of the gate electrode 10. An oxide semiconductor has a single crystal state, a polycrystalline state, an amorphous state, or the like. As described above, for example, the oxide semiconductor contains at least one of indium (In), gallium (Ga), and zinc (Zn) as the material of the oxide semiconductor film 220. As the oxide semiconductor, a ternary metal oxide such as InGaZnO (hereinafter sometimes referred to as IGZO) is used. As the oxide semiconductor, for example, a binary metal oxide such as InGaO may be used. InGaWO or InGaSiO containing at least one of tungsten (W) and silicon (Si) may be used. The oxide semiconductor may be a quaternary metal oxide such as InSnGaZnO or InAlGaZnO containing at least one of tin (Sn) and aluminum (Al). In any case, the component ratio of a metal or a non-metal element as a main component is arbitrary. Here, the InGaZn-based oxide is an oxide containing indium, gallium, and zinc as main components, and the component ratio of these metals is arbitrary. Moreover, you may contain metals other than indium, gallium, and zinc, or elements other than a metal.
In the case where the oxide semiconductor layer 220 is a layer containing IGZO, for example, the oxide semiconductor layer 220 has a composition ratio of IGZO, and targets IGZO4 that is In: Ga: Zn: O = 1: 1: 1: 4. It is formed by the sputtering method used.

  6D, as the insulating film formation step (S108), the insulating film 230 is formed to a thickness of, for example, 30 to 200 nm on the oxide semiconductor film 220 and the gate insulating film 210 by using a CVD method. Here, the gate insulating film 210 is formed with a thickness of, for example, 150 nm. For example, the insulating film 230 is a film containing silicon oxide, Teos (Tetra Ethyl Ortho Silicate: TEOS), aluminum oxide, or silicon nitride. As the insulating film 230, a stacked film of two or more films of silicon oxide, theos, aluminum oxide, and silicon nitride may be used. As a formation method, a plasma CVD method or an atomic layer vapor deposition method is preferably used. The insulating film 230 is formed to cover the oxide semiconductor film 220 and serves as a protective film for the oxide semiconductor film 220.

  FIG. 7 is a process cross-sectional view of the semiconductor device manufacturing method according to the first embodiment. FIG. 7 shows from the opening forming step (S112) to the wiring material film forming step (S118) in FIG.

  In FIG. 7A, as the opening forming step (S112), openings 150 and 152 are formed so as to penetrate the insulating film 230 from the top of the insulating film 230 to the surface of the oxide semiconductor film 220. A source opening 150 (contact hole) is formed at a position at least partially overlapping one end of the gate electrode 10 in the gate length direction. At the same time, a drain opening 152 (contact hole) is formed at a position at least partially overlapping with the other end of the gate electrode 10 in the gate length direction. By removing the exposed insulating film 230 by anisotropic etching from the substrate on which the resist pattern is formed on the insulating film 230 through a lithography process such as a resist coating process and an exposure process (not shown), The openings 150 and 152 can be formed substantially perpendicular to the surface. For example, as an example, the openings 150 and 152 may be formed by a reactive ion etching (RIE) method.

  In FIG. 7B, as the electrode material film forming step (S114), the electrode material film is formed on the insulating film 230 to have a thickness of, for example, 50 to 100 nm so as to completely fill the openings 150 and 152 by using, for example, a sputtering method. The film thickness is formed. As the electrode material film, for example, a metal film containing molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al) is used. Molybdenum nitride (MoN), titanium nitride (TiN), or tantalum nitride (TaN) may be used. Alternatively, a stacked film of two or more films of these conductive materials may be used. A film containing ITO (Indium Tin Oxide) or zinc oxide (ZnO) may be used. Or you may be comprised by the metal material film | membrane as a main material, and the barrier metal film which is not shown in figure which covers the side surface and bottom face of a metal material film | membrane.

  Then, as a planarization step (S116), the excess electrode material film protruding from the openings 150 and 152 is removed and planarized by the CMP method. Thereby, the source electrode 13 and the drain electrode 15 shown in FIG. 7B are formed.

  Subsequently, as a wiring material film forming step (S118), a wiring material film 260 is formed to a thickness of, for example, 50 to 100 nm on the insulating film 230, the source electrode 13, and the drain electrode 15 by using, for example, a sputtering method. As the wiring material film 260, for example, a metal film containing molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), or aluminum (Al) is used. Molybdenum nitride (MoN), titanium nitride (TiN), or tantalum nitride (TaN) may be used. Alternatively, a stacked film of two or more films of these conductive materials may be used. A film containing ITO (Indium Tin Oxide) or zinc oxide (ZnO) may be used. Or you may be comprised by the metal material film | membrane as a main material, and the barrier metal film which is not shown in figure which covers the side surface and bottom face of a metal material film | membrane.

  As a patterning step (S120), the wiring material film 260 is patterned by lithography and etching methods (not shown) so that only the metal wiring formation region remains, so that the source does not protrude toward the channel region 16 as shown in FIG. A wiring 12 and a drain wiring 14 are formed. By removing the exposed wiring material film 260 by an anisotropic etching method on a substrate on which a resist pattern is formed on the wiring material film 260 through a lithography process such as a resist coating process and an exposure process (not shown), The source wiring 12 and the drain wiring 14 can be formed substantially perpendicular to the surface of the substrate. For example, as an example, the source wiring 12 and the drain wiring 14 may be formed by the RIE method. Further, the source wiring 12 is connected to the source electrode 13 so that the source wiring 12 does not protrude toward the channel region 16 during patterning, but the end on the channel region 16 side is more than the end of the source electrode 13. The channel region 16 may be configured to be shifted from the opposite side. The same applies to the relationship between the drain wiring 14 and the drain electrode 15.

  In the above-described example, the example in which the source wiring 12 and the drain wiring 14 are formed after the source electrode 13 and the drain electrode 15 are formed has been described. However, the present invention is not limited to this. The source electrode 13 and the drain electrode 15, and the source wiring 12 and the drain wiring 14 may be formed at the same time. In such a case, the wiring material film 260 is formed on the insulating film 230 with a film thickness larger than the wiring thickness while completely burying the openings 150 and 152. Then, the metal wiring formation region is patterned so as not to protrude toward the channel region 16, and the wiring material film 260 exposed by the etching method may be etched so that only the metal wiring formation region remains.

  FIG. 8 is a cross-sectional view showing a modified example of the configuration of the semiconductor device according to the first embodiment. In FIG. 8, the source electrode 13 and the drain electrode 15, and the source wiring 12 and the drain wiring 14 are formed at the same time without completely filling the source / drain openings 150 and 152 with the metal film. . Other configurations are the same as those in FIG.

  In the modification of the first embodiment shown in FIG. 8, after forming the openings 150 and 152 for the source / drain, the electrode / wiring material is formed on the insulating film 230, on the bottom of the opening, and on the inner wall. . Then, the metal wiring formation region is patterned so as not to protrude toward the channel region 16, and the electrode / wiring material exposed by the etching method may be etched and removed so that only the metal wiring formation region remains.

  As described above, in the first embodiment, the source wiring 12 and the drain wiring 14 are formed so as not to protrude toward the channel region 16, so that the channel portion of the oxide semiconductor film 220 that is under the fringe portion when protruding is formed. The increase in the hydrogen concentration in can be suppressed. As a result, variation in the number of carriers and reduction in resistance in the channel portion of the oxide semiconductor film 220 can be suppressed. Therefore, it is possible to suppress the threshold voltage drop of the thin film transistor and the malfunction of the transistor.

  As described above, in the first embodiment, the configuration of the bottom gate type thin film transistor (TFT) using the oxide semiconductor film 220 illustrated in FIG. 1 has been described. It can be formed in the wiring layer. In such a case, it is preferable not to dispose a metal film over a channel region of a bottom-gate thin film transistor (TFT) using the oxide semiconductor film 220 illustrated in FIG.

  FIG. 9 is a diagram illustrating an example of a cross section of the multilayer wiring structure according to the first embodiment. FIG. 9 shows a cross section in the case where a bottom-gate thin film transistor (TFT) using the oxide semiconductor film 220 shown in FIG. 1 is formed in a wiring layer in the middle of the multilayer wiring structure. In the semiconductor device shown in FIG. 9, a gate electrode layer 40 in which a gate electrode 13 is disposed is formed on a semiconductor substrate 300 which is element-isolated and has p-type or n-type impurities implanted in each active region. On the layer 40, the wiring layer 42, the wiring layer 44, and the wiring layer 46 are formed in order from the lower layer side. In each of the wiring layers 42, 44, 46, the wiring 11 is formed. In the semiconductor device illustrated in FIG. 9, a bottom-gate thin film transistor (TFT) using the oxide semiconductor film 220 illustrated in FIG. 1 is formed in the same layer as the wiring layer 42.

  As shown in FIG. 9, upper wiring layers 44 and 46 are formed on the layer where the source wiring 12 and the drain wiring 14 are formed. In such a multilayer wiring structure, in the first embodiment, the wiring 11 in the upper wiring layers 44 and 46 is formed so as not to overlap the channel region of the oxide semiconductor film 220 in the thin film transistor (TFT). In other words, as shown in FIG. 9, the metal wiring 11 is not arranged in the region A on the channel region. With this configuration, a metal film that can produce the same effect as the fringe portion protruding to the channel side of the source wiring 12 and the drain wiring 14 can be excluded from the channel of the thin film transistor (TFT).

  FIG. 10 is a diagram illustrating another example of a cross section of the multilayer wiring structure according to the first embodiment. FIG. 10 shows a cross section when a bottom gate type thin film transistor (TFT) using the oxide semiconductor film 220 shown in FIG. 1 is formed in the uppermost wiring layer of the multilayer wiring structure. Other configurations are the same as those in FIG. In other words, in the semiconductor device shown in FIG. 10, the wiring layer 46 in which the source wiring and the drain wiring of the bottom gate type thin film transistor (TFT) using the oxide semiconductor film 220 shown in FIG. The case where it forms in the same layer is shown. The source wiring 12 and the drain wiring 14 may be formed in the uppermost layer of the multilayer wiring structure, and the layer on which the gate electrode 10 is formed may not be the uppermost wiring layer. In the example of FIG. 10, the gate electrode 10 is formed in the wiring layer 44, and the source wiring 12 and the drain wiring 14 are formed in the wiring layer 46.

  As shown in FIG. 10, the source wiring 12 and the drain wiring 14 are formed in the uppermost wiring layer 46, so that the metal wiring does not overlap with the channel portion of the oxide semiconductor film 220 in the thin film transistor (TFT). it can. With this configuration, a metal film that can produce the same effect as the fringe portion projecting to the channel side of the source wiring 12 and the drain wiring 14 can be excluded from the channel region.

  As described above, in the multilayer wiring structure, by preventing the metal wiring from being arranged on the channel portion of the oxide semiconductor film 220 in the thin film transistor (TFT), the metal film positioned above the channel portion causes the lower portion thereof. An increase in hydrogen concentration that can occur in the oxide semiconductor film 220 can be suppressed. As a result, variation in the number of carriers and reduction in resistance in the channel portion of the oxide semiconductor film 220 can be suppressed. Therefore, it is possible to suppress the threshold voltage drop of the thin film transistor and the malfunction of the transistor.

(Second Embodiment)
In the second embodiment, a structure in which a new oxide semiconductor film is positively disposed above the channel portion of the oxide semiconductor film 220 will be described.

FIG. 11 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. 11, except that the oxide semiconductor film 222 (second oxide semiconductor film) is provided on the insulating film 230 above the channel region 16 independently of the source wiring 12 and the drain wiring 14. It is the same. The following is the same as in the first embodiment except for the points to be specifically described. For example, the oxide semiconductor film 222 includes at least one of indium (In), gallium (Ga), and zinc (Zn). As the oxide semiconductor, a ternary metal oxide such as InGaZnO (hereinafter sometimes referred to as IGZO) is used. As the oxide semiconductor, for example, a binary metal oxide such as InGaO may be used. InGaWO or InGaSiO containing at least one of tungsten (W) and silicon (Si) may be used. The oxide semiconductor may be a quaternary metal oxide such as InSnGaZnO or InAlGaZnO containing at least one of tin (Sn) and aluminum (Al). In any case, the component ratio of a metal or a non-metal element as a main component is arbitrary.
Here, the InGaZn-based oxide is an oxide containing indium, gallium, and zinc as main components, and the component ratio of these metals is arbitrary. Moreover, you may contain metals other than indium, gallium, and zinc, or elements other than a metal. The formation method of the oxide semiconductor film 222 may be the same as that of the oxide semiconductor film 220.

FIG. 12 is a diagram illustrating an example of a hydrogen concentration distribution in the reference example of the second embodiment. 12 (a) to 12 (d) show TCAD (Technology Computer Aided Design) in a situation where hydrogen descends from the upper surface as monovalent hydrogen ions (H ⁺ ) and propagates by drift diffusion with respect to the InGaZnO thin film transistor. The result analyzed using is shown. Even in a situation where no bias voltage is applied to the electrode terminal, a potential distribution and an electric field distribution are generated due to the inherent work function of the constituent material and the dielectric constant. 12A to 12D, the reference example shows a case where the metal wiring on the source (S) / drain (D) electrode has a fringe portion protruding to the channel region side. Yes. In addition, a second InGaZnO film (oxide semiconductor film 222) is disposed to face the channel region. Here, the case where it arrange | positions in an insulating film is shown. FIG. 12A shows the hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor in the transient state of hydrogen drift diffusion. FIG. 12B shows a hydrogen concentration distribution on the plane of the InGaZnO film (oxide semiconductor film 220) of the InGaZnO thin film transistor in the transient state of hydrogen drift diffusion. FIG. 12C shows a hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor at the time when the hydrogen drift diffusion steady state is reached. FIG. 12D shows a hydrogen concentration distribution on the InGaZnO film (oxide semiconductor film 220) plane of the InGaZnO thin film transistor at the time when a steady state of hydrogen drift diffusion is reached. 12A to 12D, in any case, the hydrogen concentration in the InGaZnO film (oxide semiconductor film 220) under the fringe portion of the source wiring and the drain wiring that protrudes to the channel region side is the oxide semiconductor film. It shows that the hydrogen concentration is higher in the central region of 220 channels.

  FIG. 13 is a diagram illustrating an example of a hydrogen concentration distribution in the second embodiment. 13A to 13D, in the second embodiment, as shown in FIG. 11, the metal wiring on the source (S) / drain (D) electrode protrudes to the channel region side. It is configured so that there is no. In addition, an InGaZnO film (oxide semiconductor film 222) is provided over the channel region. Other configurations are the same as those of the reference example of FIG. FIG. 13A shows the hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor in the transient state of hydrogen drift diffusion. FIG. 13B shows a distribution of hydrogen concentration on the InGaZnO film (oxide semiconductor film 220) plane of the InGaZnO thin film transistor in a transient state of hydrogen drift diffusion. FIG. 13C shows the hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor at the time when the hydrogen drift diffusion steady state is reached. FIG. 13D shows the distribution of hydrogen concentration on the InGaZnO film (oxide semiconductor film 220) plane of the InGaZnO thin film transistor when the hydrogen drift diffusion steady state is reached. In the reference example, the hydrogen concentration that was high in the InGaZnO film (oxide semiconductor film 220) under the fringe portion of the source wiring and the drain wiring that protruded to the channel region side is any of FIGS. 13A to 13D. This also shows that the hydrogen concentration is lower than when there is a fringe portion of the source wiring and drain wiring.

  FIG. 14 is an example of a graph showing a hydrogen concentration distribution in the second embodiment and the reference example. FIG. 14A shows the hydrogen concentration on the vertical axis and the position in the channel length direction on the horizontal axis, and the source wiring shown in FIGS. 2A and 2B in the transient state of hydrogen drift diffusion and Hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the configuration with the fringe portion of the drain wiring, and the InGaZnO film in the configuration without the fringe portions of the source wiring and the drain wiring shown in FIGS. The hydrogen concentration of the (oxide semiconductor film 220), the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the structure with the fringe portion shown in FIGS. 12 (a) and 12 (b), and FIGS. The hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the structure without the fringe portion of the source wiring and the drain wiring shown in b) is shown. FIG. 14B shows the hydrogen concentration on the vertical axis and the position in the channel length direction on the horizontal axis. The source wiring shown in FIGS. 2C and 2D in the steady state of hydrogen drift diffusion and Hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the configuration with the fringe portion of the drain wiring, and the InGaZnO film in the configuration without the fringe portions of the source wiring and the drain wiring shown in FIGS. The hydrogen concentration of the (oxide semiconductor film 220), the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the configuration with the fringe portions of the source wiring and the drain wiring shown in FIGS. FIG. 13C shows the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) in the configuration without the fringe portions of the source wiring and the drain wiring shown in FIGS. 14A and 14B, graph A shows a configuration with a fringe portion of a source wiring and a drain wiring, and a configuration in which an InGaZnO film (oxide semiconductor film 222) is not arranged over the channel region. 2 shows the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220). Graph B shows the hydrogen of the InGaZnO film (oxide semiconductor film 220) in the structure without the fringe portion of the source wiring and the drain wiring and without the InGaZnO film (oxide semiconductor film 222) over the channel region. Indicates the concentration. Graph C shows an InGaZnO film (oxide semiconductor film 220) having a structure with a fringe portion of source and drain wirings and a structure in which an InGaZnO film (oxide semiconductor film 222) is disposed so as to face the channel region. Shows the hydrogen concentration. Graph D shows an InGaZnO film (oxide oxide) according to the second embodiment in which the source wiring and the drain wiring have no fringes, and the InGaZnO film (oxide semiconductor film 222) is arranged opposite to the channel region. The hydrogen concentration of the semiconductor film 220) is shown. In FIGS. 14A and 14B, the hydrogen in the InGaZnO film (oxide semiconductor film 220) is less in the case where there is no fringe portion in the source wiring and the drain wiring than in the configuration in which the fringe portion in the source wiring and the drain wiring is provided. It can be seen that the concentration is low. Furthermore, even when the fringe portion of the source wiring and the drain wiring is not provided, the InGaZnO film (oxide semiconductor film 222) is further disposed over the channel region, and the InGaZnO film (oxide semiconductor film 220) is further provided. It can be seen that the hydrogen concentration of is low.

  By disposing the oxide semiconductor film 222 having the same material characteristics as the oxide semiconductor film 220 so as to face the channel region of the oxide semiconductor film 220, the hydrogen concentration in the center of the channel below the oxide semiconductor film 222 is increased. Can be suppressed. Such an effect is also exerted on the regions in the vicinity of the source / drain electrodes on both sides of the oxide semiconductor film 222, and the increase in the hydrogen concentration can be further suppressed as compared with the configuration in which the fringe portion shown in FIG. 1 is eliminated. With the arrangement of the oxide semiconductor film 222, the amount of hydrogen taken into the entire channel region as well as the region near the source / drain electrodes in the channel portion of the oxide semiconductor film 220 can be reduced.

  Note that a structure in which the oxide semiconductor film 222 is opposed to the entire channel surface of the oxide semiconductor transistor may cause a short circuit with the source wiring or the drain wiring. Therefore, in the second embodiment, as illustrated in FIG. 11, the oxide semiconductor film 222 is not formed on the channel region 16.

  In the second embodiment, since the hydrogen concentration of the InGaZnO film (oxide semiconductor film 220) can be lowered as compared with the first embodiment, the source wiring 12 and the drain wiring as shown by the dotted line in FIG. 14 may protrude slightly to the channel region 16 side due to a positional deviation during patterning. Thereby, while increasing the contact area between the source wiring 12 and the source electrode 13, the alignment accuracy between the source wiring 12 and the source electrode 13 can be further lowered, and patterning can be facilitated. The same applies to the relationship between the drain wiring 14 and the drain electrode 15.

  As described above, in the second embodiment, the oxide semiconductor film 222 is formed above the channel region 16 independently of the source wiring 12 and the drain wiring 14, so that the hydrogen in the channel portion of the oxide semiconductor film 220 is formed. The increase in concentration can be suppressed. As a result, variation in the number of carriers and reduction in resistance in the channel portion of the oxide semiconductor film 220 can be suppressed. Therefore, it is possible to suppress the threshold voltage drop of the thin film transistor and the malfunction of the transistor.

  The embodiment has been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  In addition, all semiconductor devices that include the elements of the present invention and whose design can be appropriately changed by those skilled in the art and methods for manufacturing the semiconductor devices are included in the scope of the present invention.

  In addition, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as cleaning before and after processing, are omitted, but it goes without saying that these techniques may be included.

  10 gate electrode, 12 source wiring, 13 source electrode, 14 drain wiring, 15 drain electrode, 210 gate insulating film, 220, 222 oxide semiconductor film, 230 insulating film

In the following embodiments, the term "disposed on", in addition to the case of provision of direct contact, including the case where another layer or film is inserted between. Further, “provided facing” includes not only the case of being provided in direct contact with the top or bottom, but also the case of being provided with another layer or film interposed therebetween.

FIG. 1 is a cross-sectional view and a plan view showing the configuration of the semiconductor device according to the first embodiment. FIG. 1 illustrates an example of a bottom gate type (reverse stagger type) thin film transistor (TFT) using an oxide semiconductor film such as an InGaZnO film (IGZO film) as a semiconductor device. In FIG. 1, a gate electrode 10 is formed on the surface of an insulating film 200 formed on a substrate. The insulating film 200 is a film containing silicon oxide (SiO _x ) or silicon nitride (SiN _x ). The gate electrode 10 is, for example, data tungsten (W), molybdenum (Mo), copper (Cu), Ta (tantalum), or a metal film containing Al (aluminum) is used. As the gate electrode 10, titanium nitride (TiN) or tantalum nitride (TaN) may be used. An aluminum alloy may be used for the gate electrode 10. The aluminum alloy has aluminum as a main component and hillock countermeasures are taken. Further, the side surface of the gate electrode 10 may be inclined with respect to the stacking direction. That is, the side surface of the gate electrode 10 may be tapered. By making the side surface of the gate electrode 10 tapered, the coverage with the insulating film 210 formed on the gate electrode 10 is enhanced. Leakage current can be suppressed by increasing the coverage. In the example of FIG. 1, the insulating film 200 is embedded so that the surface (upper surface) of the gate electrode 10 is formed at the same height as the upper surface of the insulating film 200. In the example of FIG. 1, for example, it is assumed that the gate electrode 10 is formed in the same layer as a predetermined wiring of a multilayer wiring layer. Therefore, other wiring layers, semiconductor elements, and the like may be formed on the substrate and the insulating film 200. However, the present invention is not limited to this configuration, and the gate electrode 10 may be formed on the insulating film 200.

FIG. 9 is a diagram illustrating an example of a cross section of the multilayer wiring structure according to the first embodiment. FIG. 9 shows a cross section in the case where a bottom-gate thin film transistor (TFT) using the oxide semiconductor film 220 shown in FIG. 1 is formed in a wiring layer in the middle of the multilayer wiring structure. In the semiconductor device shown in FIG. 9, a gate electrode layer 40 in which a gate electrode 10 is disposed is formed on a semiconductor substrate 300 which is element-isolated and has p-type or n-type impurities implanted in each active region. A wiring layer 42, a wiring layer 44, and a wiring layer 46 are formed on the electrode layer 40 in order from the lower layer side. In each of the wiring layers 42, 44, 46, the wiring 11 is formed. In the semiconductor device illustrated in FIG. 9, a bottom-gate thin film transistor (TFT) using the oxide semiconductor film 220 illustrated in FIG. 1 is formed in the same layer as the wiring layer 42.

As described above, in the multilayer wiring structure, by preventing the metal wiring from being arranged on the channel portion of the oxide semiconductor film 220 in the thin film transistor (TFT), the metal film positioned above the channel portion causes the lower portion thereof. An increase in hydrogen concentration that can occur in the oxide semiconductor film 220 can be suppressed. As a result, variation in the number of carriers and reduction in resistance in the channel portion of the oxide semiconductor film 220 can be suppressed. Therefore, it is possible to suppress the threshold voltage drop of the thin film transistor and the transistor malfunction.

FIG. 12 is a diagram illustrating an example of a hydrogen concentration distribution in the reference example of the second embodiment. 12 (a) to 12 (d) show TCAD (Technology Computer Aided Design) in a situation where hydrogen descends from the upper surface as monovalent hydrogen ions (H ⁺ ) and propagates by drift diffusion with respect to the InGaZnO thin film transistor. The result analyzed using is shown. Even in a situation where no bias voltage is applied to the electrode terminal, a potential distribution and an electric field distribution are generated due to the inherent work function of the constituent material and the dielectric constant. 12A to 12D, the reference example shows a case where the metal wiring on the source (S) / drain (D) electrode has a fringe portion protruding to the channel region side. Yes. In addition, a second InGaZnO film (oxide semiconductor film 222) is disposed to face the channel region. Here, the case where it arrange | positions in an insulating film is shown. FIG. 12A shows the hydrogen concentration distribution in the cross section of the InGaZnO thin film transistor in the transient state of hydrogen drift diffusion. FIG. 12B shows a hydrogen concentration distribution on the plane of the InGaZnO film (oxide semiconductor film 220) of the InGaZnO thin film transistor in the transient state of hydrogen drift diffusion. Figure 12 (c) shows the distribution of the hydrogen concentration in the cross section of the InGaZnO TFT definitive at the time that led to the steady state drift-diffusion of hydrogen. FIG. 12D shows a hydrogen concentration distribution on the InGaZnO film (oxide semiconductor film 220) plane of the InGaZnO thin film transistor at the time when a steady state of hydrogen drift diffusion is reached. 12A to 12D, in any case, the hydrogen concentration in the InGaZnO film (oxide semiconductor film 220) under the fringe portion of the source wiring and the drain wiring that protrudes to the channel region side is the oxide semiconductor film. It shows that the hydrogen concentration is higher in the central region of 220 channels.

Claims (5)

A gate electrode;
A first insulating film disposed on the gate electrode;
An oxide semiconductor film disposed on the first insulating film;
A second insulating film disposed on the oxide semiconductor film;
A source electrode disposed in the second insulating film and connected to the oxide semiconductor film;
A source wiring disposed on the second insulating film so as not to overlap the channel portion and connected to the source electrode;
A drain electrode disposed in the second insulating film and connected to the oxide semiconductor film;
A drain wiring disposed on the second insulating film so as not to overlap the channel portion and connected to the drain electrode;
A semiconductor device comprising: On the layer where the source wiring and the drain wiring are formed, an upper wiring layer is further provided,
2. The semiconductor device according to claim 1, wherein the wiring in the upper wiring layer is formed so as not to overlap the channel portion. The semiconductor device has a multilayer wiring layer,
The semiconductor device according to claim 1, wherein the source wiring and the drain wiring are formed in an uppermost layer of the multilayer wiring layer.   4. The semiconductor device according to claim 1, further comprising: a second oxide semiconductor film that is disposed independently of the source wiring and the drain wiring on the channel portion. 5. A gate electrode;
A first insulating film disposed on the gate electrode;
A first oxide semiconductor film disposed on the first insulating film;
A second insulating film disposed on the oxide semiconductor film;
A source electrode disposed in the second insulating film and connected to the oxide semiconductor film;
A source wiring disposed on the second insulating film and connected to the source electrode;
A drain electrode disposed in the second insulating film and connected to the oxide semiconductor film;
A drain wiring disposed on the second insulating film and connected to the drain electrode;
A second oxide semiconductor film, wherein the source wiring and the drain wiring are arranged independently on the channel portion;
A semiconductor device comprising: