JP2016071158A - Semiconductor optical element manufacturing method and semiconductor optical element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor optical element manufacturing method capable of improving use efficiency for a III-V group semiconductor substrate, and a semiconductor optical element.SOLUTION: The semiconductor optical element manufacturing method for manufacturing a semiconductor optical element including a III-V group semiconductor laser element and a photonics substrate in which an optical output of a III-V group semiconductor laser is guided to an optical waveguide, includes: a first step S40 of fixing a plurality of III-V group semiconductor laser elements formed on a semiconductor substrate to a support member; a second step S50 of etching and removing the III-V group semiconductor laser elements fixed in the first step from the semiconductor substrate; and a third step S60 of coupling the III-V group semiconductor laser elements removed in the second step to the photonics substrate by intermolecular bond.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor optical element manufacturing method and a semiconductor optical element, and in particular, when mounting a waveguide type semiconductor laser on an optical waveguide component, a semiconductor optical element manufacturing method capable of simplifying mounting of a semiconductor laser structure, And a semiconductor optical element.

  In an FTTH (Fiber to the Home) system, in particular, a PON (Passive Optical Network) system, a large number of subscribers share an OLT (Optical Line Terminal). The OLT uses an optoelectronic fusion device in which an optical waveguide is formed on a silicon (Si) substrate and coupled to one or both of the Si optical waveguide, a semiconductor laser element, and a photodiode. In such an optoelectronic fusion device, there is a demand for a packaging technology that can achieve high density and low cost.

  Here, the semiconductor laser normally oscillates in a direction parallel to the surface of the substrate, and the optical waveguide is also formed parallel to the substrate. For this reason, in optoelectronic devices, semiconductor laser light is usually incident from the end face of the optical waveguide, and the surface of the Si optical waveguide and the semiconductor laser element are surface-bonded to manufacture a semiconductor optical element. Could not have thought.

  However, a technology that can be mounted in a normal semiconductor process by forming an active layer of a semiconductor laser on a surface shifted in a direction perpendicular to the silicon waveguide and coupling the silicon waveguide and the active layer with light has begun to attract attention. Yes. For example, in Non-Patent Document 1 below, a Si optical waveguide is formed on a Si substrate, a III-V group semiconductor substrate is pasted thereon, and after the pasting, a semiconductor is formed on the III-V group semiconductor substrate. A method for performing a laser forming process is disclosed. That is, since a semiconductor laser formed by executing a semiconductor laser forming process has a waveguide, Non-Patent Document 1 discloses a technique in which a waveguide of a semiconductor laser and a Si optical waveguide are coupled with light. Is disclosed.

G.-H.Duan1, et al. “III-V on Silicon Transmitters”, OFC, OM3K4, 2013

  However, the technique described in Non-Patent Document 1 is based on the process of forming a semiconductor laser on a group III-V semiconductor substrate after pasting the group III-V semiconductor substrate on the Si substrate on which the Si optical waveguide is formed. Need to run. The group III-V semiconductor substrate is generally higher in cost than the Si substrate, and the proportion of the group III-V semiconductor laser portion in the area of the Si photonics substrate is 1/100 or less. When a group III-V semiconductor substrate is attached to a Si substrate and then a semiconductor laser forming process is performed, there is a problem that most of the group III-V semiconductor substrate is not used.

  Then, an object of this invention is to provide the semiconductor optical element manufacturing method which can raise the use efficiency of a III-V group semiconductor substrate, and a semiconductor optical element.

  In order to solve the above problems, one means of the present invention is a semiconductor optical device comprising a group III-V semiconductor laser device and a photonics substrate in which the optical output of the group III-V semiconductor laser is guided to an optical waveguide. A semiconductor optical device manufacturing method for manufacturing a semiconductor optical device, comprising: a first step of fixing a plurality of group III-V semiconductor laser devices formed on a semiconductor substrate to a support member; and the III- fixed in the first step. A second step of etching and peeling the group V semiconductor laser element and the semiconductor substrate; and a third step of intermolecular bonding of the group III-V semiconductor laser element and the photonics substrate peeled in the second step. It is characterized by providing.

  Another means of the present invention is a semiconductor optical device comprising a III-V group semiconductor laser device and a photonics substrate in which the light output of the group III-V semiconductor laser device is guided to an optical waveguide. The -V group semiconductor laser device has an active layer and a clad layer sandwiching the active layer, and one of the clad layer and the photonics substrate is intermolecularly bonded.

The area of the photonics substrate is 10 to 100 times that of the group III-V semiconductor laser element. For this reason, if an element formation process is performed after joining a group III-V semiconductor substrate to a photonics substrate, much of a group III-V semiconductor substrate is wasted. However, according to the present invention, since the group III-V semiconductor laser element and the photonics substrate are intermolecularly bonded after the group III-V semiconductor laser element is manufactured, the group III-V semiconductor substrate is not wasted. .
In addition, since the III-V semiconductor laser element and the photonics substrate are intermolecularly bonded, it is not necessary to align the optical axis in the direction perpendicular to the photonics substrate.

  In a semiconductor laser element, light generally resonates inside an active layer, and laser light is emitted from an end portion. Since the clad layer of the III-V semiconductor laser device is formed as thin as 50 to 100 nm, the light emitting layer as the waveguide and the core of the optical waveguide of the photonics substrate are arranged close to each other. As a result, the evanescent light oozes out from the active layer to the cladding layer or the cladding of the optical waveguide, and the active layer and the core are coupled to each other in the light wave electromagnetic field. That is, the light resonated in the active layer of the III-V group semiconductor laser device is drawn into the core of the optical waveguide of the photonics substrate.

  According to the present invention, the use efficiency of the III-V semiconductor substrate can be increased.

1 is a structural diagram of a semiconductor optical element according to a first embodiment of the present invention. It is a figure for demonstrating a mode that the light resonated in the active layer is couple | bonded with the core of an optical waveguide. It is a flowchart for demonstrating the manufacturing method of the semiconductor optical element which is 1st Embodiment of this invention. It is a structural diagram for explaining a laser structure formed by crystal growth. It is explanatory drawing (1) for manufacturing LD chip | tip. It is explanatory drawing (2) for manufacturing LD chip | tip. It is explanatory drawing (3) for manufacturing LD chip | tip. It is explanatory drawing (4) for manufacturing LD chip | tip. It is explanatory drawing (5) for manufacturing LD chip | tip. It is explanatory drawing (6) for manufacturing LD chip | tip. It is explanatory drawing (7) for manufacturing LD chip | tip. It is explanatory drawing (8) for manufacturing LD chip | tip. It is explanatory drawing (9) for manufacturing LD chip | tip. It is explanatory drawing (10) for manufacturing LD chip | tip. It is explanatory drawing (11) for manufacturing LD chip | tip. It is explanatory drawing (12) for manufacturing LD chip | tip. It is explanatory drawing for demonstrating individualization of LD chip | tip. It is explanatory drawing for adhere | attaching several LD chip | tip on the support substrate for affixing. It is explanatory drawing for demonstrating peeling of an InP board | substrate. It is explanatory drawing for demonstrating the sticking to Si waveguide. It is a structural view of a semiconductor optical element which is a comparative example of the present invention.

  Hereinafter, an embodiment of the present invention (hereinafter referred to as “the present embodiment”) will be described in detail with reference to the drawings. Each figure is only schematically shown so that the present invention can be fully understood. Therefore, the present invention is not limited to the illustrated example. Moreover, in each figure, the same code | symbol is attached | subjected about the common component and the same component, and those overlapping description is abbreviate | omitted.

(First embodiment)
(Description of configuration)
FIG. 1 is a structural diagram of a semiconductor optical element according to the first embodiment of the present invention.
The semiconductor optical element 100 includes an SOI (Silicone on Insulate) photonics substrate 31 on which an Si optical waveguide is formed, and an LD chip 35 as a laser diode element that is intermolecularly bonded to the surface of the SOI photonics substrate 31. The SOI photonics substrate 31 includes a Si substrate 32, a SiOx insulating layer 33 stacked on the surface of the Si substrate 32, and a Si optical waveguide 34 stacked on the surface of the SiOx insulating layer 33. In other words, the LD (Laser Diode) chip 35 is laminated on the surface of the Si optical waveguide 34. Moreover, the area of the SOI photonics substrate 31 is about 100 times the area of the LD chip 35.

  The Si optical waveguide 34 is a Si fine wire optical waveguide whose core is silicon and whose cladding is a SiOx insulating film. In the case of PON, the Si optical waveguide 34 is configured such that a wavelength multiplexer / demultiplexer is formed, and multi-wavelength laser beams are combined and coupled to an optical fiber. The LD chip 35 is a Fabry-Perot type semiconductor laser oscillator, and emits light from the active layer 14 sandwiched between the n-InP layer 13 and the p-InP layer 15. ) Is coated. The reflection films 14a at both ends have a reflectance of 70 to 90%, which is different from a general semiconductor laser having a reflectance of several percent on the emission side. Further, the thickness of the clad between the core of the Si optical waveguide 34 and the n-InP layer 13 is 0.1 to 3 μm.

  The active layer 14 is an optical waveguide in which both side surfaces are filled with the p-InGaAsP layer 18, the upper surface is joined to the p-InP layer 15, and the lower surface is joined to the n-InP layer 13. In particular, the evanescent light oozes out on the n-InP layer 13 side.

  FIG. 2 is a diagram for explaining how light resonated in the active layer is coupled to the core of the optical waveguide. The light quantity distribution in the plane perpendicular to the optical axis is drawn in the active layer 14 and the core portion of the Si optical waveguide 34 in the figure. That is, the light oscillated in the active layer 14 exhibits a unimodal light quantity distribution, and the light is drawn into the core of the optical waveguide 34 through the n-InP layer 13. In other words, the active layer 14 and the core of the Si optical waveguide 34 are arranged close to each other, and the evanescent light oozes out from the active layer 14 to the n-InP layer 13 as a cladding layer and the cladding of the Si optical waveguide 34 to activate the active layer 14. Mode coupling of the light wave electromagnetic field occurs between the layer 14 and the core. Here, the n-InP layer 13 has a thickness of 50 to 100 nm (preferably 50 to 70 nm, 65 to 80 nm), and is formed to be the same as or thinner than the thickness of the cladding of the Si optical waveguide 34. . The core of the Si optical waveguide 34 is coated with a reflective film 34a at the rear end so that light is emitted in one direction. A Bragg waveguide may be provided instead of the reflective film.

Hereinafter, a method for manufacturing the semiconductor optical element 100 having the above-described structure will be described.
FIG. 3 is a flowchart for explaining a method for manufacturing a semiconductor optical element according to the first embodiment of the present invention.
First, a plurality of crystal films are deposited on the InP substrate 11 (FIG. 4), and a laminated substrate 36 (FIG. 4) having a predetermined semiconductor laser structure is prepared (S10). Next, a semiconductor manufacturing process is performed on the multilayer substrate 36, and a plurality of LD chips 35 (FIG. 6) are produced on the surface of the multilayer substrate 36 (S20). Next, the plurality of LD chips 35 formed on the surface of the multilayer substrate 36 are separated into pieces by etching (S30). Next, affixing support substrate 30 (FIG. 7) is bonded to the top of the plurality of separated LD chips 35 (S40). Next, the InP substrate 11 is peeled off by etching (FIG. 8, S50), and a plurality of LD chips 35 are adhered to the supporting substrate 30 for attachment. Next, the n-InP layer 13 of each LD chip 35 and the Si optical waveguide 34 of the SOI photonics substrate 31 are intermolecularly bonded (FIG. 9, S60).

FIG. 4 is an explanatory diagram of a semiconductor laser structure.
The LD chip 35 (FIG. 1) as a laser diode element is manufactured by processing a laminated substrate 36 having a predetermined semiconductor laser structure by a laser manufacturing process. The stacked substrate 36 includes an InP substrate 11, an n-InGaAs sacrificial layer 12 stacked on the surface of the InP substrate 11, an n-InP layer 13 stacked on the surface of the n-InGaAs sacrificial layer 12, and an n-InP layer. 13 includes an active layer (MQW layer) 14 laminated on the surface of 13 and a p-InP layer 15 laminated on the surface of the active layer 14, and these are crystal-grown by an organic metal vapor layer (MOVPE) method. .

  The InP substrate 11 is an n-type InP substrate that lattice matches with InGaAs. Here, In is a group III element, and P is a group V element. Note that the lattice constant of InP is 0.586 nm, and the band gap energy is 1.35 eV. The n-InGaAs sacrificial layer 12 is a layer that is removed by etching in order to separate the InP substrate 11 and the n-InP layer 13. That is, the etching rate of the n-InGaAs sacrificial layer 12 needs to be larger than the etching rate of the active layer 14 and the InP substrate 11. The n-InP layer 13 is Si-doped, and the p-InP layer 15 is Mg-doped. The active layer 14 is formed by alternately stacking two thin layers having different band gaps, and is a layer called a multiple quantum well (MQW) structure. The active layer 14 has a structure optimized so as to obtain a desired wavelength and characteristics.

FIG. 5 (FIGS. 5A to 5L) is an explanatory diagram for manufacturing an LD chip.
After the laminated substrate 36 of FIG. 4 is prepared, an insulating film mask 16 is deposited with a SiN film or the like using a CVD (Chemical Vapor Deposition) method or the like, and then a desired insulating mask shape is formed by a photolithography process. (FIG. 5A). Here, a rectangular mask is used.

  Next, as shown in FIG. 5B, unnecessary portions of the p-InP layer 15 and the active layer 14 are etched using the insulating film mask 16 (FIG. 5A) as a mask to form an island-shaped active layer 17. . This etching uses a mixed solution of hydrofluoric acid and nitric acid so that the n-lnP layer 13 is not selectively removed. Then, the insulating film mask 16 is removed by etching with a hydrofluoric acid aqueous solution or the like.

Next, as shown in FIG. 5C, a p-lnGaAsP layer 18 (with a band gap wavelength of about 1.2 μm) having a thickness of about 10 to 50 nm as an etching stop layer, a p-lnP layer 19 by an MOVPE method, A p ⁺ -lnGaAs layer (contact layer) 20 is grown to a desired thickness. FIG. 5C is a cross-sectional view, and the previously formed island-like active layer 17 (p-InP layer 15 and active layer 14) remains.

  Next, as shown in FIG. 5D, an insulating film mask 21 for the ridge waveguide is formed by a CVD method and a photolithography process. The stripe width of this ridge is about 1 to 3 μm. The insulating film mask 21 beside the ridge is for forming a substantially V-shaped window (FIG. 5E) for the n-electrode.

  Next, as shown in FIG. 5E, a ridge type optical waveguide 22 is formed on the insulating film mask 21. At this time, the ridge-type optical waveguide 22 is formed by dry etching until the middle of the p-InP layer 19 and the remaining ridge-type optical waveguide 22 is formed by hydrochloric acid-based wet etching. Here, since the p-lnGaAsP layer 18 has high selectivity with respect to the hydrochloric acid-based etchant, it functions as an etch stop layer, and the ridge-type waveguide 22 is formed with an inverted mesa structure. Then, since the forward mesa shape is formed at the place where the window beside the ridge is formed, the n-type electrode 23 (FIG. 5F) is easily formed without being cut off.

  Next, as shown in FIG. 5F, an n-type electrode 23 such as Au—Ge—Ni is deposited on the entire surface. That is, the n-type electrode 23 is formed on the surface of the insulating film mask 21, the surface of a substantially V-shaped window, and the surface of the p-lnGaAsP layer 18.

Next, as shown in FIG. 5G, the insulating film mask 21 is removed by etching, and unnecessary portions of the n-type electrode 23 are removed by lift-off.
Next, as shown in FIG. 5H, an insulating film 24 is formed to cover the surface. However, the insulating film 24 is formed in two lines on the upper portion of the ridge-type waveguide 22, and a stripe-shaped window for p-type electrode contact is formed. Next, as shown in FIG. 5I, a photoresist 25 (FIG. 5I) is applied except for the stripe-shaped window for p-type electrode contact.

Next, as shown in FIG. 5J, a p-type electrode 26 such as Au—Zn is deposited, and the p-type electrode 26 on the photoresist 25 is removed by lift-off. Thereby, a line-shaped p-type electrode 26 is formed on the ridge-type waveguide 22.
Next, as shown in FIG. 5K, both sides of the ridge-type waveguide 22 are embedded with polyimide 27 and cured by heat treatment. At this time, the portion of the substantially V-shaped window in which the n-type electrode 23 is formed is also filled with the polyimide 27. In the drawing, the end face of the n-type electrode 23 is exposed.
Next, as shown in FIG. 5L, after the surface is protected by the insulating film 28, patterning is performed to form pad electrodes 29 (29a, 29b, 29c, 29d). The n-type electrode 23 is connected to pad electrodes 29 a and 29 b, and the pad electrodes 29 c and 29 d are connected to a line-shaped p-type electrode 26 formed on the ridge-type waveguide 22.

Next, as shown in FIG. 6, the LD chip 35 is separated into pieces by performing a photolithography process and dry etching on the InP substrate 11.
Next, as shown in FIG. 7, the plurality of separated LD chips 35 and the supporting substrate 30 for bonding are bonded on the InP substrate 11.
Next, as shown in FIG. 8, the n-InGaAs sacrificial layer 12 is etched, and the lnP substrate 11 is peeled off. At this time, only the LD chip 35 at a desired position is selectively peeled off.

  Next, as shown in FIG. 9, the LD chip 35 at a desired position is attached to the SOI photonics substrate 31 and further peeled off from the attaching support substrate 30. At this time, the n-InP layer 13 of the LD chip 35 and the Si optical waveguide 34 of the SOI photonics substrate 31 are bonded by intermolecular bonding by heat treatment. Thereby, the semiconductor optical element 100 (FIG. 1) is manufactured. That is, in the semiconductor optical element 100, the LD chip 35 peeled from the Si substrate 32 is bonded to the surface of the SOI photonics substrate 31 on which the SiOx insulating layer 33 and the Si optical waveguide 34 are formed by intermolecular bonding.

  This enables mounting by mask alignment and improves the mounting position accuracy in the perpendicular direction with respect to the SOI photonics substrate 31. Further, unlike the conventional semiconductor process in which the InP substrate 11 is attached to the surface of the SOI photonics substrate 31, the expensive InP substrate 11 can be used without being wasted. In the semiconductor optical element 100, the light emitted from the active layer 14 of the LD chip 35 is evanescently coupled to the core of the Si optical waveguide 34. Thereby, the light emitted from the active layer 14 is drawn into the core of the Si optical waveguide 34.

By using the process and structure of this embodiment, simplification of mounting and cost reduction are expected.
(Description of operation)
On the SOI photonics substrate 31, a desired optical circuit (for example, a waveguide 34) and electrical wiring / electrical circuit are formed. The LD chip 35 is separated and separated from the optical coupling portion, and the peeled LD chip 35 is formed. Joined by intermolecular bonds. Thereafter, the electrical wiring of the SOI photonics substrate 31 and the pad electrodes 29 (29a, 29b, 29c, 29d) of the LD chip 35 are connected by wire bonding or the like. As a result, the laser light oscillated in the active layer 14 when a forward current flows through the LD chip 35 leaks into the core of the Si optical waveguide 34 due to evanescent coupling. Thereby, the light resonated in the active layer 14 is drawn into the core of the Si optical waveguide 34.

FIG. 10 is a structural diagram of a semiconductor optical element which is a comparative example of the present invention.
The optoelectronic module 50 as a semiconductor optical element is a single-core bidirectional communication module in which an optical waveguide 34b formed on a Si substrate 32b and an electric circuit mounted on the Si substrate 32b are arranged adjacent to each other. is there. The electric circuit includes a laser diode 51, a monitoring photodiode 52, a photodiode 53, and a transimpedance amplifier (TIA) 54. In the optical waveguide 34b, a wavelength multiplexer / demultiplexer 55 and a spot size converter 56 are formed. Here, the area of the optical waveguide 34b is about 16 times the area of the laser diode 51, and is usually in the range of 10 to 100 times.

  The wavelength multiplexer / demultiplexer 55 is composed of a silicon thin wire waveguide, guides the light emitted from the laser diode 51 to the spot size converter 56, and enters the light guided from the spot size converter 56 into the photodiode 53. It is something to be made. In addition, since bidirectional communication is performed with one optical fiber, the wavelength of light incident on the photodiode 53 is cut off from the wavelength of light emitted by the laser diode 51 provided at the other end of the optical fiber. I have to. For example, when the transmission wavelength of the laser diode 51 is 1310 nm and the reception wavelength of the photodiode 53 is 1490 nm, the wavelength of light incident on the photodiode 53 is emitted by the laser diode 51 provided at the other end of the optical fiber. The wavelength 1310 nm of the emitted light is cut off.

  The spot size converter 56 couples between an optical fiber (not shown) and a silicon fine wire waveguide (wavelength multiplexer / demultiplexer 55), and uses a tapered taper type. That is, the spot size converter 56 has a function of converting the size of the light beam spot.

  The transimpedance amplifier 54 converts the current generated by the photodiode 53 into a voltage while virtually grounding the voltage across the photodiode 53. The monitoring photodiode 52 is for monitoring the optical output of the laser diode 51 and performing feedback control.

  In the optoelectronic module 50, the laser diode 51 and the photodiode 53 are arranged close to the end face of the optical waveguide 34b, and it is necessary to align the laser diode 51 and the photodiode 53 with the wavelength multiplexer / demultiplexer 55. This alignment needs to be performed not only in the direction parallel to the surface of the Si substrate 32b but also in the direction perpendicular to the surface of the Si substrate 32b.

(Explanation of effect)
As described above, the optoelectronic fusion device 50 of the comparative example in which the optical waveguide 34 and the semiconductor laser are coupled is one in which the light of the semiconductor laser is incident on the end face of the optical waveguide 34. This optoelectronic device mounting method uses active alignment that aligns with the laser light that is actually oscillated by passing an electric current through the semiconductor laser, and alignment that aligns the alignment mark without laser oscillation. There is a passive alignment to be performed. In passive alignment, since an axis deviation is expected due to alignment accuracy, it is necessary to provide a structure with improved tolerance against a certain degree of positional deviation.

  However, in the semiconductor optical element 100 of the present embodiment, the positional accuracy in the mask alignment can be ensured by the semiconductor process, so that the alignment accuracy in the horizontal direction with respect to the surface of the SOI photonics substrate 31 can be improved. In addition, since the LD chip 35 peeled from the Si substrate 32 is bonded to the surface of the SOI photonics substrate 31 by intermolecular bonding, alignment is performed also in the direction perpendicular to the surface of the SOI photonics substrate 31. There is no need. That is, according to this embodiment, mounting is possible without using active alignment, and cost reduction is expected.

  In the technique described in the non-patent document, most of the InP substrate bonded on the SOI photonics substrate 31 is not used as a laser element, and the utilization rate of the expensive InP substrate is poor. The utilization efficiency of the InP substrate can be improved, and further cost reduction is expected. For example, in the photoelectric fusion module 50 of the comparative example, the area of the optical waveguide 34b is about 16 times (generally 10 to 100 times) the area of the laser diode 51. The InP substrate that is 15 times the area of the laser diode 51 is wasted.

(Modification)
The present invention is not limited to the embodiments described above, and various modifications such as the following are possible.
(1) In the above embodiment, a Fabry-Perot (FP) type semiconductor laser is described in the above embodiment, but a distributed feedback laser (DFB-LD (Distributed Feedback-Laser Diode)) or Bragg is used. The present invention can also be applied to a DBR (Distributed Bragg Reflector) type semiconductor laser using reflection.
(2) In the above embodiment, the semiconductor laser structure using the InP substrate 11 has been described. However, the present invention can also be applied to a structure using a GaAs substrate.
(3) In the above embodiment, the embedded Si optical waveguide 34 has been described. However, the present invention can be applied even when a rib-type Si optical waveguide is used.
(4) Although the above embodiment does not describe a mode conversion waveguide structure as described in non-patent literature, it is applicable even when a mode conversion structure is used.

11 InP substrate 12 n-InGaAs sacrificial layer 13 n-InP layer 14 Active layer (MQW layer)
14a Reflective film 15 p-InP layer 16 Insulating film mask (SiN)
17 island-like active layer 18 p-InGaAsP layer (etching stop layer)
19 p-InP layer 20 p ⁺ -InGaAs layer 21 Insulating film mask 22 Ridge-type optical waveguide 23 n-type electrode (Au-Ge-Ni)
24 Insulating film 25 Photoresist 26 P-type electrode (Au-Zn)
27 Polyimide 28 Insulating film 29 Pad electrode 30 Support substrate 31 for bonding 31 SOI photonics substrate 32 Si substrate 33 SiOx insulating layer 34, 34a, 34b Si optical waveguide 34a Reflective film 35 LD chip 36 Laminated substrate 50 Photoelectric fusion module (semiconductor optical element) )
51 Laser diode 52 Photodiode for monitoring 53 Photodiode 54 Transimpedance amplifier 55 Wavelength multiplexer / demultiplexer 56 Spot size converter 100 Semiconductor optical element

Claims (7)

A semiconductor optical element manufacturing method for manufacturing a semiconductor optical element, comprising: a group III-V semiconductor laser element; and a photonics substrate having an optical waveguide through which resonant light of the group III-V semiconductor laser element is guided.
A first step of fixing the plurality of group III-V semiconductor laser elements formed on the semiconductor substrate to a support member;
A second step of etching and peeling the III-V semiconductor laser element fixed in the first step and the semiconductor substrate;
And a third step of intermolecular bonding of the III-V semiconductor laser element peeled off in the second step and the photonics substrate. In the semiconductor optical element manufacturing method according to claim 1,
The photonics substrate has an optical waveguide formed thereon,
A semiconductor optical device manufacturing method, wherein the core of the optical waveguide and the active layer of the group III-V semiconductor laser device are guided by evanescent light. A semiconductor optical element comprising a group III-V semiconductor laser element and a photonics substrate through which the resonant light of the group III-V semiconductor laser element is guided to an optical waveguide,
The III-V semiconductor laser device has an active layer and a cladding layer sandwiching the active layer,
Any one of the clad layers and the photonics substrate are intermolecularly bonded. A semiconductor optical element, wherein: The semiconductor optical element according to claim 3,
The semiconductor optical element, wherein the active layer and the core of the optical waveguide are guided by evanescent coupling. The semiconductor optical element according to claim 3,
A semiconductor optical element, wherein the active layer and the core of the optical waveguide are mode-coupled. In the semiconductor optical element according to any one of claims 3 to 5,
The clad layer bonded between the molecules has a thickness of 50 nm to 100 nm. A semiconductor optical element, wherein: The semiconductor optical element according to any one of claims 3 to 6,
The area of the photonics substrate is 10 to 100 times the area of the group III-V semiconductor laser element.

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