JP2016051813A - Semiconductor device manufacturing method, semiconductor device, imaging device and imaging device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having a JFET (Junction FET) which can inhibit characteristic fluctuation due to positional deviation of a mask pattern of JFET while achieving refinement of an element.SOLUTION: A manufacturing method of a junction field effect transistor comprises: a first process of forming on a semiconductor substrate 100 where a first conductivity type first semiconductor region 121 which forms a gate region of the junction field effect transistor is arranged, a contact hole 106 included in the first semiconductor region 121 in plan view; a second process of implanting an impurity having a second conductivity type opposite to the first conductivity type through the contact hole 106 to form a second conductivity type second semiconductor region 204 which forms one of a source region and a drain region of the junction field effect transistor; and a third process of forming in the contact hole, a conductor 207 electrically connected to the second semiconductor region.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device manufacturing method, a semiconductor device, an imaging device, and an imaging device manufacturing method.

  A semiconductor device having a junction field effect transistor (JFET) is known. As a method for manufacturing a JFET, Patent Document 1 discloses a configuration in which a source region is formed larger than a contact plug electrically connected to the source region.

JP 2004-63650 A

  JFETs are arranged adjacent to each other so that a source region and a gate region form a PN junction. The JFET described in Patent Document 1 can suppress a short-circuit between the gate region and the contact plug by making the source region larger than the contact plug connected to the source region. However, in order to enlarge the source region, further examination is necessary from the viewpoint of miniaturization of the JFET. The same can be said because the drain region is also arranged adjacent to the gate region so as to form a PN junction.

  In view of the above problems, an object of the present invention is to provide a method of manufacturing a semiconductor device having a JFET capable of suppressing a short circuit between a source region or a drain region and a gate region while miniaturizing an element.

  The present invention relates to a method for manufacturing a semiconductor device having a junction field effect transistor, wherein a planar surface is formed on a semiconductor substrate on which a first semiconductor region of a first conductivity type serving as a gate region of the junction field effect transistor is disposed. A first step of forming a contact hole enclosed in the first semiconductor region in view, and a second conductivity type impurity of a conductivity type opposite to the first conductivity type is ion-implanted through the contact hole to thereby form a junction field effect transistor A second step of forming a second semiconductor region of the second conductivity type to be either the source region or the drain region of the first, and a second step of forming a conductor electrically connected to the second semiconductor region in the contact hole And 3 steps.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the manufacturing method of the semiconductor device which can suppress the short circuit with the source region or drain region of JFET, and a gate region.

Cross-sectional schematic diagram for explaining a method of manufacturing a semiconductor device Plane schematic view and cross-sectional schematic diagram of semiconductor device Cross-sectional schematic diagram for explaining a method of manufacturing a semiconductor device Plane schematic view and cross-sectional schematic diagram of semiconductor device Cross-sectional schematic diagram for explaining a method of manufacturing a semiconductor device Plane schematic view and cross-sectional schematic diagram of semiconductor device Circuit diagram of imaging device Plane schematic diagram and cross-sectional schematic diagram of imaging device

  A feature of the manufacturing method according to the embodiment of the present invention is that a semiconductor region which is either a source region or a drain region of a junction field effect transistor (JFET) is formed using a contact hole. The present embodiment can be applied to both the source region and the drain region, but in the following description, a case will be described in which one region described above is a source region and the other region is a drain region.

  A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

  In describing the relative positional relationship of each semiconductor region in the present specification, the surface of the semiconductor substrate when expressed as "depth from the surface of the semiconductor substrate" refers to each semiconductor region disposed on the semiconductor substrate. The surface on the side where the wiring layer electrically connected to is arranged. “Depth” refers to the distance from this surface. Further, “from the surface of the semiconductor substrate” may be omitted and simply expressed as “depth”, but they have the same meaning.

  Before explaining the manufacturing method, for the sake of understanding, a schematic cross-sectional view of an example of a semiconductor device obtained by the manufacturing method of this embodiment will be described with reference to FIG. The JFET 110 has a drain region 101, gate regions 102 and 111, a channel region 103, and a source region 104 disposed on the semiconductor substrate 100. In FIGS. 1A to 1C, the gate region is divided into two regions (a region denoted by reference numeral 102 and a region denoted by reference number 111).

  However, as described later with reference to FIG. 2C and the like, the gate region is one continuous region in a cross section different from the cross section shown in FIG. The channel region 103 is arranged in parallel with the surface of the semiconductor substrate 100, and the source region 104 and the channel region 103 are arranged so as to overlap in plan view.

  On the surface of the semiconductor substrate 100, an insulating film 105, which will be described in detail later, and a contact plug 207 provided in a contact hole of the insulating film 105 are provided. The drain region 101, the channel region 103, and the source region 104 are arranged so that charges move in a direction parallel to the surface of the semiconductor substrate 100.

  A manufacturing method of a semiconductor device according to an embodiment of the present invention includes at least a first process, a second process, and a third process described below.

  First, as shown in FIG. 1A, an insulating film 105 is formed on a semiconductor substrate 100 on which a first semiconductor region 121 of a first conductivity type is disposed, and the first semiconductor region is formed on the insulating film 105 in plan view. A contact hole (first contact hole) 106 is formed so as to be included in 121 (first step). A part of the first semiconductor region 121 is a region that later becomes the gate region 111. In the example of FIG. 1A, the second conductivity type semiconductor region to be the drain region 101 and the second conductivity type semiconductor region to be the channel region 103 shown in FIG. .

  Then, as shown in FIG. 1B, ion implantation of the second conductivity type opposite to the first conductivity type is performed on the first semiconductor region 121 through the contact hole 106. Thus, the second semiconductor region 204 to be the JFET source region 104 is formed (second step).

  Then, as shown in FIG. 1C, a conductor that is electrically connected to the second semiconductor region 204 in FIG. 1B is formed in the contact hole 106. Thereby, the contact plug 207 is formed (third step).

  In the JFET 110 obtained by these steps, the source region 104 and the contact plug 207 have substantially the same shape in plan view. The JFET 110 has a channel region 103 that is electrically connected to the source region 104. The channel region 103 is disposed deeper in the semiconductor substrate 100 than the source region 104, forms a PN junction with the gate regions 102 and 111, and has a structure in which the channel region 103 is sandwiched between the gate regions 102 and 111. . Further, the channel region 103 is electrically connected to the drain region 101 on the side thereof (both ends in the left-right direction in FIG. 1C). In plan view, the source region 104 and the channel region 103 are arranged to overlap each other, and the source region 104 is sandwiched between the gate regions 111.

  According to the present embodiment, in the second step, ion implantation is performed on the semiconductor substrate 100 (first semiconductor region 121) through the contact hole 106 in which the contact plug 207 electrically connected to the source region 104 is disposed later. Then, the second semiconductor region 204 to be the source region 104 is formed. Accordingly, it is possible to suppress a short circuit between the gate region 111 and the source region 104 via the contact plug 207 without unnecessarily increasing the source region 104.

  Hereinafter, specific examples of the semiconductor device and the imaging device using the manufacturing method described in this embodiment will be described.

  In each embodiment, the first conductivity type is P type, and the second conductivity type is N type opposite to the first conductivity type. A JFET whose gate region is P-type will be described. However, the conductivity type is not limited to this, and the present invention can also be applied to a JFET whose gate region is N-type by changing the conductivity type of each semiconductor region to the opposite conductivity type. Alternatively, the drain region 101 shown in FIG. 1C can be a source region, and the source region 104 can be a drain region.

(Example 1)
A method for manufacturing the semiconductor device 120 of this embodiment will be described with reference to FIGS. In the drawings, parts having similar functions are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, the structure of the semiconductor device after the contact plug is formed will be described with reference to FIG. FIG. 2A is a schematic plan view of the semiconductor device 120 of this embodiment. Here, the schematic plan view is a diagram showing the semiconductor device 120 in a plan view. Further, the plan view refers to viewing from the direction perpendicular to the surface of the semiconductor substrate 100. The same applies to the following embodiments. FIG. 2B is a schematic cross-sectional view taken along line AB of FIG. FIG.2 (c) is a cross-sectional schematic diagram in CD of Fig.2 (a).

  The semiconductor device 120 includes a JFET 110 disposed on the semiconductor substrate 100. The semiconductor substrate 100 means the whole substrate made of a semiconductor, and indicates the whole member on which each semiconductor region constituting the JFET 110 is arranged.

  As shown in FIG. 2C, a contact plug 209 is electrically connected to the drain region 101, and a contact plug 208 is electrically connected to the gate region 102 (111). As shown in FIG. 2B, a contact plug 207 is electrically connected to the source region 104. Contact plugs 207, 208, and 209 are disposed on the insulating film 105.

  As shown in FIG. 2A, the drain region 101 is disposed so as to include the gate regions 102 and 111, the source region 104, and the channel region 103 in plan view. The drain region 101 may be composed of an N-type semiconductor substrate 100, or a P-type well is formed in the N-type semiconductor substrate 100, and an N-type semiconductor region is formed in a part of the P-type well. May be configured.

  An insulating film 105 and a wiring layer (not shown) are disposed on the semiconductor substrate 100. The insulating film 105 can be made of an inorganic material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. Alternatively, silicon glass in which impurities are added to silicon, such as a BPSG (Boron Phosphorus Silicon Glass) film, may be used. The insulating film 105 functions as an interlayer insulating film disposed between the semiconductor substrate 100 and the wiring layer. A contact plug 207 that is electrically connected to the source region 104 is disposed on the insulating film 105.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIG. FIGS. 3A to 3D, 3F, and 3H show states in each manufacturing process at the cross section taken along line AB in FIG. 2A. FIG. 3G shows a state of the cross section taken along the line CD in FIG. 2A in the same step as FIG.

  First, the semiconductor substrate 100 provided with the P-type semiconductor region (first semiconductor region) 320 is prepared. The semiconductor substrate 100 in which the P-type semiconductor region 320 is arranged in advance may be prepared, or a semiconductor substrate in which the P-type semiconductor region 320 is not formed is prepared, and then the P-type semiconductor region is formed by ion implantation or the like. May be. The latter method will be described below.

  As shown in FIG. 3A, a photoresist film is formed on a semiconductor substrate 100 made of a silicon wafer or the like. Then, by using a photolithography method, an opening 316 is formed by patterning the photoresist film, and a mask 315 is formed. By using this mask 315 to ion-implant N-type impurities, an N-type semiconductor region 314 (fifth semiconductor region) is formed in the semiconductor substrate 100. Although the N-type semiconductor region 314 is formed here by ion implantation, it may be formed by providing an N-type epitaxial layer. Thereafter, the mask 315 is removed.

  Next, as illustrated in FIG. 3B, a mask 318 having an opening 319 is formed on the semiconductor substrate 100 by a method similar to the mask 315. The opening 319 is included in the N-type semiconductor region 314 of FIG.

  A P-type semiconductor region (sixth semiconductor region) 317 is formed by implanting P-type ions into the N-type semiconductor region 314 using the mask 318.

  Here, of the N-type semiconductor region 314 shown in FIG. 3A, the region that is not implanted with P-type ions and remains as the N-type semiconductor region is the N-type semiconductor region (first) in FIG. 3 semiconductor regions) 301. As shown in FIG. 3B, the P-type semiconductor region 317 is surrounded by the N-type semiconductor region 301. As will be described later, the N-type semiconductor region 301 becomes a drain region. Thereafter, the mask 318 is removed.

  Next, as shown in FIG. 3C, a mask (first mask) 321 having an opening 322 is formed on the semiconductor substrate 100 in the same manner as the mask 315. The opening 322 is disposed so as to be included in the N-type semiconductor region 301 in plan view. And as shown in FIG.3 (c), the both ends of the opening part 322 are distribute | arranged on the N-type semiconductor region 301 in at least one cross section. More specifically, in one cross section, both ends defining the outer periphery of the opening 322 are positioned inside both ends of the N-type semiconductor region 301 in the left-right direction, and above both ends of the P-type semiconductor region 317 or The P-type semiconductor region 317 is positioned outside both ends.

  Then, N-type ions are implanted into the P-type semiconductor region 317 using the mask 321, thereby extending N in a direction parallel to the surface of the semiconductor substrate 100 as shown in FIG. A type semiconductor region 303 (fourth semiconductor region) is formed. By this step, the P-type semiconductor region 317 shown in FIG. 3B is separated vertically in a certain cross section, and two P-type semiconductor regions (320, 302) are formed. (FIG. 3C).

  Of the two P-type semiconductor regions, the region including the surface of the semiconductor substrate 100 is a P-type semiconductor region (first semiconductor region) 320, and is disposed deeper in the semiconductor substrate 100 than the P-type semiconductor region 320. The region is indicated as a P-type semiconductor region 302. However, in some other cross section, the two P-type semiconductor regions shown in FIG. 3C are continuous and not separated.

  Also, in the step of FIG. 3B, ion implantation is performed with different ion implantation energies to form the P-type semiconductor region 320 and the P-type semiconductor region 302. In the step of FIG. An N-type semiconductor region 303 may be formed therebetween. In this case, it is necessary to perform P-type ion implantation to electrically connect the P-type semiconductor region 320 and the P-type semiconductor region 302.

  The state in which the above process is performed on the semiconductor substrate 100 corresponds to the first process described in the embodiment.

  Next, as illustrated in FIG. 3D, an insulating film 105 is formed on the semiconductor substrate 100. Subsequently, a contact hole 106 is formed by etching a part of the insulating film 105. As shown in the schematic plan view of FIG. 3E, the contact hole 106 is disposed so as to be included in the P-type semiconductor region 320 in a plan view (first step). Note that the mask for etching the contact hole 106 is a mask formed using a photoresist (not shown). Also, as shown in the plan view of FIG. 3E, contact plugs 208 and 209 (see FIG. 2A) are formed in contact holes (third contact holes) 213 and contact holes (second contact holes). ) 212 is also formed at the same time as the contact hole 106.

  Next, as shown in FIGS. 3 (f) and 3 (g), a mask (second) having an opening 323 arranged so as to contain the contact hole 106 in a plan view and covering the contact holes 212 and 213. Mask) 324 is formed. The mask 324 is formed by forming a photoresist film on the insulating film 105 and then patterning it by a photolithography method. Note that the P-type semiconductor region 302 in FIG. 3G can be regarded as the first semiconductor region 121 described in the embodiment.

  Then, an N-type impurity is ion-implanted into a part of the P-type semiconductor region 320 in FIG. 3D through the opening 323 and the contact hole 106, thereby including the surface of the semiconductor substrate 100 and the N-type semiconductor region. An N-type semiconductor region 304 (second semiconductor region) is formed so as to be electrically connected to 303. Therefore, the N-type semiconductor region 304 is formed between the N-type semiconductor region 303 and the surface of the semiconductor substrate 100.

  Here, in the P-type semiconductor region 320 shown in FIG. 3D, a region remaining as a P-type semiconductor region without being implanted with N-type ions is a P-type semiconductor region 311. As a result, the N-type semiconductor region 304 is disposed so as to be sandwiched between the P-type semiconductor regions 311, and the P-type semiconductor region 311 and the N-type semiconductor region 304 form a PN junction (second step).

  Note that the shape of the N-type semiconductor region 304 formed by ion implantation in the P-type semiconductor region 320 through the contact hole 106 is substantially the same as the shape of the source region. The reason why they are described as being substantially the same is that the shape may differ somewhat depending on the subsequent heat treatment.

  Next, as shown in FIG. 3H, after removing the mask 324, a conductor is embedded in the contact hole 106 and the contact holes 212 and 213 in FIG. Is formed (third step).

  The JFET is formed through the above steps. The P-type semiconductor region 311 shown in FIG. 3F becomes the gate region 111 as shown in FIG. 3H, and the P-type semiconductor region 302 shown in FIG. 3F is shown in FIG. 3H. The gate region 102 is formed. Further, the N-type semiconductor region 303 becomes the channel region 103, the N-type semiconductor region 301 becomes the drain region 101, and the N-type semiconductor region 304 becomes the source region 104. Thereafter, wirings and the like are formed by a well-known method to complete a semiconductor device having a JFET.

  In this manner, by forming the contact plug 207 in the contact hole 106 used in the ion implantation in the second step, it is possible to suppress the positional deviation between the source region 104 and the contact plug 207. As a result, it is possible to prevent the contact plug 207 and the gate region 111 from contacting each other and the gate region 111 and the source region 104 of the JFET 110 from being short-circuited.

  Note that the impurity in the N-type semiconductor region 304 may be diffused by heat-treating the semiconductor substrate 100 after the second step and before the contact plug 207 is formed.

  The area of the contact hole 106 is preferably larger than at least the area of the contact hole 212. This is because the contact resistance can be lowered by increasing the contact area between the source region 104 and the contact plug 207.

  Furthermore, it is preferable to perform ion implantation so that the impurity concentration of the N-type semiconductor region 304 is higher than the impurity concentration of the N-type semiconductor region 303 in the second step. Thereby, the contact resistance between the contact plug 207 and the source region 104 can be lowered. Therefore, according to such a configuration, the voltage drop due to the drain current supplied to the JFET 110 can be reduced.

(Example 2)
A method for manufacturing the semiconductor device 420 of this embodiment will be described with reference to FIGS. In the drawings, parts having the same functions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The difference between the first embodiment and the present embodiment is that, in the first embodiment, the channel region 103 is arranged in a direction parallel to the surface of the semiconductor substrate 100, whereas the channel region 403 of the present embodiment is different from the first embodiment. In other words, the semiconductor substrate 100 is arranged in a direction perpendicular to the surface.

  First, the structure of the JFET after the contact plug is formed will be described with reference to FIG. FIG. 4A is a schematic plan view of a semiconductor device 420 according to the second embodiment of the present invention. FIG. 4B is a schematic cross-sectional view taken along line AB shown in FIG. Components having the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  The semiconductor device 420 includes the semiconductor substrate 100 and has a JFET 410. The JFET 410 has an N-type drain region 101, a P-type gate region 402, an N-type source region 104, and an N-type channel region 403.

  The channel region 403 is disposed at a position deeper than the source region 104 in the semiconductor substrate 100 so as to extend in a direction perpendicular to the surface of the semiconductor substrate 100. The source region 104 and the channel region 403 are arranged so as to overlap in a plan view, and the source region 104 and the channel region 403 are sandwiched between the gate regions 402 to form a PN junction.

  Next, a method for manufacturing the JFET 410 along the line AB in FIG. 4A will be described with reference to FIG. FIG. 5 shows steps after FIG. 3C described in the first embodiment. Since the process of the present embodiment is the same up to the process described with reference to FIG.

  As shown in FIG. 5A, an opening 526 is provided on the semiconductor substrate 100 in which the N-type semiconductor region (third semiconductor region) 301 and the P-type semiconductor region (sixth semiconductor region) 527 are arranged. A mask 525 is formed. The mask 525 is provided so that the opening 526 is included in the P-type semiconductor region 527 in plan view.

  Then, by performing N-type ion implantation through the opening 526 using the mask 525, the N-type semiconductor region including the surface of the semiconductor substrate 100 and being electrically connected to the N-type semiconductor region 303 is used. 528 is formed. The N-type semiconductor region 528 is formed to a depth that is electrically connected to the N-type semiconductor region 301. Alternatively, the N-type semiconductor region 528 may be formed from the surface of the semiconductor substrate 100 to a depth that is electrically connected to the N-type semiconductor region 301.

  Next, as shown in FIG. 5B, an insulating film 105 having contact holes 106 is formed. At this time, other contact holes for forming contact plugs 208 and 209 are formed in the insulating film 105 in the same manner as described with reference to FIG. The contact hole 106 is formed so as to overlap with the P-type semiconductor region 527 in plan view (so as to be included in the P-type semiconductor region 527).

  After that, as described with reference to FIGS. 3F and 3G in the first embodiment, the opening 530 is disposed so as to include the contact hole 106 in a plan view, and covers the other contact holes. A mask (second mask) 529 is formed. This mask 529 is made of a photoresist. Then, N-type ion implantation is performed on a part of the P-type semiconductor region 527 through the opening 530 and the contact hole 106 to form an N-type semiconductor region 304 at a position shallower than the N-type semiconductor region 528 (FIG. 5 ( c)).

  Here, the N-type semiconductor region 304 is formed in a part of the P-type semiconductor region 527 in FIG.

  Further, when the N-type semiconductor region 528 is arranged up to the surface of the semiconductor substrate 100, the N-type semiconductor region 304 is formed in a part of the N-type semiconductor region 528. That is, in this case, a part of the N-type semiconductor region 528 becomes a channel region and the other part becomes a source region. Therefore, the N-type semiconductor region 528 is a region that becomes at least a part of the channel region.

  Next, the mask 529 is removed.

  Subsequently, as shown in FIG. 5D, using the insulating film 105 having the contact hole 106 as a mask, a conductor is formed in the contact hole 106 and other contact holes, and the N-type semiconductor shown in FIG. A contact plug 207 that is electrically connected to the region 304 is formed. At the same time, contact plugs 208 and 209 are formed.

  Through the above steps, the JFET 410 shown in FIG. 5D is formed. The P-type semiconductor region 502 becomes the gate region 402. Further, the N-type semiconductor region 528 becomes the channel region 403, the N-type semiconductor region 301 becomes the drain region 101, and the N-type semiconductor region 304 becomes the source region 104.

  Note that the contact between the contact plug 207 and the P-type gate region 402 can be further suppressed by diffusing impurities in the N-type semiconductor region 304 by heat treatment after the step of FIG.

(Example 3)
FIG. 6 shows a semiconductor device 520 according to the third embodiment of the present invention. FIG. 6A is a schematic plan view of the semiconductor device 720 of this example. FIG. 6B is a schematic cross-sectional view taken along line CD of FIG. Components having the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  The difference between the present embodiment and the first embodiment is that a plurality of openings (contact holes) for forming a semiconductor region serving as a source region are arranged for one JFET. Here, one JFET is a structure having one semiconductor region partitioned by an N-type semiconductor region or an element isolation region by an insulator as a gate region.

  In this embodiment, the mask 705 corresponds to the insulating film 105 of the first embodiment, and the contact hole 706 corresponds to the contact hole 106 of the first embodiment. A source region 704 corresponds to the source region 104 of the first embodiment. The gate region 711 corresponds to the gate region 111 of the first embodiment, and the contact plug 707 corresponds to the contact plug 207 of the first embodiment.

  A difference between the present embodiment and the first embodiment is that a mask (insulating layer) 705 having a plurality of contact holes 706 is provided so as to be included in the same P-type semiconductor region in plan view, and a contact plug 707 is provided. That is, a plurality of source regions 704 are configured. Here, the same means a semiconductor region forming one region in plan view.

  This will be described below.

  As shown in FIG. 6A, in this embodiment, three contact plugs 707 are arranged for the semiconductor device 720.

  Therefore, as shown in FIG. 6B, the mask 705 has a plurality of contact holes 706. The plurality of contact holes 706 are arranged so as to be enclosed in a gate region 711 which is a P-type semiconductor region as shown in FIG. 6A in plan view.

  Then, a JFET 710 is formed through a plurality of contact holes 706 by the same method as the manufacturing method described in the first embodiment. Thereby, a plurality of source regions 704 are formed corresponding to the plurality of contact holes 706. The plurality of source regions 704 are electrically connected to the common channel region 103. The gate region 711 is composed of another part of the P-type semiconductor region 320 and is arranged so as to sandwich each of the plurality of source regions 104.

  Further, a contact plug 707 is formed in each of the plurality of contact holes 706.

  In this manner, by adopting a configuration in which the contact holes 706 are plural, the substantial area of the source region 704 can be increased. Thereby, the contact resistance between the source region 704 and the contact plug 707 can be lowered.

  However, here, as a representative example, the number of contact holes 706 is three, but the number is not particularly limited as long as the number is plural. According to such a configuration, the JFET 710 can be driven at high speed. This configuration can also be applied to other embodiments.

(Application example to imaging device)
The semiconductor device manufacturing method described in the first to third embodiments can be used for various semiconductor devices. Here, an imaging device will be described as an example of a semiconductor device.

  FIG. 7 shows a circuit diagram for one pixel of an image pickup apparatus using a JFET obtained by the manufacturing method according to the embodiment of the present invention. FIG. 8 shows a schematic plan view and a cross section for explaining the characteristics of one pixel of the imaging device.

  In this embodiment, the JFET 410 of Embodiment 2 is used as the pixel amplification transistor 820.

  In this embodiment, the signal charge is assumed to be a hole, and each transistor will be described as a P-type MOS transistor and an N-type JFET.

  In FIG. 7, the photoelectric conversion unit generates charge pairs of an amount corresponding to the amount of incident light by photoelectric conversion, and accumulates holes as signal charges. For example, here, a photodiode 816 is used as the photoelectric conversion unit.

  The transfer unit transfers holes generated in the photodiode 816. For example, here, a transfer transistor 817 is used as the transfer unit. The transfer transistor 817 transfers holes of the photodiode 816 to an input node of an amplification transistor 820 described later.

  A charge holding portion 818 is generated in the photodiode 816 and holds holes transferred by the transfer transistor 817. The charge holding unit 818 is disposed on the semiconductor substrate 100 and is configured by the gate region of the JFET 410. The gate region is composed of a P-type semiconductor region.

  The amplification unit includes an amplification transistor 820, and amplifies and outputs a signal based on the holes transferred by the transfer transistor 817.

  A predetermined voltage is supplied to the drain of the amplification transistor 820. The amplification transistor 820 can form a source follower circuit together with a current source (not shown).

  The reset unit sets at least the potential of the FD to a predetermined potential. For example, here, a reset transistor 819 is used as the reset unit. The source of the reset transistor 819 is electrically connected to the gate of the amplification transistor 820. A predetermined voltage is supplied to the drain of the reset transistor 819. Therefore, the reset transistor 819 can set the gate potential of the amplification transistor 820 to a predetermined potential.

  FIG. 8A is a schematic plan view of one pixel, FIG. 8B is a schematic cross-sectional view taken along line AB of FIG. 8A, and FIG. 8C is FIG. It is a cross-sectional schematic diagram along the CD line.

  Here, the N-type semiconductor region 904 corresponds to the source region 104 of the second embodiment. Further, the N-type semiconductor region 903 corresponds to the channel region 403 of the second embodiment, and the P-type semiconductor region 902 corresponds to the gate region 402 of the second embodiment. The N-type semiconductor region 901 corresponds to the drain region 101, and the contact plug 907 corresponds to the contact plug 207.

  In the pixel 827, a region where each element is formed is partitioned by an insulator separation portion 926 and a PN junction separation layer 925, and a photodiode 816, a transfer transistor 817, an amplification transistor 820, and a reset transistor 819 are arranged in this region.

  As shown in FIG. 8B, the photodiode 816 has a PN junction composed of a P-type semiconductor region 923 and an N-type semiconductor region 901. Further, an embedded type photodiode 816 is configured by arranging an N-type semiconductor region 934 on the surface of the P-type semiconductor region 923. Holes generated by the incident light are accumulated in the P-type semiconductor region 923 as signal charges.

  The transfer transistor 817 includes a P-type semiconductor region 923, a gate electrode 922, and a P-type semiconductor region 921. The holes accumulated in the P-type semiconductor region 923 are transferred to the P-type semiconductor region 921 by the transfer transistor 817. Although the P-type semiconductor region 921 is provided here, the P-type semiconductor region 902 may accumulate holes from the P-type semiconductor region 923 without providing the P-type semiconductor region 921. However, it is preferable to dispose the P-type semiconductor region 902 and the P-type semiconductor region 923 constituting the photodiode 816 in a distant position.

  Here, the reason why the JFET 410 is used for the amplification transistor 820 will be described.

  First, when a MOS transistor is used as the amplification transistor 820, the gate electrode of the amplification transistor is formed on the active region. Therefore, the P-type semiconductor region 921 constituting the FD and the gate electrode need to be electrically connected by wiring.

  On the other hand, when the JFET 410 is used for the amplification transistor 820, the gate region of the JFET 410 is configured by the P-type semiconductor region 902. Therefore, the P-type semiconductor region 921 and the P-type semiconductor region 902 may be connected. It is also possible to form the P-type semiconductor region 921 and the P-type semiconductor region 902 with one P-type semiconductor region.

  As a result, the wiring resistance and the parasitic capacitance can be suppressed, and miniaturization can be achieved by eliminating the wiring. Further, by forming the JFET 410 in the amplification transistor 820, the influence of 1 / f noise generated at the interface between the gate oxide film and the silicon substrate can be suppressed as compared with the MOS transistor.

  As shown in FIG. 8C, the reset transistor 819 includes a P-type semiconductor region 928 serving as a drain region, a gate electrode 929, and a P-type semiconductor region 902 serving as a source region. The P-type semiconductor region 902 constitutes the gate region of the JFET 410.

  Here, the JFET 410 according to the second embodiment has been described as the JFET serving as the amplification transistor 820, but the JFET 110 according to the first embodiment may be used.

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 106 Contact hole 110 Junction field effect transistor 120 Semiconductor device 121 1st semiconductor region 204 2nd semiconductor region 207 Contact plug

Claims (12)

A method of manufacturing a semiconductor device having a junction field effect transistor,
A first contact included in the first semiconductor region in plan view on a semiconductor substrate on which a first semiconductor region of a first conductivity type is disposed, a part of which becomes a gate region of the junction field effect transistor A first step of forming a hole;
Through the first contact hole, ion implantation of the second conductivity type opposite to the first conductivity type is performed, and the second conductivity type second ion which becomes one of the source region or the drain region of the junction field effect transistor. A second step of forming two semiconductor regions in the first semiconductor region;
Forming a conductor electrically connected to the second semiconductor region in the first contact hole;
A method for manufacturing a semiconductor device, comprising: And a step of forming a second conductivity type fourth semiconductor region to be a channel region,
The fourth semiconductor region is ion-implanted with a second conductivity type impurity using a first mask having an opening having a shape different from that of the contact hole in plan view. The fourth semiconductor region is formed such that the second semiconductor region is positioned between the fourth semiconductor region and the fourth semiconductor region and the second semiconductor region are electrically connected to each other. 2. A method for manufacturing a semiconductor device according to 1. Furthermore,
Before forming the fourth semiconductor region,
Forming a second semiconductor region of the second conductivity type by performing second conductivity type ion implantation on the semiconductor substrate;
Forming the sixth semiconductor region of the first conductivity type so as to be included in the fifth semiconductor region by performing ion implantation of the first conductivity type into a part of the fifth semiconductor region; Have
Of the fifth semiconductor region, a portion where the first conductivity type ion implantation is not performed at the time of ion implantation forming the sixth semiconductor region is the source region or the drain region of the junction field effect transistor. A third semiconductor region to be the other region of
At least a portion of the sixth semiconductor region serves as the gate region;
The method for manufacturing a semiconductor device according to claim 2, wherein the third semiconductor region and the fourth semiconductor region serving as the channel region are electrically connected.   4. The method of manufacturing a semiconductor device according to claim 3, wherein an end of the opening of the first mask is arranged on the third semiconductor region in a plan view. In the first step,
Forming a second contact hole disposed on the third semiconductor region and a third contact hole disposed on the first semiconductor region in plan view; 5. The method for manufacturing a semiconductor device according to claim 3, wherein the method is a semiconductor device. After the first step, a second mask is formed which covers the second contact hole and the third contact hole and has an opening arranged so as to include the first contact hole in a plan view. And
Using the second mask, ion implantation in the second step is performed,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the third step is performed after removing the second mask. The first contact hole has a plurality of contact holes,
The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of contact holes are included in one first semiconductor region in a plan view.   8. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is heat-treated after performing the second step and before performing the third step.   A semiconductor device manufactured by the manufacturing method according to claim 1. A method for manufacturing an imaging device including at least a photoelectric conversion unit and an amplification transistor, and having a pixel using a junction field effect transistor as the amplification transistor,
A first contact included in the first semiconductor region in plan view on a semiconductor substrate on which a first semiconductor region of a first conductivity type is disposed, a part of which becomes a gate region of the junction field effect transistor A first step of forming a hole;
Through the first contact hole, ion implantation of the second conductivity type opposite to the first conductivity type is performed, and the second conductivity type second ion which becomes one of the source region or the drain region of the junction field effect transistor. A second step of forming two semiconductor regions;
Forming a conductor electrically connected to the second semiconductor region in the first contact hole;
Forming a semiconductor region constituting the photoelectric conversion portion at a position away from the first semiconductor region;
A method for manufacturing an imaging apparatus, comprising:   The method further includes the step of forming a second conductivity type semiconductor region on the semiconductor substrate, wherein the photoelectric conversion portion and the first semiconductor region are formed in the second conductivity type semiconductor region. The manufacturing method of the imaging device according to claim 10.   An imaging apparatus manufactured by the manufacturing method according to claim 10 or 11.

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