JP2016051489A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a refreshing failure of a memory cell reduced in information holding characteristics based on access history.SOLUTION: A semiconductor device includes a plurality of memory cells each selected corresponding to a plurality of bit lines and a plurality of word lines, a plurality of pump circuits 92 each disposed corresponding to the plurality of word lines to increase or decrease potentials of internal nodes N20 and N21 corresponding to the access history of a corresponding word line, and an OR circuit configured to activate a detection signal MAX when the potential of the internal node of any one of the plurality of pump circuits 92 exceeds a reference potential RVREF.EFFECT: A word line corresponding to the memory cell reduced in information holding characteristics due to a disturbance phenomenon is additionally refreshed to enable correct holding of information irrespective of access history to the memory cell. Additionally, as the access history is counted based on a voltage level, the increase of a circuit size can also be suppressed.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that needs to hold information by a refresh operation.

  A DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, stores information by charges accumulated in a cell capacitor, and therefore information is lost unless a refresh operation is periodically performed. For this reason, a refresh command for instructing a refresh operation is periodically issued from the control device that controls the DRAM (see Patent Document 1). The refresh command is issued from the control device at a frequency at which all word lines are always refreshed once during one refresh cycle (for example, 64 msec).

JP 2011-258259 A

  However, depending on the access history to the memory cell, the information retention characteristic of the predetermined memory cell may be deteriorated. When the information holding time of a predetermined memory cell is reduced to less than one refresh cycle, even if a refresh command is issued with a frequency that all word lines are refreshed once during one refresh cycle, a part of the information is stored. There was a risk of being lost.

  A semiconductor device according to an aspect of the present invention includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells selected corresponding to the plurality of bit lines and the plurality of word lines, and the plurality of the plurality of memory cells. A plurality of potential generation circuits which are provided corresponding to the word lines, and which increase or decrease the potential of the internal node in response to activation of the corresponding word line, and any one of the plurality of potential generation circuits A detection circuit that activates a detection signal when the potential of the internal node crosses the reference potential.

  A semiconductor device according to another aspect of the present invention includes a first and second word lines, a pump circuit that updates a charge level of a capacitor in response to the selection of the first word line, A selection circuit that selects the second word line in response to the charge level exceeding a threshold value.

  According to the present invention, since the word line corresponding to the memory cell having the deteriorated information retention characteristic is additionally refreshed, it is possible to correctly retain the information regardless of the access history to the memory cell. In addition, since the access history is counted based on the voltage level, it is possible to suppress an increase in circuit scale.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. 3 is an enlarged circuit diagram showing a part of a memory cell array 11. FIG. FIG. 3 is a cross-sectional view of two memory cells MC sharing a bit line, and a word line WL includes a trench gate type cell transistor Tr embedded in a semiconductor substrate 4. 3 is a circuit diagram of a refresh control circuit 40 according to the first embodiment. FIG. (A) is a circuit diagram of the address pointer 62, and (b) is a schematic diagram for explaining the function of the address pointer 62. 3 is a block diagram showing a configuration of an access count unit 50. FIG. FIG. 6 is a timing chart for explaining the operation of the semiconductor device 10 using the refresh control circuit 40 according to the first embodiment. _{3 is} a circuit diagram of counter circuits 52 ₀ and 52 _1. FIG. 3 is a circuit diagram of a first pump circuit 82. FIG. FIG. 6 is a timing chart for explaining the operation of the first pump circuit 82. It is a circuit diagram of counter circuits 52 ₀ , 52 ₁ according to a first modification. FIG. 12 is a circuit diagram of counter circuits 52 ₀ and 52 ₁ according to a second modification. 3 is a circuit diagram showing an example of an OR circuit 53. FIG. It is a schematic plan view which shows the structure of the memory cell array 11 in the 2nd Embodiment of this invention. FIG. 6 is a circuit diagram of a refresh control circuit 40 according to a second embodiment. 3 is a block diagram of an address generation unit 200. FIG. 7 is a timing chart for explaining operations of an additional refresh counter 280 and a selection signal generation circuit 270. FIG. 3 is a circuit diagram of a selection signal generation circuit 270. FIG. FIG. 10 is a timing chart for explaining the operation of the semiconductor device 10 using the refresh control circuit 40 according to the second embodiment. FIG. 6 is a circuit diagram of a refresh control circuit 40 according to a third embodiment. FIG. 6 is a circuit diagram of a voltage generation circuit 300 for generating a reference potential RVREF. FIG. 10 is a circuit diagram illustrating an example in which an analog counter circuit using voltage levels is applied to a latency counter 400, which is an application example of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is an LPDDR3 (Low Power Double Data Rate 3) type DRAM integrated on a single semiconductor chip, and is mounted on the external substrate 2. The external substrate 2 is a memory module substrate or a mother board, and is provided with an external resistor Re. The external resistor Re is connected to the calibration terminal ZQ of the semiconductor device 10, and its impedance is used as the reference impedance of the calibration circuit 38. In the present embodiment, the ground potential VSS is supplied to the external resistor Re.

  As shown in FIG. 1, the semiconductor device 10 has a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL, and has a configuration in which memory cells MC are arranged at intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13.

  Further, the semiconductor device 10 is provided with a command address terminal 21, a reset terminal 22, a clock terminal 23, a data terminal 24, power supply terminals 25 and 26, and a calibration terminal ZQ as external terminals.

  The command address terminal 21 is a terminal to which an address signal ADD and a command signal COM are input from the outside. The address signal ADD input to the command address terminal 21 is supplied to the address latch circuit 32 via the command address input circuit 31 and latched. The address signal IADD latched by the address latch circuit 32 is supplied to the row decoder 12, the column decoder 13, or the mode register 14. The mode register 14 is a circuit in which a parameter indicating the operation mode of the semiconductor device 10 is set.

  The command signal COM input to the command address terminal 21 is supplied to the command decode circuit 33 via the command address input circuit 31. The command decode circuit 33 is a circuit that generates various internal commands by decoding the command signal COM. The internal commands include an active signal IACT, a column signal ICOL, a refresh signal IREF, a mode register set signal MRS, a calibration signal ZQC, and the like.

  The active signal IACT is a signal that is activated when the command signal COM indicates row access (active command). When the active signal IACT is activated, the address signal IADD latched in the address latch circuit 32 is supplied to the row decoder 12. As a result, the word line WL designated by the address signal IADD is selected.

  The column signal ICOL is a signal that is activated when the command signal COM indicates column access (read command or write command). When the internal column signal ICOL is activated, the address signal IADD latched in the address latch circuit 32 is supplied to the column decoder 13. As a result, the bit line BL designated by the address signal IADD is selected.

  Accordingly, when an active command and a read command are input and a row address and a column address are input in synchronization with these, read data is read from the memory cell MC specified by the row address and the column address. The read data DQ is output to the outside from the data terminal 24 via the read / write amplifier 15 and the input / output circuit 16.

  On the other hand, when an active command and a write command are input, and a row address and a column address are input in synchronization therewith, and then write data DQ is input to the data terminal 24, the write data DQ is input to the input / output circuit 16 and the read The data is supplied to the memory cell array 11 via the write amplifier 15 and written to the memory cell MC specified by the row address and the column address.

  The refresh signal IREF is a signal that is activated when the command signal COM indicates a refresh command. The refresh signal IREF is supplied to the refresh control circuit 40. The refresh control circuit 40 is a circuit that activates a predetermined word line WL included in the memory cell array 11 by controlling the row decoder 12, thereby executing a refresh operation. In addition to the refresh signal IREF, the refresh control circuit 40 is supplied with an active signal IACT, an address signal IADD, and a reset signal RESET input via the reset terminal 22. Details of the refresh control circuit 40 will be described later.

  The mode register set signal MRS is a signal that is activated when the command signal COM indicates a mode register set command. Therefore, if a mode register set command is input and a mode signal is input from the command address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.

  Here, returning to the description of the external terminals provided in the semiconductor device 10, the external clock signals CK and / CK are input to the clock terminal 23. The external clock signal CK and the external clock signal / CK are complementary signals, and both are supplied to the clock input circuit 34. The external clock signals CK and / CK input to the clock input circuit 34 are supplied to the internal clock generation circuit 35, thereby generating the internal clock signal ICLK. The internal clock signal ICLK is supplied to the timing generator 36, whereby various internal clock signals are generated. Various internal clock signals generated by the timing generator 36 are supplied to circuit blocks such as the address latch circuit 32 and the command decode circuit 33, and define the operation timing of these circuit blocks.

  The power supply terminal 25 is a terminal to which power supply potentials VDD and VSS are supplied. The power supply potentials VDD and VSS supplied to the power supply terminal 25 are supplied to the internal power supply generation circuit 37. The internal power supply generation circuit 37 generates various internal potentials VPP, VOD, VARY, VPERI and a reference potential ZQVREF based on the power supply potentials VDD and VSS. The internal potential VPP is a potential mainly used in the row decoder 12, the internal potentials VOD and VARY are potentials used in the sense amplifier in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks. Potential. On the other hand, the reference potential ZQVREF is a reference potential used in the calibration circuit 38.

  The power supply terminal 26 is a terminal to which power supply potentials VDDQ and VSSQ are supplied. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal 26 are supplied to the input / output circuit 16. The power supply potentials VDDQ and VSSQ are the same as the power supply potentials VDD and VSS supplied to the power supply terminal 25, respectively, but the input / output circuit 16 does not propagate power supply noise generated by the input / output circuit 16 to other circuit blocks. Uses dedicated power supply potentials VDDQ and VSSQ.

  The calibration terminal ZQ is connected to the calibration circuit 38. When the calibration circuit 38 is activated by the calibration signal ZQC, the calibration circuit 38 performs a calibration operation with reference to the impedance of the external resistor Re and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the input / output circuit 16, whereby the impedance of an output buffer (not shown) included in the input / output circuit 16 is designated.

  FIG. 2 is an enlarged circuit diagram showing a part of the memory cell array 11.

  As shown in FIG. 2, a plurality of word lines WL extending in the Y direction and a plurality of bit lines BL extending in the X direction are provided inside the memory cell array 11, and memory cells are arranged at the intersections. MC is arranged. The memory cell MC is a so-called DRAM cell, and has a configuration in which a cell transistor Tr composed of an N-channel MOS transistor and a cell capacitor C are connected in series. The gate electrode of the cell transistor Tr is connected to the corresponding word line WL, one of the source / drain is connected to the corresponding bit line BL, and the other of the source / drain is connected to the cell capacitor C.

  The memory cell MC stores information by the electric charge accumulated in the cell capacitor C. Specifically, when the cell capacitor C is charged to the internal potential VARY, that is, when charged to a high level, one logic level (for example, logic value = 1) is stored, and the cell capacitor C When charged to the ground potential VSS, that is, when charged to a low level, the other logic level (for example, logic value = 0) is stored. Since the electric charge accumulated in the cell capacitor C is gradually lost due to the leakage current, it is necessary to perform a refresh operation every time a certain time elapses.

  The refresh operation is basically the same as the row access in response to the active signal IACT. That is, the word line WL to be refreshed is driven to an active level, thereby turning on the cell transistor Tr connected to the word line WL. The activation level of the word line WL is, for example, the internal potential VPP, which is higher than the internal potential VPERI used in most peripheral circuits. Accordingly, since the cell capacitor C is connected to the corresponding bit line BL, the potential of the bit line BL varies according to the charge accumulated in the cell capacitor C. Then, by activating the sense amplifier SA to amplify the potential difference generated between the paired bit lines BL and then returning the word line WL to the inactive level, the charge level of the cell capacitor C is regenerated. . The inactive level of the word line WL is, for example, a negative potential VKK lower than the ground potential VSS.

  The cycle for performing the refresh operation is called a refresh cycle, and is defined as, for example, 64 msec by the standard. Therefore, if the information holding time of each memory cell MC is designed to be longer than the refresh cycle, the information can be continuously held by a periodic refresh operation. Actually, the information holding time of each memory cell MC has a sufficient margin with respect to the refresh cycle. Therefore, when the refresh operation is performed in a slightly longer cycle than the refresh cycle defined by the standard. Even so, it is possible to correctly hold the information of the memory cell MC.

  However, in recent years, a disturb phenomenon in which the information holding time of the memory cell MC is lowered due to the access history has been a problem. The disturb phenomenon is a phenomenon in which when a certain word line WL is repeatedly accessed, the information retention characteristics of the memory cells MC connected to the other word lines WL adjacent thereto are deteriorated. For example, when the word line WLm shown in FIG. 2 is repeatedly accessed, the information retention characteristics of the memory cells MC connected to the word lines WLm−1 and WLm + 1 adjacent thereto are deteriorated. There are various theories about the cause, but it is considered to be caused by, for example, a parasitic capacitance Cp generated between adjacent word lines.

  That is, when a predetermined word line WLm is repeatedly accessed, the potential repeatedly changes from the negative potential VKK to the high potential VPP. Therefore, the adjacent word lines WLm−1 and WLm + 1 are fixed to the negative potential VKK. Regardless, the potential increases slightly due to the coupling by the parasitic capacitance Cp. As a result, the off-leak current of the cell transistor Tr connected to the word lines WLm−1 and WLm + 1 increases, and the charge level of the cell capacitor C is lost faster than usual.

  There are also other ideas such as: FIG. 3 is a cross-sectional view of two memory cells MC sharing a bit line, and includes a trench gate type cell transistor Tr in which a word line WL is embedded in a semiconductor substrate 4. The word lines WLm and WLm + 1 shown in FIG. 3 are embedded in the same active region partitioned by the element isolation region 6, and when this is activated, a channel is formed between the corresponding source / drain SD. One of the source / drain SD is connected to the bit line node, and the other is connected to the capacitor node. In such a cross section, when the word line WLm is accessed and then the cell transistor Tr is turned off (that is, the channel is cut), floating electrons as carriers are generated near the channel. When access to the word line WLm is repeated, the stray electrons accumulate, the accumulated stray electrons move to the capacitor node on the word line WLm + 1 side, induce a PN junction leak, and the charge level of the cell capacitor C is lost. Make it.

  In any case, when the information holding time of the memory cell MC is reduced by such a mechanism, there is a risk that the information holding time falls below the refresh cycle defined by the standard. If the information holding time falls below the refresh cycle, some data will be lost even if the refresh operation is executed correctly.

  The semiconductor device 10 according to the present embodiment is characterized in that an additional refresh operation is performed based on the access history in consideration of the disturb phenomenon described above. Hereinafter, the configuration and operation of the refresh control circuit 40 provided in the semiconductor device 10 will be described in detail.

  FIG. 4 is a circuit diagram of the refresh control circuit 40 according to the first embodiment.

  As shown in FIG. 4, the refresh control circuit 40 according to the first embodiment includes a refresh counter 41, an access count unit 50, a pulse generation circuit 70, an address generation unit 60, and a selection circuit 42.

  The refresh counter 41 is a circuit that generates a row address (refresh address) RADDa to be refreshed in response to a refresh signal IREF. The refresh address RADDa that is the count value is updated (incremented or decremented) in response to the refresh signal IREF. For this reason, if a refresh command is input from the outside a plurality of times (for example, 8k times) so that the count value of the refresh counter 41 makes one round during one refresh cycle, all word lines WL are refreshed during one refresh cycle. be able to. However, when the selection signal SEL is activated, the count value is not updated even if the refresh signal IREF is input. When the reset signal RESET is input, the count value of the refresh counter 41 is reset to the initial value.

  The access count unit 50 is a circuit that analyzes the history of row access to the memory cell array 11. Although details of the access count unit 50 will be described later, when the number of accesses to any one of the word lines WL exceeds a predetermined value, the detection signal MAX is activated. The detection signal MAX is supplied to the pulse generation circuit 70.

  When the detection signal MAX is activated, the pulse generation circuit 70 activates the pointer control signals P1 and P2 sequentially. The pointer control signals P1 and P2 are supplied to the address generator 60.

  The address generator 60 is a circuit for generating a row address of a word line to be additionally refreshed, and includes an address register 61, an address pointer 62, and an address write circuit 63 as shown in FIG.

The address register 61 includes a plurality of register circuits 61 _{0 to} 61 _q that respectively store row addresses of word lines to be additionally refreshed. The register circuits 61 _{0 to} 61 _q are selected by the address pointer 62, and the row address to be written to the selected register circuits 61 _{0 to} 61 _q is generated by the address write circuit 63. Further, a reset signal RESET is supplied to the address register 61, and when it is activated, the stored contents of all the register circuits 61 _{0 to} 61 _q are reset. Such a reset operation can be omitted.

  FIG. 5A is a circuit diagram of the address pointer 62, and FIG. 5B is a schematic diagram for explaining the function of the address pointer 62.

As shown in FIG. 5A, the address pointer 62 includes a write pointer 62W and a read pointer 62R, a selection signal generation circuit 62S, and a latch circuit 62L. The write pointer 62W is a counter circuit that generates the write point signal WP, and the write point signal WP, which is the count value, is updated (incremented or decremented) in response to the pointer control signals P1 and P2. As described above, when the detection signal MAX is activated, the pulse generation circuit 70 sequentially activates the pointer control signals P1 and P2, so that the write pointer 62W is updated twice. As shown in FIG. 5B, the write point signal WP is used to designate one of the register circuits 61 _{0 to} 61 _q in which the row address is written. In the example shown in FIG. 5B, the register circuit _61j is designated by the write point signal WP.

The read pointer 62R is a counter circuit that generates a read point signal RP, and the read point signal RP that is the count value is updated (incremented or decremented) in response to the output of the AND gate circuit G. The AND gate circuit G is supplied with a refresh signal IREF and a selection signal PSEL, which will be described later, and is therefore updated in response to the refresh signal IREF on condition that the selection signal PSEL is activated to a high level. . As shown in FIG. 5B, the read point signal RP is used to designate one of the register circuits 61 _{0 to} 61 _q from which the row address is read. In the example shown in FIG. 5B, the register circuit 61 _i is designated by the read point signal RP. The row address (refresh address) RADDb read from the address register 61 in this way is supplied to the selection circuit 42.

  The selection signal generation circuit 62S compares the write point signal WP and the read point signal RP, and activates the selection signal PSEL to a high level when WP> RP. When WP = RP, the selection signal PSEL is deactivated to a low level. The value of the write point signal WP and the value of the read point signal RP match that a valid row address is not stored in the address register 61. The number of row addresses stored in the address register 61 is given by the difference (WP−RP) between the value of the write point signal WP and the value of the read point signal RP.

  The selection signal PSEL is supplied to the latch circuit 62L. The latch circuit 62L latches the selection signal PSEL in response to the refresh signal IREF, and outputs the latched signal as the selection signal SEL. Therefore, the logic level of the selection signal PSEL is reflected in the selection signal SEL in response to the next refresh signal IREF.

  The reset signal RESET is supplied to the write pointer 62W and the read pointer 62R, and when this is activated, the write point signal WP and the read point signal RP are initialized.

Returning to FIG. 4, the address write circuit 63 is supplied with an address signal IADD and pointer control signals P1 and P2. When the pointer control signal P1 is activated, the address write circuit 63 generates a row address (Addn + 1) obtained by incrementing the value (Addn) of the address signal IADD in response to the activation, and outputs this to the address register 61. Further, when the pointer control signal P2 is activated, a row address (Addn-1) obtained by decrementing the value (Addn) of the address signal IADD is generated in response to this, and this is output to the address register 61. These row addresses Addn + 1 and Addn−1 output to the address register 61 are stored in different register circuits 61 _{0 to} 61 _q according to the value of the write point signal WP.

  With the above configuration, the refresh address RADDa is generated by the refresh counter 41, and the refresh address RADDb is generated by the address generator 60. The refresh addresses RADDa and RADDb are supplied to the selection circuit 42. The selection circuit 42 receives these refresh addresses RADDa and RADDb and outputs either one to the row decoder 12 as the refresh address RADD. Specifically, when the selection signal SEL is deactivated to a low level, the refresh address RADDa is selected, and when the selection signal SEL is activated to a high level, the refresh address RADDb is selected. . This is because the refresh address RADDa is selected when a valid row address is not stored in the address register 61, and the refresh address RADDb is selected when a valid row address is stored in the address register 61. Means that.

  FIG. 6 is a block diagram illustrating a configuration of the access count unit 50.

As shown in FIG. 6, the access count unit 50 includes a decode circuit 51, counter circuits 52 _{0 to} 52 _p, and an OR circuit 53. The decode circuit 51 receives the active signal IACT, the refresh signal IREF, the address signal IADD, and the refresh address RADD, and generates the count signals RACT0 to RACTp and the reset signals RREF0 to RREFp based on them.

Specifically, when the active signal IACT is activated, one of the count signals RACT0 to RACTp is activated by decoding the address signal IADD. The count signals RACT0 to RACTp are supplied to the counter circuits 52 _{0 to} 52 _p , respectively, whereby the count values of the corresponding counter circuits 52 _{0 to} 52 _p are counted up. On the other hand, when the refresh signal IREF is activated, one of the reset signals RREF0 to RREFp is activated by decoding the refresh address RADD. Reset signal RREF0~RREFp is supplied to each of the counter circuits ₅₂ 0 to 52 _p, which count value of the corresponding counter circuit ₅₂ 0 to 52 _p is reset by.

Although details will be described later, the counter circuits 52 _{0 to} 52 _p are analog counter circuits that hold the count value according to the voltage level of the internal node, unlike a general counter circuit that holds the count value in a digital format. is there. When the count values of the counter circuits 52 _{0 to} 52 _p reach a predetermined value, the corresponding detection signals MAX 0 to MAXp are activated. The detection signals MAX0 to MAXp are input to the OR circuit 53.

  The OR circuit 53 constitutes a detection circuit that activates the detection signal MAX when any of the detection signals MAX0 to MAXp is activated. As described above, the detection signal MAX is input to the pulse generation circuit 70 shown in FIG. Then, the pulse generation circuit 70 sequentially activates the pointer control signals P1 and P2 when the detection signal MAX is activated.

  Next, the operation of the semiconductor device 10 using the refresh control circuit 40 according to the present embodiment will be described.

  FIG. 7 is a timing chart for explaining the operation of the semiconductor device 10 using the refresh control circuit 40 according to the present embodiment.

In the example shown in FIG. 7, an active command ACT is issued from outside at time t10, and a refresh command REF is issued from outside at times t21, t22, t23, and t24. Although not shown, the time t10 even earlier, have been performed many times in a row access by issuing the active command ACT, the count value of the counter circuit 52 _n to thereby corresponding to the row address Addn, counts up to a predetermined value -1 Has been up.

In this state, when the row address Addn along with the active command ACT to the time t10 is input, the count value of the corresponding counter circuit 52 _n is to reach a predetermined value, the detection signal MAX is activated at time t11. When the detection signal MAX is activated, the pulse generation circuit 70 activates the pointer control signals P1 and P2 at times t12 and t13, respectively. In response to this, the write pointer 62W included in the address pointer 62 updates the count value of the write point signal WP at times t12 and t13. In the example shown in FIG. 7, the value of the light point signal WP becomes “1” at time t12, and the value of the light point signal WP becomes “2” at time t13.

Further, in response to the activation of the pointer control signals P 1 and P 2, the address write circuit 63 sequentially outputs the row addresses Addn−1 and Addn + 1 to the address register 61. Thus, the row address Addn-1 to the register circuit 61 ₁ included in the address register 61 is stored in the row address Addn + 1 is stored in the register circuit 61 _2. Since the value of the lead point signal RP is “0” at this time, the selection signal PSEL is activated to a high level at time t11. However, the selection signal SEL is still at the low level at this point, and therefore the selection circuit 42 selects the refresh address RADDa that is the output of the refresh counter 41. In the example shown in FIG. 7, the value of the refresh address RADDa at this time is Addm, and therefore the value of the refresh address RADD output from the selection circuit 42 is also Addm.

  Next, when a refresh command REF is issued from the outside at time t21, the command decode circuit 33 shown in FIG. 1 activates the refresh signal IREF. As described above, since the value of the refresh address RADD at this time is Addm, the row decoder 12 accesses the word line WLm indicated by the row address Addm. Thereby, the information of the memory cells MC connected to the word line WLm is refreshed.

In response to the activation of the refresh signal IREF, the count value of the refresh counter 41 is updated to Addm + 1, and the read pointer 62R included in the address pointer 62 changes the value of the read point signal RP that is the count value. Update to “1”. Thus, from the address register 61, a row address Addn-1 stored in the register circuit 61 ₁ is output.

  Further, since the selection signal SEL changes to high level in response to the activation of the refresh signal IREF, the selection circuit 42 selects the refresh address RADDb that is the output of the address register 61. Therefore, the value of the refresh address RADD output from the selection circuit 42 is Addn-1.

Further, based on the refresh signal IREF and the refresh address RADD, the reset signal RREFm + 1 is activated by the decode circuit 51 shown in FIG. 6, and the counter circuit 52 _{m + 1} corresponding to the word line WLm _{+ 1} is reset. This is because one of the reasons that the word line WLm is disturbed is the row access to the word line WLm + 1 (see FIG. 2). As a result of the word line WLm being refreshed and the charge being regenerated, the row access to the word line WLm + 1 is performed. This is because it is not necessary to prevent the disturb failure of the word line WLm due to the counting of.

However, row access to the word line WLm + 1 causes disturbance not only to the word line WLm but also to the word line WLm + 2. It is considered that the counter circuit 52 _{m + 1} corresponding to WLm + 1 should be reset. However, if the refresh operation for the word line WLm is in response to the refresh command REF, the word line WLm + 2 is refreshed if the refresh counter 41 is updated two more times. It is clear that it will be refreshed. Considering this point, in this embodiment, the counter circuit 52 _{m + 1} corresponding to the word line WLm _{+ 1} is reset in response to the refresh of the word line WLm without waiting for the refresh operation to the word line WLm + 2. .

Of course, it is also possible to configure the decode circuit 51 so that the counter circuit 52 _{m + 1} corresponding to the word line WLm _{+ 1} is reset on condition that both the word line WLm and the word line WLm + 2 are refreshed. However, in this case, the circuit configuration of the decoding circuit 51 is somewhat complicated.

Alternatively, if the refresh for the word line WLm is in response to the refresh command REF, it is possible to reset the counter circuit 52 _m-1 corresponding to the word line WLm-1. This is because one of the reasons that the word line WLm is disturbed is the row access to the word line WLm−1. As a result of the word line WLm being refreshed and the charge being regenerated, the row access to the word line WLm−1 is performed. This is because it is not necessary to prevent the disturb failure of the word line WLm due to counting.

Again, row access to the word line WLm-1 causes disturbance to the word line WLm-2 as well as the word line WLm, so that both the word line WLm and the word line WLm-2 are refreshed. It is considered that the counter circuit 52 _m−1 corresponding to the word line WLm−1 should be reset on the condition. However, when the refresh operation for the word line WLm is in response to the refresh command REF, it is considered that the word line WLm-2 is immediately after being refreshed in relation to the refresh counter 41. 52 _m−1 can be reset.

Furthermore, if a refresh for the word line WLm is that in response to the refresh command REF, reset the counter circuit _{52 m-1} corresponding to the word lines WLm-1, both of the counter circuit _{52 m + 1} corresponding to the word line WLm + 1 It is also possible to do.

  When the refresh command REF is issued again at time t22, the row decoder 12 accesses the word line WLn-1 indicated by the row address Addn-1. That is, the refresh operation is executed in an interrupt manner not on the row address Addm + 1 indicated by the refresh counter 41 but on the row address Addn-1 indicated by the address register 61. As a result, the information in the memory cells MC connected to the word line WLn−1 is refreshed. The word line WLn−1 is a word line adjacent to the word line WLn, and is disturbed by many row accesses to the word line WLn. As a result, the information retention characteristic of the memory cell MC connected to the word line WLn−1 may be deteriorated, but the refresh operation to the word line WLn−1 is executed in an interrupt manner at time t22. Therefore, it becomes possible to hold the information correctly.

At this time, since the selection signal SEL is at a high level, even if the refresh signal IREF is activated, the count value of the refresh counter 41 is not updated and is maintained as Addm + 1. Further, in response to the activation of the refresh signal IREF, the read pointer 62R included in the address pointer 62 updates the value of the read point signal RP that is the count value to “2”. Thus, from the address register 61, a row address Addn + 1 stored in the register circuit 61 ₂ is output. Therefore, the value of the refresh address RADD output from the selection circuit 42 is also Addn + 1. Further, since the value of the read point signal RP matches the value of the write point signal WP, the selection signal PSEL changes to a low level. However, at this time, the selection signal SEL remains at a high level.

  When the refresh command REF is further issued at time t23, the row decoder 12 accesses the word line WLn + 1 indicated by the row address Addn + 1. That is, the refresh operation is executed in an interrupt manner for the row address Addn + 1 indicated by the address register 61, and the information in the memory cell MC is refreshed. The word line WLn + 1 is also a word line adjacent to the word line WLn and is disturbed. However, since the refresh operation to the word line WLn + 1 is executed in an interrupt manner at time t23, the information can be held correctly. It becomes possible.

  At this time, the selection signal SEL is at the high level, so even if the refresh signal IREF is activated, the count value of the refresh counter 41 is not updated and is maintained as Addm + 1. Further, in response to the activation of the refresh signal IREF, the selection signal SEL changes to a low level. Thereby, since the selection circuit 42 selects the refresh address RADDa output from the refresh counter 41, the value of the refresh address RADD output from the selection circuit 42 is switched to Addm + 1.

When the refresh command REF is issued at time t24, the row decoder 12 accesses the word line WLm + 1 indicated by the row address Addm + 1. That is, as usual, the refresh operation is performed on the row address indicated by the refresh counter 41. In response to the activation of the refresh signal IREF, the count value of the refresh counter 41 is updated to Addm + 2. Further, the reset signal RREFm + 2 is activated, and the counter circuit 52 _{m + 2} corresponding to the word line WLm _{+ 2} is reset.

  Thus, in the present embodiment, when the number of row accesses to the word line WLn indicated by the row address Addn reaches a predetermined value, an additional refresh operation is performed on the word lines WLn−1 and WLn + 1 adjacent thereto. The charge amount of the memory cell MC which has been executed and decreased due to the disturb is reproduced. Thereby, it is possible to correctly hold the information stored in each memory cell MC regardless of the access history.

  In addition, when an additional refresh operation is performed, the update of the count value of the refresh counter 41 is stopped, so that the normal refresh operation can be correctly executed. However, when the update of the count value of the refresh counter 41 is stopped, the number of times of issuing the refresh command REF necessary for the count value of the refresh counter 41 to go around increases. This means that the refresh cycle is slightly longer than the design value, but as described above, the information retention time of each memory cell MC actually has a sufficient margin for the refresh cycle. Therefore, even when the refresh operation is performed in a cycle slightly longer than the refresh cycle determined by the standard, the information in the memory cell MC is correctly held.

Next, some specific circuit configurations of the counter circuits 52 _{0 to} 52 _p will be described. Note that the counter circuits 52 _{0 to} 52 _p each input and output corresponding signals and have the same circuit configuration. Therefore, in the following description, the description will focus on the counter circuits 52 ₀ and 52 _1. Proceed.

FIG. 8 is a circuit diagram of the counter circuits 52 ₀ and 52 ₁ .

As shown in FIG. 8, each of the counter circuits 52 ₀ and 52 ₁ has a configuration in which two unit circuits 80 and 90 that perform an analog counting operation are connected in series. Unit circuits 80 and 90 each function as a potential generation circuit.

  The unit circuit 80 receives a corresponding count signal RACT0, RACT1 and generates a control signal UP, a first pump circuit 82 that receives the control signal UP and charges the capacitors C10 and C11, and a capacitor C10. , C11 and a comparison circuit 83 for comparing the reference potential RVREF. Capacitors C10 and C11 are connected between internal nodes N10 and N11 and the ground wiring, respectively. The control signal UP includes a pump signal PUMP, a charge signal CHARGE, and a drive signal DRIVE which will be described later.

  The unit circuit 80 further includes a transistor 84 that resets the charge levels of the capacitors C10 and C11, and a first reset circuit 85 that controls the transistor 84. When transistor 84 is turned on, internal node N10 or N11 is initialized to the ground level. The initialization of the internal node N10 or N11 may be at a predetermined power supply level instead of the ground level.

With this configuration, when the internal node N10 or N11 is not initialized to the ground level and the charging operation is repeated a predetermined number of times, as a result of the internal node N10 or N11 exceeding the reference potential RVREF, the comparison circuit The count signals S10 and S11 output from 83 are inverted to a high level. The count signals S10 and S11 are supplied to the unit circuits 90 included in the counter circuits 52 ₀ and 52 ₁ , respectively.

  The unit circuit 90 has a configuration similar to that of the unit circuit 80. The unit circuit 90 receives the corresponding count signals S10 and S11 and generates the control signal UP, the second pump circuit 92 that receives the control signal UP and charges the capacitors C20 and C21, and the capacitor C20. , C21 and a comparison circuit 93 for comparing the reference potential RVREF. Capacitors C20 and C21 are connected between internal nodes N20 and N21 and the ground wiring, respectively.

  The unit circuit 90 further includes a transistor 94 that resets the charge levels of the capacitors C20 and C21, and a second reset circuit 95 that controls the transistor 94. When transistor 94 is turned on, internal node N20 or N21 is initialized to the ground level.

  With such a configuration, when the internal node N20 or N21 is not initialized to the ground level and the charging operation is repeated a predetermined number of times, the level of the internal node N20 or N21 exceeds the reference potential RVREF. The detection signals MAX0 and MAX1 output from 93 are inverted to a high level. As already described, the detection signals MAX0 and MAX1 are input to the OR circuit 53.

  FIG. 9 is a circuit diagram of the first pump circuit 82.

  As shown in FIG. 9, the first pump circuit 82 includes N-channel type transistors Q0 to Q2 and capacitors Ca0 to Ca2. The gate electrode and the source region of the transistor Q1 are short-circuited. Further, the power supply potential VPERI is supplied to the drain region of the transistor Q1 through the transistor Q0. The source region of transistor Q1 is connected to internal node N10 or N11 via transistor Q2. A charge signal CHARGE and a drive signal DRIVE are input to the gate electrodes of the transistors Q0 and Q2, respectively.

  One end of the capacitor Ca0 is connected to the gate electrode of the transistor Q1, and the other end receives the pump signal PUMP. One end of the capacitor Ca1 is connected to the drain region of the transistor Q1, and the power supply potential VSS is supplied to the other end. One end of the capacitor Ca2 is connected to the source region of the transistor Q1, and the other end is supplied with the power supply potential VSS.

  FIG. 10 is a timing chart for explaining the operation of the first pump circuit 82.

  FIG. 10 shows an operation when the word lines WL corresponding to the first pump circuit 82 are continuously selected. As shown in FIG. 10, when the word line WL is selected, the charge signal CHARGE, the pump signal PUMP, and the drive signal DRIVE are temporarily activated in this order. As described above, the charge signal CHARGE, the pump signal PUMP, and the drive signal DRIVE correspond to the control signal UP illustrated in FIG. Generation of the charge signal CHARGE, the pump signal PUMP, and the drive signal DRIVE in response to the activation of the word line WL may be performed once or a plurality of times.

  When the charge signal CHARGE is temporarily activated, the transistor Q0 is temporarily turned on, so that the node Na1 shown in FIG. 9 is charged to the VPERI level. Next, when the pump signal PUMP is temporarily activated, the gate electrode and the source region of the transistor Q1 are pumped up via the capacitor Ca0. Here, since the gate electrode and the source region of the transistor Q1 are short-circuited, in principle, the gate-source voltage of the transistor Q1 does not change. However, since there is a slight difference in signal transmission time, a voltage is generated between the gate and the source for a very short time, and the transistor Q1 is turned on for a moment. Thereby, the node Na1 and the node Na2 are electrically connected for a moment, and the potential of the node Na2 is slightly increased.

  When the drive signal DRIVE is temporarily activated, the transistor Q2 is temporarily turned on, so that the potential of the internal node N10 or N11 slightly increases. By repeating such an operation, the potential of the internal node N10 or N11 can be increased by one pitch each time the corresponding word line WL is selected.

  As a result of repeating such operations, when the level of the internal node N10 or N11 exceeds the reference potential RVREF, the count signal S10 or S11 output from the comparison circuit 83 is inverted to a high level. The count signal S10 or S11 is supplied to the second control circuit 91. In this specification, the maximum count value K is defined as the number of pump-ups of the first pump circuit 82 necessary for the activation of the count signal S10 or S11.

  The second control circuit 91 and the second pump circuit 92 included in the unit circuit 90 have the same circuit configuration as the first control circuit 81 and the first pump circuit 82 included in the unit circuit 80, respectively. Therefore, when the count signal S10 or S11 is activated, the second control circuit 91 temporarily activates the charge signal CHARGE, the pump signal PUMP, and the drive signal DRIVE in this order. As a result, the second pump circuit 92 performs a pumping operation and raises the potential of the internal node N20 or N21 by one pitch.

  The count signal S10 or S11 is fed back to the first reset circuit 85, and when this is activated, the first reset circuit 85 turns on the transistor 84. As a result, the level of the internal node N10 or N11 is reset, and the count value becomes zero. The first reset circuit 85 and the second reset circuit 95 are also supplied with a reset signal RESET and corresponding reset signals RREF0 and RREF1, and when these are activated, the levels of the internal nodes N10, N11 and N20, N21 are reset. The

  When the level of the internal node N20 or N21 exceeds the reference potential RVREF, the detection signal MAX0 or MAX1 output from the corresponding comparison circuit 93 is inverted to a high level. As described above, the detection signals MAX0 and MAX1 are supplied to the OR circuit 53. When the detection signal MAX0 or MAX1 is activated, the detection signal MAX is activated, and the pulse generation circuit 70 shown in FIG. 4 is activated. In this specification, the number of pump-ups of the second pump circuit 92 necessary for the activation of the detection signals MAX0 and MAX1 is defined as the maximum count value J.

With such a configuration, each of the counter circuits 52 _{0 to} 52 _p activates the corresponding detection signals MAX _{0 to} MAXp when performing the counting operation K × J times. For example,
When K≈J≈400 times, the detection signal MAX can be activated when a certain word line WL is accessed about 160,000 times. For this reason, even when the maximum count value K of the unit circuit 80 and the maximum count value J of the unit circuit 90 are not so large, the number of selections of the word lines WL required for activating the detection signals MAX0 to MAXp is sufficient. Can be secured.

  Note that the counting operation by the unit circuits 80 and 90 is an analog method using the voltage level as a count value, and therefore, unlike the digital method, there is a possibility that a certain amount of error occurs in the values of the maximum count values K and J. However, there is no problem if the value is set in consideration of the error. For example, if it is absolutely necessary to perform the above control after 160,000 accesses, the values of K and J should be appropriate values so that the above control is theoretically performed with 120,000 accesses. Should be designed as follows.

  Here, in order to increase the value of the maximum count value K or J, it is only necessary to reduce the potential difference that changes by one pump-up operation. However, if the potential difference that changes by one pump-up operation is too small, an error occurs. Will increase. For this reason, in this embodiment, by connecting the two unit circuits 80 and 90 in series, a certain amount of potential difference is ensured to suppress an error, and a larger number of counts is ensured in total. Therefore, when it is necessary to secure a larger number of counts, three or more unit circuits may be connected in series.

However, in the present invention, it is not indispensable to connect a plurality of unit circuits in series. When the necessary number of counts is not so large, the counter circuits 52 _{0 to} 52 _p are connected only by the unit circuit 80 as shown in FIG. You may comprise.

  Furthermore, as shown in FIG. 12, a configuration in which the comparison circuit 83 is shared by a plurality of unit circuits 80 may be used. In the example shown in FIG. 12, a plurality of internal nodes N10 to N1k are connected to the gate electrodes of the corresponding transistors 86, respectively. The drain of each transistor 86 is wired OR connected to the input node of the comparison circuit 83. Thus, when the potential level of any one of the internal nodes N10 to N1k exceeds the threshold value of the transistor 86, the detection signal MAX0k output from the comparison circuit 83 is inverted.

  In the example shown in FIG. 12, the active signal IACT is input to the comparison circuit 83, and the current consumption is reduced by activating the comparison circuit 83 only during row access.

  Further, the first pump circuit 82 and the second pump circuit 92 need not be circuits that boost the internal node, and may be circuits that step down the internal node. In this case, the connection of the inverting input terminal and the non-inverting input terminal in the comparison circuits 83 and 93 is reversed.

  FIG. 13 is a circuit diagram showing an example of the OR circuit 53.

  In the example shown in FIG. 13, the detection signal MAX is generated based on 8192 detection signals MAX0 to MAX8191. Here, 8192 detection signals MAX0 to MAX8191 are classified into 16 groups, and each group is wired or connected. For example, the detection signals MAX0 to MAX511 are wired or connected.

  The output signals of each group connected by wired OR are supplied to one of the input nodes of the corresponding OR gates OR0 to OR7. Then, the output signals of OR0 to OR7 are input to the 8-input OR gate OR8, and the output signal is used as the detection signal MAX.

  As described above, if the OR circuit 53 is configured by the wired OR connection and the OR gate, it is possible to avoid an overload due to excessive wired OR connection while reducing the number of elements.

As described above, in this embodiment, since the analog counter circuits 52 _{0 to} 52 _p that hold the count value according to the voltage level of the internal node are used, the digital counter circuit using the latch circuit is used. Compared to the case of using the circuit, the circuit scale can be greatly reduced.

  Next, a second embodiment of the present invention will be described.

  FIG. 14 is a schematic plan view showing the structure of the memory cell array 11 in the second embodiment of the present invention.

  As shown in FIG. 14, in this embodiment, word lines WL (for example, word lines WLn (0) and WLn (1)) corresponding to two cell transistors Tr sharing the bit line contact BLC are close to each other. The interval is W1. The bit line contact BLC is a contact conductor for connecting one of the source / drain of the cell transistor Tr and the bit line BL. The other of the source / drain is connected to a cell capacitor C (not shown) via a cell contact CC.

  On the other hand, the interval between adjacent word lines WL (for example, word lines WLn (1) and WLn + 1 (0)) corresponding to the cell transistors Tr not sharing the bit line contact BLC is an interval W2 wider than the interval W1. . As shown in FIG. 14, such a layout is obtained because active regions ARa whose longitudinal direction is the A direction and active regions ARb whose longitudinal direction is the B direction are alternately formed in the X direction. It is.

  When the memory cell array 11 has such a layout, even if a certain word line WLn (0) is repeatedly accessed, a parasitic capacitance is applied to the adjacent word line WLn (1) at the interval W1. Although the disturb phenomenon occurs because Cp1 is large, the disturb phenomenon hardly occurs because the parasitic capacitance Cp2 is small with respect to the adjacent word line WLn-1 (1) at the interval W2. Therefore, in the case of such a layout, it is necessary to perform an additional refresh operation for the word line WLn (1) in which the disturb phenomenon occurs, but the other word line WLn−1 ( For 1), no additional refresh operation is required.

  In addition, word lines WLn (0) and WLn (1) that are adjacent at the interval W1 differ only in the least significant bit (A0) of the assigned row address, and the values of the other bits (A1 to A13) match. ing. In consideration of such characteristics, in the present embodiment, the circuit configuration of the refresh control circuit 40 is simplified. Hereinafter, the configuration and operation of the refresh control circuit 40 in the present embodiment will be described in detail.

  FIG. 15 is a circuit diagram of the refresh control circuit 40 according to the second embodiment.

  As shown in FIG. 15, the refresh control circuit 40 according to the second embodiment is the same as that shown in FIG. 4 except that the address generation unit 200 is used instead of the address generation unit 60 and the pulse generation circuit 70 is deleted. The refresh control circuit 40 has substantially the same configuration. However, the address signal IADD supplied to the access count unit 50 is only 13 bits including bits A1 to A13 among the bits A0 to A13. That is, the least significant bit A0 is degenerated.

  FIG. 16 is a block diagram of the address generator 200.

  As shown in FIG. 16, the address generation unit 200 includes a matrix array 210, a row decoder 220, an address write circuit 230, and an address read circuit 240. Although not particularly limited, for example, the matrix array 210 has a configuration in which a plurality of latch circuits are arranged in a matrix. Specifically, it has a configuration in which r + 1 word lines RRWL0 to RRWLr and 13 bit lines RRBL1 to RRBL13 are provided, and latch circuits are respectively arranged at intersections thereof. Note that the element is not limited to a latch circuit and may be any element that can hold information.

  Selection of the word lines RRWL0 to RRWLr is performed in response to the refresh signal IREF based on the row address RA output from the write counter 250 or the read counter 260. The row address RA output from the write counter 250 is referred to when the row address IADD (A1 to A13) is written to the matrix array 210 using the address write circuit 230. The row address RA output from the read counter 260 is referred to when the refresh address RADDb (A1 to A13) is read from the matrix array 210 using the address read circuit 240. As will be described later, the row address IADD (A1 to A13) written in the matrix array 210 indicates the word line WLn (0) or WLn (1) whose number of accesses has reached a predetermined value.

The address write circuit 230 includes write circuits 230 _{1 to} 230 ₁₃ corresponding to the respective bits of the row address IADD (A1 to A13), and the row address IADD (A1 to A13) is applied to the row address RA output from the write counter 250. Play the role of writing.

On the other hand, the address read circuit 240 includes read circuits 240 ₁ to 240 ₁₃ corresponding to the respective bits of the refresh address RADDb (A1 to A13), and the refresh address RADDb (A1 to A13) from the row address RA output from the read counter 260. ). Further, the address read circuit 240 includes a LSB output circuit 240 _0, the least significant bit A0 of the refresh address RADDb, the output signal of the LSB output circuit 240 ₀ is used. Bit A0 is the output signal of the LSB output circuit 240 _0, the clock signal CLKA output from the selection signal generating circuit 270, inverted on the basis of CLKB.

  The selection signal generation circuit 270 is a circuit that generates the selection signal SEL and the clock signals CLKA and CLKB described above based on the selection signal PSEL and the refresh signal IREF. The selection signal SEL is supplied to the selection circuit 42 shown in FIG. 15 and is used not only to select the refresh address RADDa or RADDb, but also to the refresh counter 41, and performs an update operation of the refresh counter 41 in response to the refresh signal IREF. Used to allow or prohibit.

  The selection signal PSEL is generated by the additional refresh counter 280. The additional refresh counter 280 is a circuit that counts up by 2 counts in response to the detection signal MAX and counts down by 1 count in response to the refresh signal IREF. If the count value is 1 or more, the additional refresh counter 280 activates the selection signal PSEL. Make it.

  FIG. 17 is a timing chart for explaining operations of the additional refresh counter 280 and the selection signal generation circuit 270.

  In the example shown in FIG. 17, the active signal IACT is activated at times t31 and t32, and the refresh signal IREF is activated at times t41, t42, t43, t44, and t45. Further, the detection signal MAX is activated in response to the activation of the active signal IACT at times t31 and t32. This is because the number of accesses to a certain word line WL exceeds a predetermined value due to the row access in response to the active signal IACT at time t31, and another word line WL is also caused by the row access in response to the active signal IACT at time t32. This means that the number of accesses exceeds the predetermined value.

  In this case, the count value of the additional refresh counter 280 is incremented from “0” to “2” in response to the first activation of the detection signal MAX, and is added in response to the second activation of the detection signal MAX. The count value of the refresh counter 280 is counted up from “2” to “4”. Further, in response to the count value of the additional refresh counter 280 becoming “1” or more, the selection signal PSEL is activated to a high level.

  Thereafter, in response to activation of the refresh signal IREF at times t41, t42, t43, and t44, the count value of the additional refresh counter 280 is counted down to “3”, “2”, “1”, “0”, The selection signal PSEL returns to the low level. At time t45, the refresh signal IREF is activated, but at this time, the count value of the additional refresh counter 280 has already reached the minimum value (0), so that value does not change.

  FIG. 18 is a circuit diagram of the selection signal generation circuit 270.

  As shown in FIG. 18, the selection signal generation circuit 270 includes a latch circuit 271 that latches the selection signal PSEL in response to the refresh signal IREF, and the output signal is used as the selection signal PSEL. Therefore, the selection signal SEL changes to the high level in response to the next refresh signal IREF (the refresh signal IREF at time t41 shown in FIG. 17) after the selection signal PSEL is activated to the high level. In addition, after the selection signal PSEL is deactivated to the low level, it returns to the low level in response to the next refresh signal IREF (refresh signal IREF at time t45 shown in FIG. 17).

Further, the selection signal SEL and the refresh signal IREF are supplied to the gate circuit G5 shown in FIG. 18, and on the condition that the selection signal SEL is activated to the high level, the latch circuit is based on the refresh signal IREF. 272 and 273 are selected alternately. Since the selected latch circuits 272 and 273 invert their output signals, the clock signals CLKA and CLKB are alternately activated in response to the refresh signal IREF. This means that if the selection signal SEL is activated to a high level, whenever the refresh signal IREF is activated, the bit A0 is an output signal of the LSB output circuit 240 ₀ is meant to reverse.

  As shown in FIG. 16, a reset signal RESET is supplied to a predetermined circuit block constituting the address generation unit 200, and when this is activated, the circuit block is reset to an initial state. For example, all the data held in the matrix array 210 is reset in response to the reset signal RESET. Such an operation can be performed by outputting an initial value from the address write circuit 230 to the matrix array 210 in a state where all the word lines RRWL0 to RRWLr are selected by the row decoder 220.

  Next, the operation of the semiconductor device 10 using the refresh control circuit 40 according to the present embodiment will be described.

  FIG. 19 is a timing chart for explaining the operation of the semiconductor device 10 using the refresh control circuit 40 according to the present embodiment.

  In the example shown in FIG. 19, an active command ACT is issued from outside at time t50, and a refresh command REF is issued from outside at times t61, t62, t63, and t64. Although not shown, before the time t50, many row accesses are performed by issuing the active command ACT, and the count value corresponding to the row address Addn of the access count unit 50 is counted up to a predetermined value -1. Has been up. As described above, since the least significant bit A0 is degenerated in the row address IADD input to the access count unit 50, the row address Addn is connected to the word line WLn (0) to which the row address Addn (0) is assigned. This is common to both of the word lines WLn (1) to which the row address Addn (1) is assigned. Further, before the time t50, the count value of the additional refresh counter 280 is zero.

  In this state, when the row address Addn is input together with the active command ACT at time t50, the detection signal MAX is activated. When the detection signal MAX is activated, the count value of the additional refresh counter 280 shown in FIG. 16 changes from 0 to 2, and the selection signal PSEL becomes high level. Furthermore, since the address write circuit 230 is activated in response to the activation of the detection signal MAX, the row address IADD (Addn) input together with the active command ACT is written into the matrix array 210. For example, the write counter 250 designates the word line RRWL0 as a write destination of the row address IADD (Addn).

  However, at this time, the selection signal SEL is still at the low level, and therefore the selection circuit 42 selects the refresh address RADDa that is the output of the refresh counter 41. In the example shown in FIG. 19, the value of the refresh address RADDa at this time is Addm (0), and therefore the value of the refresh address RADD output from the selection circuit 42 is also Addm (0). Here, Addm (0) means that the value of the upper bits A1 to A13 is m and the value of the least significant bit A0 is 0.

  Next, when a refresh command REF is issued from the outside at time t61, the command decode circuit 33 shown in FIG. 1 activates the refresh signal IREF. As described above, since the value of the refresh address RADD at this time is Addm (0), the row decoder 12 accesses the word line WLm indicated by the row address Addm (0). As a result, the information in the memory cells MC connected to the word line WLm (0) is refreshed.

In response to activation of the refresh signal IREF, the count value of the refresh counter 41 is updated to Addm (1), and the word line RRWL0 is designated by the read counter 260. Here, Addm (1) means that the value of the upper bits A1 to A13 is m and the value of the least significant bit A0 is 1. As a result, the address read circuit 240 outputs the refresh address RADDb (Addn) stored in the row address corresponding to the word line RRWL0. At this point, since the clock signal CLKA is activated, the value of the LSB output circuit 240 ₀ is 0, the value of the refresh address RADDb therefore is Addn (0). Here, Addn (0) means that the value of the upper bits A1 to A13 is n and the value of the least significant bit A0 is 0.

  Further, since the selection signal SEL changes to high level in response to the activation of the refresh signal IREF, the selection circuit 42 selects the refresh address RADDb that is the output of the address register 61. Therefore, the value of the refresh address RADD output from the selection circuit 42 is Addn (0). Further, the count value of the additional refresh counter 280 is decremented from 2 to 1.

  Furthermore, activation of the reset signal RREFm initializes a count value corresponding to Addm, which is the value of the refresh address RADD. The count value corresponding to Addm is a common count value for the word line WLm (0) and the word line WLm (1). Since these word lines differ only in the least significant bit A0 of the row address, the word line WLm ( It is considered that the time from the refresh of 0) to the refresh of the word line WLm (1) is very short. Considering this point, regardless of which of the word lines WLm (0) and WLm (1) is actually refreshed, if one of them is refreshed, the count value corresponding to both is reset.

  When the refresh command REF is issued again at time t62, the row decoder 12 accesses the word line WLn (0) indicated by Addn (0) that is the value of the refresh address RADD. That is, the refresh operation is executed in an interrupt manner on the row address Addn (0) output from the address read circuit 240, not on the row address Addm (1) indicated by the refresh counter 41. As a result, the information in the memory cells MC connected to the word line WLn (0) is refreshed. Furthermore, activation of the reset signal RREFn initializes a count value corresponding to Addn which is the value of the refresh address RADD.

  At this time, since the selection signal SEL is at a high level, even if the refresh signal IREF is activated, the count value of the refresh counter 41 is not updated and is maintained as Addm (1). Further, the count value of the additional refresh counter 280 is decremented from 1 to 0. As a result, the selection signal PSEL changes to a low level.

Further, in response to the refresh signal IREF, the selection signal generation circuit 270 activates the clock signal CLKB. Thus, the value of the LSB output circuit 240 ₀ is 1, the value of the refresh address RADDb changes to Addn (1). Here, Addn (1) means that the value of the upper bits A1 to A13 is n and the value of the least significant bit A0 is 1.

  When the refresh command REF is further issued at time t63, the row decoder 12 accesses the word line WLn (1) indicated by the row address Addn (1). That is, the refresh operation is executed in an interrupt manner for the row address Addn (1) output from the address read circuit 240, and the information in the memory cell MC is refreshed.

  At this time, the selection signal SEL is at the high level, so even if the refresh signal IREF is activated, the count value of the refresh counter 41 is not updated and is maintained as Addm (1). Further, in response to the activation of the refresh signal IREF, the selection signal SEL changes to a low level. Thus, since the selection circuit 42 selects the refresh address RADDa output from the refresh counter 41, the value of the refresh address RADD output from the selection circuit 42 becomes Addm (1).

  When the refresh command REF is issued at time t64, the row decoder 12 accesses the word line WLm (1) indicated by the row address Addm (1). That is, as usual, the refresh operation is performed on the row address indicated by the refresh counter 41. In response to activation of the refresh signal IREF, the count value of the refresh counter 41 is updated to Addm + 1 (0). Further, activation of the reset signal RREFm + 1 initializes a count value corresponding to Addm + 1 which is the value of the refresh address RADD.

  Thus, when the total number of row accesses to the word line WLn (0) and the word line WLn (1) indicated by the row address Addn reaches a predetermined value, the word lines WLn (0) and WLn (1) Additional refresh operations are performed. In the present embodiment, since the least significant bit A0 of the row address IADD is degenerated, those adjacent to each other at the interval W1 regardless of which of the word lines WLn (0) and WLn (1) is disturbed. An additional refresh operation is performed on both word lines WLn (0) and WLn (1). Therefore, the capacity of the matrix array included in the access count unit 50 can be reduced by half.

  In addition, since the matrix array 210 is used to count the number of accesses and to hold a row address to be additionally refreshed, the area occupied on the chip can be reduced.

  FIG. 20 is a circuit diagram of the refresh control circuit 40 according to the third embodiment.

  As shown in FIG. 20, the refresh control circuit 40 according to the third embodiment is different from the refresh control circuit shown in FIG. 4 in that an output circuit BUF for outputting the detection signal MAX to the external terminal OUT is added. 40. The other points are the same as those of the refresh control circuit 40 shown in FIG.

If the refresh control circuit 40 according to the present embodiment is used, the detection signal MAX can be monitored by an external tester. Therefore, the detection signal MAX is generated when the counter circuits 52 _{0 to} 52 _p actually count. It can be evaluated. The reason for performing such evaluation is that, as already described, an analog counter circuit is used in the present embodiment, and an error may occur in the count value. Since the detection signal MAX can be monitored according to the present embodiment, it is possible to check at the manufacturing stage how much error has occurred in the count value due to process conditions and the like.

  When evaluating the error of the count value, it is desirable to offset the reference potential RVREF based on the evaluation result. That is, it is preferable to change the maximum count value by changing the level of the reference potential RVREF.

  FIG. 21 is a circuit diagram of a voltage generation circuit 300 for generating the reference potential RVREF.

  A voltage generation circuit 300 illustrated in FIG. 21 includes a fuse circuit 310 including a plurality of fuse elements, and an offset circuit 320 that generates a reference potential RVREF by offsetting the reference potential VREF according to the program content of the fuse circuit 310. . Programming to the fuse circuit 310 is performed by a program circuit 330 that receives a program signal FPROG and a program address FADD. Thus, by programming the fuse circuit 310 based on the result of evaluating the error of the count value, the level of the reference potential RVREF can be changed, so that the error can be canceled out.

  In the voltage generation circuit 300 shown in FIG. 21, the test signals TEST0 to TESTk are input to the offset circuit 320, and the level of the reference potential RVREF is set for each counter circuit or for each counter circuit group composed of a plurality of counter circuits. Can be adjusted. Thereby, even if the error is different for each counter circuit or for each counter circuit group, the maximum count value can be made substantially constant.

  FIG. 22 is an application example of the present invention, and is a circuit diagram showing an example in which an analog counter circuit using a voltage level is applied to the latency counter 400.

  The latency counter 400 shown in FIG. 21 receives a read command Read_com and generates a control signal UP, a first pump circuit 402 that receives the control signal UP and charges the capacitor C30, and charges the capacitor C30. A comparison circuit 403 that compares the level and the reference potential VREF_Latency is included. The latency counter 400 further includes a transistor 404 that resets the charge level of the capacitor C30, and a first reset circuit 405 that controls the transistor 404.

  When the read command Read_com is activated, the first control circuit 401 continuously generates the control signal UP in synchronization with the internal clock signal ICLK. As a result, the level of the internal node N30 gradually increases, and when the reference potential VREF_Latency is exceeded, the read signal Int_Read output from the comparison circuit 403 is activated. When the read signal Int_Read is activated, the transistor 404 is turned on by the first reset circuit 405, and the charge level of the capacitor C30 is reset.

  The number of counts from when the read command Read_com is activated until the read signal Int_Read is generated can be adjusted by the reference potential VREF_Latency. Therefore, if the latency counter 400 shown in FIG. 22 is used, the number of counts from when the read command Read_com is activated until the read signal Int_Read is generated can be adjusted to an arbitrary value. Note that the read signal Int_Read is used, for example, in the input / output circuit 16 in FIG. 1 to control read data output timing.

  Thus, the present invention can be applied to other circuits that require a counter.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

2 External substrate 4 Semiconductor substrate 6 Element isolation region 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 15 Read / write amplifier 16 Input / output circuit 21 Command address terminal 22 Reset terminal 23 Clock terminal 24 Data terminal 25, 26 Power supply Terminal 31 Command address input circuit 32 Address latch circuit 33 Command decode circuit 34 Clock input circuit 35 Internal clock generation circuit 36 Timing generator 37 Internal power generation circuit 38 Calibration circuit 40 Refresh control circuit 41 Refresh counter 42 Selection circuit 50 Access count unit 51 decode circuit ₅₂ 0 to 52 _p counter circuit 53 OR circuit 60 the address generator 61 the address register ₆₁ 0 to 61 _q register circuit 62 Dress pointer 62L Latch circuit 62R Read pointer 62S Selection signal generation circuit 62W Write pointer 63 Address write circuit 70 Pulse generation circuit 80, 90 Unit circuit 81, 91 Control circuit 82, 92 Pump circuit 83, 93 Comparison circuit 84, 94 Transistor 85, 95 reset circuit 86 transistor 210 matrix array 200 address generation unit 220 row decoder 230 address write circuit 230 _{1 to} 230 ₁₃ write circuit 240 address read circuit 240 ₁ to 240 ₁₃ read circuit 250 write counter 260 read counter 270 selection signal generation circuit 271 273 Latch circuit 280 Additional refresh counter 300 Voltage generation circuit 310 Fuse circuit 320 Offset circuit 330 Program circuit 400 Latency Counter 401 Control circuit 402 Pump circuit 403 Comparison circuit 404 Transistor 405 Reset circuit ACT Active command ARa, ARb Active region BL Bit line BLC Bit line contact BUF Output circuit C Cell capacitor CC Cell contact G, G5 Gate circuit IACT Active signal IADD Address signal IREF refresh signal MAX, MAX0 to MAX8191 detection signal MC memory cell N10, N11, N20, N21, N30 internal node OR0 to OR8 OR gate OUT external terminal P1, P2 pointer control signal PSEL selection signal PUMP pump signal Q0 to Q2 transistors RACT0 to RACTp Count signals RADD, RADDa, RADDb Refresh address REF Refresh command RESET Set signal RP readpoint signal RRBL1~RRBL13 bit line RREF0~RREFp reset signal RRWL0~RRWLr word line SA the sense amplifier Tr cell transistor UP control signal WL word line WP Write point signal ZQ calibration terminal

Claims (18)

Multiple bit lines,
Multiple word lines,
A plurality of memory cells selected corresponding to the plurality of bit lines and the plurality of word lines, respectively;
A plurality of potential generating circuits which are provided corresponding to the plurality of word lines, respectively, and which increase or decrease the potential of the internal node in response to activation of the corresponding word lines;
A semiconductor device comprising: a detection circuit that activates a detection signal when the potential of the internal node of any of the plurality of potential generation circuits crosses a reference potential.   The semiconductor device according to claim 1, further comprising: an address register that stores an address related to the corresponding word line in response to activation of the detection signal.   The semiconductor device according to claim 2, further comprising a selection circuit that outputs the address stored in the address register in response to a refresh command.   4. The device according to claim 1, further comprising: a reset circuit that resets a potential of the internal node of the potential generation circuit related to the word line selected in response to a refresh command among the plurality of potential generation circuits. The semiconductor device according to one item.   The plurality of potential generation circuits are determined by comparing a pump circuit that boosts or lowers the potential of the internal node in response to activation of the corresponding word line, and the potential of the internal node and the reference potential The semiconductor device according to claim 1, further comprising a comparison circuit that generates a signal. The plurality of potential generation circuits have a configuration in which a plurality of unit circuits including the pump circuit and the comparison circuit are connected in series,
The semiconductor device according to claim 5, wherein the pump circuit included in the subsequent unit circuit boosts or lowers the potential of the internal node in response to a determination signal output from the previous unit circuit.   The semiconductor device according to claim 5, wherein the detection circuit combines the determination signals output from the plurality of potential generation circuits.   The semiconductor device according to claim 7, wherein the detection circuit synthesizes at least a part of the determination signals output from the plurality of potential generation circuits by a wired OR method.   The pump circuit includes a first transistor, a first capacitor having one end connected to the gate electrode of the first transistor and a pump signal input to the other end, and one end being a drain region of the first transistor. And a third capacitor having one end connected to the source region of the first transistor and the other end supplied with the power supply potential. The semiconductor device according to claim 5, wherein the gate electrode and the source region of the first transistor are short-circuited.   The semiconductor device according to claim 9, wherein the pump signal is activated in response to activation of the corresponding word line.   The pump circuit further includes: a second transistor that charges the drain region of the first transistor; and a third transistor that is connected between the source region of the first transistor and the internal node. The semiconductor device according to claim 9 or 10, further comprising:   A charge signal is input to the gate electrode of the second transistor, a drive signal is input to the gate electrode of the third transistor, and the charge signal and the pump are responsive to activation of the corresponding word line. The semiconductor device according to claim 11, wherein the signal and the drive signal are activated in this order.   The semiconductor device according to claim 1, wherein the reference potential is variable.   The semiconductor device according to claim 1, further comprising an output circuit that outputs the detection signal to the outside. First and second word lines;
A pump circuit for updating a charge level of a capacitor in response to selection of the first word line;
And a selection circuit that selects the second word line in response to the charge level of the capacitor exceeding a threshold value.   The semiconductor device according to claim 15, wherein the first and second word lines are adjacent to each other.   The semiconductor device according to claim 15, further comprising a reset circuit that initializes the charge level of the capacitor in response to selection of the second word line.   The semiconductor device according to claim 15, further comprising a plurality of DRAM memory cells connected to the first and second word lines.

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