JP2013009212A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces power consumed by charging and discharging of a signal transfer line.SOLUTION: A semiconductor device includes: a receiver circuit R0k including an amplifier circuit AMP having a flip-flop configuration; and a transistor M7 disposed between a data bus DB and an input terminal T2 of the receiver circuit R0k, and turning off when a potential of the data bus DB reaches VPERI-NVth. Since an amplitude at the input terminal T2 is limited by the transistor M7, a transfer rate when changing the data bus DB from a low level to a high level is improved. Further, since the amplifier circuit AMP has the flip-flop configuration, no penetration current is generated after inversion of the flip-flop. Thereby, power consumption is further reduced.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a signal transfer line and a signal receiving circuit.

  A signal transfer line is used for signal transfer inside the semiconductor device and signal transfer between a plurality of semiconductor devices. As a signal transfer method, a single-end method using a single signal, a differential method using a complementary signal, and the like are known (see Patent Document 1).

JP 2007-273980 A JP 2011-91708 A

  However, in any method, when the logic level of the signal to be transferred is inverted, the signal transfer line is charged or discharged, and this consumes power. For this reason, when the number of signal transfer lines is large, the charge / discharge current increases accordingly. Therefore, in applications where low power consumption is required, it is desirable to suppress the power consumed by charging / discharging the signal transfer line as much as possible.

  The inventor has proposed a semiconductor device capable of reducing power consumption due to charge / discharge of a signal transfer line in Patent Document 2. The semiconductor device proposed in Patent Document 2 limits the signal amplitude on the signal transfer line, thereby enabling reduction of power consumption due to charging / discharging. And this inventor earnestly examined in order to further reduce power consumption.

  A semiconductor device according to the present invention is connected between a driver circuit that outputs a signal to a first terminal, a receiver circuit that receives the signal from a second terminal, and the first and second terminals. A switch circuit for limiting an amplitude, and the receiver circuit includes a flip-flop amplifier circuit having a pair of first and second signal nodes, and the first signal node is connected to the second terminal. It is connected.

  According to the present invention, since the amplitude of the signal is limited by the switch circuit, power consumption due to charging / discharging is reduced. In addition, since the receiver circuit includes a flip-flop amplifier circuit, no through current is generated after the flip-flop is inverted. Thereby, power consumption is further reduced.

It is a block diagram which shows the structure of the semiconductor device by preferable embodiment of this invention. 2 is a circuit diagram of a write control circuit 30. FIG. FIG. 4 is a block diagram showing a connection relationship between a driver circuit DAk and a receiver circuit RAk and a driver circuit D0k and a receiver circuit R0k. It is a block diagram which shows the circuit part X shown in FIG. 3 in detail. FIG. 5 is a circuit diagram of the circuit block shown in FIG. 4. FIG. 10 is a waveform diagram showing an operation when write data DATA changes from a low level (VSS) to a high level (VPERI). FIG. 6 is a waveform diagram showing an operation when write data DATA changes from a high level (VPERI) to a low level (VSS). It is a circuit diagram which shows a modification. It is a circuit diagram of other embodiments. FIG. 10 is a waveform diagram showing an operation when write data DATA changes from a low level (VSS) to a high level (VPERI) in another embodiment. It is a wave form diagram showing operation in case write data DATA changes from a high level (VPERI) to a low level (VSS) in other embodiments.

  In recent years, the speed of semiconductor devices has been increased. For example, in a dynamic random access memory (DRAM), a DDR3 type that is faster than a DDR (Double Data Rate) type 2 has been put into practical use. Since the DDR3-type DRAM performs an 8-bit prefetch operation, the number of data buses is approximately doubled as compared with the DDR2-type.

  Patent Document 2 discloses a switch circuit and a voltage supply circuit for reducing the signal amplitude of a signal transfer line in order to suppress current consumption. The receiver circuit disclosed in Patent Document 2 has an advantage that the time taken to amplify the amplitude of the signal transferred in the receiver circuit is short because the circuit that receives the signal transferred from the signal transfer line is an inverter circuit. have. However, when low data (VSS) is transferred to the data transfer line, a through current flows through the voltage supply circuit because the switch circuit is in a conductive state.

  Accordingly, the present inventor has further improved the current consumption by improving the receiver circuit in a semiconductor device that is desired to further suppress the current consumption, such as a DDR3 type DRAM in which the number of data buses is increased. Considered to reduce. The present invention has been made as a result of such studies.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a preferred embodiment of the present invention. The present embodiment is an example when the present invention is applied to a DDR (Double Data Rate) type 3 DRAM (Dynamic Random Access Memory). However, it goes without saying that the application target of the present invention is not limited to this.

  As shown in FIG. 1, the semiconductor device according to the present embodiment has eight memory banks BANK0 to BANK7 and data to which read data read from these memory banks is output or write data to be written to the memory banks is input. Input / output terminals DQ0 to DQn are provided. The number of data input / output terminals (= n + 1) is not particularly limited, and can be, for example, 32 (n = 31). These n + 1 data input / output terminals DQ0 to DQn are shared by the eight memory banks BANK0 to BANK7. Therefore, n + 1-bit read data or write data input / output via the data input / output terminals DQ0 to DQn. Data is assigned to one of the memory banks BANK0 to BANK7. A memory bank is a unit that can receive commands individually and can operate independently of each other.

  The command is input from the outside via the command input terminal CMD. External commands including a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and a chip select signal / CS are input to the command input terminal CMD. These external commands are supplied to the control unit 10, and an internal read enable signal RE, an internal write enable signal WE, and the like are generated according to a combination of logic levels. The internal read enable signal RE is a signal that is activated when an external command indicates a read operation, and is supplied to the read control circuit 20. The internal write enable signal WE is a signal that is activated when an external command indicates a write operation, and is supplied to the write control circuit 30.

  When the internal read enable signal RE is input, the read control circuit 20 activates the read control signal REA and activates one of the read control signals RE0 to RE3. Similarly, when the internal write enable signal WE is input, the write control circuit 30 activates the write control signal WEA and activates one of the write control signals WE0 to WE3.

  Which of the read control signals RE0 to RE3 or the write control signals WE0 to WE3 is activated is specified by the bank addresses BA0 to BA2 input from the address input terminal ADD. The bank addresses BA0 to BA2 are input to the decode circuit 12, and bank selection signals BA0E to BA3E generated by the decode circuit 12 are supplied to the read control circuit 20 and the write control circuit 30. As a result, any one of the read control signals RE0 to RE3 is activated during the read operation, and any one of the write control signals WE0 to WE3 is activated during the write operation. The bank addresses BA0 to BA2 are addresses for selecting the memory banks BANK0 to BANK7, and are input from the outside in conjunction with an external command.

  FIG. 2 is a circuit diagram of the write control circuit 30.

  As shown in FIG. 2, the write control circuit 30 is supplied with bank selection signals BA0E to BA3E at one input terminal and AND circuits 40 to 43 to which an internal write enable signal WE is supplied at the other input terminal, An OR circuit 44 that performs an OR operation on outputs of the AND circuits 40 to 43 is provided. The outputs of the AND circuits 40 to 43 are used as write control signals WE0 to WE3, respectively. Thus, when the internal write enable signal WE is activated, any one of the write control signals WE0 to WE3 is activated based on the bank selection signals BA0E to BA3E. The write control signal WEA is activated when the internal write enable signal WE is activated and any of the bank selection signals BA0E to BA3E is activated. Since the circuit configuration of the read control circuit 20 is the same, redundant description is omitted.

  The read control circuit 20 and the write control circuit 30 described above are circuits that operate when the memory banks BANK0 to BANK3 are selected. Although not shown, when the memory banks BANK4 to BANK7 are selected, another read control circuit and a write control circuit operate, and thereby a corresponding read control signal or write control signal is activated.

  Returning to FIG. 1, the data input / output terminals DQ0 to DQn are provided with an input buffer IB and an output buffer OB, respectively. In FIG. 1, only the input buffer IBk and the output buffer OBk provided at the data input / output terminal DQk are illustrated for simplicity. As described above, the semiconductor device according to the present embodiment is a DDR3-type DRAM, and therefore performs an 8-bit prefetch operation. That is, 8-bit write data serially input to the data input / output terminal DQk is written in parallel via the eight read / write buses RWBSk, and conversely in parallel via the eight read / write buses RWBSk. The read 8-bit read data is serially output from the data input / output terminal DQk. Thus, since eight read / write buses RWBS are provided for each data input / output terminal DQ, when the number of data input / output terminals (= n + 1) is 32, at least 256 (= 32 × 8) ) A read / write bus RWBS is required. Further, in the present embodiment, the area where the memory banks BANK0 to BANK3 are formed (the left area in FIG. 1) and the area where the memory banks BANK4 to BANK7 are formed (the right area in FIG. 1) are divided. Since the read / write bus RWBS is allocated to the total number of 512, the read / write bus RWBS is provided in total. However, in FIG. 1, only the read / write bus RWBSk assigned to the memory banks BANK0 to BANK3 and the data input / output terminal DQk is shown for simplicity.

  As shown in FIG. 1, the read / write bus RWBSk is connected to a driver circuit DAk and a receiver circuit RAk. The driver circuit DAk is a circuit activated by the write control signal WEA, and the receiver circuit RAk is a circuit activated by the read control signal REA. The output terminal of the driver circuit DAk and the input terminal of the receiver circuit RAk are connected to a data bus DB (signal transfer line).

  The data bus DB is a wiring that connects the driver circuit DAk and the receiver circuit RAk to the driver circuits D0k to D3k and the receiver circuits R0k to R3k provided in each of the memory banks BANK0 to BANK3, and includes eight read / write buses RWBSk. 8 lines are provided corresponding to (8 lines are shown by one solid line in FIG. 1). Each data bus DB is commonly connected to driver circuits D0k to D3k and receiver circuits R0k to R3k. Driver circuits D0k to D3k are exclusively activated by read control signals RE0 to RE3, respectively, and receiver circuits R0k to R3k are exclusively activated by write control signals WE0 to WE3, respectively. Accordingly, read data output from any of the driver circuits D0k to D3k is transferred to the receiver circuit RAk via the data bus DB during the read operation, and is output from the driver circuit DAk during the write operation. Write data is transferred to one of the receiver circuits R0k to R3k via the data bus DB. FIG. 3 shows a connection relationship between the driver circuit DAk and the receiver circuit RAk corresponding to one data bus DB, the driver circuit D0k, and the receiver circuit R0k. As shown in FIG. 3, the input terminal of the driver circuit D0k and the output terminal of the receiver circuit R0k are connected to the I / O line MIO. The I / O line MIO is a wiring connected to a selected memory cell in the memory bank BANK0.

  The driver circuit, the receiver circuit, and the data bus shown in FIG. 1 are elements related to the data input / output terminal DQk among the circuits and wirings assigned to the memory banks BANK0 to BANK3. Therefore, actually, n + 1 sets of these elements are provided for the memory banks BANK0 to BANK3, and further provided for the memory banks BANK4 to BANK7. Therefore, in the present embodiment, 512 read / write buses RWBS are provided, and 512 data buses DB corresponding thereto are provided. In particular, since the data bus DB is a long wiring crossing four memory banks, a relatively large amount of power is consumed by charging and discharging. In the present embodiment, power consumption associated with such charging / discharging of the data bus DB is reduced.

  Each memory bank BANK0 to BANK7 includes a large number of memory cells (not shown), and the selection is performed by an address signal different from the bank addresses BA0 to BA2. The selection of the memory cells in the memory bank is not directly related to the gist of the present invention, and thus the description thereof is omitted.

  FIG. 4 is a block diagram showing the circuit portion X shown in FIG. 3 in more detail.

  As shown in FIG. 4, the driver circuit DAk outputs write data to the data bus DB via the first terminal T1, and the receiver circuit R0k receives write data from the second terminal T2. A switch circuit 120 for limiting the amplitude of the write data is inserted between the first and second terminals T1 and T2. The switch circuit 120 is a circuit that is turned on when the potential of the data bus DB is equal to or lower than a predetermined potential, and is turned off when the potential of the data bus DB exceeds the predetermined potential. Play a limiting role. The switch circuit 120 is disposed in the vicinity of the second terminal T2, and therefore, most of the load capacity of the data bus DB exists on the first terminal T1 side. That is, the relationship between the load capacity (C1) of the first terminal T1 and the load capacity (C2) of the second terminal T2 is C1 >> C2.

  The receiver circuit R0k includes an amplifier circuit AMP connected to the second terminal T2, and a latch circuit LAT that latches the output of the amplifier circuit AMP. The amplifier circuit AMP is a main circuit portion of the receiver circuit R0k, and plays a role of detecting the potential of the second terminal T2 and amplifying it. The latch circuit LAT is a circuit that latches the signal amplified by the amplifier circuit AMP and drives the I / O line MIO based on the logic level of the latched signal.

  As shown in FIG. 3, since the data bus DB is a bidirectional bus, the circuit configurations of the driver circuit D0k and the receiver circuit RAk have the same configuration as that shown in FIG. .

  FIG. 5 is a circuit diagram of the circuit block shown in FIG.

  As shown in FIG. 5, the driver circuit DAk includes N-channel MOS transistors M9 and M8 connected in series between power supply lines to which a power supply potential VPERI and a ground potential VSS are supplied, and gate electrodes of these transistors M9 and M8. Has a logic circuit L for generating a signal to be supplied to. The connection point of the transistors M9 and M8 is connected to the data bus DB. VPERI and VSS are used as the operation power supply of the logic circuit L, whereby the input signal supplied to the gate electrodes of the transistors M9 and M8 has an amplitude of VPERI to VSS. The transistors M9 and M8 may be MIS transistors. The same applies to all MOS transistors described below.

  With this configuration, when the threshold voltage of the transistors M9 and M8 is LVth, the data bus DB is driven to VPERI-LVth when the transistor M9 is turned on, and the data bus DB is driven to VSS when the transistor M8 is turned on. become. The threshold voltage LVth is designed to be relatively low. In the figure, the small circles attached to the transistors M9 and M8 mean that the threshold voltage is designed to be relatively low. The same applies to other transistors described below. In this specification, the ground potential VSS may be referred to as a “first potential”, and the power supply potential VPERI may be referred to as a “second potential”.

  The logic circuit L included in the driver circuit DAk receives the write control signal WEA and the write data DATA supplied from the read / write bus RWBSk, and generates signals to be applied to the gate electrodes of the transistors M9 and M8 based on these logic levels. . Specifically, when the write control signal WEA is activated to a high level, one of the transistors M9 and M8 is turned on based on the logic level of the write data DATA, and the write control signal WEA is not set to a low level. When activated, both transistors M9 and M8 are turned off.

  The switch circuit 120 includes an N-channel MOS transistor M7 having one end connected to the first terminal T1 and the other end connected to the second terminal T2. A power supply potential VPERI is supplied to the gate electrode of the transistor M7. With this configuration, when the threshold voltage of the transistor M7 is NVth, when the potential of the data bus DB is equal to or lower than VPERI-NVth, the transistor M7 becomes conductive, and the potential of the data bus DB exceeds VPERI-NVth. The transistor M7 changes from the conductive state to the cut-off state. The threshold voltage NVth is designed to be relatively high. That is, NVth> LVth. As described above, the transistor M7 is disposed in the vicinity of the second terminal T2, so that when the transistor M7 is in the off state, the load capacitance (C1) of the first terminal T1 and the second terminal There is a significant difference from the load capacity (C2) of T2 (C1 >> C2).

  The amplifier circuit AMP included in the receiver circuit R0k has a flip-flop configuration. The amplifier circuit AMP has a pair of first and second signal nodes S1 and S2, and first and second power supply nodes V1 and V2, and the first signal node S1 is connected to the second terminal T2. Has been. The second signal node S2 is connected to the latch circuit LAT.

  The amplifier circuit AMP has N channel type MOS transistors M1, M3, M5 and P channel type MOS transistors M2, M4, M6. The transistor M1 is connected between the power supply line to which the ground potential VSS is supplied and the power supply node V1, and the write control signal WE0 is supplied to the gate electrode. The transistor M2 is connected between the power supply line to which the power supply potential VPERI is supplied and the power supply node V2, and the inverted write control signal WE0 is supplied to the gate electrode. As a result, when the write control signal WE0 is activated to a high level, the transistors M1 and M2 are turned on and the amplifier circuit AMP is activated.

  Transistors M3 and M5 each constitute a cross-coupled circuit whose source is connected to power supply node V1. Similarly, the transistors M4 and M6 each constitute a cross-coupled circuit whose source is connected to the power supply node V2. More specifically, transistor M3 is connected between signal node S1 and power supply node V1, and its gate electrode is connected to signal node S2. The transistor M5 is connected between the signal node S2 and the power supply node V1, and its gate electrode is connected to the signal node S1. Transistor M4 is connected between signal node S1 and power supply node V2, and its gate electrode is connected to signal node S2. Transistor M6 is connected between signal node S2 and power supply node V2, and its gate electrode is connected to signal node S1.

  Thereby, when the transistors M1 and M2 are turned on, the potential difference between the signal nodes S1 and S2 is amplified by the amplifier circuit AMP. The threshold value of the amplifier circuit AMP is an intermediate potential (VPERI / 2) between the power supply potential VPERI and the ground potential VSS, and this level is lower than VPERI-NVth. The data amplified by the amplifier circuit AMP is supplied to the latch circuit LAT via the signal node S2, and is taken in synchronization with the falling edge of the write control signal WE0. The write data DOUT captured by the latch circuit LAT is supplied into the memory bank BANK0 via the I / O line MIO.

  With the above configuration, the write data DATA whose amplitude is VPERI-VSS is reduced in amplitude by the driver circuit DAk, and the reduced amplitude write data DATA is transferred via the data bus DB. On the receiver circuit R0k side, the signal reception circuit 110 reproduces the amplitude to VPERI-VSS and outputs it as write data DOUT.

  FIG. 6 is a waveform diagram showing an operation when the write data DATA changes from the low level (VSS) to the high level (VPERI).

  As shown in FIG. 6, when the write control signals WEA and WE0 are activated after the write data DATA changes from the low level (VSS) to the high level (VPERI), the transistor M9 is turned on. Begins to rise from VSS. However, since the data bus DB has a long wiring length and a large parasitic capacitance, the rising speed thereof becomes moderate to some extent. Here, since the threshold voltage of the transistor M7 constituting the switch circuit 120 is NVth, the transistor M7 is on until the potential of the data bus DB exceeds VPERI-NVth, and therefore, the second terminal The potential of T2 also rises in conjunction with the potential of the data bus DB. Further, the transistors M3 and M6 are turned on and the transistors M4 and M5 are turned off until the potential of the second terminal T2 exceeds the intermediate potential which is the threshold value of the amplifier circuit AMP. Therefore, a current flows through the transistors M9, M3, and M1 during this period, but the current supply capability of the transistors M1 and M3 is sufficiently small, and the current consumption due to this is also small. There are few.

  When the potential of the data bus DB exceeds the intermediate potential that is the threshold value of the amplifier circuit AMP, the transistors M3 and M6 are turned off and the transistors M4 and M5 are turned on. Further, when the potential of the data bus DB exceeds VPERI-NVth, the transistor M7 is turned off. As a result, the second terminal T2 is disconnected from the data bus DB, and the second terminal T2 is no longer driven by the transistor M9. However, since the transistors M2 and M4 included in the amplifier circuit AMP are already turned on at this time, the potential of the second terminal T2 is raised by the transistors M2 and M4. At this time, the load (C2) to be driven by the transistors M2 and M4 is very small (not including the load C1 of the data bus DB) because the transistor M7 is turned off, as shown in FIG. The potential at the second terminal T2 rises rapidly toward VPERI.

  As a result, the amplification operation by the amplifier circuit AMP is quickly performed, and the write data DOUT changes to the high level. Thereafter, the level of the data bus DB continues to rise gradually, and the off state of the transistor M7 is secured. The level of the data bus DB is finally charged to VPERI-LVth.

  Thus, in this embodiment, since the data bus DB is not charged up to VPERI, it is possible to suppress the charge / discharge current of the data bus DB.

  FIG. 7 is a waveform diagram showing an operation when the write data DATA changes from the high level (VPERI) to the low level (VSS).

  As shown in FIG. 7, when the write control signals WEA and WE0 are activated after the write data DATA changes from the high level (VPERI) to the low level (VSS), the potential of the data bus DB becomes VPERI by turning on the transistor M8. -Decrease from LVth. Also in this case, the rate of decrease is somewhat moderate due to the parasitic capacitance of the data bus DB. Here, since the threshold voltage of the transistor M7 constituting the switch circuit 120 is NVth, the transistor M7 is in an off state until the potential of the data bus DB becomes equal to or lower than VPERI-NVth. At this time, since the transistors M2 and M4 are on, the potential of the second terminal T2 is maintained at VPERI.

  Thereafter, when the potential of the data bus DB becomes equal to or lower than VPERI-NVth, the transistor M7 is turned on. As a result, the second terminal T2 is connected to the data bus DB, and the potential of the signal node S1 quickly decreases. At this time, since the transistors M2 and M4 are also on, current flows through the transistors M2, M4 and M8 during this period, but the current supply capability of the transistors M2 and M4 is sufficiently small, and the period is also slightly Therefore, the current consumption due to this is very small.

  When the potential of the data bus DB falls below the intermediate potential that is the threshold value of the amplifier circuit AMP, the transistors M3 and M6 are turned on and the transistors M4 and M5 are turned off. As a result, the amplification operation by the amplifier circuit AMP is quickly performed, and the write data DOUT changes to a low level. Thereafter, the level of the data bus DB continues to decrease gradually, and the on state of the transistor M7 is secured. The level of the data bus DB is finally discharged to VSS.

  As described above, according to the present embodiment, since the amplitude of the data bus DB is reduced to VPERI-LVth, it is possible to reduce power consumption associated with charging / discharging of the data bus DB. Moreover, when the amplitude of the data bus DB exceeds VPERI-NVth, the second terminal T2 is disconnected from the data bus DB, and the second terminal T2 is charged by the amplifier circuit AMP. It is also possible to increase the speed of change. On the other hand, a slight through current is generated in the period until the amplifier circuit AMP is inverted, but the increase in power consumption due to this is sufficiently smaller than the reduction in power consumption due to the amplitude reduction of the data bus DB. In particular, in the semiconductor device described in Patent Document 2, a through current is generated during a period in which the write control signals WEA and WE0 are activated when the level changes from a high level to a low level. Such a through current does not occur. As a result, the power consumption can be further reduced as compared with the semiconductor device described in Patent Document 2.

  FIG. 8 is a circuit diagram showing a modification, and the circuit configuration of the driver circuit DAk and the voltage applied to the gate electrode of the transistor M7 are different from those of the circuit shown in FIG. Since other circuit configurations are the same as those in FIG. 5, the same reference numerals are given to the same elements, and duplicate descriptions are omitted.

  In the modification shown in FIG. 8, an N-channel MOS transistor M10 is inserted between the power supply wiring to which the power supply potential VPERI is supplied and the transistor M9, and the internal potential VBUS (<VPERI) is supplied to the gate electrode. Has been. As a result, the source potential of the transistor M10 becomes VBUS-LVth, and the signal amplitude on the data bus DB is reduced to VBUS-LVth. Since the internal potential VBUS is also supplied to the gate electrode of the transistor M7 constituting the switch circuit 120, the amplitude of the signal passing through the switch circuit 120 is further limited to VBUS-NVth. As a result, the current consumption can be further reduced as compared with the circuit shown in FIG. In this specification, the internal potential VBUS may be referred to as a “third potential”.

  FIG. 9 is a circuit diagram of another embodiment.

  As shown in FIG. 9, the circuit according to the present embodiment is different from the circuit shown in FIG. Mainly different from the circuit shown in. The clocked inverter INV is inserted between the amplifier circuit AMP and the latch circuit LAT, and its input node is connected to the second signal node S2. N-channel MOS transistors M11 and M12 are connected in series between the second signal node S2 and the ground potential VSS. A write control signal REB is supplied to the gate electrodes of the transistors M11 and M12. For this reason, the second signal node S2 is fixed to the low level during the period in which the write control signal REB is at the high level. The write control signal REB is a signal obtained by delaying the inverted signal of the write control signal WEA, and is activated when the transistor M7 constituting the switch circuit 120 is turned off when the write data DATA changes from low level to high level. The amount of delay is adjusted so that

  FIG. 10 is a waveform diagram showing an operation when the write data DATA changes from the low level (VSS) to the high level (VPERI).

  As shown in FIG. 10, when the write control signal WEA is activated after the write data DATA changes from the low level (VSS) to the high level (VPERI), the transistor M9 is turned on, so that the potential of the data bus DB becomes VSS. Start to rise. As described above, since the data bus DB has a large parasitic capacitance, its rising speed becomes moderate to some extent. Here, since the threshold voltage of the transistor M7 constituting the switch circuit 120 is NVth, the transistor M7 is on until the potential of the data bus DB exceeds VPERI-NVth, and therefore, the second terminal The potential of T2 also rises in conjunction with the potential of the data bus DB. During this period, the write control signal REB is still at the high level. For this reason, the amplifier circuit AMP is inactive, and the second signal node S2 is fixed to the low level by the transistors M11 and M12. Since the amplifier circuit AMP is inactive, no current flows through the amplifier circuit AMP during this period.

  When the potential of the data bus DB exceeds VPERI-NVth, the transistor M7 changes to an off state. At this timing, the write control signal REB is activated to a low level, whereby the amplifier circuit AMP and the clocked inverter INV are activated. When the amplifier circuit AMP is activated, the potential of the first signal node S1 is sufficiently higher than the potential of the second signal node S2, so that the first signal node S1 is at the VPERI level and the second signal node is Stable to VSS level. As a result, the write data DOUT immediately becomes high level.

  As described above, in the present embodiment, since the second signal node S2 is at the low level in the initial state, it is necessary to invert the amplifier circuit AMP when the write data DATA changes from the low level to the high level. Absent. For this reason, it is possible to expand the operation margin when the write data DATA changes from the low level to the high level.

  FIG. 11 is a waveform diagram showing an operation when the write data DATA changes from the high level (VPERI) to the low level (VSS).

  As shown in FIG. 11, when the write control signal WEA is activated after the write data DATA changes from the high level (VPERI) to the low level (VSS), the potential of the data bus DB becomes VPERI-LVth by turning on the transistor M8. Start to decline. Also in this case, the rate of decrease is somewhat moderate due to the parasitic capacitance of the data bus DB. Here, since the threshold voltage of the transistor M7 included in the switch circuit 120 is NVth, the transistor M7 is in an off state until the potential of the data bus DB becomes equal to or lower than VPERI−NVth. When the potential of the data bus DB becomes equal to or lower than VPERI-NVth, the transistor M7 is turned on, and the parasitic capacitance of the data bus DB is connected to the first signal node S1. During this period, the write control signal REB is still at the high level. For this reason, the amplifier circuit AMP is inactive, and the second signal node S2 is fixed to the low level by the transistors M11 and M12. During this period, no current flows through the amplifier circuit AMP.

  Thereafter, when the write control signal REB is activated to a low level, the transistors M1 and M2 are turned on, so that the amplifier circuit AMP is activated. At this time, the level of the second signal node S2 is VSS, which is lower than the level of the first signal node S1, but at this time, the first signal node S1 is already connected to the data bus DB. The capacity of the first signal node S1 becomes very large with respect to the operating current of the amplifier circuit AMP. As a result, the amplifier circuit AMP is immediately inverted, and the first signal node S1 is driven to the VSS level and the second signal node is driven to the VPERI level. As a result, the write data DOUT becomes low level.

  As described above, in the present embodiment, although the second signal node S2 is set to the low level in the initial state, there is a large difference in the capacitance balance between the signal nodes S1 and S2. It becomes possible to invert AMP immediately.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the case where the semiconductor device according to the present invention is applied to a DRAM has been described as an example. However, the application target of the present invention is not limited to this, and other semiconductor memories (SRAM, flash memory, (PRAM, MRAM, RRAM, etc.) can also be applied to semiconductor devices other than memories. In short, the present invention can be applied to a data transmission / reception circuit including a general “driver circuit” and “receiver circuit”.

10 control unit 12 decode circuit 20 read control circuit 30 write control circuit 120 switch circuit D0k to D3k, DAk driver circuit DB data bus DQ0 to DQn data input / output terminals M1 to M12 transistors R0k to R3k, RAk receiver circuit RWBS read / write bus

Claims (11)

A driver circuit for outputting a signal to the first terminal;
A receiver circuit for receiving the signal from a second terminal;
A switch circuit connected between the first and second terminals for limiting the amplitude of the signal,
The receiver circuit includes a flip-flop amplifier circuit having a pair of first and second signal nodes, and the first signal node is connected to the second terminal. apparatus.   The amplifier circuit includes first and second power supply nodes, a first power supply line to which a first potential is supplied, and a first conductivity type first node connected between the first power supply node. The semiconductor device further comprises a transistor, a second power supply wiring to which a second potential is supplied, and a second conductivity type second transistor connected between the second power supply node. 2. The semiconductor device according to 1. The amplifier circuit is
A third transistor of the first conductivity type connected between the first signal node and the first power supply node and having a gate electrode connected to the second signal node;
A second transistor of the second conductivity type connected between the first signal node and the second power supply node and having a gate electrode connected to the second signal node;
A fifth transistor of the first conductivity type connected between the second signal node and the first power supply node and having a gate electrode connected to the first signal node;
And a sixth transistor of the second conductivity type connected between the second signal node and the second power supply node and having a gate electrode connected to the first signal node. The semiconductor device according to claim 2.   4. The semiconductor device according to claim 1, wherein the receiver circuit further includes a latch circuit connected to the second signal node of the amplifier circuit. 5.   5. The switch circuit according to claim 2, wherein the switch circuit includes a seventh transistor of a first conductivity type connected between the first and second terminals and having a predetermined potential supplied to a gate electrode. The semiconductor device as described in any one.   The semiconductor device according to claim 5, wherein the predetermined potential is equal to the second potential.   6. The semiconductor device according to claim 5, wherein the predetermined potential is a third potential that is lower than the second potential. The driver circuit includes eighth to tenth transistors connected in series in this order between the first power supply wiring and the second power supply wiring,
A connection point between the eighth transistor and the ninth transistor is connected to the first terminal,
The third potential is supplied to the gate electrode of the tenth transistor,
8. The semiconductor device according to claim 7, wherein the eighth and ninth transistors are exclusively turned on based on an input signal. The receiver circuit further includes a clocked inverter having an input node connected to the second signal node of the amplifier circuit;
The semiconductor device according to claim 5, wherein the amplifier circuit and the clocked inverter are activated simultaneously.   The semiconductor device according to claim 9, wherein the amplifier circuit and the clocked inverter are activated after the driver circuit is activated.   The semiconductor device according to claim 10, wherein the amplifier circuit and the clocked inverter are activated at a timing when the seventh transistor is turned off after the driver circuit is activated.

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