JP2016048300A - Method for driving display device and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a reverse shift (negative shift) of the threshold value of a transistor caused when a reverse bias voltage is applied to a TFT element.SOLUTION: A display device 1 includes a row of pixels each having an EL element 66 and a driving transistor 61, and is driven by a method having a reverse bias application time and an initiation time. The reverse bias application time is for application of a reverse bias voltage to between a gate electrode and a source electrode of a driving transistor 61 and the initiation time is for application of an initiation voltage, which is larger than a threshold voltage of the driving transistor 61 and producing a forward bias between the gate electrode and the source electrode of the driving transistor 61, to between the gate electrode and the source electrode of the driving transistor 61, and the length of the initiation time or the magnitude of the initiation voltage is set according to variations in the threshold voltage of the driving transistor 61 in the reverse bias application time.SELECTED DRAWING: Figure 3

Description

  The present disclosure relates to a display device that displays image data.

  A TFT element deteriorates when a voltage is applied between the gate electrode and the source electrode of the transistor. On the other hand, in Patent Document 1, a reverse bias voltage is applied between a gate electrode and a source electrode of a TFT (Thin Film Transistor) element to reduce the deterioration (for example, refer to Patent Document 1).

JP 2005-164894 A

  It is an object of the present disclosure to provide a display device driving method and a display device capable of suppressing the shift of the transistor threshold value in the reverse direction (negative shift) when a reverse bias voltage is applied to the TFT element. And

  In an EL display device according to one embodiment of the present disclosure, pixels each including a light-emitting element that emits light according to a supplied current and a driving transistor that supplies a current according to the magnitude of a luminance signal to the light-emitting element are arranged in a matrix. A driving method of a plurality of display devices, wherein a reverse bias application period in which a reverse bias voltage is applied between the gate and source of the driving transistor, and a threshold value of the driving transistor between the gate and source of the driving transistor An initialization period in which an initialization voltage that is a voltage greater than the voltage and is applied with a forward bias between the gate electrode and the source electrode of the drive transistor is applied, and the length of the initialization period or the initialization The magnitude of the voltage is set according to the fluctuation amount of the threshold voltage of the drive transistor during the reverse bias application period.

  According to the present disclosure, when a reverse bias voltage is applied to a TFT element, the threshold value of the transistor can be prevented from shifting in the reverse direction (negative shift).

It is an example of the functional block diagram of the display apparatus which concerns on embodiment. FIG. 11 illustrates an example of a circuit configuration of a display pixel included in a display device according to an embodiment. 5 is a timing chart for explaining an example of an operation at the time of driving of the display device according to the embodiment. It is a figure which shows an example of operation | movement of the pixel circuit in the timing chart shown in FIG. It is a figure which shows an example of operation | movement of the pixel circuit in the timing chart shown in FIG. It is a figure which shows an example of operation | movement of the pixel circuit in the timing chart shown in FIG. It is a figure which shows an example of operation | movement of the pixel circuit in the timing chart shown in FIG. It is a figure which shows an example of operation | movement of the pixel circuit in the timing chart shown in FIG. It is a figure which shows an example of operation | movement of the pixel circuit in the timing chart shown in FIG. It is a figure which shows the relationship between the deterioration amount of a TFT element, and the amount of forward bias voltage application. It is an external view of a thin flat TV with a built-in display device. It is a figure which shows the structure of the general pixel circuit of EL display apparatus. It is a figure which shows the relationship between the applied voltage and current amount of a TFT element in the pixel circuit shown in FIG. It is a figure which shows the relationship between the stress concerning a TFT element, and the deterioration amount of the threshold voltage of a TFT element.

  Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

  In addition, the inventors provide the accompanying drawings and the following description in order for those skilled in the art to fully understand the present disclosure, and are intended to limit the subject matter described in the claims. is not.

(Knowledge that became the basis of this disclosure)
Hereinafter, before explaining the details of the present disclosure, the knowledge forming the basis of the present disclosure will be described. FIG. 7 is a diagram illustrating a configuration of a general pixel circuit in the display device.

As illustrated in FIG. 7, the pixel circuit 100 includes a drive transistor 161, a switch 162, an EL element 166, and a capacitor element 167. Further, the pixel circuit 100 includes a Data line 176 (data line), an RFV line 168 (V _REF or V _REV ), an EL anode power line 169 (V _TFT ), and an EL cathode power line 170 (V _EL ). Is provided.

  Here, the TFT element constituting the driving transistor 161 is deteriorated by applying a voltage (Vgs) between the gate electrode and the source electrode. FIG. 8 is a diagram showing the relationship between the voltage applied to the TFT element and the amount of current in the pixel circuit 100 shown in FIG. FIG. 9 is a diagram showing the relationship between the stress applied to the TFT element and the deterioration amount of the threshold voltage of the TFT element.

  That is, as shown in FIG. 8, when a predetermined voltage is applied, the actual current flowing through the TFT element becomes smaller than the target current. Therefore, in order to pass the target current to the TFT element, it is necessary to increase the voltage applied between the gate electrode and the source electrode of the TFT element.

  Such deterioration of the TFT element can be reduced by applying a reverse bias voltage to the TFT element. However, when a reverse bias voltage is applied to a TFT element that has not deteriorated, there is a problem that the threshold voltage Vth of the TFT element shifts in the reverse direction (negative shift).

  In particular, as shown in FIG. 9, when a reverse bias voltage is applied to the TFT element when the TFT element is in an unstressed state, the TFT element is more likely to be negatively shifted than when the TFT element is high or low stress. There is a problem. Here, the no-stress state refers to a state where no voltage is applied to the pixel, such as black display.

  Thus, a display device and a driving method thereof according to one embodiment of the present invention are specifically described below with reference to the drawings. According to this configuration, it is possible to suppress a negative shift of the threshold value of the transistor when a reverse bias voltage is applied to the TFT element.

  Note that each of the embodiments described below shows a specific example of the present invention. The numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements. Also, the following figures are schematic diagrams and are not necessarily shown strictly.

(Embodiment)
[1-1. Configuration of EL display device]
In this embodiment, the case where an organic EL element is used as a light-emitting element of a display device according to one embodiment of the present disclosure will be described with reference to FIGS.

  FIG. 1 is an example of a functional block diagram of a display device according to an embodiment.

  A display device 1 shown in FIG. 1 includes a display panel control circuit 2, a scanning line driving circuit 3, a data line driving circuit 5, and a display panel 6.

  The display panel 6 is an organic EL panel, for example. The display panel 6 has at least N (for example, N = 1080) scanning lines arranged in parallel to each other, N lighting control lines, and M source signal lines arranged orthogonally ( Not shown). Further, the display panel 6 has a pixel circuit (not shown) including a thin film transistor and an EL element at each intersection of the source signal line and the scanning line.

  The display panel control circuit 2 is an example of a control unit that controls operations in a predetermined period and an initialization period described later. The display panel control circuit 2 generates a control signal S2 for controlling the data line driving circuit 5 based on the display data signal S1, and outputs the generated control signal S2 to the data line driving circuit 5. In addition, the display panel control circuit 2 generates a control signal S3 for controlling the scanning line driving circuit 3 based on the input synchronization signal. Then, the display panel control circuit 2 outputs the generated control signal S3 to the scanning line driving circuit 3.

  Here, the display data signal S1 is a signal indicating display data including a video signal, a vertical synchronization signal, and a horizontal synchronization signal. The video signal is a signal that designates each pixel value that is gradation information for each frame. The vertical synchronization signal is a signal for synchronizing the processing timing in the vertical direction with respect to the screen, and is a signal serving as a reference for processing timing for each frame. The horizontal synchronization signal is a signal for synchronizing the processing timing in the horizontal direction with respect to the screen.

  The control signal S2 includes a video signal and a horizontal synchronization signal. The control signal S3 includes a vertical synchronization signal and a horizontal synchronization signal.

  The data line driving circuit 5 drives the source signal line of the display panel 6 based on the control signal S2 generated by the display panel control circuit 2. More specifically, the data line driving circuit 5 outputs a source signal to each pixel circuit based on the video signal and the horizontal synchronization signal.

  The scanning line driving circuit 3 drives the scanning lines of the display panel 6 based on the control signal S3 generated by the display panel control circuit 2. More specifically, the scanning line driving circuit 3 outputs a scanning signal, a Ref signal, a Merge signal, and an Init signal to each pixel circuit based on the vertical synchronizing signal and the horizontal synchronizing signal.

  The display panel control circuit 2 holds in advance data indicating the relationship between the light emission state of the display panel 6 (a plurality of light emitting elements) and the fluctuation amount (deterioration amount) of the drive transistor 61 described later. Further, the display panel control circuit 2 may calculate the amount of variation in the threshold voltage of the drive transistor from the light emission state of the display panel 6 and adjust the length of the initialization period or the magnitude of the initialization voltage.

  As described above, the display device 1 is configured.

  The display device 1 includes, for example, a CPU (Central Processing Unit), a storage medium such as a ROM (Read Only Memory) that stores a control program, a working memory such as a RAM (Random Access Memory), and a communication device (not shown). A circuit may be included. The display data signal S1 is generated, for example, when the CPU executes a control program.

  FIG. 2 is a diagram illustrating an example of a circuit configuration of a display pixel included in the display device according to the embodiment.

  A pixel circuit 60 illustrated in FIG. 2 is one pixel included in the display panel 6 and has a function of emitting light by a data signal (data signal voltage) supplied via a data line 76 (data line).

The pixel circuit 60 is an example of a display pixel (light emitting pixel) and is arranged in a matrix. The pixel circuit 60 includes a drive transistor 61, a switch 62, a voltage application unit 31 having a switch 63, a switch 64, a switch 65, an EL element 66, and a capacitor element 67. Further, the pixel circuit 60 includes a data line 76 (data line), an RFV line 68 (V _REF or V _REV ), an EL anode power line 69 (V _TFT ), and an EL cathode power line 70 (V _EL ). The initialization power supply line 71 (V _INI ) and the Merge line 75 (merge line) are provided.

  Here, the Data line 76 is an example of a signal line (source signal line) for supplying a data signal voltage.

The RFV line 68 supplies a reference voltage V _REF or a reverse bias voltage V _REV as shown in FIG. 2, for example. The EL anode power supply line 69 (V _TFT ) is a high voltage side power supply line for determining the potential of the drain electrode of the drive transistor 61, and is, for example, 20V. The EL cathode power supply line 70 (V _EL ) is a low voltage side power supply line connected to the second electrode (cathode) of the EL element 66. The initialization power supply line 71 (V _INI ) is a first power supply that supplies a voltage V _INI (also referred to as an initialization voltage V _INI ) for initializing the voltage between the source and gate of the drive transistor 61, that is, the voltage of the capacitor 67. It is an example of a line.

Here, the potential difference between the reference voltage V _REF supplied by the RFV line 68 and the voltage V _INI of the initialization power supply line 71 is larger than the threshold voltage (Vth) of the driving transistor 61, that is, the threshold voltage Vth <(reference voltage). V _{REF −voltage} V _INI ).

The reference voltage V _REF supplied by the RFV line 68 and the voltage V _INI of the initialization power supply line 71 are set as follows so that no current flows through the EL element 66.

Voltage V _INI <Voltage V _EL + (Forward current threshold voltage of EL element 66), Reference voltage V _REF <Voltage V _EL + (Forward current threshold voltage of EL element 66) + (Threshold voltage Vth of drive transistor 61)

Incidentally, RFV line 68, for example, a reference voltage _{V REF} and the reverse bias voltage _{V REV} is composed of a plurality of power supply lines for supplying respectively, is switched by switching power switch (not shown), the reference voltage _{V REF,} or A reverse bias voltage V _REV may be supplied.

The EL element 66 is an example of a light emitting element that emits light according to the current supplied by the driving transistor 61 and is arranged in a matrix. The EL element 66 is, for example, an organic EL element. The EL element 66 has a cathode (second electrode) connected to the EL cathode power supply line 70 and an anode (first electrode) connected to the source (source electrode) of the drive transistor 61. Here, the voltage supplied to the EL cathode power supply line 70 is _VEL , for example, 0 (v).

  The drive transistor 61 is a voltage-driven drive element that controls the supply of current to the EL element 66, and the EL element 66 emits light by supplying a current corresponding to the voltage held in the capacitive element 67 to the EL element 66. Let

  For example, in the light emission period (period T <b> 11 described later), the drive transistor 61 causes the EL element 66 to emit light by flowing a current corresponding to the voltage (data signal voltage) held in the capacitor 67 to the EL element 66. More specifically, the drive transistor 61 converts the data signal voltage supplied to the gate electrode into a current corresponding to the data signal voltage, and supplies the converted current to the EL element 66, whereby the EL element 66 is caused to emit light.

  Further, for example, in a non-light emission period (a period T12 described later) subsequent to the light emission period, the drive transistor 61 does not cause the EL element 66 to emit light by not increasing the current to the EL element 66.

  Further, for example, a reverse bias is applied between the gate electrode and the source electrode of the drive transistor 61 in a predetermined period (reverse bias period, period T2 described later) before the initialization period. Thereby, the fluctuation amount of the threshold voltage Vth can be suppressed. After that, in an initialization period (period T5 described later), a voltage necessary for flowing a drain current to perform threshold voltage compensation of the drive transistor 61 is applied between the source electrode and the gate electrode of the drive transistor 61, In the threshold compensation period (period T6 described later), the threshold voltage of the drive transistor 61 is compensated. Although details will be described later, the description is omitted here. In this way, in addition to the threshold compensation function for correcting the fluctuation of the threshold voltage Vth, a reverse bias application function for suppressing the fluctuation amount of the threshold voltage Vth is provided. By providing the drive transistor 61 (pixel circuit 60), the threshold voltage Vth is included in the operation compensation range for a longer period of time.

  The thin film transistor (TFT) constituting the driving transistor 61 may be n-type, p-type, or a combination of both. The channel layer of the thin film transistor may be formed of any one of amorphous silicon, microcrystalline silicon, polysilicon, an oxide semiconductor, an organic semiconductor, and the like. For example, an oxide semiconductor material containing at least one of indium (In), gallium (Ga), and zinc (Zn) can be used for the oxide semiconductor. An oxide semiconductor has low off-state current, high electron mobility even in an amorphous state, and can be formed by a low-temperature process. For example, an oxide semiconductor can be formed using amorphous indium gallium zinc oxide (InGaZnO).

The capacitive element 67 is a storage capacitor for holding a voltage, and holds a voltage that determines the amount of current that the drive transistor 61 flows. Specifically, the second electrode (electrode on the node B side) of the capacitive element 67 is between the source electrode (EL cathode power supply line 70 side) of the drive transistor 61 and the anode (first electrode) of the EL element 66. It is connected. The first electrode (electrode on the node A side) of the capacitive element 67 is connected to the gate electrode of the drive transistor 61 via the switch 65. The first electrode of the capacitive element 67 is connected to the RFV line 68 that supplies the reference voltage V _REF or the reverse bias voltage V _REV via the switch 63 and the switch 65.

  The switch 62 is an example of a second switch that switches between conduction and non-conduction between a data line 76 (signal line) for supplying a data signal voltage and the first electrode of the capacitive element 67. Specifically, in the switch 62, one terminal of the drain and the source is connected to the Data line 76, the other terminal of the drain and the source is connected to the first electrode of the capacitor 67, and the scan is the scan line. A switching transistor connected to line 72. In other words, the switch 62 has a function of writing a data signal voltage (data signal) corresponding to the video signal voltage (video signal) supplied via the Data line 76 to the capacitor 67.

In the initialization period (period T5) in which the drive transistor 61 is initialized, the voltage application unit 31 applies a voltage higher than the threshold voltage Vth of the drive transistor 61 to the drive transistor 61 and the gate electrode and the source electrode of the drive transistor 61. A reference voltage V _REF with a forward bias is applied. In the predetermined period (period T2) before the initialization period (period T5), the voltage application unit 31 applies a reverse bias voltage to the drive transistor 61 that is a voltage that causes a reverse bias between the gate electrode and the source electrode of the drive transistor 61. Is applied. More specifically, the voltage application unit 31 applies a reverse bias voltage to the gate electrode of the drive transistor 61 with reference to the initialization power supply line 71 (first power supply line) in the predetermined period (period T2). Further, the voltage application unit 31 applies the reference voltage V _REF to the gate electrode of the drive transistor 61 in the initialization period (period T5) based on the initialization power line 71 (first power line).

  Here, for example, the voltage application unit 31 includes a switch 63 as shown in FIG.

The switch 63 is a fourth switch that switches between conduction and non-conduction between the RFV line 68 that supplies the reference voltage V _REF or the reverse bias voltage V _REV and the gate electrode of the driving transistor 61 and one of the drain and source terminals of the switch 65. It is an example. Specifically, as shown in FIG. 2, in the switch 63, one terminal of the drain and the source is connected to the RFV line 68, and the other terminal of the drain and the source is the gate electrode of the driving transistor 61 and the drain of the switch 65. And a switching transistor connected to one terminal of the source and having a gate connected to the Ref line 73. In other words, the switch 63 has a function of applying the reference voltage (V _REF ) or the reverse bias voltage V _REV to the gate electrode of the driving transistor 61.

The voltage application unit 31 is not limited to the configuration shown in FIG. As described above, when the RFV line 68 includes a plurality of power supply lines that respectively supply the reference voltage _VREF and the reverse bias voltage _VREF , the voltage application unit 31 includes a switch and a power supply changeover switch (not shown). ).

The switch 64 is an example of a first switch that switches between conduction and non-conduction between the second electrode of the capacitive element 67 and the source electrode of the drive transistor 61 and the initialization power supply line 71 (first power supply line). Specifically, the switch 64 has one of drain and source terminals connected to the initialization power supply line 71 (V _INI ), and the other drain and source terminal connected to the second electrode of the capacitor 67 and the drive transistor 61. The switching transistor is connected to the source electrode and the gate is connected to the Init line 74. In other words, the switch 64 has a function of applying the initialization voltage V _INI to the second electrode of the capacitor 67 and the source electrode of the driving transistor 61.

  The switch 65 is an example of a third switch that switches between conduction and non-conduction between the first electrode of the capacitive element 67 and the gate electrode of the drive transistor 61. Specifically, in the switch 65, one terminal of the drain and the source is connected to the other terminal of the drain and the source of the switch 63 and the gate electrode of the driving transistor 61, and the other terminal of the drain and the source is the capacitive element 67. The switching transistor has a gate connected to the Merge line 75. In other words, the switch 65 has a function of applying the potential of the first electrode of the capacitor 67 to the gate electrode of the driving transistor 61.

  The pixel circuit 60 is configured as described above.

  The switches 62 to 65 constituting the pixel circuit 60 will be described below as n-type TFTs, but are not limited thereto. The switches 62 to 65 may be p-type TFTs.

[1-2. Operation of EL display device]
Next, a driving method of the pixel circuit shown in FIG. 2 will be described with reference to FIGS.

FIG. 3 is a timing chart for explaining an example of the operation at the time of driving the display device according to the embodiment. 4A to 4F are diagrams illustrating an example of the operation of the pixel circuit in the timing chart illustrated in FIG. In FIG. 3, the horizontal axis represents time. Further, in the horizontal axis direction, the scan line 72, the Ref line 73, the Init line 74, the Merge line 75, and the Data line 76 are generated for the pixel circuit 60 in the corresponding row among the pixel circuits 60 in the n rows constituting the display panel 6. A voltage waveform diagram is shown. The RFV line 68 will be described below assuming that the reference voltage V _REF is supplied when the voltage level is HIGH and the reverse bias voltage V _REV is supplied when the voltage level is LOW.

  The driving method (scanning method) in this embodiment can be realized by performing the period T1 to the period T12 with the structure of the pixel circuit 60 illustrated in FIG.

  Hereinafter, the operation of the pixel circuit 60 will be specifically described by taking an example.

(Period T1)
A period T1 between time t1 and time t2 shown in FIG. 3 is a transition period for switching the voltage supplied by the RFV line.

More specifically, at time t1, the scanning line driving circuit 3 maintains the voltage levels of the Scan line 72 and the Init line 74 at LOW and the voltage levels of the Ref line 73 and the Merge line 75 at HIGH. , The voltage supplied by the RFV line 68 is switched from the reference voltage V _REF to the reverse bias voltage V _REV . That is, at time t1, the voltage supplied to the RFV line 68 is maintained while the switch 62 and the switch 64 are in a non-conductive state (off state) and the switch 63 and the switch 65 are in a conductive state (on state). _Switch from _REF to reverse bias voltage V _REV .

  Thus, by providing the period T1 that is a transition period for switching the voltage supplied by the RFV line, it is possible to prevent a through current from flowing between the EL anode power supply line 69 and the initialization power supply line 71. be able to.

When the size of the display panel 6 constituting the display device 1 or the size of one pixel (pixel circuit 60) is large, the wiring time constant of the gate signal lines (Scan line 72 to Merge line 75) increases. For this reason, when the change speed of the signal voltage of the gate signal line greatly fluctuates in the plane of the display panel 6 and the time constant of each gate signal line is different, the signal change timing may be different even in the same pixel. For example, the voltage level of the Init line 74 may become HIGH before the RFV line 68 is “L”, that is, the voltage supplied by the RFV line 68 becomes the reverse bias voltage V _REV , and a large Vgs is applied to the drive transistor 61. As a result, a through current may flow from the EL anode power supply line 69 to the initialization power supply line 71. The through current affects the power consumption of the display panel 6 and has a drawback that the power consumption increases.

  In addition, for example, when a current flows through the initialization power supply line 71, the voltage of the initialization power supply line 71 far from the power supply end increases, and the voltage applied in the initialization period becomes higher than a predetermined voltage. There is a problem in that the Vgs voltage at the start cannot be taken sufficiently and the operable Vth range becomes narrow.

Therefore, by providing the period T1 is a transition period for switching the voltage supplied to the RFV line 68 while the switch 64 non-conductive from the reference voltage _{V REF} to the reverse bias voltage _{V REV,} initialization power and the EL anode power supply line 69 A through current is prevented from flowing between the line 71 and the line 71. As an advantage of this method, further considering the period T2, since the potential of the node C is already set in the period T1, only the node B needs to be charged in the period T2, and the potential of the node B is set to the initialization power line 71. The voltage V _INI can be set in a short period (the initialization voltage V _INI is written).

(Period T2: Reverse bias period)
A period T2 from time t2 to time t3 illustrated in FIG. 3 is a reverse bias period in which the reverse bias voltage V _REV is applied to the drive transistor 61. Here, the reverse bias voltage V _REV is a voltage that causes a reverse bias between the gate electrode and the source electrode of the drive transistor 61 when the voltage V _INI of the initialization power supply line 71 is applied to the source electrode of the drive transistor 61. It is. Here, as described above, the reverse bias voltage V _REV <the initialization voltage V _INI is set.

Specifically, as shown in the operation state of the pixel circuit 60 in FIG. 4A, at the time t2, the scanning line driving circuit 3 sets the voltage level of the Scan line 72 to LOW, the Ref line 73, and the Merge line 75. the voltage level HIGH, the and, while maintaining the voltage supplied by the RFV line 68 to the reverse bias voltage _{V REV,} changing the voltage level of the Init line 74 from LOW to HIGH. That is, at time t2, the switch 62 is in a non-conductive state (off state), the switch 63 and the switch 65 are in a conductive state (on state), and the voltage supplied from the RFV line 68 is maintained at the reverse bias voltage V _REV . The switch 64 is turned on (on state).

  As described above, by providing the period T2 which is the reverse bias period in which the gate electrode and the source electrode of the drive transistor 61 are reversely biased, the variation amount of the threshold voltage Vth of the drive transistor 61 can be suppressed. In addition, the threshold voltage shifted in the light emission period (period T11) is shifted in the reverse direction, so that the fluctuation of the threshold voltage is reduced before and after one frame.

  Note that the period T2 is set so that the fluctuation of the threshold voltage becomes small before and after one frame depending on the magnitude of the reverse bias voltage to be applied and the threshold voltage shift amount in the light emission period (period T11). For example, when a forward bias voltage is 4V and a 70% period of one frame is applied, the reverse bias voltage is -10V and the reverse bias period is inserted about 20% of one frame.

  In the present embodiment, the capacitive element 67 is a semiconductor capacitor, and in order to match the deterioration characteristics of the drive transistor 61 and the capacitive element 67, the voltage level of the Merge line 75 is set to HIGH during the period T2 (reverse bias period). Although the description has been made assuming that the switch 65 is kept on, the present invention is not limited to this. When the capacitor 67 has an MIM configuration (Metal-Insulator-Metal Structure), the voltage level of the Merge line 75 may be LOW (the switch 65 is turned off) in the period T2 (reverse bias period).

(Period T3)
A period T3 from time t3 to time t4 shown in FIG. 3 is a predetermined period for turning off the switch 63 in order to switch the voltage supplied by the RFV line.

The display panel control circuit 2 makes the switch 63 conductive (ON) in a state where the switch 62 is non-conductive (OFF), the switch 65 is conductive (ON), and the switch 64 is conductive (ON), and By supplying the reverse bias voltage V _REV to the RFV line 68 to the gate electrode of the driving transistor 61, the period T3 (predetermined period) is executed.

More specifically, at time t3, the scanning line driving circuit 3 sets the voltage level of the Scan line 72 to LOW, the voltage level of the Init line 74 and the Merge line 75 to HIGH, and the voltage supplied from the RFV line 68. While maintaining the reverse bias voltage V _REV , the voltage level of the Ref line 73 is changed from HIGH to LOW. That is, at time t3, the switch 62 is in a non-conductive state (off state), the switch 64 and the switch 65 are in a conductive state (on state), and the voltage supplied from the RFV line 68 is maintained at the reverse bias voltage V _REV . The switch 63 is turned off (off state).

As described above, by providing the period T3 which is a period for making the switch 63 non-conductive, the reference voltage V _REF is applied to the gate electrode of the drive transistor 61 when the voltage supplied by the RFV line is switched, and the EL anode It is possible to prevent a through current from flowing between the power supply line 69 and the initialization power supply line 71. Without this period T3, in a pixel where the RFV line 68 rises early, a through current flows between the EL anode power supply line 69 and the initialization power supply line 71 from an early stage. On the other hand, in order to initialize, the previous pixel needs to rise to the reference voltage V _REF , and the period corresponding to the period T3 and the period T4 until the previous pixel enters the initialization period (period T5) becomes long. As a result, the ratio of the through current to the light emission current increases in consideration of the number of pixels and the time, and the power consumption of the panel increases regardless of the light emission.

(Period T4)
A period T4 from time t4 to time t5 shown in FIG. 3 is a transition period for switching the voltage supplied by the RFV line.

More specifically, at time t4, the scanning line driving circuit 3 maintains the voltage levels of the Scan line 72 and the Ref line 73 at LOW and the voltage levels of the Init line 74 and the Merge line 75 at HIGH. , The voltage supplied by the RFV line 68 is switched from the reverse bias voltage V _REV to the reference voltage V _REF . That is, at time t4, the voltage supplied to the RFV line 68 is reversed bias voltage while the switch 62 and the switch 63 are kept in a non-conductive state (off state) and the switch 64 and the switch 65 are kept in a conductive state (on state). _Switch from V _REV to reference voltage V _REF .

  Here, since the change (rise) of the voltage level of the Ref line 73 is faster than the switching of the voltage supplied by the RFV line 68, the switching of the voltage supplied by the RFV line 68 and the change of the voltage level of the Ref line 73 are performed. Without switching at the same time, the voltage supplied from the RFV line 68 is switched first.

  As described above, by providing the period T4 which is a transition period for switching the voltage supplied by the RFV line first, an indefinite voltage is applied to the gate electrode of the driving transistor 61 when the voltage supplied by the RFV line is switched. Can be prevented.

(Period T5: Initialization period)
A period T5 from time t5 to time t6 illustrated in FIG. 3 is an initialization period in which the drive transistor is initialized. Here, the initialization period is a period in which a voltage necessary for flowing a drain current to compensate the threshold voltage of the driving transistor 61 is applied between the gate electrode and the source electrode of the driving transistor 61.

  The negative shift by applying a reverse bias voltage between the gate electrode and the source electrode of the TFT element (drive transistor 61) has a property that it easily returns when a forward bias voltage is applied to the TFT element. Therefore, in the period T5, an initialization voltage for threshold voltage (Vth) compensation is applied in accordance with the light emitting state of the EL element 66 or the deterioration state of the screen.

In the present embodiment, in the initialization period, a reference voltage that is higher than the threshold voltage Vth of the drive transistor 61 and that has a forward bias between the gate electrode and the source electrode of the drive transistor 61 is applied to the gate electrode of the drive transistor 61. _Apply V _REF .

  Further, as an initialization voltage, a forward bias voltage is adjusted and applied so as not to create a stress-free state in which the TFT element performs a negative shift. The forward bias voltage is adjusted by extending the voltage application time or increasing the applied voltage.

The display panel control circuit 2 makes the switch 63 conductive (ON) with the switch 62 non-conductive (OFF), the switch 65 conductive (ON), and the switch 64 conductive (ON), and the RFV By supplying the reference voltage V _REF to the gate electrode of the driving transistor 61 through the line 68, the period T5 (initialization period) is executed.

Specifically, as shown in the operation state of the pixel circuit 60 of FIG. 4B, at time t5, the scanning line driving circuit 3 sets the voltage level of the Scan line 72 to LOW, and the voltages of the Init line 74 and the Merge line 75. The voltage level of the Ref line 73 is changed from LOW to HIGH while the level is HIGH and the voltage supplied by the RFV line 68 is maintained at the reference voltage _VREF . That is, at time t5, the switch 62 is in a non-conductive state (off state), the switch 64 and the switch 65 are in a conductive state (on state), and the voltage supplied from the RFV line 68 is maintained at the reference voltage V _REF. 63 is turned on (on state).

  Thus, the initialization period is started by changing the voltage level of the Ref line 73 from LOW to HIGH (rise).

Thereby, the potential of the node A (node C) is set to the reference voltage V _REF supplied by the RFV line 68. In addition, since the switch 64 is in a conductive state (on state), the potential of the node B is set to the voltage V _INI of the initialization power supply line 71. That is, in the drive transistor 61, the reference voltage V _REF supplied from the RFV line 68 is applied to the gate electrode, and the voltage V _INI of the initialization power supply line 71 is applied to the source electrode, so that the gate electrode of the drive transistor 61 and A predetermined voltage of forward bias is applied between the source electrodes.

  Here, the length of the period T5 is adjusted to a length (time) until the potentials of the node A (node C) and the node B become a predetermined potential according to the light emitting state of the EL element 66.

  For example, in the frame after black display, the length of the period T5 is set to 5% of one frame period (period T1 to period T12). Thereby, it can suppress that a TFT element will be in an unstressed state, and can suppress that a TFT element carries out a negative shift when a reverse bias voltage is applied.

In addition, the voltage between the gate electrode and the source electrode (predetermined voltage) of the drive transistor 61 needs to be set to a voltage that can secure a drain current necessary for performing the threshold voltage compensation operation. Therefore, as described above, the potential difference between the reference voltage V _REF of the RFV line 68 and the voltage V _INI of the initialization power supply line 71 is larger than the threshold voltage Vth of the driving transistor 61, that is, the threshold voltage Vth <(reference voltage V _{REF -Initialization} voltage V _INI ). Further, the reference voltage V _REF and the initialization voltage V _INI are set such that the initialization voltage V _INI <voltage V _EL + (the forward current threshold voltage of the EL element 66) and the reference so that no current flows through the EL element 66. Voltage V _REF <voltage V _EL + (forward current threshold voltage of EL element 66) + threshold voltage Vth.

  Note that the initialization voltage may be adjusted according to the light emission state of the EL element 66, or may be adjusted according to the deterioration state of the drive transistor 61 (a variation amount of the threshold voltage).

  The initialization voltage may be adjusted by adjusting the application time of the initialization voltage (the length of the period T5), or the magnitude of the forward bias voltage applied between the gate electrode and the source electrode of the TFT element, that is, Alternatively, the forward bias voltage application amount may be adjusted. For example, the case where the forward bias voltage application amount is adjusted will be described below.

  FIG. 5 is a diagram showing the relationship between the deterioration amount of the TFT element and the forward bias voltage application amount.

  As shown in FIG. 8, when a predetermined voltage is applied, the actual current flowing through the TFT element is smaller than the target current. That is, the TFT element deteriorates with time. Therefore, in order to pass the target current to the TFT element, it is necessary to increase the magnitude of the voltage (forward bias voltage application amount) applied between the gate electrode and the source electrode of the TFT element.

  Here, as shown in FIG. 9, the deterioration amount ΔVth of the TFT element decreases with time, so the forward bias voltage application amount applied between the gate electrode and the source electrode of the TFT element is the deterioration of the TFT element. You may make it small according to quantity (DELTA) Vth. That is, as shown in FIG. 5, the forward bias voltage applied between the gate electrode and the source electrode of the TFT element in the period T5 may be decreased with the passage of time.

  Further, the initialization voltage is adjusted based on the data indicating the relationship between the light emitting state of the EL element 66 and the variation (degradation amount) of the TFT element, which is held in advance in the display panel control circuit 2. This may be done by adjusting the length or the magnitude of the initialization voltage.

  The initialization voltage is adjusted by calculating the amount of fluctuation of the threshold voltage of the drive transistor from the light emitting state of the EL element 66 by the display panel control circuit 2 and adjusting the length of the initialization period or the magnitude of the initialization voltage. It may be done by doing. For example, by calculating the cumulative lighting time in the plane and grasping the degradation state in the plane, such as the pixel that is not lit most in the plane, it may be set to a voltage that does not affect the negative shift.

(Period T6: Threshold compensation period)
Next, a period T6 from time t6 to time t7 in FIG. 3 is a threshold compensation period in which the threshold voltage Vth of the driving transistor 61 is compensated.

Specifically, as shown in the operation state of the pixel circuit 60 in FIG. 4C, at time t6, the scanning line driving circuit 3 sets the voltage level of the Scan line 72 to LOW, the voltage level of the Ref line 73, and the Merge line 75. , And the voltage supplied by the RFV line 68 is maintained at the reference voltage V _REF , and the voltage level of the Init line 74 is changed from HIGH to LOW. That is, at time t6, the switch 62 is in a non-conductive state (off state), the switch 63 and the switch 65 are in a conductive state (on state), and the voltage supplied by the RFV line 68 is maintained at the reference voltage V _REF. 64 is turned on (on state).

Here, since the voltage (predetermined voltage) between the gate electrode and the source electrode of the driving transistor 61 is set as described above in the initialization period (period T5), no current flows through the EL element 66. The driving transistor 61 is the drain current supplied by the voltage V _TFT of the EL anode power supply line 69, the source potential of the driving transistor 61 is changed therewith. In other words, the driving transistor 61, a change in the source potential of the driving transistor 61 to the point where the drain current supplied by the voltage V _TFT of the EL anode power supply line 69 is 0.

Thus, in a state where RFV line 68 to the gate electrode of the driving transistor 61 is applied a reference voltage _{V REF} supplied, conduct (switch 65 is changed to LOW voltage level of the Init line 74 from HIGH state (ON state) The threshold compensation operation of the drive transistor 61 is started.

  At the end of the period T6 (time t7), the voltage between the gate electrode and the source electrode of the driving transistor 61 (potential difference between the node A (node C) and the node B) is a potential difference corresponding to the threshold voltage of the driving transistor 61. It becomes. This potential difference (voltage) is held (stored) in the capacitor 67.

(Period T7)
A period T7 from time t7 to time t8 illustrated in FIG. 3 is a period for ending the threshold compensation operation.

More specifically, at time t7, the scanning line drive circuit 3 refers to the voltage supplied by the RFV line 68 and the voltage level of the Scan line 72 and the Init line 74 set to LOW, the voltage level of the Ref line 73 set to HIGH. While maintaining the voltage _VREF , the voltage level of the Merge line 75 is changed from HIGH to LOW. That is, at time t7, the switch 62 and the switch 64 are in a non-conductive state (off state), the switch 63 is in a conductive state (on state), and the voltage supplied by the RFV line 68 is maintained at the reference voltage V _REF. 65 is turned off (off state).

  In this way, a period T7 is provided in which the voltage level of the Ref line 73 and the Merge line 75 is not changed at the same time, and the voltage level of the Merge line 75 is changed first to make the switch 65 non-conductive. Thereby, the penetration of the change in the voltage of the gate signal line (Scan line 72 to Merge line 75) affecting the potential of the node A through the parasitic capacitance of the switch 63 and the switch 65 can be reduced, resulting in variation in the penetration amount. The resulting display unevenness can be reduced.

  When the voltage level of the Ref line 73 and the Merge line 75 are set to LOW at the same time or when the voltage level of the Ref line 73 is first set to LOW, first, the penetration through the switch 63 propagates to the node A. When the switch 65 is turned on, the penetration by the switch 65 is then propagated to the node A.

  On the other hand, when the period T7 is provided, the penetration by the switch 65 propagates to the node A, but the penetration by the switch 63 does not propagate to the node A because the switch 65 is already in the off state. And this amount is the effect of reducing the amount of penetration.

(Period T8)
In a period T8 from time t8 to time t9 shown in FIG. 3, the data signal voltage supplied via the Data line 76 and the reference voltage V _{REF of the} RFV line 68 are set by turning off the switch 63. Is a period for preventing simultaneous application to the node A.

Specifically, at time t8, the scanning line driving circuit 3 maintains the voltage levels of the scan line 72, the init line 74, and the merge line 75 at LOW and the voltage supplied by the RFV line 68 at the reference voltage _VREF . However, the voltage level of the Ref line 73 is changed from HIGH to LOW. That is, at time t8, the switch 62, the switch 64, and the switch 65 are in a non-conductive state (off state), and the voltage supplied from the RFV line 68 is maintained at the reference voltage V _REF , while the switch 63 is in a non-conductive state (off). State).

In this way, the switch 63 is further turned off (off state) by the operation of the Ref line 73, and the period T8 in which the switch 62 and the switch 63 are turned off (off state) is provided. it is possible to prevent a data signal voltage supplied from the switch 62, from it and the reference voltage V _REF of RFV line 68 is simultaneously applied to the node a (the first electrode of the capacitor 67) Te.

  Note that the switch 63 and the switch 65 may be simultaneously turned off (off state), and the periods T7 and T8 may be combined into one.

In order to accurately reflect the potential difference of (video signal voltage−reference voltage V _REF ), the period T26 is preferably as short as possible.

(Period T9: Writing period)
Next, during a period T9 from time t9 to time t10 in FIG. 3, a video signal voltage (data signal voltage) corresponding to the display gradation is captured from the Data line 76 to the pixel circuit 60 via the switch 62 and is stored in the capacitor 67. It is a writing period for writing.

Specifically, as shown in the operation state of the pixel circuit 60 in FIG. 4D, at time t9, the scanning line driving circuit 3 sets the voltage levels of the Ref line 73, the Init line 74, and the Merge line 75 to LOW, The voltage level of the scan line 72 is changed from LOW to HIGH while maintaining the voltage supplied from the RFV line 68 at the reference voltage _VREF . That is, at time t9, the switch 63, the switch 64, and the switch 65 are in a non-conductive state (off state), and the voltage supplied from the RFV line 68 is maintained at the reference voltage V _REF , while the switch 62 is in a conductive state (on state). To.

  Thus, the video signal voltage is stored (held) in the capacitive element 67 in addition to the threshold voltage Vth of the drive transistor 61 stored in the threshold compensation period (period T6).

  As the screen is enlarged (the size of the display panel 6 is increased) and the number of the pixel circuits 60 is increased, the frame frequency for driving the pixel circuits 60 is increased. Although the scan line 72 wiring time constant increases with an increase in screen size, it becomes difficult to write a predetermined gradation voltage in the pixel circuit 60 due to the shortening of the horizontal scanning period. Therefore, in the present embodiment, even if the waveform of the scan line 72 is rounded, the scan line 72 completes the rise before the predetermined video signal (data signal voltage) is input to the data line 76, and the switch 62 Is in a conductive state (on state).

  As a result, even a large-screen display panel 6 with a large screen and a large number of pixels that has a large load (wiring time constant) on the scan line 72 and takes a long time to start can be reliably written.

(Period T10)
A period T10 between time t10 and time t11 illustrated in FIG. 3 is a period for surely bringing the switch 62 into a non-conduction state (off state).

More specifically, at time t10, the scanning line driving circuit 3 maintains the voltage levels of the Ref line 73, the Init line 74, and the Merge line 75 at LOW and the voltage supplied by the RFV line 68 at the reference voltage _VREF . However, the voltage level of the scan line 72 is changed from HIGH to LOW. That is, at time t10, the switch 63, the switch 64, and the switch 65 are in a non-conductive state (off state), and the voltage supplied from the RFV line 68 is maintained at the reference voltage V _REF while the switch 62 is in a non-conductive state (off state). State).

  Thus, the switch 62 can be reliably turned off (off state) before the switch 65 is turned on (on state) in the subsequent period T11 (light emission period).

  Note that in the case where the period T11 is not provided and the switch 65 and the switch 62 are turned on at the same time (on state), the potential of the node B is increased by the drain current of the driving transistor 61, while the potential of the node A is the data Since it becomes a signal voltage, the voltage between the source electrode and the gate electrode of the drive transistor 61 becomes small. In this case, there is a problem because light is emitted with less luminance than desired luminance. In order to prevent this, in this embodiment, after providing the period T10 to ensure that the switch 62 is in a non-conducting state (off state), the switch 65 is brought into a conducting state (on state) in the subsequent period T11. To do.

(Period T11: Light emission period)
Next, a period T11 from time t11 to time t12 illustrated in FIG. 3 is a light emission period during which the EL element 66 emits light.

Specifically, as shown in the operation state of the pixel circuit 60 in FIG. 4E, at time t11, the scanning line driving circuit 3 sets the voltage levels of the Scan line 72, the Ref line 73, and the Init line 74 to LOW, While maintaining the voltage supplied by the RFV line 68 at the reference voltage _VREF , the voltage level of the Merge line 75 is changed from LOW to HIGH. That is, at time t11, the switch 62, the switch 63, and the switch 64 are in a non-conductive state (off state), and the switch 65 is in a conductive state (on state) while maintaining the voltage supplied by the RFV line 68 at the reference voltage _VREF. To.

  In this way, by making the switch 65 conductive (on state), the drive transistor 61 is supplied with current to the EL element 66 in accordance with the voltage (data signal voltage) stored in the capacitor 67, and the EL element 66 is turned on. Can emit light.

(Period T12)
A period T12 from time t12 to time t1 shown in FIG. 3 is a black insertion period, for example, for improving moving image response, and is a period in which the EL element 66 is brought into a non-light emitting state.

More specifically, as shown in the operation state of the pixel circuit 60 in FIG. 4F, at time t12, the scanning line driving circuit 3 sets the voltage levels of the scan line 72 and the init line 74 to LOW and the merge line 75. The voltage level of the Ref line 73 is changed from LOW to HIGH while the voltage level is HIGH and the voltage supplied from the RFV line 68 is maintained at the reference voltage _VREF . That is, at time t12, the switch 62 and the switch 64 are in a non-conductive state (off state), the switch 65 is in a conductive state (on state), and the voltage supplied by the RFV line 68 is maintained at the reference voltage V _REF. 63 is made conductive.

  By the sequence as described above, the pixel circuit 60 performs gradation display.

  The display panel control circuit 2 performs the same driving method line-sequentially for the other pixel circuits 60 constituting the display panel 6.

  As described above, according to the EL display device according to the present embodiment, it is possible to suppress the TFT element from being in a stress-free state and to suppress the negative shift of the TFT element when a reverse bias voltage is applied. it can.

[1-3. Effect]
As described above, an EL display device according to one embodiment of the present disclosure includes a light-emitting element that emits light according to a supplied current and a driving transistor that supplies a current according to the magnitude of a luminance signal to the light-emitting element. A driving method of a display device in which a plurality of pixels are arranged in a matrix, wherein a reverse bias application period in which a reverse bias voltage is applied between the gate and source of the driving transistor, and between the gate and source of the driving transistor, An initialization period in which an initialization voltage is applied that is a voltage greater than the threshold voltage of the drive transistor and is forward-biased between the gate electrode and the source electrode of the drive transistor, and the length of the initialization period Alternatively, the magnitude of the initialization voltage is set according to a variation amount of the threshold voltage of the driving transistor during the reverse bias application period.

  According to this structure, it can suppress that a TFT element will be in an unstressed state, and can suppress that a TFT element carries out a negative shift when a reverse bias voltage is applied.

  The variation amount of the threshold voltage of the drive transistor may be obtained from data on the light emission state of the light emitting element acquired in advance.

  According to this configuration, the amount of fluctuation in the threshold voltage of the drive transistor is determined when the reverse bias voltage is applied by adjusting the application time or the magnitude of the forward bias voltage from the light emission state data acquired in advance. In addition, negative shift of the TFT element can be suppressed.

  The variation amount of the threshold voltage of the driving transistor may be obtained by calculating from the light emitting state of the light emitting element.

  According to this configuration, it is possible to suppress the negative shift of the TFT element when the reverse bias voltage is applied by adjusting the application time or magnitude of the forward bias voltage by calculating from the light emitting state of the light emitting element. it can.

  Further, in the display device having a plurality of pixels arranged in a matrix, each of the plurality of pixels has a light emitting element, a capacitor element for holding a voltage, and a voltage held in the capacitor element. A driving transistor that causes the light emitting element to emit light by supplying a corresponding current to the light emitting element, and a voltage that is higher than a threshold voltage of the driving transistor in the driving transistor in an initialization period in which the pixel is initialized. Applying an initializing voltage in which a forward bias is applied between the gate electrode and the source electrode of the driving transistor, and in the predetermined period of the period during which the light emitting element does not emit light before the initializing period, A voltage application unit for applying a reverse bias voltage in which a reverse bias is applied between the gate electrode and the source electrode of the driving transistor. The voltage application unit performs the initialization according to the amount of change in the threshold voltage of the drive transistor during the reverse bias application period so that the threshold of the drive transistor does not shift in the reverse direction due to the application of the reverse bias voltage. You may set the length of a period, or the magnitude | size of the said initialization voltage.

  According to this structure, it can suppress that a TFT element will be in an unstressed state, and can suppress that a TFT element carries out a negative shift when a reverse bias voltage is applied.

  The variation amount of the threshold voltage of the driving transistor may be obtained from data on the light emitting state of the light emitting element.

  According to this configuration, the amount of fluctuation in the threshold voltage of the drive transistor is determined when the reverse bias voltage is applied by adjusting the application time or the magnitude of the forward bias voltage from the light emission state data acquired in advance. In addition, negative shift of the TFT element can be suppressed.

  The variation amount of the threshold voltage of the driving transistor may be obtained by calculating from the light emitting state of the light emitting element.

  According to this configuration, it is possible to suppress the negative shift of the TFT element when the reverse bias voltage is applied by adjusting the application time or magnitude of the forward bias voltage by calculating from the light emitting state of the light emitting element. it can.

(Other embodiments)
As described above, the embodiment described above has been described as an example of the technology disclosed in the present application. However, the technology in the present disclosure is not limited thereto, and changes, replacements, additions, omissions, and the like are appropriately performed. The present invention can also be applied to other embodiments. In addition, it is possible to combine the components described in the embodiment to form a new embodiment.

  For example, the EL element 66 is typically an organic light emitting element, but may be any current-to-light conversion device as long as the light emission intensity changes according to the current.

  Further, for example, the pixel circuit constituting the display device is not limited to the pixel circuit 60 described above, and may be realized by another circuit configuration.

  For example, a voltage application unit is configured at a location different from the voltage application unit 31 shown in FIG. 2, and an Enable line is connected to the gate between the gate electrode and the source electrode of the drive transistor 61 instead of the switch 65 of FIG. A switch may be configured. One terminal of the drain and the source of the switch 63 included in the voltage application unit 31 may be connected between the switch 62 and the node A.

  Further, for example, the pixel circuit includes an enable line between the drain electrode of the drive transistor 61 and the EL anode power line 69 instead of the voltage application unit having a configuration different from the voltage application unit 31 of FIG. 2 and the switch 65 of FIG. May be a pixel circuit having a switch connected to the gate. In this case, the voltage application unit switches between conduction and non-conduction between the REV line 68 (VREF) and the gate electrode of the drive transistor 61, and conduction and non-conduction between the REV 68 (VREV) and the gate electrode of the drive transistor 61. And a switch for switching. One terminal of the drain and the source of the switch 63 and the switch 63 is connected between the switch 62 and the node A.

  Furthermore, for example, a pixel circuit having a combination of the above circuit configurations may be used. That is, the pixel circuit may have another switch instead of the above-described switch.

In the above-described embodiment, a reverse bias is applied between the gate electrode and the source electrode of the driving transistor 61 in a predetermined period (reverse bias period, period T2 described later) before the initialization period. A forward bias is applied between the gate electrode and the source electrode of the driving transistor 61. In this embodiment, an example in the case of being applied to the gate electrode of the drive transistor 61 is described, but the present invention is not limited thereto. The reverse bias may be applied not to the gate electrode of the driving transistor but to the source electrode. In that case, the reference voltage V _REF may be supplied from the gate electrode side, and the initialization voltage V _INI or the reverse bias voltage V _REV may be supplied from the source electrode side. In the example of the present disclosure, since the reference voltage V _REF <the reverse bias voltage V _REV , the potential difference between the reverse bias voltages V _REV and V _EL increases, and the EL element lights up. Therefore, it is necessary to further adjust the voltage V _EL so that (V _EL + EL forward current threshold voltage)> (reverse bias voltage V _REV ).

  As described above, the embodiments have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.

  Accordingly, among the components described in the accompanying drawings and the detailed description, not only the components essential for solving the problem, but also the components not essential for solving the problem in order to illustrate the above technique. May also be included. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

  Moreover, since the above-mentioned embodiment is for demonstrating the technique in this indication, a various change, substitution, addition, abbreviation, etc. can be performed in a claim or its equivalent range.

  The present invention can be used for a display device and a driving method thereof, and in particular, can be used for an FPD display device such as a television as shown in FIG.

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Display panel control circuit 3 Scan line drive circuit 5 Data line drive circuit 6 Display panel 31 Voltage application part 60 Pixel circuit (pixel)
61, 161 Drive transistor 62, 63, 64, 65, 162 Switch 66 EL element 67 Capacitance element 68 RFV line 69 EL anode power line 70 EL cathode power line 72 Scan line 74 Init line 75 Merge line 76 Data line

Claims (6)

A driving method of a display device in which a plurality of pixels each having a light emitting element that emits light according to a supplied current and a driving transistor that supplies a current according to the magnitude of a luminance signal to the light emitting element are arranged in a matrix. ,
A reverse bias application period in which a reverse bias voltage is applied between the gate and source of the driving transistor;
An initializing period in which an initializing voltage is applied between the gate and source of the driving transistor, the voltage being higher than the threshold voltage of the driving transistor and being forward biased between the gate electrode and the source electrode of the driving transistor; Have
The length of the initialization period or the magnitude of the initialization voltage is set according to a variation amount of the threshold voltage of the driving transistor in the reverse bias application period.
A driving method of a display device. The amount of fluctuation of the threshold voltage of the driving transistor is obtained from data of the light emitting state of the light emitting element acquired in advance.
The method for driving the display device according to claim 1. The amount of fluctuation of the threshold voltage of the driving transistor is obtained by calculating from the light emitting state of the light emitting element.
The method for driving the display device according to claim 1. A display device having a plurality of pixels arranged in a matrix,
Each of the plurality of pixels is
A light emitting element;
A capacitive element for holding the voltage;
A driving transistor for causing the light emitting element to emit light by supplying a current corresponding to the voltage held in the capacitor element to the light emitting element;
In an initialization period in which the pixel is initialized, an initialization voltage that is higher than a threshold voltage of the drive transistor and is forward biased between the gate electrode and the source electrode of the drive transistor is applied to the drive transistor. , A voltage for applying a reverse bias voltage that causes a reverse bias between the gate electrode and the source electrode of the drive transistor to the drive transistor in a predetermined period of time during which the light emitting element does not emit light before the initialization period An application unit,
The voltage application unit includes:
The length of the initialization period or the initial value is set according to the amount of fluctuation of the threshold voltage of the driving transistor in the reverse bias application period so that the threshold of the driving transistor does not shift in the reverse direction due to the application of the reverse bias voltage. Set the voltage level,
Display device. The fluctuation amount of the threshold voltage of the driving transistor is obtained from data of the light emitting state of the light emitting element.
The display device according to claim 4. The amount of fluctuation of the threshold voltage of the driving transistor is obtained by calculating from the light emitting state of the light emitting element.
The display device according to claim 4.

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