JP2016025336A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration in characteristics of a semiconductor device.SOLUTION: A semiconductor device has, on an n-type semiconductor substrate 1 made of silicon carbide, an n-type semiconductor layer 2, a p-type semiconductor region 3, a p-type base region 4, an n-type well region 8, an n-type source region 6, and a p-type contact region 7. The semiconductor region 3 is provided in a part of a surface region of the semiconductor layer 2. The base region 4 is provided on a surface of the semiconductor region 3. The well region 8 is provided on a surface of the semiconductor layer 2 so as to be in contact with the base region 4. The well region 8 is formed by ion-implanting phosphorus atoms into a part of a semiconductor layer made of silicon carbide, which is to be the base region 4, and substituting the ion-implanted phosphorus atoms with silicon atoms in the silicon carbide by heat treatment. The source region 6 and the contact region 7 may also be formed by ion implantation and heat treatment.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In a silicon carbide semiconductor device, when forming an arbitrary conductor region by ion implantation, activation heat treatment at a high temperature may be performed after ion implantation. During this activation heat treatment, surface roughness may occur due to the surface reconstruction process. Further, carbon atoms (C) remaining due to evaporation of silicon atoms may adversely affect the surface structure of the semiconductor device (see, for example, Non-Patent Document 1). In addition, when an n-type region is formed by ion implantation of nitrogen atoms (N), a large amount of carbon atoms may remain in silicon carbide by replacing nitrogen atoms with carbon atoms in silicon carbide ( For example, refer nonpatent literature 2).

  Conventionally, a method for suppressing surface roughness by depositing carbide or the like on the surface and performing high-temperature heat treatment has been disclosed. An example of the carbide includes a graphite film obtained by carbonizing an organic film such as a photoresist (see, for example, Patent Document 1). Further, a method for avoiding an adverse effect on the surface structure by oxidizing and cleaning the surface is disclosed (for example, see Patent Document 2).

JP 2005-260267 A JP 2008-53418 A

Hiroyuki Matsunami, 3 others, “Semiconductor SiC Technology and Application (Second Edition)”, Nikkan Kogyo Shimbun, p. 250 Kazuo Arai, 1 other, “Basics and Applications of SiC Devices”, Ohmsha, p. 99

  However, the conventional method of performing a heat treatment by depositing carbide or the like on the surface has a problem when applied to a semiconductor device having an insulated gate structure made of a metal-oxide film-semiconductor such as a metal oxide semiconductor (MOS). May occur. For example, when heat treatment is performed by carbonizing an organic film such as a photoresist, impurities in the photoresist react or diffuse on the surface of silicon carbide, thereby causing an interface between an insulating film such as an oxide film and a semiconductor. A large amount of impurity order may occur. As a result, there is a problem that the film quality of the gate insulating film is deteriorated, and there is a risk of deterioration of characteristics such that the breakdown voltage is lowered.

  Further, in the conventional method of cleaning by oxidizing the surface, the surface structure is cleaned by cutting, so that the amount that can be cut is limited and the cleaning may not be performed sufficiently. As a result, there is a problem that the above-described characteristic deterioration may occur.

  In order to solve the above-described problems caused by the conventional technology, the present invention can suppress the deterioration of the film quality of the gate insulating film and avoid the decrease of the breakdown voltage, thereby suppressing the deterioration of the characteristics of the semiconductor device. An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a semiconductor substrate made of silicon carbide of a first conductivity type, and the semiconductor substrate provided on the first main surface of the semiconductor substrate. A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate, a second conductivity type semiconductor region provided in a part of the surface region of the semiconductor layer, and provided on the surface of the semiconductor region; A second conductivity type base region having an impurity concentration lower than that of the semiconductor region; and a first conductivity type carbonization provided on the surface of the semiconductor layer in contact with the base region and having an impurity concentration lower than that of the semiconductor substrate. A well region made of silicon, a source region of a first conductivity type having a higher impurity concentration than the well region, provided in a surface region of the base region apart from the well region; and on a surface of the semiconductor region Said A contact region of a second conductivity type having a higher impurity concentration than the base region, a source electrode in contact with the contact region, the well region of the base region, and the well region A gate insulating film provided on the surface of the region sandwiched between the source regions, a gate electrode provided on the surface of the gate insulating film, and a drain electrode provided on the second main surface of the semiconductor substrate And a part of silicon atoms in the well region are replaced with ion-implanted phosphorus atoms.

  Also, some silicon atoms in the surface region of the well region are replaced with ion-implanted phosphorus atoms, and some carbon atoms in a region deeper than the surface region of the well region are ion It is characterized by being substituted with implanted nitrogen atoms.

  Further, the thickness of the surface region of the well region is 0.1 μm or more.

  Further, the surface region of the well region is formed by mixing nitrogen atoms and phosphorus atoms, and the ratio of phosphorus atoms to the total amount of nitrogen and phosphorus is 20 at% or more.

Further, the impurity concentration of the well region by ion implantation of phosphorus atoms is 1 × 10 ¹⁶ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less.

  The crystallographic plane index of the first main surface of the semiconductor substrate is a plane parallel to the (000-1) plane or a plane tilted within 10 degrees.

  The crystallographic plane index of the first main surface of the semiconductor substrate is a plane parallel to the (0001) plane or a plane tilted within 10 degrees.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first conductivity type first impurity having a lower impurity concentration than the semiconductor substrate is formed on a first main surface of a semiconductor substrate made of a first conductivity type silicon carbide. A step of providing a semiconductor layer; a step of ion-implanting a second conductivity type impurity into a part of a surface region of the first semiconductor layer to provide a first ion implantation region; Providing a second semiconductor layer of the second conductivity type on the base region and patterning the base region; and sandwiching the first semiconductor layer in the surface region of the first semiconductor layer between the first ion implantation region and the second semiconductor layer. Providing a second ion-implanted region by ion-implanting phosphorus atoms so that the impurity concentration is lower than that of the semiconductor substrate, and in the surface region of the second semiconductor layer. The area away from the ion implantation area In addition, a third ion implantation region is provided by ion implantation of a first conductivity type impurity so that the impurity concentration is higher than that of the second ion implantation region, and the second semiconductor layer includes the first ion implantation region. Impurities of the second conductivity type are added to regions above the first ion implantation region and in contact with the base region and the third ion implantation region so that the impurity concentration is higher than that of the second semiconductor layer. A step of performing ion implantation to provide a fourth ion implantation region in an arbitrary order and a heat treatment so that the first ion implantation region is a second conductivity type semiconductor region; A part of the ion implantation region is replaced with silicon atoms by phosphorus ions implanted, thereby forming a first conductivity type well region in contact with the first semiconductor layer, and the third ion implantation region is a first region. Conductive type A second conductivity type contact region in contact with the source region and the base region, and the well region and the source region of the second semiconductor layer, A step of providing a gate insulating film over the base region, a step of providing a gate electrode on the gate insulating film, a step of providing a source electrode in contact with the contact region, and a second main surface of the semiconductor substrate Providing a drain electrode on the substrate.

  Further, the second semiconductor layer is sandwiched between the first ion implantation region in the surface region of the first semiconductor layer between the step of patterning the second semiconductor layer and the step of performing the heat treatment. A step of providing a fifth ion implantation region by ion implantation of nitrogen atoms in a region deeper than the second ion implantation region, and performing the heat treatment. The ion-implanted region is replaced with a carbon atom by the ion-implanted nitrogen atom, thereby forming a deep region of the first conductivity type well region in contact with the first semiconductor layer, and the second ion-implanted region is By replacing the ion-implanted phosphorus atoms with silicon atoms, the surface region of the well region of the first conductivity type is in contact with the deep region of the well region and shallower than the deep region of the well region. And wherein the door.

  According to the present invention, the phosphorus atoms ion-implanted in the region to be the well region are replaced with silicon atoms having a similar atomic number in the silicon carbide during the activation heat treatment. It is possible to suppress carbon atoms that cause characteristic deterioration from remaining on the interface. As a result, deterioration of the film quality of the gate insulating film can be suppressed, and a decrease in breakdown voltage can be avoided. In addition, since the amount of phosphorus ion implantation is reduced and the temperature of the activation heat treatment can be lowered, the time and cost required for the heat treatment can be saved.

  According to the semiconductor device and the manufacturing method of the semiconductor device according to the present invention, it is possible to provide the semiconductor device and the manufacturing method of the semiconductor device capable of suppressing the deterioration of characteristics.

It is sectional drawing which shows an example of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows the state in the middle of manufacture in an example of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. FIG. 3 is a cross-sectional view showing a continuation of FIG. 2. FIG. 4 is a cross-sectional view showing a continuation of FIG. 3. FIG. 5 is a cross-sectional view showing a continuation of FIG. 4. FIG. 6 is a cross-sectional view showing a continuation of FIG. 5. It is a characteristic view which shows an example of the pressure | voltage resistant characteristic of the Example and comparative example of the semiconductor device concerning Embodiment 1 of this invention. It is a characteristic view which shows an example of the on-resistance characteristic of the Example and comparative example of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows an example of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing which shows the state in the middle of manufacture in an example of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is a characteristic view which shows an example of the concentration distribution of the ion implantation of the phosphorus atom and the nitrogen atom in the semiconductor device concerning Embodiment 2 of this invention. It is a characteristic view which shows an example of the pressure | voltage resistance characteristic and on-resistance characteristic in the semiconductor device concerning Embodiment 2 of this invention. It is a characteristic view which shows an example of the pressure | voltage resistance characteristic and on-resistance characteristic in the semiconductor device concerning Embodiment 2 of this invention.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached thereto. Further, “-” attached to p means that the impurity concentration is lower than that of the p-type layer or region attached with “-”. In this specification, in the notation of Miller index, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

  Here, a case where the semiconductor device is a MOSFET (MOS Field-Effect Transistor) of a breakdown voltage class of 1200 V, for example, will be described as an example. However, the breakdown voltage of the semiconductor device according to the present invention is not limited to the 1200 V class. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
Example of Semiconductor Device According to First Embodiment FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to the first embodiment of the present invention. As illustrated in FIG. 1, the semiconductor device 100 according to the first embodiment includes an active region 101 and a breakdown voltage structure 102. The breakdown voltage structure 102 may be arranged so as to surround the active region 101. The semiconductor device 100 includes an n ⁺ semiconductor substrate 1 and an n semiconductor layer 2 made of silicon carbide (SiC).

The n ⁺ semiconductor substrate 1 may be, for example, a silicon carbide single crystal substrate in which silicon carbide is doped with nitrogen atoms at an impurity concentration of about 2 × 10 ¹⁸ / cm ³ . The n ⁺ semiconductor substrate 1 becomes a drain region, for example. The first main surface of the n ⁺ semiconductor substrate 1 may be, for example, a (000-1) plane. The first main surface of the n ⁺ semiconductor substrate 1 may be, for example, a plane parallel to the (000-1) plane, or may be a plane inclined at an angle of 10 degrees or less. The first main surface of the n ⁺ semiconductor substrate 1 may be, for example, a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction. In the description of the present embodiment, it is assumed that the front surface of the n ⁺ semiconductor substrate 1 is the first main surface and the back surface is the second main surface.

The n semiconductor layer 2 is provided on the first main surface of the n ⁺ semiconductor substrate 1. The impurity concentration of the n semiconductor layer 2 is lower than that of the n ⁺ semiconductor substrate 1. The n semiconductor layer 2 may be a semiconductor layer in which, for example, silicon carbide is doped with nitrogen atoms at an impurity concentration of about 1 × 10 ¹⁶ / cm ³ . The n semiconductor layer 2 becomes an n-type drift layer, for example. The thickness of the n semiconductor layer 2 may be about 10 μm, for example. The n semiconductor layer 2 may be stacked on the n ⁺ semiconductor substrate 1 by an epitaxial growth method.

The structure of the active region 101 will be described. In the active region 101, the MOS structure of the semiconductor device 100, that is, the element structure is formed on the first main surface side of the n ⁺ semiconductor substrate 1. In the example shown in FIG. 1, only one MOS structure is shown in the active region 101, but a plurality of MOS structures may be provided in parallel.

The semiconductor device 100 includes, for example, a p ⁺ semiconductor region 3, a p base region 4, an n ⁺ source region 6, a p ⁺ contact region 7, a source electrode 13, a gate insulating film 9, and a gate electrode 10 as a MOS structure. In the active region 101, on the second main surface side of the n ⁺ semiconductor substrate 1, for example, a back electrode to be the drain electrode 12 and a back electrode pad to be the drain electrode pad 16 are provided.

The p ⁺ semiconductor region 3 is provided in a part of the surface region of the n semiconductor layer 2. The p ⁺ semiconductor region 3 may be provided, for example, so as to sandwich another part of the surface region of the n semiconductor layer 2. The p ⁺ semiconductor region 3 may be a semiconductor region in which, for example, silicon carbide is doped with aluminum atoms (Al) at an impurity concentration of about 3 × 10 ¹⁸ / cm ³ . The width of the p ⁺ semiconductor region 3 may be about 13 μm, for example. The depth of the p ⁺ semiconductor region 3 may be about 0.5 μm, for example. A region between adjacent p ⁺ semiconductor regions 3 and p ⁺ semiconductor region 3 is a region of n semiconductor layer 2. The distance between adjacent p ⁺ semiconductor regions 3 and p ⁺ semiconductor regions 3 may be about 2 μm, for example.

The p base region 4 is provided on the surface of the p ⁺ semiconductor region 3. The impurity concentration of the p base region 4 is lower than that of the p ⁺ semiconductor region 3. The p base region 4 may be a semiconductor region in which, for example, silicon carbide is doped with aluminum atoms at an impurity concentration of about 8 × 10 ¹⁵ / cm ³ . The thickness of the p base region 4 may be about 0.5 μm, for example. The p base region 4 may be formed by patterning a p semiconductor layer stacked on the n semiconductor layer 2 by an epitaxial growth method.

N well region 8 is provided on the surface of a region between adjacent p ⁺ semiconductor regions 3 and p ⁺ semiconductor region 3 of n semiconductor layer 2. N well region 8 is provided in contact with p base region 4. The impurity concentration of the n well region 8 is lower than that of the n ⁺ semiconductor substrate 1. The impurity concentration of the n well region 8 may be, for example, 1 × 10 ¹⁶ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. The impurity concentration of the n-well region 8 may be about 2 × 10 ¹⁶ / cm ³ , for example. The n-well region 8 may preferably be a semiconductor region having the above-described impurity concentration by doping, for example, silicon carbide with phosphorus atoms (P) as a dopant. Some silicon atoms (Si) in the n-well region 8 are replaced with ion-implanted phosphorus atoms. For example, the n-well region 8 becomes an n-type drift region together with the n semiconductor layer 2. The n-well region 8 is a region obtained by inverting the conductivity type of a part of the p-semiconductor layer stacked on the n-semiconductor layer 2 by, for example, epitaxial growth as described above by ion implantation of phosphorus atoms and heat treatment. Also good. The depth of the n well region 8 may be about 0.6 μm, for example. The width of the n-well region 8 may be about 2 μm, for example.

The n ⁺ source region 6 is provided in the surface region of the p base region 4 on the p ⁺ semiconductor region 3. N ⁺ source region 6 is provided apart from n well region 8. The impurity concentration of n ⁺ source region 6 is higher than that of n well region 8.

The p ⁺ contact region 7 is provided on the opposite side of the n well region 8 across the p base region 4, that is, on the breakdown voltage structure portion 102 side away from the n well region 8. The p ⁺ contact region 7 is in contact with the n ⁺ source region 6. For example, as described above, the p ⁺ contact region 7 penetrates the p semiconductor layer that becomes the p base region 4 on the n semiconductor layer 2 and is in contact with the p ⁺ semiconductor region 3. The impurity concentration of the p ⁺ contact region 7 is higher than that of the p base region 4.

Gate insulating film 9 is provided on the surface of the region sandwiched between n well region 8 and n ⁺ source region 6 in p base region 4. The gate insulating film 9 extends from the surface of one p base region 4 adjacent to the n well region 8 to the surface of the other p base region 4 through the surface of the n well region 8, for example. Also good. For example, the gate insulating film 9 may extend to the breakdown voltage structure 102. The gate insulating film 9 may be an oxide film, for example. The thickness of the gate insulating film 9 may be about 100 nm, for example.

  The gate electrode 10 is provided on the surface of the gate insulating film 9. The gate electrode 10 may extend, for example, from one adjacent p base region 4 across the n well region 8 to the other p base region 4 through the n well region 8. The gate electrode 10 may be made of a conductive material. The gate electrode 10 may be made of, for example, polycrystalline silicon doped with phosphorus atoms. For example, the gate electrode 10 may be electrically connected to the gate pad in a region that does not appear in FIG.

  The gate electrode 10 may be covered with, for example, an interlayer insulating film 11. For example, the interlayer insulating film 11 may extend to the breakdown voltage structure 102. The interlayer insulating film 11 may be made of, for example, phosphorus glass (PSG: Phospho Silicate Glass). The thickness of the interlayer insulating film 11 may be about 1 μm, for example.

The source electrode 13 is provided, for example, in a contact hole that penetrates the interlayer insulating film 11 provided in the active region 101 and the breakdown voltage structure 102 and the gate insulating film 9 provided in the active region 101 and the breakdown voltage structure 102. Yes. Source electrode 13 is in contact with n ⁺ source region 6 and p ⁺ contact region 7. Source electrode 13 is electrically connected to n ⁺ source region 6 and p ⁺ contact region 7. The source electrode 13 is insulated from the gate electrode 10 by the interlayer insulating film 11.

  The semiconductor device 100 may have the source electrode pad 14. The source electrode pad 14 is provided so as to cover the source electrode 13 and the interlayer insulating film 11 in the active portion 101. The source electrode pad 14 is in contact with the source electrode 13. The source electrode pad 14 is electrically connected to the source electrode 13. The thickness of the portion of the source electrode pad 14 on the interlayer insulating film 11 may be 5 μm, for example. The source electrode pad 14 may be made of aluminum containing silicon (Al—Si) at a ratio of about 1 wt%, for example.

The drain electrode 12 is provided on the second main surface of the n ⁺ semiconductor substrate 1. The drain electrode 12 may be made of a conductive film, such as a metal film. The drain electrode 12 may be made of, for example, nickel (Ni). The drain electrode 12 is in ohmic contact with the n ⁺ semiconductor substrate 1.

  The drain electrode pad 16 is provided on the surface of the drain electrode 12. The drain electrode pad 16 may be made of a conductive film, for example, a metal film. The drain electrode pad 16 may be formed by, for example, sequentially laminating titanium (Ti), nickel, and gold (Au) from the drain electrode 12 side. The drain electrode pad 16 is electrically connected to the drain electrode 12.

The structure of the breakdown voltage structure 102 will be described. The semiconductor device 100 may include a p ⁻ semiconductor region 5 a, a p ⁻ semiconductor region 5 b, and a protective film 15 in the breakdown voltage structure 102.

The p ⁻ semiconductor region 5 a is provided in a part of the surface region of the n semiconductor layer 2 in the breakdown voltage structure 102. The p ⁻ semiconductor region 5 a is in contact with, for example, the p ⁺ semiconductor region 3. The p ⁻ semiconductor region 5 a may be provided so as to surround the p ⁺ semiconductor region 3. The p ⁻ semiconductor region 5a may be a semiconductor region in which, for example, silicon carbide is doped with aluminum atoms. The impurity concentration of p ⁻ semiconductor region 5 a is lower than the impurity concentration of p ⁺ semiconductor region 3.

The p 2 ⁻ semiconductor region 5 b is provided in part of the surface region of the n semiconductor layer 2 in the breakdown voltage structure 102. The p ⁻⁻ semiconductor region 5b is in contact with, for example, the p ⁻ semiconductor region 5a. The p ⁻ semiconductor region 5b may be provided so as to surround the p ⁻ semiconductor region 5a. p ^- semiconductor regions 5b, for example aluminum atoms may be a semiconductor region doped with silicon carbide. p ^- impurity concentration of the semiconductor region 5b is, p ^- lower than the impurity concentration of the semiconductor region 5a.

As described above, the semiconductor device 100 includes a double zone JTE (junction) arranged in parallel so that two p-type regions having different impurity concentrations are in contact by the first p ⁻ -type region 5a and the second p ⁻ -type region 5b. It may have a Termination Extension) structure. The semiconductor device 100 is not limited to the double zone JTE structure, and may have a multi-zone JTE structure arranged in parallel so that three or more p-type regions having different impurity concentrations are in contact with each other. Further, the semiconductor device 100 may have a termination structure in which a plurality of p-type regions are arranged at a predetermined interval, such as a field limiting ring structure.

  The protective film 15 may be provided so as to cover the end of the source electrode pad 14 on the pressure-resistant structure 102 side. The protective film 15 becomes a passivation film. The protective film 15 has a function of preventing discharge. The protective film 15 may be made of polyimide, for example.

Example of Manufacturing Method of Semiconductor Device According to First Embodiment FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing in an example of a manufacturing method of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a continuation of FIG. FIG. 4 is a cross-sectional view showing a continuation of FIG. FIG. 5 is a cross-sectional view showing a continuation of FIG. 6 is a cross-sectional view showing a continuation of FIG.

First, as shown in FIG. 2, an n ⁺ semiconductor substrate 1 made of n-type silicon carbide is prepared. Then, a first semiconductor layer made of silicon carbide is epitaxially grown on the first main surface of the n ⁺ semiconductor substrate 1 to a thickness of, for example, about 10 μm while doping an n-type impurity such as a nitrogen atom. This first semiconductor layer becomes the n semiconductor layer 2. The state up to this point is shown in FIG.

Next, as shown in FIG. 3, a mask (not shown) having a desired opening is formed on the surface of the n semiconductor layer 2 by, for example, an oxide film by a photolithography technique. Then, p-type impurities such as aluminum atoms are ion-implanted by ion implantation. Thereby, as indicated by a broken line in FIG. 3, a first ion implantation region 21 having a width of about 13 μm and a depth of about 0.5 μm is formed in a part of the surface region of the n semiconductor layer 2. The distance between the ion implantation region 21 and the first ion implantation region 21 is about 2 μm. The first ion implantation region 21 becomes the p ⁺ semiconductor region 3 through, for example, a heat treatment described later. The dose amount during ion implantation for providing the first ion implantation region 21 may be set so that the impurity concentration of the p ⁺ semiconductor region 3 is about 3 × 10 ¹⁸ / cm ³ , for example.

Next, the mask used at the time of ion implantation for providing the first ion implantation region 21 is removed. Then, a second semiconductor layer 22 made of silicon carbide is epitaxially grown on the surface of the n semiconductor layer 2 to a thickness of, for example, about 0.5 μm while doping p-type impurities such as aluminum atoms. The second semiconductor layer 22 becomes the p base region 4 through, for example, a photolithography technique and an etching process which will be described later. The epitaxial growth conditions for providing the second semiconductor layer 22 may be set so that the impurity concentration of the p base region 4 is about 8 × 10 ¹⁵ / cm ³ , for example. The state up to here is shown in FIG.

  Next, as shown in FIG. 4, a mask (not shown) having a desired opening is formed on the surface of the second semiconductor layer 22 by photolithography. Then, the p semiconductor region 22 is formed by patterning the second semiconductor layer 22 by performing an etching process, and the second semiconductor layer 22 is formed to have a thickness of, for example, about 0.7 μm in the region that becomes the breakdown voltage structure 102. The n semiconductor layer 2 is exposed by removing at a depth. Subsequently, the mask used in the etching process for patterning the second semiconductor layer 22 is removed.

Next, a mask (not shown) having a desired opening is formed by, for example, an oxide film on the exposed surface of the n semiconductor layer 2 and the surface of the p base region 4 by photolithography. Then, p-type impurities such as aluminum atoms are ion-implanted by ion implantation. Thereby, as indicated by a broken line in FIG. 4, the sixth ion implantation region 23 is formed in a part of the surface region of the n semiconductor layer 2, for example, in the first ion implantation region 21 in the region to be the breakdown voltage structure portion 102. It is provided to touch. The sixth ion implantation region 23 becomes, for example, the p ⁻ semiconductor region 5a in the above-described double zone JTE structure, for example, through heat treatment described later. The dose amount during ion implantation for providing the sixth ion implantation region 23 may be set to, for example, about 2 × 10 ¹³ / cm ² . Subsequently, the mask used at the time of ion implantation for providing the sixth ion implantation region 23 is removed.

Next, a mask (not shown) having a desired opening is formed by, for example, an oxide film on the exposed surface of the n semiconductor layer 2 and the surface of the p base region 4 by photolithography. Then, p-type impurities such as aluminum atoms are ion-implanted by ion implantation. As a result, as indicated by a broken line in FIG. 4, in the region that becomes the breakdown voltage structure portion 102, the seventh ion implantation region 24 is formed in a part of the surface region of the n semiconductor layer 2, for example, in the sixth ion implantation region 23. It is provided to touch. The seventh ion implantation region 24 becomes, for example, the p ⁻ semiconductor region 5b in the above-described double zone JTE structure by performing a heat treatment described later, for example. The dose at the time of ion implantation for providing the seventh ion implantation region 24 may be set to, for example, about 1 × 10 ¹³ / cm ² . Subsequently, the mask used at the time of ion implantation for providing the seventh ion implantation region 24 is removed. The state up to this point is shown in FIG.

Next, as shown in FIG. 5, a mask (not shown) having a desired opening is formed by, for example, an oxide film on the exposed surface of the n semiconductor layer 2 and the surface of the p base region 4 by a photolithography technique. Then, n-type impurities such as phosphorus atoms are ion-implanted by ion implantation. Thereby, as indicated by a broken line in FIG. 5, in the second semiconductor layer 22, the region above the region of the n semiconductor layer 2 sandwiched between the adjacent first ion implantation region 21 and the first ion implantation region 21. For example, a second ion implantation region 25 having a width of about 2 μm is provided in the region. The second ion implantation region 25 becomes, for example, the n-well region 8 through, for example, a heat treatment described later. You may set the dose amount at the time of the ion implantation for providing the 2nd ion implantation area | region 25 on the conditions formed with an impurity concentration of about 2 * 10 < ¹⁶ > / cm < ³ >. Subsequently, the mask used at the time of ion implantation for providing the second ion implantation region 25 is removed.

Next, a mask (not shown) having a desired opening is formed by, for example, an oxide film on the exposed surface of the n semiconductor layer 2 and the surface of the p base region 4 by photolithography. Then, an n-type impurity such as phosphorus is ion-implanted by an ion implantation method. As a result, as shown by a broken line in FIG. 5, a third ion implantation region 26 is provided in a region away from the second ion implantation region 25 in the surface region of the second semiconductor layer 22. The third ion implantation region 26 becomes, for example, the n ⁺ source region 6 through, for example, a heat treatment described later. The dose at the time of ion implantation for providing the third ion implantation region 26 may be set so that the impurity concentration is higher than that of the second ion implantation region 25. Subsequently, the mask used at the time of ion implantation for providing the third ion implantation region 26 is removed.

Next, a mask (not shown) having a desired opening is formed by, for example, an oxide film on the exposed surface of the n semiconductor layer 2 and the surface of the p base region 4 by photolithography. Then, a p-type impurity such as aluminum is ion-implanted by an ion implantation method. Thereby, as indicated by a broken line in FIG. 5, in the second semiconductor layer 22, the region above the first ion implantation region 21 and the region in contact with the p base region 4 and the third ion implantation region 26. A fourth ion implantation region 27 is provided. The fourth ion implantation region 27 becomes, for example, the p ⁺ contact region 7 through, for example, heat treatment described later. The dose at the time of ion implantation for providing the fourth ion implantation region 27 may be set so that the impurity concentration is higher than that of the p base region 4. Subsequently, the mask used at the time of ion implantation for providing the fourth ion implantation region 27 is removed.

  The order of ion implantation for providing the sixth ion implantation region 23, the seventh ion implantation region 24, the second ion implantation region 25, the third ion implantation region 26, and the fourth ion implantation region 27, respectively. Are not limited to the order described above, and can be variously changed. The state up to here is shown in FIG.

Next, as shown in FIG. 6, heat treatment (annealing) is performed, for example, a first ion implantation region 21, a second ion implantation region 25, a third ion implantation region 26, a fourth ion implantation region 27, The sixth ion implantation region 23 and the seventh ion implantation region 24 are activated. Thereby, the first ion implantation region 21 becomes the p ⁺ semiconductor region 3. The second ion-implanted region 25 becomes the n-well region 8 by replacing the ion-implanted phosphorus atoms with silicon atoms and inverting the conductivity type. The third ion implantation region 26 becomes the n ⁺ source region 6. The fourth ion implantation region 27 becomes the p ⁺ contact region 7. The sixth ion implantation region 23 becomes the p ⁻ semiconductor region 5a. The seventh ion implantation region 24 becomes the p ⁻ semiconductor region 5b. The temperature of the heat treatment may be about 1620 ° C., for example. The heat treatment time may be, for example, about 2 minutes. As described above, the respective ion implantation regions may be activated collectively by one heat treatment, or may be activated by performing heat treatment every time ion implantation is performed.

Next, the surface on which the p base region 4, the n ⁺ source region 6, the p ⁺ contact region 7, the n well region 8, the p ⁻ semiconductor region 5a and the p ⁻ semiconductor region 5b are provided is thermally oxidized, for example, For example, a gate insulating film 9 having a thickness of about 100 nm is provided on the entire surface. This thermal oxidation treatment may be realized, for example, by performing a heat treatment at a temperature of, for example, about 1000 ° C. in an oxygen atmosphere.

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. The polycrystalline silicon layer is patterned and left on the gate insulating film 9 on the region of the p base region 4 sandwiched between the n ⁺ source region 6 and the n well region 8, thereby providing the gate electrode 10. .

Next, for example, phosphor glass is formed to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, and an interlayer insulating film 11 is provided. By patterning and selectively removing the interlayer insulating film 11 and the gate insulating film 9, a contact hole is formed, and the n ⁺ source region 6 and the p ⁺ contact region 7 are exposed. Thereafter, heat treatment (reflow) is performed to planarize the interlayer insulating film 11.

  Next, a conductive film to be the source electrode 13 is provided in the contact hole and on the interlayer insulating film 11. The conductive film is selectively removed to leave the source electrode 13 only in the contact hole, for example.

Next, the drain electrode 12 made of, for example, a nickel film is provided on the second main surface of the n ⁺ semiconductor substrate 1. Thereafter, heat treatment is performed at a temperature of, for example, about 970 ° C., and the n ⁺ semiconductor substrate 1 and the drain electrode 12 are ohmic-bonded. The state up to this point is shown in FIG.

  Next, as shown in FIG. 1, an aluminum (Al—Si) film containing silicon at a rate of, for example, about 1 wt% so as to cover the source electrode 13 and the interlayer insulating film 11 is formed by, for example, sputtering. 11 is provided so that the thickness of the portion above 11 is, for example, about 5 μm. Thereafter, the Al—Si film is selectively removed to leave the source electrode 13 and the interlayer insulating film 11 in the active region 101 so as to form the source electrode pad 14.

  Next, a protective film 15 made of polyimide, for example, is provided so as to cover the end portions of the source electrode pads 14 of the breakdown voltage structure 102 and the active portion 101 on the breakdown voltage structure 102 side.

  Next, the drain electrode pad 16 is provided on the surface of the drain electrode 12 by sequentially laminating, for example, titanium, nickel, and gold. As described above, the semiconductor device 100 shown in FIG. 1 is completed.

Example 1
A semiconductor device 100 in which the n-well region 8 is formed by ion implantation of phosphorus atoms is referred to as Example 1. In the semiconductor device 100, a semiconductor device in which the n-well region 8 is formed by ion implantation of nitrogen atoms is referred to as Comparative Example 1.

The results of verifying the breakdown voltage characteristics of Example 1 and Comparative Example 1 will be described. FIG. 7 is a characteristic diagram showing an example of a breakdown voltage characteristic between the example of the semiconductor device according to the first embodiment of the present invention and the comparative example. In FIG. 7, the vertical axis represents the breakdown voltage (unit: V), and the horizontal axis represents the impurity concentration (unit: cm ⁻³ ) of the n-well region 8. As shown in FIG. 7, as a result of the verification, in the range where the impurity concentration of the n-well region 8 is in the range of 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁸ / cm ³ , Example 1 is more preferable than Comparative Example 1. It was confirmed that the breakdown voltage characteristics were improved.

The results of verifying the on-resistance characteristics of Example 1 and Comparative Example 1 will be described. FIG. 8 is a characteristic diagram showing an example of on-resistance characteristics between the example and the comparative example of the semiconductor device according to the first embodiment of the present invention. In FIG. 8, the vertical axis represents the on-resistance (unit: Ωcm ² ), and the horizontal axis represents the impurity concentration (unit: cm ⁻³ ) of the n-well region 8. As shown in FIG. 8, as a result of the verification, in Example 1 and Comparative Example 1, for example, the impurity concentration in the n-well region 8 is in the range of 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁸ / cm ^3. It was confirmed that there was no difference in resistance characteristics.

  From the above verification results, by forming the n well region 8 by ion implantation of phosphorus atoms, the breakdown voltage characteristics are improved with the same on-resistance as compared with the case where the n well region 8 is formed by ion implantation of nitrogen atoms. I found out that I could do it.

  According to the first embodiment, the phosphorus atoms ion-implanted into the second ion implantation region 25 to be the n-well region 8 are replaced with silicon atoms having similar atomic numbers in silicon carbide during the activation heat treatment. It is possible to suppress carbon atoms that cause characteristic deterioration from remaining at the interface between the gate insulating film 9 and the n-well region 8. As a result, it is possible to prevent the film quality of the gate insulating film 9 from deteriorating, so that it is possible to avoid a decrease in breakdown voltage. Accordingly, deterioration of the characteristics of the semiconductor device 100 can be suppressed.

(Embodiment 2)
Example of Semiconductor Device According to Second Embodiment FIG. 9 is a cross-sectional view showing an example of a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 9, the semiconductor device 200 according to the second embodiment has an n well region 8 having a surface region 8a and a deep region 8b.

The surface region 8 a of the n well region 8 is provided in a shallow portion of the n well region 8. The thickness of the surface region 8a of the n-well region 8 may be, for example, about 0.03 μm to 0.25 μm. The thickness of the surface region 8a of the n-well region 8 may be, for example, 0.1 μm or more. The thickness of the surface region 8a of the n-well region 8 may be, for example, about 0.25 μm. The impurity concentration of the surface region 8a of the n-well region 8 may be, for example, 1 × 10 ¹⁶ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less, similarly to the n-well region 8 of the first embodiment. Good. The impurity concentration of the surface region 8a of the n-well region 8 may be about 2 × 10 ¹⁶ / cm ³ , for example. In the surface region 8a of the n-well region 8, for example, some silicon atoms in silicon carbide are replaced with ion-implanted phosphorus atoms. The surface region 8a of the n-well region 8 is formed by mixing nitrogen atoms and phosphorus atoms, and the ratio of phosphorus atoms to the total amount of nitrogen and phosphorus may be, for example, 20 at% or more.

The deep region 8 b of the n well region 8 is provided in a portion deeper than the surface region 8 a of the n well region 8. The thickness of the deep region 8b of the n-well region 8 is, for example, 0.4 μm (when the thickness of the surface region 8a of the n-well region 8 is 0.25 μm) to 0.62 μm (of the surface region 8a of the n-well region 8). It may be about (when the thickness is 0.03 μm). The thickness of the deep region 8b of the n-well region 8 may be about 0.4 μm, for example. The impurity concentration in the deep region 8b of the n-well region 8 is, for example, 1 × 10 ¹⁶ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less, similarly to the n-well region 8 of the first embodiment. Good. The impurity concentration of the deep region 8b of the n-well region 8 may be about 2 × 10 ¹⁶ / cm ³ , for example. In the deep region 8b of the n-well region 8, for example, some carbon atoms in silicon carbide are replaced with ion-implanted nitrogen atoms.

  Since the other configuration of the semiconductor device 200 according to the second embodiment is the same as the configuration of the semiconductor device 100 according to the first embodiment, a duplicate description is omitted.

Example of Manufacturing Method of Semiconductor Device According to Second Embodiment FIG. 10 is a cross-sectional view showing a state in the middle of manufacturing in an example of a manufacturing method of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 10, after patterning the second semiconductor layer 22, for example, before performing the activation heat treatment of the second to fourth, sixth, and seventh ion implantation regions 23 to 27, For example, nitrogen atoms are implanted into a region deeper than the ion implantation region 25. As a result, as shown by a broken line in FIG. 10, a fifth ion implantation region 28 is provided in a portion deeper than the second ion implantation region 25. In this case, the second ion implantation region 25 becomes, for example, the surface region 8a of the n-well region 8 by replacing the ion-implanted phosphorus atoms with silicon atoms during the activation heat treatment, for example. The fifth ion-implanted region 28 becomes, for example, a deep region 8b of the n-well region 8 by replacing the nitrogen atoms implanted with carbon atoms during the activation heat treatment. The ion implantation for providing the second ion implantation region 25 and the ion implantation for providing the fifth ion implantation region 28 may be performed before and after. If it does so, the 2nd ion implantation area | region 25 and the 5th ion implantation area | region 28 can be provided only by changing a dopant using the same mask.

The dose of the ion implantation for providing the second ion implantation region 25, for example, 4 × ¹⁰ 10 phosphorus at ^{40keV cm -2, 4 × 10 10} cm -2 at 70keV, 8 × ^{10 10} cm at 100keV ^-2 and 150 keV may be set to 8 × 10 ¹⁰ cm ⁻² , 200 keV to 8 × 10 ¹⁰ cm ⁻² , and 250 keV to 1 × 10 ¹¹ cm ⁻² . Under the above conditions, a box profile having an impurity concentration of, for example, about 2 × 10 ¹⁶ / cm ³ and a depth of, for example, about 0.25 μm can be formed in the surface region 8 a of the n-well region 8.

The dose during ion implantation for providing the fifth ion implantation region 28 is, for example, 1.3 × 10 ¹¹ cm ⁻² at 180 keV, 1.4 × 10 ¹¹ cm ^{−2 at} 240 keV, and 1 at 300 keV. It may be set to a condition of 1.6 × 10 ¹¹ cm ⁻² at 4 × 10 ¹¹ cm ⁻² and 360 keV and 2.8 × 10 ¹¹ cm ⁻² at 460 keV. Under the above conditions, a box profile having an impurity concentration of about 2 × 10 ¹⁶ / cm ³ and a depth of about 0.4 μm, for example, can be formed in the deep region 8 b of the n-well region 8.

  Since the other manufacturing method of the semiconductor device 200 according to the second embodiment is the same as the manufacturing method of the semiconductor device 100 according to the first embodiment, a duplicate description is omitted.

FIG. 11 is a characteristic diagram showing an example of a concentration distribution of ion implantation of phosphorus atoms and nitrogen atoms in the semiconductor device according to the second embodiment of the present invention. FIG. 11 shows a case where the dose amount at the time of ion implantation for providing the second ion implantation region 25 is combined with the dose amount at the time of ion implantation for providing the fifth ion implantation region 28 described above. The impurity concentration is shown. In FIG. 11, the vertical axis represents the impurity concentration (unit: cm ⁻³ ), and the horizontal axis represents the depth (unit: Å). The plot of “P” is the impurity concentration of phosphorus atoms, the plot of “N” is the impurity concentration of nitrogen atoms, and the “mixed phase” plot is the impurity concentration of phosphorus atoms combined with nitrogen atoms. As shown in FIG. 11, the impurity concentration is 2 × by combining the dose amount for providing the second ion implantation region 25 and the dose amount for providing the fifth ion implantation region 28 described above. A box profile of about 10 ¹⁶ cm ⁻³ is obtained.

Example 2
Example 2 is a semiconductor device 200 in which the surface region 8a of the n-well region 8 is formed by ion implantation of phosphorus atoms and the deep region 8b of the n-well region 8 is formed by ion implantation of nitrogen atoms.

The result of verifying the breakdown voltage characteristics and the on-resistance characteristics with respect to the depth of the surface region 8a of the n-well region 8 in Example 2 will be described. FIG. 12 is a characteristic diagram illustrating an example of a breakdown voltage characteristic and an on-resistance characteristic in the semiconductor device according to the second embodiment of the present invention. In FIG. 12, the vertical axis represents the breakdown voltage (unit: V) or the on-resistance (unit: Ωcm ² ), and the horizontal axis represents the depth (unit: μm) of the surface region 8 a of the n-well region 8. As shown in FIG. 12, as a result of the verification, the thickness of the surface region 8a of the n-well region 8 is less than 0.1 μm in the range where the thickness of the surface region 8a of the n-well region 8 is 0.1 μm to 0.5 μm. It was confirmed that the withstand voltage characteristics were improved without increasing the on-resistance as compared with the case of.

  By the way, when the surface region 8a of the n-well region 8 and the deep region 8b of the n-well region 8 are formed by the ion implantation method, the constituent atoms of the regions 8a and 8b may be mixed with each other in the boundary region between the regions 8a and 8b. is there. Thereby, for example, nitrogen atoms may exist in a shallow region of the surface region 8a of the n-well region 8, and such nitrogen atoms may affect the characteristics of the semiconductor device. Therefore, in Example 2, in order to investigate the influence of the amount of nitrogen atoms existing in the shallow region of the surface region 8a of the n-well region 8 on the characteristics of the semiconductor device, phosphorus atoms in the surface region 8a of the n-well region 8 are examined. The withstand voltage characteristics and on-resistance characteristics were verified by changing the concentration.

The result of verifying the breakdown voltage characteristic and the on-resistance characteristic with respect to the concentration of phosphorus atoms in the surface region 8a of the n-well region 8 will be described for Example 2. FIG. 13 is a characteristic diagram illustrating an example of a breakdown voltage characteristic and an on-resistance characteristic in the semiconductor device according to the second embodiment of the present invention. In FIG. 13, the vertical axis represents breakdown voltage (unit: V) or on-resistance (unit: Ωcm ² ), and the horizontal axis represents the concentration of phosphorus atoms. The plot of “0.2 μm breakdown voltage” is the breakdown voltage when the thickness of the surface region 8 a of the n-well region 8 is 0.2 μm. The plot of “0.5 μm breakdown voltage” is the breakdown voltage when the thickness of the surface region 8 a of the n-well region 8 is 0.5 μm. The plot of “0.2 μm on-resistance” is the on-resistance when the thickness of the surface region 8 a of the n-well region 8 is 0.2 μm. The plot of “0.5 μm on-resistance” is the on-resistance when the thickness of the surface region 8a of the n-well region 8 is 0.5 μm. As shown in FIG. 13, when the concentration of phosphorus atoms in the surface region 8a of the n well region 8 is 20 at% or more as a result of the verification, the concentration of phosphorus atoms in the surface region 8a of the n well region 8 is less than 20 at%. It was confirmed that the withstand voltage characteristics were improved without increasing the on-resistance as compared with the case of.

  According to the second embodiment, as in the first embodiment, it is possible to prevent carbon atoms that cause characteristic deterioration from remaining at the interface between the gate insulating film 9 and the surface region 8a of the n-well region 8. Therefore, the deterioration of the film quality of the gate insulating film 9 can be suppressed, and the breakdown voltage can be prevented from decreasing. Therefore, deterioration of the characteristics of the semiconductor device 200 can be suppressed. According to the second embodiment, since the deep region 8b of the n well region 8 is formed by ion implantation of nitrogen atoms, the amount of phosphorus atom ion implantation in the n well region 8 is reduced. In order to ionize the ion-implanted phosphorus atoms, it is necessary to perform the activation heat treatment at a high temperature. However, the temperature of the activation heat treatment can be lowered by reducing the ion implantation amount of the phosphorus atoms. Therefore, the time and cost required for the activation heat treatment can be saved.

In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. For example, the surface orientation of the first main surface of the n ⁺ semiconductor substrate 1 can be variously changed. For example, the first main surface of the n ⁺ semiconductor substrate 1 is a plane parallel to the (0001) plane or a plane inclined at an angle of 10 degrees or less with respect to the (0001) plane, for example, 4 in the <11-20> direction. It may be a (0001) plane having an off angle on the order of degrees. A semiconductor device such as a Schottky barrier diode may be formed on the first main surface. For example, the dimensions and concentrations described in each embodiment are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for, for example, a high voltage semiconductor device, and are used particularly for power supply devices such as power conversion devices and various industrial machines. Suitable for high voltage semiconductor devices.

1 n ⁺ semiconductor substrate 2 n semiconductor layer (first semiconductor layer)
3 p ⁺ semiconductor region 4 p base region 6 n ⁺ source region 7 p ⁺ contact region 8 n well region 8a surface region of n well region 8b deep region of n well region 9 gate insulating film 10 gate electrode 12 drain electrode 13 source electrode DESCRIPTION OF SYMBOLS 21 1st ion implantation area | region 22 2nd semiconductor layer 25 2nd ion implantation area | region 26 3rd ion implantation area | region 27 4th ion implantation area | region 28 5th ion implantation area | region 100,200 Semiconductor device

Claims (9)

A semiconductor substrate made of silicon carbide of the first conductivity type;
A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate, provided on the first main surface of the semiconductor substrate;
A semiconductor region of a second conductivity type provided in a part of the surface region of the semiconductor layer;
A base region of a second conductivity type provided on the surface of the semiconductor region and having an impurity concentration lower than that of the semiconductor region;
A well region made of silicon carbide of the first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the surface of the semiconductor layer in contact with the base region;
A source region of a first conductivity type provided in a surface region of the base region apart from the well region and having a higher impurity concentration than the well region;
A second conductivity type contact region having a higher impurity concentration than the base region, provided on the surface of the semiconductor region in contact with the source region and the base region;
A source electrode in contact with the contact region;
A gate insulating film provided on a surface of a region of the base region sandwiched between the well region and the source region;
A gate electrode provided on a surface of the gate insulating film;
A drain electrode provided on the second main surface of the semiconductor substrate,
A semiconductor device, wherein a part of silicon atoms in the well region is substituted with ion-implanted phosphorus atoms. Some silicon atoms in the surface region of the well region are replaced with ion-implanted phosphorus atoms,
2. The semiconductor device according to claim 1, wherein a part of carbon atoms in a region deeper than the surface region of the well region is substituted with ion-implanted nitrogen atoms.   The semiconductor device according to claim 2, wherein the thickness of the surface region of the well region is 0.1 μm or more.   4. The semiconductor device according to claim 3, wherein the surface region of the well region is formed by mixing nitrogen atoms and phosphorus atoms, and a ratio of phosphorus atoms to a total amount of nitrogen and phosphorus is 20 at% or more. . The impurity concentration in the well region by ion implantation of phosphorus atoms is 1 × 10 ¹⁶ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. A semiconductor device according to 1.   6. The crystallographic plane index of the first main surface of the semiconductor substrate is a plane parallel to a (000-1) plane or a plane tilted within 10 degrees. The semiconductor device according to any one of the above.   6. The crystallographic plane index of the first principal surface of the semiconductor substrate is a plane parallel to the (0001) plane or a plane tilted within 10 degrees. The semiconductor device as described in any one. Providing a first conductivity type first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate on a first main surface of a semiconductor substrate made of silicon carbide of the first conductivity type;
Providing a first ion implantation region by ion-implanting a second conductivity type impurity into a part of the surface region of the first semiconductor layer;
Providing a second conductivity type second semiconductor layer on the first semiconductor layer and patterning the base region;
Phosphorus atoms in the surface region of the second semiconductor layer above the region sandwiched between the first ion implantation regions so as to have an impurity concentration lower than that of the semiconductor substrate. To provide a second ion implantation region, and in the surface region of the second semiconductor layer, in a region away from the second ion implantation region, the impurity concentration is higher than that of the second ion implantation region. Providing a third ion-implanted region by ion-implanting a first conductivity type impurity so as to be high, and in the second semiconductor layer above the first ion-implanted region, and Providing a fourth ion implantation region by ion implantation of a second conductivity type impurity in the base region and a region in contact with the third ion implantation region so that the impurity concentration is higher than that of the second semiconductor layer. When And performing in any order,
A heat treatment is performed to make the first ion implantation region a second conductivity type semiconductor region, and a part of the second ion implantation region is replaced with silicon atoms by ion-implanted phosphorus atoms. The first conductivity type well region is in contact with the first semiconductor layer, the third ion implantation region is a first conductivity type source region, and the fourth ion implantation region is used as the source region and the base region. Forming a contact region of a second conductivity type in contact;
Providing a gate insulating film on a base region between the well region and the source region of the second semiconductor layer;
Providing a gate electrode on the gate insulating film;
Providing a source electrode in contact with the contact region;
Providing a drain electrode on the second main surface of the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: Between the step of patterning the second semiconductor layer and the step of performing the heat treatment, the surface of the first semiconductor layer of the second semiconductor layer is sandwiched between the first ion implantation regions Further comprising a step of providing a fifth ion implantation region by implanting nitrogen atoms into a region deeper than the second ion implantation region.
In the heat treatment step, the fifth ion implantation region is made a deep region of the first conductivity type well region in contact with the first semiconductor layer by replacing the nitrogen atoms implanted with carbon atoms. The second ion-implanted region is replaced with silicon atoms by ion-implanted phosphorus atoms, thereby contacting a deep region of the well region and a first conductivity type well shallower than the deep region of the well region. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the surface region is a region of the region.

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