JP2017147471A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a low contact resistance.SOLUTION: A semiconductor device according to an embodiment comprises: an SiC layer; an electrode electrically connected with the SiC layer; and an impurity region provided between the SiC layer and the electrode, and whose maximum concentration of an impurity is 1×10cmor more and 5×10cmor less, and in which a first distance between a first position of the maximum concentration of the impurity and a second position where the concentration of the impurity is reduced by one digit from the maximum concentration at the SiC layer side from the first position, is 50 nm or less, and a second distance between the electrode and the second position is 50 nm or less.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  SiC (silicon carbide) is expected as a material for next-generation semiconductor devices. Compared with Si (silicon), SiC has excellent physical properties such as a band gap of 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing this characteristic, it is possible to realize a semiconductor device capable of operating at high temperature with low loss.

  However, a semiconductor device using SiC has a problem that the contact resistance between the SiC layer and the contact electrode is increased. The high contact resistance is believed to be due to the low impurity concentration and activation rate in the SiC layer.

JP 2007-141950 A

  An object of the present invention is to provide a semiconductor device having a low contact resistance.

The semiconductor device of the embodiment is provided between the SiC layer, the electrode electrically connected to the SiC layer, and the SiC layer and the electrode, and the maximum impurity concentration is 1 × 10 ²⁰ cm ⁻³ or more. 5 × 10 ²² cm ⁻³ or less, and a first position of the maximum concentration of the impurity, and a second position where the concentration of the impurity on the SiC layer side from the first position is decreased by an order of magnitude. And an impurity region having a first distance between the electrode and the second position of 50 nm or less.

1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. The figure which shows the crystal structure of the SiC semiconductor of 1st Embodiment. The figure which shows the element profile of the semiconductor device of 1st Embodiment. FIG. 3 is a process flow diagram illustrating a method for manufacturing the semiconductor device of the first embodiment. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. Explanatory drawing of an effect | action of 1st Embodiment. FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 6 is a process flow diagram illustrating a method for manufacturing a semiconductor device of a second embodiment. In the manufacturing method of the semiconductor device of a 2nd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 2nd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 2nd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 2nd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. Explanatory drawing of an effect | action of 2nd Embodiment. FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a third embodiment. FIG. 9 is a process flow diagram illustrating a method for manufacturing a semiconductor device of a third embodiment. In the manufacturing method of the semiconductor device of a 3rd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 3rd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 3rd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 3rd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 3rd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 3rd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 3rd embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members and the like are denoted by the same reference numerals, and the description of the members and the like once described is omitted as appropriate.

In the following description, the notations n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ represent the relative level of impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n, and n ⁻ indicates that the n-type impurity concentration is relatively lower than n. Further, p ⁺ indicates that the p-type impurity concentration is relatively higher than p, and p ⁻ indicates that the p-type impurity concentration is relatively lower than p. In some cases, n ⁺ type and n ⁻ type are simply referred to as n type, p ⁺ type and p ⁻ type as simply p type.

  In this specification, “projected range” means the peak concentration position of impurities ion-implanted from the surface of the SiC layer. The “projected range” can be controlled by ion implantation conditions.

(First embodiment)
The semiconductor device of this embodiment is provided between the SiC layer, the electrode electrically connected to the SiC layer, and the SiC layer and the electrode, and the maximum impurity concentration is 1 × 10 ²⁰ cm ⁻³ or more and 5 ×. An impurity region having a maximum impurity concentration of 10 ²² cm ⁻³ or less and a distance between the maximum concentration position and the position on the SiC layer side where the impurity concentration is decreased by an order of magnitude of the maximum concentration is 50 nm or less; Is provided.

  FIG. 1 is a schematic cross-sectional view showing a configuration of a PIN diode that is a semiconductor device of the present embodiment.

The PIN diode 100 includes a SiC substrate 10. The SiC substrate 10 includes an n-type SiC layer 10a and an n ⁻ -type SiC drift layer 10b on the n ^- type SiC layer 10a.

SiC layer 10a has first and second surfaces. In FIG. 1, the first surface is the upper surface of the drawing, and the second surface is the lower surface of the drawing. The SiC layer 10a is, for example, 4H—SiC SiC containing, for example, N (nitrogen) as an n-type impurity having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  FIG. 2 is a diagram showing a crystal structure of the SiC semiconductor. A typical crystal structure of the SiC semiconductor is a hexagonal system such as 4H—SiC. One of the surfaces (the top surface of the hexagonal column) whose normal is the c-axis along the axial direction of the hexagonal column is the (0001) surface. A plane equivalent to the (0001) plane is referred to as a silicon plane and expressed as a {0001} plane. Si (silicon) is arranged on the silicon surface.

  The other side of the surface (the top surface of the hexagonal column) having the c-axis along the axial direction of the hexagonal column as a normal is the (000-1) plane. A plane equivalent to the (000-1) plane is referred to as a carbon plane and expressed as a {000-1} plane. C (carbon) is arranged on the carbon surface

  On the other hand, the side surface (column surface) of the hexagonal column is an M plane that is equivalent to the (1-100) plane, that is, the {1-100} plane. Further, the plane passing through a pair of ridge lines that are not adjacent to each other is the plane A equivalent to the (11-20) plane, that is, the {11-20} plane. Both Si (silicon) and C (carbon) are arranged on the M plane and the A plane.

  Hereinafter, the case where the first surface of SiC layer 10a is a surface inclined by 0 to 8 degrees with respect to the silicon surface and the second surface is a surface inclined by 0 to 8 degrees with respect to the carbon surface will be described as an example. To do. A surface inclined by 0 ° or more and 8 ° or less with respect to the silicon surface and a surface inclined by 0 ° or more and 8 ° or less with respect to the carbon surface can be regarded as substantially equivalent to the silicon surface and the carbon surface, respectively.

The drift layer 10b is, for example, a SiC epitaxial growth layer formed by epitaxial growth on the SiC layer 10a. The impurity concentration of the n-type impurity in the drift layer 10b is, for example, 5 × 10 ¹⁵ or more and 2 × 10 ¹⁶ cm ⁻³ or less. The n-type impurity is, for example, N (nitrogen).

  The surface of the drift layer 10b is also a surface inclined at 0 ° or more and 8 ° or less with respect to the silicon surface. The film thickness of the drift layer 10b is, for example, not less than 5 μm and not more than 150 μm.

On the surface of the drift layer 10b, for example, a p-type anode layer (SiC layer) 12 having an impurity concentration of p-type impurities of 1 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less is formed. The depth of the anode layer 12 is, for example, about 0.3 μm.

  A metal anode electrode (electrode) 14 is provided on the anode layer 12. The anode layer 12 and the anode electrode 14 are electrically connected.

  The anode electrode 14 is, for example, a metal. The metal forming the anode electrode 14 is, for example, TiN (titanium nitride). For example, another metal such as Al (aluminum) may be laminated on TiN. In addition to the metal, for example, a conductive material such as polycrystalline silicon containing an n-type impurity can be applied.

The carbon concentration in the metal forming the anode electrode 14 is 1 × 10 ¹⁸ cm ⁻³ or less.

  A p-type impurity region (impurity region) 16 containing a p-type impurity is provided between the anode layer 12 and the anode electrode 14.

FIG. 3 is a diagram showing an element profile of the semiconductor device of this embodiment. A concentration profile of p-type impurities in a cross section including a p-type anode layer (p-type SiC layer) 12 and an anode electrode (electrode) 14 is shown. In the p-type impurity region 16, the maximum concentration of the p-type impurity is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ²² cm ⁻³ or less. The p-type impurity concentration of the p-type impurity region 16 can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry).

  As shown in FIG. 3, p-type impurities are segregated at a high concentration at the interface between the anode layer 12 and the anode electrode 14. The distance (d in FIG. 3) between the position of the maximum concentration of the p-type impurity and the position where the concentration of the p-type impurity on the anode layer 12 side is decreased by an order of magnitude from the position of the maximum concentration of the p-type impurity is 50 nm. It is as follows. The distance between the position of the maximum concentration of the p-type impurity and the position where the concentration of the p-type impurity on the anode layer 12 side is decreased by an order of magnitude from the position of the maximum concentration of the p-type impurity is, for example, AFM (Atomic Force Microscope). ). Alternatively, the density distribution can also be measured by an atom probe.

  In the p-type impurity region 16, for example, a p-type impurity enters the SiC lattice position and is activated.

  The p-type impurity contained in the p-type impurity region 16 is, for example, Al (aluminum). The p-type impurity may be B (boron), Ga (gallium), or In (indium).

  A metal cathode electrode 18 is formed on the opposite side to the drift layer 10b of the SiC substrate 10, that is, on the second surface side. The cathode electrode 18 is constituted by, for example, a laminate of a Ni (nickel) barrier metal layer and an Al (aluminum) metal layer on the barrier metal layer. The Ni barrier metal layer and the Al metal layer may form an alloy by reaction. Further, Ni may react with SiC substrate 10 to form silicide.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. In the method of manufacturing a semiconductor device according to the present embodiment, impurities are ion-implanted into a SiC layer in a predetermined projected range, the SiC layer is oxidized to a region deeper than the projected range of ion implantation, and an oxide film is formed. The oxide film is peeled off and an electrode is formed on the SiC layer. The manufacturing method of the semiconductor device of this embodiment is an example of a manufacturing method of the semiconductor device shown in FIG.

  FIG. 4 is a process flow diagram illustrating the method for manufacturing a semiconductor device of this embodiment. 5 to 8 are schematic cross-sectional views showing a semiconductor device being manufactured in the method for manufacturing a semiconductor device according to the present embodiment.

As shown in FIG. 4, the method of manufacturing the semiconductor device of this embodiment includes n ⁻ SiC layer formation (step S100), p-type impurity ion implantation (step S102), annealing (step S104), and oxide film formation (step S106). ), Oxide film peeling (step S108), anode electrode formation (step S110), and cathode electrode formation (step S112).

  First, an n-type SiC layer 10a having a first surface that is a silicon surface and a second surface that is a carbon surface is prepared.

Next, in step S100, an n ⁻ type SiC drift layer 10b is formed on the first surface of the SiC layer 10a by epitaxial growth. N-type SiC layer 10a and n ⁻ -type drift layer 10b constitute SiC substrate 10 (FIG. 5).

Next, in step S102, p-type impurities are ion-implanted into the drift layer 10b by a known ion implantation method (FIG. 6). The p-type impurity is, for example, Al (aluminum). The dose amount of ion implantation is, for example, 1 × 10 ¹⁵ cm ⁻² or more and 1 × 10 ¹⁷ cm ⁻² or less. From the viewpoint of increasing the concentration of the p-type impurity region 16 to be formed later, it is desirably 1 × 10 ¹⁶ cm ⁻² or more.

  Next, in step S104, after the p-type impurity is ion-implanted, activation annealing for activating the p-type impurity is performed. The activation annealing is performed, for example, at a temperature of 1700 ° C. or higher and 1900 ° C. or lower in an inert gas atmosphere.

  A p-type anode layer 12 is formed by ion implantation of p-type impurities and activation annealing.

  Next, in step S106, the drift layer 10b is thermally oxidized to form an oxide film 20 (FIG. 7). The drift layer 10b is thermally oxidized to a region deeper than the projected range (Rp) of Al ion implantation to form an oxide film 20.

  The thermal oxidation is performed, for example, at a temperature of 800 ° C. or higher and 1500 ° C. or lower in an oxidizing atmosphere. It is desirable that it is 900 degreeC or more and 1350 degrees C or less. It is further desirable that the temperature is 1000 ° C. or higher and 1300 ° C. or lower.

  The thickness of the oxide film 20 to be formed depends on the projected range (Rp). However, when the Si surface is used as in this embodiment, it is preferably 50 nm to 1000 nm, and preferably 100 nm to 300 nm. It is more desirable. Below the above range, the p-type impurity region 16 may not be sufficiently concentrated. Moreover, when it exceeds the said range, there exists a possibility that manufacturing time may increase and manufacturing cost may increase.

  When the oxide film 20 is formed, the p-type impurity piles up at the interface between the oxide film 20 and the anode layer 12 and segregates at a high concentration, and the p-type impurity region 16 is formed. The p-type impurity enters and activates carbon vacancies formed on the surface of the anode layer 12 during thermal oxidation. Alternatively, the p-type impurity enters and activates the Si lattice position after substitution of carbon vacancies formed on the surface of the anode layer 12 and Si (silicon) during thermal oxidation.

  Further, interstitial carbon generated on the surface of the anode layer 12 during thermal oxidation diffuses into the anode layer 12 and the SiC substrate 10 and enters carbon vacancies inside the anode layer 12 and the SiC substrate 10. Thereby, the density | concentration of the carbon void | hole in the anode layer 12 and the SiC substrate 10 reduces.

  Next, in step S108, the oxide film 20 is removed (FIG. 8). The oxide film 20 is removed by, for example, hydrofluoric acid-based wet etching.

  Thereafter, the anode electrode 14 is formed on the anode layer 12 in step 110 by a known process. In step 112, the cathode electrode 18 is formed on the back side of the SiC substrate 10, and the PIN diode 100 of the present embodiment shown in FIG. 1 is manufactured.

  Hereinafter, the operation and effect of the semiconductor device and the method for manufacturing the semiconductor device of the present embodiment will be described.

  When the SiC was thermally oxidized, the stability of impurities present in the SiC was examined by the first principle calculation. The energy difference between the case where impurities in SiC diffuse into the oxide film at the interface between SiC and the oxide film during thermal oxidation and the case where impurities remain in SiC was calculated.

  As a result of calculation based on the first principle, Al (aluminum), B (boron), Ga (gallium) or In (indium) as p-type impurities, N (nitrogen) as n-type impurities, As (arsenic), P In both cases of (phosphorus) and Sb (antimony), it was found that staying in SiC is more stable than diffusing into the oxide film. Further, the diffusion coefficients of p-type impurities and n-type impurities in SiC are extremely small.

  FIG. 9 is an explanatory diagram of the operation of the present embodiment. In each of FIGS. 9A to 9C, the right side is the front surface side (first surface side) of the SiC substrate, and the left side is the back surface side (second surface side) of the SiC substrate.

  In the present embodiment, for example, Al (aluminum) as a p-type impurity is ion-implanted into SiC from the surface side and activated by annealing (FIG. 9A). FIG. 9A shows a projected range (Rp) of ion implantation.

  Thereafter, a silicon oxide film is formed by thermal oxidation (FIG. 9B). At this time, it is energetically stable that Al remains on the SiC side rather than diffusing into the silicon oxide film as described above. Also, the diffusion coefficient of Al in SiC is extremely small. For this reason, Al piles up at the interface between SiC and the silicon oxide film. In particular, in this embodiment, since an oxide film is formed by thermal oxidation to a region deeper than the projected range of ion implantation, a large amount of Al piles up at the interface, and a high concentration and narrow p-type impurity region Is formed at the interface.

  When the silicon oxide film is formed, carbon is released from the SiC lattice, thereby forming carbon vacancies. When Al enters this carbon vacancy, it is stabilized and Al is activated. Alternatively, SiC Si (silicon) enters the carbon vacancies, and Al is activated at the position of the SiC Si lattice. Therefore, activated Al is present at a high concentration in the p-type impurity region. That is, in the process of the present embodiment, Al in the p-type impurity region is activated by oxidation, and thus a high-temperature process for activation after oxidation is not always necessary.

  For example, a metal electrode is formed on the p-type impurity region where activated Al is present at a high concentration (FIG. 9C). The barrier width between the p-type SiC and the electrode is narrowed by the presence of the activated p-type impurity region having a high impurity concentration. Therefore, a low-resistance ohmic contact is realized between the p-type SiC and the electrode.

  With the above operation, in the PIN diode 100 of this embodiment, a low-resistance ohmic contact is realized between the anode layer 12 and the anode electrode 14. Therefore, the PIN diode 100 having a low on-resistance and a large forward current is realized.

  In the present embodiment, the p-type impurity region 16 is formed in a very narrow region of, for example, 50 nm or less, at the interface between the anode layer 12 and the anode electrode 14. Therefore, for example, it becomes easy to control the p-type impurity concentration of the anode layer 12 from the viewpoint of optimizing characteristics other than the contact resistance such as the breakdown voltage of the pn junction and the parasitic resistance.

  From the viewpoint of increasing the concentration of the p-type impurity region 16 and increasing the degree of freedom in designing the impurity concentration of the anode layer 12, it is desirable that the width of the p-type impurity region 16 in the depth direction is narrow. Therefore, the distance between the position of the maximum concentration of the p-type impurity and the position where the concentration of the p-type impurity on the anode layer 12 side is decreased by an order of magnitude from the position of the maximum concentration of the p-type impurity (d in FIG. 3). Is preferably 20 nm or less, and more preferably 10 nm or less.

  Further, in the method for manufacturing the PIN diode 100 of the present embodiment, interstitial carbon generated on the surface of the anode layer 12 during thermal oxidation diffuses into the anode layer 12 and the SiC substrate 10, and the anode layer 12 and the SiC substrate 10. Enter the internal carbon vacancies. Thereby, the density | concentration of the carbon void | hole in the anode layer 12 and the SiC substrate 10 reduces.

  Carbon vacancies in SiC cause a decrease in minority carrier lifetime and an increase in impurity layer resistance. According to the present embodiment, the concentration of carbon vacancies in the anode layer 12 and the SiC substrate 10 is reduced, so that the minority carrier lifetime is increased and the impurity layer resistance is reduced. Therefore, the PIN diode 100 having a low on-resistance is realized.

  Further, for example, there is a method of forming a low contact resistance electrode by reacting SiC with a metal to form silicide. In this case, surplus carbon existing in the interface between SiC and silicide or in the silicide film may cause peeling of the electrode film.

  In the method for manufacturing the PIN diode 100 of the present embodiment, since the high-concentration p-type impurity region 16 is formed, silicidation between SiC and the electrode is not necessarily required. Excess carbon taken into the oxide film during thermal oxidation is removed by peeling off the oxide film.

Therefore, it is possible to form the anode electrode 12 in which the carbon concentration in the metal is reduced to 1 × 10 ¹⁸ cm ⁻³ or less. Therefore, a highly reliable PIN diode 100 without film peeling or the like can be realized.

  As described above, according to the present embodiment, the PIN diode 100 having a low contact resistance is realized.

(Second Embodiment)
The semiconductor device of this embodiment is different from that of the first embodiment in that an n-type impurity region is provided at the interface between the n-type SiC substrate and the electrode. The description overlapping with the first embodiment is omitted.

  FIG. 10 is a schematic cross-sectional view showing a configuration of a PIN diode that is a semiconductor device of the present embodiment.

The PIN diode 200 includes a SiC substrate 10, an anode layer 12, an anode electrode 14, a cathode electrode 18, and an n-type impurity region 22. SiC substrate 10 includes an n-type SiC layer 10a and an n ⁻ -type drift layer 10b on SiC layer 10a. The PIN diode 200 includes an n-type impurity region 22.

  In the present embodiment, the anode electrode 14 is, for example, a metal. The metal forming the anode electrode 14 is constituted by, for example, a laminate of a Ni (nickel) barrier metal layer and an Al (aluminum) metal layer on the barrier metal layer. The Ni barrier metal layer and the Al metal layer may form an alloy by reaction. Further, Ni may react with SiC substrate 10 to form silicide.

  The cathode electrode 18 is, for example, a metal. The metal forming the cathode electrode 18 is, for example, TiN (titanium nitride). For example, another metal such as Al (aluminum) may be laminated on TiN.

  N-type impurity region 22 is provided between n-type SiC layer 10 a and cathode electrode 18. N-type impurity region 22 contains an n-type impurity.

In the n-type impurity region 22, the maximum concentration of the n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ²² cm ⁻³ or less. At the interface between the n-type SiC layer 10a and the cathode electrode 18, n-type impurities are segregated at a high concentration.

  The distance between the position of the maximum concentration of the n-type impurity and the position where the concentration of the n-type impurity on the n-type SiC layer 10a side is decreased by an order of magnitude from the position of the maximum concentration of the n-type impurity is 50 nm or less. This distance is desirably 20 nm or less, and more desirably 10 nm or less.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. In the method of manufacturing a semiconductor device according to this embodiment, impurities are ion-implanted into a SiC layer, oxidized to a region containing 90% or more of impurities introduced by ion implantation, the oxide film is peeled off, and an electrode is formed on the SiC layer. Form. The manufacturing method of the semiconductor device of this embodiment is an example of the manufacturing method of the semiconductor device shown in FIG. The region containing 90% or more of impurities introduced by ion implantation is, for example, a region deeper than three times the projected range. Depending on the profile of the ion implantation, there may be a need for about four times the projected range.

  FIG. 11 is a process flow diagram illustrating the method for manufacturing a semiconductor device of this embodiment. 12 to 15 are schematic cross-sectional views showing a semiconductor device being manufactured in the method for manufacturing a semiconductor device of this embodiment.

As shown in FIG. 11, the manufacturing method of the semiconductor device of this embodiment includes n ⁻ SiC layer formation (step S200), p-type impurity ion implantation (step S202), annealing (step S204), and backside n-type impurity ion implantation. (Step S206), backside oxide film formation (Step S208), backside oxide film peeling (Step S210), anode electrode formation (Step S212), and cathode electrode formation (Step S214).

  First, an n-type SiC layer 10a having a first surface that is a silicon surface and a second surface that is a carbon surface is prepared. The second surface of n-type SiC layer 10a is referred to as the back surface.

Next, in step S200, n ⁻ -type drift layer 10b is formed on the first surface of SiC layer 10a by epitaxial growth. The n-type SiC layer 10 a and the n ⁻ -type drift layer 10 b constitute the SiC substrate 10.

  Next, in step S202, p-type impurities are ion-implanted into the drift layer 10b by a known ion implantation method. The p-type impurity is, for example, Al (aluminum).

  Next, in step S204, after the p-type impurity is ion-implanted, activation annealing for activating the p-type impurity is performed. The activation annealing is performed, for example, at a temperature of 1700 ° C. or higher and 1900 ° C. or lower in an inert gas atmosphere. A p-type anode layer 12 is formed by ion implantation of p-type impurities and activation annealing (FIG. 12).

Next, in step S206, n-type impurities are ion-implanted from the back side into the n-type SiC layer 10a by a known ion implantation method. An n ⁺ type region 24 is formed in the region where the n type impurity is ion-implanted (FIG. 13). The n-type impurity is, for example, N (nitrogen). The n-type impurity may be As (arsenic), P (phosphorus), or antimony (Sb).

The dose amount of ion implantation is, for example, 1 × 10 ¹⁵ cm ⁻² or more and 1 × 10 ¹⁷ cm ⁻² or less. From the viewpoint of increasing the concentration of the n-type impurity region 22 to be formed later, it is desirably 1 × 10 ¹⁶ cm ⁻² or more.

Next, in step 208, the n-type SiC layer 10a is thermally oxidized to form the back surface oxide film 26 (FIG. 14). The n-type SiC layer 10a is thermally oxidized to a region deeper than three times the projected range (Rp) of ion implantation to form a back oxide film 26. At this time, almost the entire n ⁺ -type region 24 is oxidized. By oxidizing almost the entire region, dopants introduced by ion implantation can be collected and concentrated.

  The thermal oxidation is performed, for example, at a temperature of 800 ° C. or higher and 1500 ° C. or lower in an oxidizing atmosphere. It is desirable that it is 900 degreeC or more and 1350 degrees C or less. It is further desirable that the temperature is 1000 ° C. or higher and 1300 ° C. or lower. The second surface is a carbon surface. The carbon surface is about 10 times faster in oxidation rate than the silicon surface. Therefore, an oxide film having a thickness equivalent to that of the silicon surface can be formed in a shorter time or at a lower temperature than the silicon surface.

  The thickness of the back oxide film 26 to be formed depends on the projected range (Rp), but when the C plane is used as in this embodiment, it is preferably 500 nm or more and 10,000 nm or less, and 1000 nm or more and 3000 nm or less. More desirable. If it is below the above range, there is a possibility that it cannot be oxidized up to 3 times the projected range (Rp). Moreover, when it exceeds the said range, there exists a possibility that manufacturing time may increase and manufacturing cost may increase. Although the thickness of the oxide film 26 depends on the projected range (Rp), when the surface orientation of the surface to be oxidized is the A plane or the M plane, it may be considered to be about half of the C plane. The thickness is desirably 250 nm or more and 5000 nm or less, and more desirably 500 nm or more and 1500 nm or less. This is because the oxidation speed is about half that of the C-plane.

  When the back oxide film 26 is formed, n-type impurities are piled up at the interface between the back oxide film 26 and the n-type SiC layer 10a, so that segregation occurs at a high concentration, and the n-type impurity region 22 is formed. The n-type impurity enters and activates carbon vacancies formed on the surface of the SiC layer 10a during thermal oxidation. Alternatively, the n-type impurity enters and activates the Si lattice position after substitution of carbon vacancies formed on the surface of the SiC layer 10a and Si (silicon) during thermal oxidation.

  Further, interstitial carbon generated on the surface of SiC layer 10 a during thermal oxidation diffuses into SiC substrate 10 and enters carbon vacancies inside SiC substrate 10. Thereby, the concentration of carbon vacancies inside SiC substrate 10 is reduced.

  Next, in step S210, the back surface oxide film 26 is peeled off (FIG. 15). The back oxide film 26 is removed by, for example, hydrofluoric acid-based wet etching.

  Thereafter, in step 212, the anode electrode 14 is formed on the anode layer 12 by a known process. In step 214, the cathode electrode 18 is formed on the back side of the SiC substrate 10, and the PIN diode 200 of the present embodiment shown in FIG. 10 is manufactured.

  Hereinafter, the operation and effect of the semiconductor device and the method for manufacturing the semiconductor device of the present embodiment will be described.

  As described above, as a result of the calculation based on the first principle, Al (aluminum), B (boron), Ga (gallium) or In (indium) as p-type impurities, N (nitrogen) as n-type impurities, As In any case of (arsenic), P (phosphorus), and Sb (antimony), it has become clear that staying in SiC is more stable than diffusing into the oxide film. Further, the diffusion coefficients of p-type impurities and n-type impurities in SiC are extremely small.

  FIG. 16 is a diagram for explaining the operation of the present embodiment. In each of FIGS. 16A to 16C, the right side is the back surface side (second surface side) of the SiC substrate, and the left side is the front surface side (first surface side) of the SiC substrate.

  In this embodiment, for example, N (nitrogen) is ion-implanted into SiC from the back side as an n-type impurity (FIG. 16A). FIG. 16A shows the projected range (Rp) of ion implantation and three times the projected range (3Rp).

  Thereafter, a silicon oxide film is formed by thermal oxidation (FIG. 16B). At this time, it is energetically stable that N stays on the SiC side rather than diffusing into the silicon oxide film as described above. Further, the diffusion coefficient of N in SiC is extremely small. For this reason, N piles up at the interface between SiC and the silicon oxide film. In particular, in this embodiment, since an oxide film is formed by thermal oxidation to a region deeper than three times the projected range of ion implantation, a large amount of N piles up at the interface, and a high concentration and narrow n A type impurity region is formed at the interface.

  When the silicon oxide film is formed, carbon is released from the SiC lattice, thereby forming carbon vacancies. When N enters this carbon vacancy, it is stabilized and N is activated. Alternatively, SiC is activated when Si (silicon) enters carbon vacancies and N enters the Si lattice position of SiC. Therefore, the activated N exists at a high concentration in the n-type impurity region.

  In this embodiment, most of the region containing N introduced by ion implantation is oxidized. Since N is activated by oxidation, annealing for activation after N ion implantation is not necessarily required.

  For example, a metal electrode is formed on the n-type impurity region where the activated N is present at a high concentration (FIG. 16C). The barrier width between the n-type SiC and the electrode is narrowed by the presence of an activated n-type impurity region having a high impurity concentration. Therefore, a low-resistance ohmic contact is realized between the n-type SiC and the electrode.

  With the above operation, in the PIN diode 200 of the present embodiment, an ohmic contact having a low resistance is realized between the SiC layer 10a and the cathode electrode 18. Therefore, the PIN diode 200 having a low on-resistance and a large forward current is realized.

  In the present embodiment, the n-type impurity region 22 is formed in an extremely narrow region of, for example, 50 nm or less, at the interface between the SiC layer 10a and the cathode electrode 18. Therefore, for example, it becomes easy to control the n-type impurity concentration of the SiC layer 10a from the viewpoint of optimizing characteristics other than the contact resistance such as the breakdown voltage of the pn junction and the parasitic resistance.

  From the viewpoint of increasing the concentration of n-type impurity region 22 and increasing the degree of freedom in designing the impurity concentration of SiC layer 10a, it is desirable that the width of n-type impurity region 22 in the depth direction be narrow. Therefore, the distance between the position of the maximum concentration of the n-type impurity and the position where the concentration of the n-type impurity on the SiC layer 10a side is decreased by an order of magnitude from the position of the maximum concentration of the n-type impurity is 20 nm or less. It is desirable that the thickness is 10 nm or less.

  In the method for manufacturing the PIN diode 200 of the present embodiment, interstitial carbon generated on the surface of the SiC layer 10a during thermal oxidation diffuses into the SiC substrate 10 and enters the carbon vacancies inside the SiC substrate 10. Thereby, the density | concentration of the carbon void | hole inside SiC substrate 10 reduces.

  Carbon vacancies in SiC cause a decrease in minority carrier lifetime and an increase in impurity layer resistance. According to the present embodiment, the concentration of carbon vacancies inside the SiC substrate 10 is reduced, so that the minority carrier lifetime is increased and the impurity layer resistance is reduced. Therefore, the PIN diode 200 having a low on-resistance is realized.

  Further, for example, there is a method of forming an electrode by forming a silicide by reacting SiC and a metal. In this case, surplus carbon existing in the interface between SiC and silicide or in the silicide film may cause peeling of the electrode film.

  In the manufacturing method of the PIN diode 200 of the present embodiment, since the high-concentration n-type impurity region 22 is formed, silicidation between SiC and the electrode is not necessarily required. Excess carbon taken into the oxide film during thermal oxidation is removed by peeling off the oxide film.

Therefore, it is possible to form the cathode electrode 18 in which the carbon concentration in the metal is reduced to 1 × 10 ¹⁸ cm ⁻³ or less. Therefore, a highly reliable PIN diode 200 without film peeling or the like can be realized.

  As described above, according to the present embodiment, the PIN diode 200 with low contact resistance is realized.

(Third embodiment)
In the semiconductor device of the present embodiment, the SiC layer has an n-type region and a p-type region, the impurity region is a first region in which the impurity is an n-type impurity, and a second region in which the impurity is a p-type impurity. The first and second embodiments are different in that the first region is provided between the n-type region and the electrode, and the second region is provided between the p-type region and the electrode. ing. The description overlapping with the first or second embodiment is omitted.

  FIG. 17 is a schematic cross-sectional view showing the configuration of a MOSFET that is a semiconductor device of this embodiment. The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 300 is, for example, a Double Implantation MOSFET (DIMOSFET) that forms a p-well and a source region by ion implantation.

This MOSFET 300 includes a SiC substrate 10. SiC substrate 10 includes an n-type SiC layer 10a and an n ⁻ -type drift layer 10b on SiC layer 10a.

SiC layer 10a has first and second surfaces. In FIG. 17, the first surface is the upper surface of the drawing, and the second surface is the lower surface of the drawing. The first surface is a surface inclined at an angle of 0 ° to 8 ° with respect to the silicon surface. The SiC layer 10a is, for example, 4H—SiC SiC containing, for example, N (nitrogen) as an n-type impurity having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

The drift layer 10b is, for example, a SiC epitaxial growth layer formed by epitaxial growth on the SiC layer 10a. The impurity concentration of the n-type impurity in the drift layer 10b is, for example, 5 × 10 ¹⁵ or more and 2 × 10 ¹⁶ cm ⁻³ or less. The n-type impurity is, for example, N (nitrogen).

  The surface of the drift layer 10b is also a surface inclined at 0 ° or more and 8 ° or less with respect to the silicon surface. The film thickness of the drift layer 10b is, for example, not less than 5 μm and not more than 150 μm.

A p-type p-well region 30 having a p-type impurity concentration of about 5 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁷ cm ⁻³ is formed on a partial surface of the drift layer 10b. The depth of the p well region 30 is, for example, about 0.6 μm. The p well region 30 functions as a channel region of the MOSFET 300. The p-type impurity is, for example, Al.

An n ⁺ -type source region (n-type region) 32 having an n-type impurity impurity concentration of about 1 × 10 ¹⁸ cm ⁻³ or more and about 1 × 10 ²⁰ cm ⁻³ or less, for example, is formed on a partial surface of the p-well region 30. Has been. The depth of the source region 32 is shallower than the depth of the p-well region 30 and is, for example, about 0.3 μm. The n-type impurity is, for example, N (nitrogen).

Further, on the partial surface of the p well region 30 and on the side of the n ⁺ type source region 32, for example, the impurity concentration of the p type impurity is about 1 × 10 ¹⁸ cm ⁻³ or more and about 1 × 10 ²⁰ cm ⁻³ or less. A p ⁺ -type p-well contact region (p-type region) 34 is formed. The depth of the p well contact region 34 is shallower than the depth of the p well region 30 and is, for example, about 0.3 μm. The p-type impurity is, for example, Al.

  A gate insulating film 36 is formed on the surface of the drift layer 10b and the p-well region 30 so as to straddle these regions and layers. For example, a silicon oxide film or a high-k insulating film can be applied to the gate insulating film 36.

  A gate electrode 40 is formed on the gate insulating film 36. For the gate electrode 40, for example, polycrystalline silicon doped with impurities can be used. On the gate electrode 40, for example, an interlayer insulating film 42 formed of a silicon oxide film is formed.

  A p-well region 30 sandwiched between the source region 32 and the drift layer 10 b under the gate electrode 40 functions as a channel region of the MOSFET 300.

  A conductive source / p-well common electrode 44 is provided on the source region (n-type region) 32 and the p-well contact region (p-type region) 34. The source region 32 and the p-well contact region 34 and the source / p-well common electrode 44 are electrically connected.

  The source / p well common electrode 44 is, for example, a metal. The metal forming the source / p-well common electrode 44 is, for example, TiN (titanium nitride). For example, another metal such as Al (aluminum) may be laminated on TiN. In addition to the metal, for example, a conductive material such as polycrystalline silicon containing impurities can be applied.

  An n-type impurity region (first region) 46 containing an n-type impurity is provided between the source region (n-type region) 32 and the source / p-well common electrode 44. A p-type impurity region (second region) 48 containing a p-type impurity is provided between the p-well contact region (p-type region) 34 and the source / p-well common electrode 44.

In the n-type impurity region 46, the maximum concentration of the n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ²² cm ⁻³ or less. At the interface between the source region 32 and the source / p-well common electrode 44, n-type impurities are segregated at a high concentration. The n-type impurity is, for example, N (nitrogen). The n-type impurity may be As (arsenic), P (phosphorus), or antimony (Sb).

  The distance between the position of the maximum concentration of the n-type impurity and the position where the concentration of the n-type impurity on the source region (n-type region) 32 side is one digit lower than the position of the maximum concentration of the n-type impurity is 50 nm or less. is there. This distance is desirably 20 nm or less, and more desirably 10 nm or less.

In the p-type impurity region 48, the maximum concentration of the p-type impurity is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ²² cm ⁻³ or less. At the interface between the p-well contact region 34 and the source / p-well common electrode 44, p-type impurities are segregated at a high concentration. The p-type impurity is, for example, Al (aluminum). The p-type impurity may be B (boron), Ga (gallium), or In (indium).

  The distance between the position of the maximum concentration of the p-type impurity and the position where the concentration of the p-type impurity on the p-well contact region (p-type region) 34 side is decreased by an order of magnitude from the position of the maximum concentration of the p-type impurity is 50 nm. It is as follows. This distance is desirably 20 nm or less, and more desirably 10 nm or less.

  A conductive drain electrode 50 is formed on the second surface side of the SiC substrate 10. The drain electrode 50 is, for example, Ni (nickel).

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. In the method of manufacturing a semiconductor device according to the present embodiment, a first ion implantation of an n-type impurity is performed on a SiC layer in a predetermined first projected range to form an n-type region, and a predetermined second projecting is performed on the SiC layer. A second ion implantation of a p-type impurity is performed in a ted range to form a p-type region, and an SiC film is formed by oxidizing the SiC layer to a region deeper than the first and second projected ranges. The oxide film is peeled off, and electrodes are formed on the n-type region and the p-type region. The manufacturing method of the semiconductor device of this embodiment is an example of the manufacturing method of the semiconductor device shown in FIG.

  FIG. 18 is a process flow diagram illustrating the method for manufacturing a semiconductor device of this embodiment. 19 to 25 are schematic cross-sectional views illustrating a semiconductor device being manufactured in the method for manufacturing a semiconductor device according to the present embodiment.

As shown in FIG. 18, the method of manufacturing the semiconductor device of this embodiment includes n ⁻ SiC layer formation (step S300), p-type impurity ion implantation (step S302), n-type impurity ion implantation (step S304), and p-type. Impurity ion implantation (step S306), annealing (step S308), oxide film formation (step S310), oxide film removal (step S312), gate insulating film formation (step S314), gate electrode formation (step S316), interlayer film formation (Step S318), source / p-well common electrode formation (Step S320), drain electrode formation (Step S322), and annealing (Step S324).

  First, an n-type SiC layer 10a having a first surface that is a silicon surface and a second surface that is a carbon surface is prepared.

Next, in step S300, n ⁻ -type drift layer 10b is formed on the first surface of SiC layer 10a by epitaxial growth. N-type SiC layer 10a and n ⁻ -type drift layer 10b constitute SiC substrate 10 (FIG. 19).

Next, for example, a first mask material 52 of SiO ₂ is formed by patterning by photolithography and etching. In step S302, using this first mask material 52 as an ion implantation mask, Al, which is a p-type impurity, is ion-implanted into the drift layer 10b to form a p-well region 30 (FIG. 20).

Next, for example, a second mask material 54 of SiO ₂ is formed by patterning by photolithography and etching. In step S304, N, which is an n-type impurity, is ion-implanted into the drift layer 10b using the second mask material 54 as an ion implantation mask to form a source region (n-type region) 32 (FIG. 21). This ion implantation is referred to as first ion implantation. The concentration profile of N after the first ion implantation includes a first projected range (Rp ₁ ).

Next, for example, a third mask material 56 of SiO ₂ is formed by patterning by photolithography and etching. In step S306, using the third mask material 56 as an ion implantation mask, Al, which is a p-type impurity, is ion-implanted into the drift layer 10b to form a p-well contact region (p-type region) 34 (FIG. 22). ). This ion implantation is referred to as second ion implantation. The Al concentration profile of the second ion implantation includes a second projected range (Rp ₂ ).

  Next, in step S308, annealing for activating p-type impurities and n-type impurities is performed. The activation annealing is performed, for example, at a temperature of 1700 ° C. or higher and 1900 ° C. or lower in an inert gas atmosphere.

Next, in step S308, the drift layer 10b is thermally oxidized to form an oxide film 60 (FIG. 23). The drift layer 10b is thermally oxidized to a region deeper than both the first projected range (Rp ₁ ) of the first ion implantation and the second projected range (Rp ₂ ) of the second ion implantation. A film 60 is formed.

  The thermal oxidation is performed, for example, at a temperature of 800 ° C. or higher and 1500 ° C. or lower in an oxidizing atmosphere. It is desirable that it is 900 degreeC or more and 1350 degrees C or less. It is further desirable that the temperature is 1000 ° C. or higher and 1300 ° C. or lower.

  The thickness of the oxide film 60 to be formed depends on the projected range, but when using the Si surface as in this embodiment, it is preferably 50 nm or more and 1000 nm or less, and more preferably 100 nm or more and 300 nm or less. desirable. Below the above range, the n-type impurity region 46 and the p-type impurity region 48 to be formed later may not be sufficiently high in concentration. Moreover, when it exceeds the said range, there exists a possibility that manufacturing time may increase and manufacturing cost may increase.

  When the thermal oxide film 60 is formed, the n-type impurity piles up at the interface between the oxide film 60 and the source region (n-type region) 32 and segregates at a high concentration, and the n-type impurity region (first region) 46 is formed. Is formed. Further, p-type impurities are piled up at the interface between the oxide film 60 and the p-well contact region (p-type region) 34 to segregate at a high concentration, and a p-type impurity region (second region) 48 is formed. The

  Next, in step S312, the oxide film 60 is removed (FIG. 24). The oxide film 60 is removed by, for example, hydrofluoric acid-based wet etching.

  Next, in step S314, for example, a gate insulating film 36 of a silicon oxide film is formed by a CVD (Chemical Vapor Deposition) method or a thermal oxidation method. In step S 316, for example, a polycrystalline silicon gate electrode 40 is formed on the gate insulating film 36. In step S318, an interlayer insulating film 42 of, eg, a silicon oxide film is formed on the gate electrode 40 (FIG. 25).

  Thereafter, in step S320, a conductive source / p well common electrode 44 electrically connected to the source region 32 and the p well contact region 34 is formed. The source / p well common electrode 44 is formed by sputtering of TiN and Al, for example.

  Next, in step S322, a conductive drain electrode 50 is formed on the second surface side of SiC substrate 10. The drain electrode 50 is formed, for example, by sputtering of Ni.

  In step S324, in particular, annealing at a low temperature is performed in order to reduce the contact resistance of the drain electrode 50. Annealing is performed at 400 ° C. in an argon gas atmosphere, for example.

  The MOSFET 300 shown in FIG. 17 is formed by the above manufacturing method.

  As described above, it is generally difficult to reduce the contact resistance of the contact electrode to the SiC layer due to the low impurity concentration and activation rate in the SiC layer. In addition, it is difficult to simultaneously form a common contact electrode for an n-type SiC region and a p-type SiC region having different Fermi levels.

  In the MOSFET 300 of this embodiment, an n-type impurity region 46 in which activated n-type impurities are segregated at a high concentration is provided between the source / p-well common electrode 44 and the source region 32. A p-type impurity region 48 in which activated p-type impurities are segregated at a high concentration is provided between the source / p-well common electrode 44 and the p-well contact region (p-type region) 34.

  Therefore, the barrier width is reduced by the same action as described in the first and second embodiments, and the ohmic resistance is low with respect to both the n-type source region 32 and the p-type p-well contact region 34. A source / p-well common electrode 44 to be a contact is realized. Therefore, a high-performance MOSFET 300 is realized by a simple manufacturing method.

  As described above, according to the present embodiment, the MOSFET 300 having a low contact resistance is realized.

(Fourth embodiment)
The semiconductor device of this embodiment is different from the first to third embodiments in that it is a transparent diode. Hereinafter, the description overlapping with the first to third embodiments is omitted.

  FIG. 26 is a schematic cross-sectional view showing the configuration of a transparent diode that is the semiconductor device of the present embodiment.

The transparent diode 400 includes a SiC substrate 10 and a p ⁺ -type SiC layer (p-type region) 70. SiC substrate 10 includes an n-type SiC layer 10a and an n ⁻ -type drift layer 10b on SiC layer 10a.

Then, a p ⁻ type SiC layer 72 and an n ⁺ type SiC layer (n type region) 74 are formed on the drift layer 10 b in a region between the p ⁺ type SiC layers 70.

An anode electrode 76 is provided on the n ⁺ -type SiC layer (n-type region) 74 and the p ⁺ -type SiC layer (p-type region) 70. The n ⁺ -type SiC layer (n-type region) 74 and the p ⁺ -type SiC layer (p-type region) 70 and the anode electrode 76 are electrically connected.

  The anode electrode 76 is, for example, a metal. The metal forming the anode electrode 76 is, for example, TiN (titanium nitride). For example, another metal such as Al (aluminum) may be laminated on TiN. In addition to the metal, for example, a conductive material such as polycrystalline silicon containing an n-type impurity can be applied.

An n-type impurity region (first region) 80 containing an n-type impurity is provided between the n ⁺ -type SiC layer (n-type region) 74 and the anode electrode 76. A p-type impurity region (second region) 82 containing a p-type impurity is provided between the p ⁺ -type SiC layer (p-type region) 70 and the anode electrode 76.

In the n-type impurity region 80, the maximum concentration of the n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ²² cm ⁻³ or less. At the interface between the n ⁺ -type SiC layer (n-type region) 74 and the anode electrode 76, n-type impurities are segregated at a high concentration. The n-type impurity is, for example, N (nitrogen). The n-type impurity may be As (arsenic), P (phosphorus), or antimony (Sb).

The distance between the position of the maximum concentration of the n-type impurity and the position where the concentration of the n-type impurity on the n ⁺ -type SiC layer (n-type region) 74 side is decreased by an order of magnitude from the position of the maximum concentration of the n-type impurity. Is 50 nm or less. This distance is desirably 20 nm or less, and more desirably 10 nm or less.

In the p-type impurity region 82, the maximum concentration of the p-type impurity is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ²² cm ⁻³ or less. At the interface between the p ⁺ -type SiC layer (p-type region) 70 and the anode electrode 76, p-type impurities are segregated at a high concentration. The p-type impurity is, for example, Al (aluminum). The p-type impurity may be B (boron), Ga (gallium), or In (indium).

The distance between the position of the maximum concentration of the p-type impurity and the position where the concentration of the p-type impurity on the p ⁺ -type SiC layer (p-type region) 70 side is decreased by an order of magnitude from the position of the maximum concentration of the p-type impurity. Is 50 nm or less. This distance is desirably 20 nm or less, and more desirably 10 nm or less.

  A conductive cathode electrode 78 is formed on the second surface side of SiC substrate 10. The cathode electrode 78 is, for example, Ni (nickel).

  The n-type impurity region 80 and the p-type impurity region 82 can be formed by the same method as in the third embodiment.

According to the present embodiment, the anode electrode 76 that is an ohmic contact with low resistance to both the n ⁺ -type SiC layer (n-type region) 74 and the p ⁺ -type SiC layer (p-type region) 70 is realized. The Further, the n ⁺ -type SiC layer (n-type region) 74 can be easily made thin. Therefore, a high-performance transparent diode 400 is realized by a simple manufacturing method.

  As described above, in the embodiment, the case of 4H—SiC is described as an example of the crystal structure of silicon carbide, but the present invention can also be applied to silicon carbide having other crystal structures such as 6H—SiC, 3C—SiC, and the like. is there. Further, although the embodiment has been described by taking the case where the contact electrode is formed on the Si surface and the C surface as an example, the present embodiment is also applicable when the contact electrode is formed on the A surface, the M surface, or an intermediate surface thereof. The invention can be applied.

  In the embodiments, PIN diodes, MOSFETs, and transparent diodes have been described as examples of semiconductor devices. However, for example, low resistance ohmic contacts are required in IGBTs (Insulated Gate Bipolar Transistors), MPSs (Merged PIN Schottky) diodes, and the like. The present invention can also be applied to an electrode on an SiC layer.

  It should be noted that a combination such as the transparent diode shown in the fourth embodiment may be used for the built-in diode portion of the MOSFET of the third embodiment.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10a n-type SiC layer (SiC layer)
10b n ⁻ type drift layer (SiC layer)
12 Anode layer (SiC layer)
14 Anode electrode
16 p-type impurity region (impurity region)
18 Cathode electrode
22 n-type impurity region (impurity region)
32 source region (n-type region)
34 p-well contact region (p-type region)
44 Source / p-well common electrode (electrode)
46 n-type impurity region (first region)
48 p-type impurity region (second region)
70 p ⁺ type SiC layer (p-type region)
74 n ⁺ type SiC layer (n-type region)
76 Anode electrode
80 n-type impurity region (first region)
82 p-type impurity region (second region)
100 PIN diode (semiconductor device)
200 PIN diode (semiconductor device)
300 MOSFET (semiconductor device)
400 Transparent diode (semiconductor device)

Claims (12)

A SiC layer;
An electrode electrically connected to the SiC layer;
Provided between the SiC layer and the electrode, wherein a maximum concentration of impurities is 1 × 10 ²⁰ cm ⁻³ or more and 5 × 10 ²² cm ⁻³ or less, and a first position of the maximum concentration of impurities, The first distance between the first position and the second position on the SiC layer side where the impurity concentration is reduced by an order of magnitude of the maximum concentration is 50 nm or less, and the electrode and the second position An impurity region having a second distance between the first and second regions of 50 nm or less;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the SiC layer is p-type and the impurity is a p-type impurity.   The semiconductor device according to claim 2, wherein the p-type impurity is Al (aluminum), B (boron), Ga (gallium), or In (indium).   The semiconductor device according to claim 1, wherein the SiC layer is n-type and the impurity is an n-type impurity.   The semiconductor device according to claim 4, wherein the n-type impurity is N (nitrogen), P (phosphorus), As (arsenic), or Sb (antimony). The SiC layer has an n-type region and a p-type region;
The impurity region includes a first region in which the impurity is an n-type impurity and a second region in which the impurity is a p-type impurity;
The semiconductor device according to claim 1, wherein the first region is provided between the n-type region and the electrode, and the second region is provided between the p-type region and the electrode.   The semiconductor device according to claim 1, wherein the electrode is a metal. The semiconductor device according to claim 7, wherein a carbon concentration in the metal is 1 × 10 ¹⁸ cm ⁻³ or less.   The semiconductor device according to claim 1, wherein the first distance and the second distance are 20 nm or less.   The semiconductor device according to claim 1, wherein the first distance and the second distance are 10 nm or less.   The semiconductor device according to claim 1, wherein a concentration profile of the impurity between the first position and the second position is convex downward.   The semiconductor device according to claim 1, wherein the first position is located at an interface between the electrode and the impurity region.