JP2016018274A - Method for calculating control input to control device, and control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for calculating control input to a control device and the control device with which it is possible to prevent a reduction in the accuracy of calculating control input in spite of a calculation in which the number of bits is relatively small.SOLUTION: For example, a preliminary measure is adopted so that control input U(n-1) is divided into U(n-1) and U(n-1) as it is stored. Each time a calculation based on difference equation is made, the current deviation E(n) is stored in a RAM 23 as a 16-bit fixed-point number. Then, each of U(n-1) and A, U(n-2) and A, E(n) and B, E(n-1) and B, E(n-2) and B, U(n-1) and A, and U(n-2) and Ais read out from the RAM and multiplied on by a multiplication unit 31, and the control input U(n) indicated by the calculation result integrated in Acc 34 is divided, as it is stored, into U(n-1) and U(n-1), as substantially a 31(=16+15) bit fixed-point number, for calculation in the next cycle.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method for calculating an operation amount of a control device that calculates, in a time series, an operation amount input to a control target based on a differential equation corresponding to a pulse transfer function, and a control device that executes the operation method.

  As a control method for stabilizing the output voltage of the DC / DC converter, a voltage mode control method that feeds back the output voltage is widely used. The voltage mode control method is relatively easy to control but has a complicated phase compensation circuit.

  On the other hand, the current mode control method that feeds back the output current in addition to the output voltage makes the control itself relatively complicated, but the phase compensation circuit is simple and the line regulation is excellent, and the feedback loop is stable. It is said that there are many advantages, such as being high in parallel and suitable for increasing the capacity (see, for example, Patent Document 1).

  There has been proposed a method for simplifying the configuration by digitizing the function of the control circuit in the power supply apparatus. For example, in Patent Document 2, the CPU calculates a control command value at regular intervals based on the A / D conversion value of the fed back voltage, and determines the duty of the PWM signal to be given to the switching element based on the control command value. A voltage mode control type power supply apparatus is described.

JP 2007-209135 A JP 2013-70509 A

  However, for example, when a complicated control method such as a current mode control method is adopted, high-precision calculation is often required, and when using an arithmetic unit, microcomputer, or DSP with a large number of bits that can be handled at one time, It becomes a factor of cost increase.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a control capable of preventing a decrease in the calculation accuracy of the manipulated variable in spite of performing a calculation with a relatively small number of bits. An object of the present invention is to provide a method for calculating an operation amount of a device and a control device.

  The operation amount calculation method of the control device according to the present invention is a control device that controls an operation amount input to a control target whose transfer characteristic is represented by a pulse transfer function based on a deviation of the control amount from a target value. In the method of iteratively calculating the manipulated variable based on a differential equation corresponding to a pulse transfer function, a storage unit, and a multiplication unit that multiplies an N-digit (N is an integer of 2 or more) fixed-point multiplier and multiplicand. And the storage unit stores in advance the coefficients of the deviation and the manipulated variable as N-digit fixed-point numbers, and each time the calculation based on the difference equation, the deviation and the manipulated variable are stored in N digits and N + M, respectively. Stored as a fixed-point number with digits (M is a natural number smaller than N), and the multiplication unit calculates the deviation and the coefficient of the deviation, the upper N digits of the manipulated variable, and the manipulated variable each time an operation is performed based on the difference equation. Person in charge And characterized by multiplying the respective coefficients of lower M digits and the operation amount of the operation amount is read from the storage unit.

The operation amount calculation method of the control device according to the present invention provides an integration unit that integrates the multiplication results of the multiplication unit, and the difference equation is the following equation (1), in the integration result of the integration unit: The M digit from the least significant digit and the N digit following the M digit are defined as U _L (n) and U _H (n) in the calculation result of the formula (1).
U _H (n) + _UL (n) · 2 ^−M = b ₀ · E (n) + b ₁ · E (n-1) + ·· + bm · E (n−m) + a ₁ · U _H (n− 1) + a ₂ · U _H (n−2) + ·· + a _k • U _H (n−k) + {a ₁ • U _L (n−1) + a ₂ • U _L (n−2) +・ ・ + A _k・_UL (n−k)} 2 ^−M (1)
However,
n: integer m greater than or equal to 2, k: integer satisfying 1 ≦ m ≦ k ≦ n−1 E (n): deviation of control amount for the nth time U _H (n): nth manipulated variable U ( n) upper N digits U _L (n): lower M digits of the nth manipulated variable U (n) bm: coefficient of deviation a _k : coefficient of manipulated variable

  The control device according to the present invention controls an operation amount input to a control target whose transfer characteristic is represented by a pulse transfer function based on a deviation of the control amount with respect to a target value, and uses a difference equation corresponding to the pulse transfer function. In the control device that repeatedly calculates the manipulated variable, the coefficient of each of the deviation and manipulated variable is stored as a fixed-point number of N digits (N is an integer of 2 or more), and each calculation based on the difference equation, A storage unit that stores the deviation and the operation amount as N-digit and N + M-digit (M is a natural number smaller than N) fixed-point numbers, and for each calculation based on the difference equation, the deviation and the coefficient of the deviation, the operation And a multiplication unit that reads out and multiplies the upper N digits of the quantity and the coefficient of the manipulated variable, and the lower M digits of the manipulated variable and the coefficient of the manipulated variable from the storage unit.

  In the control device according to the present invention, the control target includes a PWM generation unit that generates a PWM signal based on the calculated operation amount, and a voltage conversion unit that has a switching element that is switched by the PWM signal generated by the PWM generation unit. It is characterized by including.

  The control device according to the present invention is characterized in that the control amount is a current output from the voltage converter.

In the present invention, before the calculation based on the difference equation corresponding to the pulse transfer function, the coefficients of the deviation and the manipulated variable are stored in advance in the storage unit as N-digit fixed-point numbers, and the deviation and the manipulated variable are respectively stored. An area to be stored as a fixed-point number of N digits and N + M digits (M is a natural number smaller than N) is secured. For each calculation based on the difference equation, the current deviation is first stored in the storage unit as an N-digit fixed-point number. Then, the deviation and its coefficient, the upper N digits of the manipulated variable and the manipulated variable coefficient, and the lower M digit of the manipulated variable and the manipulated variable coefficient are read from the storage unit and multiplied by the multiplier, and the difference equation is calculated. The operation amount indicated by the result is stored in the storage unit as a fixed-point number of N + M digits.
As a result, the operation amount indicated by the calculation result is succeeded to the next calculation with high accuracy despite the use of a multiplication unit that multiplies the multiplier and multiplicand of N digits or less.

In the present invention, the multiplication results of the plurality of multiplication terms included in the equation (1) are integrated, and the upper N digits and the lower M digits of the N + M digits from the lowest in the integration result are expressed by the equation (1). ) To U _H (n−1) and U _L (n−1) in the calculation result.
As a result, prior to the (n + 1) th calculation of Equation (1), U (n) is substituted into U _H (n−1) and U _L (n−1) without any loss of digits.

In the present invention, the PWM generator generates a PWM signal based on the calculated operation amount, and the switching element of the voltage converter is switched by the generated PWM signal.
Accordingly, the switching element of the voltage conversion unit is controlled to be turned on / off based on the operation amount calculated by the calculation method that prevents the calculation accuracy from being lowered.

  In the present invention, the current output from the voltage converter is the controlled variable, and the current output from the voltage converter is controlled with high accuracy by a so-called current mode control method.

According to the present invention, despite the use of a multiplication unit that multiplies a multiplier and a multiplicand of N digits or less, the operation amount indicated by the operation result is succeeded to the next operation with high accuracy.
Accordingly, it is possible to prevent a reduction in the calculation accuracy of the manipulated variable even though an operation with a relatively small number of bits is performed.

It is a block diagram which shows the structural example of the control apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the function structure of the control part in a control apparatus. It is a block diagram which shows the structural example of the calculator in the control apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process sequence of CPU which calculates the operation amount with respect to a PWM circuit with the control apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structural example of the calculator in the control apparatus which concerns on Embodiment 2 of this invention. It is a flowchart which shows the process sequence of CPU which calculates the operation amount with respect to a PWM circuit with the control apparatus which concerns on Embodiment 2 of this invention.

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of a control device according to Embodiment 1 of the present invention, and FIG. 2 is a block diagram illustrating a functional configuration of a control unit 2 in the control device. The control device shown in FIG. 1 includes, for example, a DC / DC converter (corresponding to a voltage conversion unit: hereinafter simply referred to as a converter) 1 that steps down the voltage of an external battery 4 and supplies the voltage to a load 5, And a control unit 2 for providing Converter 1 may boost or step up or down the voltage of battery 4.

  The converter 1 includes a switching element 11 having one end connected to the battery 4, a second switching element 12 and an inductor 13 each having one end connected to the other end of the switching element 11, and the other end of the inductor 13. A resistor 14 having one end connected thereto and a capacitor 15 connected between the other end of the resistor 14 and a ground potential are provided. The other end of the second switching element 12 is connected to the ground potential. The load 5 is connected across the capacitor 15. The switching element 11 and the second switching element 12 are, for example, N-channel MOSFETs each having one end as a drain.

  The converter 1 also includes a drive circuit 16 that provides a drive signal for driving the switching element 11 and the second switching element 12 on / off. The drive circuit 16 supplies the PWM signal supplied from the control unit 2 and a PWM signal complementary to the PWM control signal to the gates of the switching element 11 and the second switching element 12.

  The control unit 2 includes a CPU 21. The CPU 21 measures various times such as a ROM 22 that stores information such as a program, a RAM (corresponding to a storage unit) 23 that stores temporarily generated information, and a PWM control cycle. Are connected to each other by a bus.

  The CPU 21 also detects a voltage at both ends of the resistor 14 by generating a PWM circuit (corresponding to a PWM generator) 25 that generates a PWM signal to be supplied to the drive circuit 16, and converts the current flowing through the resistor 14 to a digital current value. An A / D conversion circuit 26 for conversion and an A / D conversion circuit 27 for converting the voltage at both ends of the capacitor 15 into a digital voltage value are bus-connected. The PWM circuit 25 and the converter 1 correspond to control targets.

  2, the control unit 2 realizes the functions of the voltage loop controller 28 and the current loop controller 29 for controlling the voltage supplied to the load 5 by a so-called current mode control method. In the control unit 2, the voltage loop control by the voltage loop controller 28 and the current loop control by the current loop controller 29 are executed in parallel. The symbol “◯” in the figure represents a subtractor.

  The voltage loop controller 28 controls the subsequent current loop based on the deviation obtained by subtracting the digital voltage value Vo obtained by converting the output voltage supplied to the load 5 by the A / D conversion circuit 27 from the target voltage value Vref. An operation amount that is a target current value Iref for the calculator 29 is calculated. In this voltage loop control, the voltage output from the converter 1 is the control amount.

  The current loop controller 29 is based on a deviation obtained by subtracting the digital current value Il obtained by converting the current flowing through the resistor 14 by the A / D conversion circuit 26 from the target current value Iref from the voltage loop controller 28. An operation amount for the PWM circuit 25 is calculated. The PWM circuit 25 generates a PWM signal having a duty corresponding to a given operation amount. In this current loop control, the current output from the converter 1 is the control amount.

  When performing PID control as voltage loop control, the current value I as the operation amount is calculated by, for example, the following equation (2). Since the value of equation (2) can be repeatedly calculated using a known method for obtaining the product sum of fixed-point numbers having a fixed number of digits, description of the calculation method is omitted.

I (n) = I (n -1) + K p · {e (n) -e (n-1)} + K i · {e (n) + e (n-1)} + K d · [{e (n ) -E (n-1)}-{e (n-1) -e (n-2)}] (2)
However,
n: integer of 2 or more I (n): n-th manipulated variable e (n): deviation of the n-th controlled variable from the n-th target value K _p : proportional term coefficient K _i : integral term coefficient K _d : Coefficient of differential term

  Next, current loop control will be described. The pulse transfer function Gc (z) to be controlled in the discrete time control system can be generally expressed by the following equation (3) by z conversion.

Gc (z) = (b ₀ + b ₁ · z ⁻¹ + b ₂ · z ⁻² + ·· + b ^m · z ^−m ) / (1−a ₁ · z ⁻¹ −a ₂ · z ⁻² − ·· − a _k · z ^−k ) (3)
However, m ≦ k

  The difference equation corresponding to Equation (3) is expressed by Equation (4) below. When U (n) calculated by the equation (4) is an operation amount for the PWM circuit 25, E (n) is an A / D conversion circuit 26 for I (n) calculated by the equation (2). It is the deviation of the converted digital current value.

_{U (n) = b 0 ·} E (n) + b 1 · E (n-1) + ·· + bm · E (n-m) + a 1 · U (n-1) + a 2 · U (n-2 ) + ・ ・ + _Ak・ U (nk) (4)
However,
n: integer m greater than or equal to 2, k: integer satisfying 1 ≦ m ≦ k ≦ n−1 E (n): deviation of the nth controlled variable from the target value U (n): nth manipulated variable bm: deviation Coefficient a _k : coefficient of manipulated variable

  When the right side of Expression (4) is calculated as a product sum of N-digit (N is an integer of 2 or more) fixed-point numbers, the number of digits of the operation result is 2N or more. When substituting for (n), the lower N digits of the operation result are lost and the operation accuracy is reduced. Therefore, U (n), U (n−1),... U (n−k) is a fixed-point number of N + M digits (M is a natural number smaller than N), and equation (4) is expressed by the above equation (1). ). Equation (1) is shown again below.

U _H (n) + _UL (n) · 2 ^−M = b ₀ · E (n) + b ₁ · E (n-1) + ·· + bm · E (n−m) + a ₁ · U _H (n− 1) + a ₂ · U _H (n−2) + ·· + a _k • U _H (n−k) + {a ₁ • U _L (n−1) + a ₂ • U _L (n−2) +・ ・ + A _k・_UL (n−k)} 2 ^−M (1)
However,
U _H (n): Upper N digits of the nth manipulated variable U (n) _UL (n): Lower M digits of the nth manipulated variable U (n)

Here, in particular, when there is a large difference in numerical value between the coefficient of deviation and the coefficient of manipulated variable, the multiplication result of the coefficient with the smaller numerical value and the manipulated variable or deviation will not be sufficiently reflected in the manipulated variable on the left side, Control cannot be performed accurately. For example, when each numerical value of the coefficient bm is smaller than each numerical value of the coefficient _ak by J digits (where J is a natural number smaller than N), the expression (1) is replaced with the following expression (5). In other words, the coefficient bm is preliminarily multiplied by 2 ^{J so} that the product sum of the coefficient bm and the deviation is not lost.

U _H (n) + U _L (n) · 2 ^−M = {(b ₀ · 2 ^J ) · E (n) + (b ₁ · 2 ^J ) · E (n−1) + ·· + (bm • ^{2 J) · E (n-} m)} 2 -J + a 1 · U H (n-1) + a 2 · U H (n-2) + ·· + a k · U H (n-k) + { _{a 1 · U L (n-} 1) + a 2 · U L (n-2) + ·· + a k · U L (n-k)} 2 -M ··· (5)

In this way, the upper N digits and the lower M digits of the manipulated variable with the increased number of digits are divided and operated, and the numerical precision of bm is converted to multiply each coefficient by the manipulated variable or deviation. High-precision arithmetic can be performed without increasing the number of digits of the multiplier and multiplicand from N digits in the multiplier.
In the following, an example in which an N-digit fixed-point number is represented by an N-digit binary number will be described. However, the present invention is not limited to a binary number, and may be applied to, for example, an arithmetic operation on an N-digit decimal number. In the first embodiment, N = 16 and M = 15 (details will be described later).

  When the calculation based on the formula (5) is actually performed, it is preferable to calculate first from the product sum in which the numerical value of the calculation result is small, and to avoid the carry loss as much as possible. Here, equation (5) may be transformed into, for example, the following equation (6) for calculation.

U _H (n) + _UL (n) · 2 ^−M = [{a ₁ · _UL (n−1) + a ₂ · _UL (n−2) + ·· + _ak · _UL (n−k )} 2 ^JM + (b ₀ · 2 ^J ) · E (n) + (b ₁ · 2 ^J ) · E (n−1) + ·· + (b m · 2 ^J ) · E (n−m)] 2 ^−J + a ₁ · U _H (n−1) + a ₂ · U _H (n−2) + ·· + _ak · U _H (n−k) (6)

  Next, current loop control will be described using specific numerical values. In the current loop control, the switching element 11 is controlled to be turned on / off by feeding back the current flowing through the inductor 13, and the change in the current flowing through the inductor 13 is steep with respect to the change in the PWM signal generated by the PWM circuit 25. is there. In order to cope with such characteristics, it is preferable that the deviation coefficient bm in the equations (1) and (4) to (6) is sufficiently smaller than 1.

  When there are two poles and two zero points in the pulse transfer function Gc (z) represented by Expression (3), Gc (z) is represented by Expression (7) below.

Gc (z) = (b ₀ + b ₁ · z ⁻¹ + b ₂ · z ⁻² ) / (1−a ₁ · z ⁻¹ −a ₂ · z ⁻² ) (7)

  The difference equation corresponding to the equation (7) is extracted from the equation (6) and becomes the following equation (8).

U _H (n) + _UL (n) · 2 ^−M = [{a ₁ · _UL (n−1) + a ₂ · _UL (n−2)} 2 ^JM + (b ₀ · 2 ^J ) · E (n) + (b ₁ · 2 ^J ) · E (n−1) + (b ₂ · 2 ^J ) · E (n−2)] 2 ^−J + a ₁ · U _H (n−1) + a ₂・ U _H (n-2) (8)

  When a specific example of the numerical value of each coefficient in the equation (8) is represented by a decimal number, the following equations (9) and (10) are obtained.

a ₁ = 1.997, a ₂ = −0.997 (9)
b ₀ = 0.0004076, b ₁ = 0.0001103, b ₂ = −0.0002973 (10)

In other words, the maximum absolute value of the coefficient _ak is about 5,000 times larger than the maximum absolute value of the coefficient bm. This is about 12 to 13 digits larger in binary. In the following, for example, J = 12.
Next, an arithmetic unit realized by the control unit 2 that performs the calculation based on Expression (8) will be described with reference to a flowchart showing the operation.

  FIG. 3 is a block diagram illustrating a configuration example of the arithmetic unit in the control device according to the first embodiment of the present invention. FIG. 4 illustrates an operation amount for the PWM circuit 25 in the control device according to the first embodiment of the present invention. It is a flowchart which shows the process sequence of CPU21 which calculates. The process of FIG. 4 is started at every cycle of performing the calculation based on Expression (8), that is, every control cycle of PWM control, and is executed by the CPU 21 according to a control program stored in the ROM 22 in advance.

  In FIG. 3, reference numerals 31 and 32 denote multiplication units, and the multiplication unit 31 multiplies the 16-bit multiplier and multiplicand stored in the RAM 23, respectively. The multiplication result of the multiplication unit 31 is cumulatively added to the contents of the 32-bit Acc 34 by the addition unit 33. The multiplying unit 32 arithmetically shifts the contents of the 32-bit Acc 34 by the number of digits corresponding to the contents stored in the RAM 23. Therefore, the adding unit 33 and Acc 34 correspond to an integrating unit. The most significant bit of Acc34 is a sign bit.

Before starting the iterative calculation, the CPU 21 arithmetically shifts the constants a ₁ and a ₂ in the equation (8) to the left by a predetermined number of bits (hereinafter referred to as D), and the accuracy as the operand is increased. Try to be the highest. Specifically, when the number of operands is viewed as an integer, the absolute value is made as large as possible within the range of −32768 to 32767. Here, since D = 14, a ₁ and a ₂ are arithmetically shifted to the left by 14 bits. However, in order to prevent overflow during operation, the number of digits to be shifted to the arithmetic left may be 13 bits or less.

A ₁ and A ₂ shown in FIG. 3 are numerical values calculated in advance by the following equation (11) as described above, and are stored in the RAM 23. Thus, when each of A ₁ and A ₂ is viewed as a 16-bit signed fixed-point number from bit 0 (LSB) to bit 15 (MSB), it is treated as having a decimal point between bits 13 and 14. . Since D = 14 here, A ₁ and A ₂ have an integer part of 1 bit and a decimal part of 14 bits excluding the sign bit.

A ₁ = a ₁ · 2 ^D , A ₂ = a ₂ · 2 ^D , (11)

On the other hand, b ₀ , b _1, and b ₂ are coefficients that should be shifted to the arithmetic left by J bits further than a ₁ and a ₂ , so that B ₀ , B _1, and B ₂ shown in FIG. It is calculated by Expression (12) and stored in the RAM 23. When D = 14 and J = 12, B ₀ , B ₁ and B ₂ are treated as having a decimal point between the bits 25 and 26 virtually.

B ₀ = b ₀ · 2 ^{D + J} , B ₁ = b ₁ · 2 ^{D + J} , B ₂ = b ₂ · 2 ^{D + J} (12)

Further, each of A _EL and A _HL shown in FIG. 3 is obtained by previously calculating the other constants in the equation (8) according to the following equation (13), and is stored in the RAM 23.

A _EL = 2 ^JM , A _HL = 2 ^-J (13)

In addition, _UL (n-1), _UL (n-2), E (n-1), E (n-2), _UH (n-1) and _UH (n-2) shown in FIG. ) Is stored in the RAM 23 as an initial value. The initial value of Acc34 is 0.

Next, moving on to FIG. 4, the process of repeatedly calculating the equation (8) by the calculator shown in FIG. 3 will be described in detail. In the following, “store” is used in the same meaning as “memory”. All storage or storage is performed on the RAM 23 except for storage or storage on the Acc 34. The contents of A ₁ , A ₂ , B ₀ , B ₁ , B ₂ , A _EL , A _HL stored in advance in the RAM 23 are read from the RAM 23 in a timely manner.

  When the process of FIG. 4 is started, the CPU 21 sets the deviation of the digital current value converted by the A / D conversion circuit 26 from the target value, with I (n) calculated by the equation (2) as the target value. Calculate (S11), and store the calculated deviation in E (n) (S12). In the first embodiment, as an example, E (n) is normalized so that the absolute value becomes a value of an appropriate size smaller than 1. That is, E (n) is treated as if bit 15 is a sign bit and there is a decimal point between bits 14 and 15. However, normalization of E (n) is not essential.

Next, the CPU 21 multiplies the contents of A ₁ and U _L (n−1) by the multiplication unit 31 and adds the multiplication result to Acc 34 by the addition unit 33 (S13). Similarly, the CPU 21 multiplies the contents of A ₂ and U _L (n−2) by the multiplication unit 31, and adds the multiplication result to Acc 34 by the addition unit 33 (S14).

Then, CPU 21 is an arithmetic shift in accordance with the contents of Acc34 the contents of the A _EL (S15). Specifically, since 2 ^JM is stored in A _EL , the CPU 21 arithmetically shifts the contents of Acc 34 by ^JM bits (in other words, arithmetic right shift by MJ bits).

Next, the CPU 21 multiplies the contents of B ₀ and E (n) by the multiplication unit 31, and adds the multiplication result to Acc 34 by the addition unit 33 (S16). Similarly, the CPU 21 multiplies the contents of B ₁ and E (n−1) by the multiplier 31 and adds the multiplication result to Acc 34 by the adder 33 (S17), and B ₂ and E (n−2). Is multiplied by the multiplication unit 31, and the multiplication result is added to Acc34 by the addition unit 33 (S18).

Here, B ₀ , B ₁ and B ₂ are virtually 26 bits in the decimal part, and E (n), E (n−1) and E (n−2) are 15 bits in the decimal part. , Acc 34 in which these product sums are accumulated and stored has a virtual decimal part of 41 bits. That is, when Acc34 is viewed as a signed fixed-point number, there is a decimal point between bits 40 and 41 virtually.

Then, CPU 21 is an arithmetic shift in accordance with the contents of Acc34 the contents of the A _HL (S19). Specifically, since 2 ^−J is stored in A _HL , the CPU 21 arithmetically shifts the contents of Acc 34 by J bits. After performing this arithmetic right shift, the decimal point position of Acc34 is between bits 28 and 29.

Next, the CPU 21 multiplies the contents of A ₁ and U _H (n−1) by the multiplication unit 31 and adds the multiplication result to Acc 34 by the addition unit 33 (S20). Similarly, the CPU 21 multiplies the contents of A ₂ and U _H (n−2) by the multiplication unit 31, and adds the multiplication result to Acc 34 by the addition unit 33 (S21). At this time, U (n) is already stored in Acc34 as the calculation result of Expression (8).

Thereafter, the CPU 21 reads out the contents of U _H (n−1) and U _L (n−1) from the RAM 23 for the calculation in the next cycle, and reads U _H (n−2) and U _L (n− 2) (S22).

  In the first embodiment, U (n) is an operation amount for the PWM circuit 25 and is calculated as a value representing a duty whose absolute value is smaller than 1. That is, in U (n), bit 15 is a sign bit and there is a decimal point between bits 14 and 15. On the other hand, since Acc 34 as the calculation result of step S21 has a decimal point between bits 28 and 29, 31 bits from bit 30 to bit 0 of Acc 34, including the sign bit (bit 30), are U (n). It may be extracted as

Therefore, the CPU 21 stores the contents of bits 30 to 15 and bits 14 to 0 of Acc 34 in U _H (n−1) and U _L (n−1) for calculation in the next cycle (S23). . In this case, the contents of bits 14-0 of Acc34 are stored right-justified in U _L (n-1).

  Thereafter, the CPU 21 stores the contents of E (n-1) in E (n-2) (S24), and further stores the contents of E (n) in E (n-1) (S25). Terminate the process. The output voltage of the converter 1 is controlled by the current mode control method by repeatedly repeating the above steps S11 to S25.

As described above, according to the first embodiment, before starting the calculation based on the difference equation of the equation (8) corresponding to the pulse transfer function represented by the equation (7), the coefficient of each of the deviation and the manipulated variable is calculated. b ₀ , b ₁ , b ₂ and a ₁ , a ₂ are previously stored in the RAM 23 as 16-bit fixed-point numbers, and the deviations E (n), E (n−1), E (n−2) and the manipulated variable are stored. An area for storing U (n), U (n−1), and U (n−2) as 16-bit and 31-bit fixed-point numbers is secured in the RAM 23. In this case, U (n-1) is in U _H (n-1) and U _L (n-1), and U (n-2) is in U _H (n-2) and U _L (n-2). , To be stored separately. For each calculation based on the difference equation of equation (8), the current deviation E (n) is first stored in the RAM 23 as a 16-bit fixed point number. Then, U _L (n-1) and _{A 1, U L (n-} 2) and A _2, E (n) and _{B 0, E (n-1} ) and _{B 1, E (n-2} ) and B ₂ , U _H (n−1) and A ₁ , and U _H (n−2) and A ₂ are read from the RAM 23 and multiplied by the multiplication unit 31, and the manipulated variable U ( n) is divided into U _H (n−1) and U _L (n−1) and stored as a fixed-point number of substantially 31 (= 16 + 15) bits.
Accordingly, U (n) indicated by the operation result is succeeded to the next operation with an accuracy of 31 bits, although the multiplication unit 31 that multiplies the 16-bit multiplier and multiplicand is used.
Accordingly, it is possible to prevent a reduction in the calculation accuracy of the manipulated variable even though an operation with a relatively small number of bits is performed.

Further, according to the first embodiment, the multiplication results of the plurality of multiplication terms included in Equation (8) are accumulated in Acc34, and the upper 16 bits and the lower 14 bits of the 30 bits from the least significant in the accumulation result, respectively. Are defined as U _H (n−1) and U _L (n−1) in the calculation result of Expression (8).
Therefore, prior to the (n + 1) th calculation of Equation (8), U (n) can be substituted into U _H (n−1) and U _L (n−1) without any loss of digits.

Furthermore, according to the first embodiment, the PWM circuit 25 generates a PWM signal based on the calculated operation amount U (n), and the switching element 11 of the converter 1 is switched by the generated PWM signal.
Therefore, the switching element 11 of the converter 1 can be controlled to be turned on / off based on the operation amount U (n) calculated by the calculation method that prevents the calculation accuracy from being lowered.

  Furthermore, according to the first embodiment, the current output from converter 1 is a controlled variable, and the current output from converter 1 can be controlled with high accuracy by a so-called current mode control method.

(Embodiment 2)
In the first embodiment, the product-sum is calculated three times in the calculation based on the formula (8), whereas in the second embodiment, the product-sum is calculated in the calculation based on the simplified formula (8). In this form, the calculation is divided into two times.
Since the block configuration of the control device and the functional configuration of the control unit 2 in the second embodiment are the same as those in the first embodiment, the corresponding parts are denoted by the same reference numerals and the description thereof is omitted.

Now, in the first embodiment, for example, when J has the same number of digits as N, by multiplying the coefficients a ₁ and a ₂ in equation (8) by 2 ^JN in advance, equation (8) becomes the following equation: It is deformed as in (14). Thereby, the number of times of calculating the product sum of the right side can be reduced from 3 times to 2 times without reducing the accuracy of the calculation.

_{U H (n) + U L} (n) · 2 -N = {(a 1 · 2 JN) · U L (n-1) + (a 2 · 2 JN) · U L (n-2) + (b ₀ · 2 ^J ) · E (n) + (b ₁ · 2 ^J ) · E (n−1) + (b ₂ · 2 ^J ) · E (n−2)} 2 ^−J + a ₁ · U _H ( n-1) + a ₂ · U _H (n-2) (14)

Next, an arithmetic unit realized by the control unit 2 that performs the calculation based on Expression (14) will be described with reference to a flowchart showing the operation.
FIG. 5 is a block diagram illustrating a configuration example of a computing unit in the control device according to the second embodiment of the present invention. FIG. 6 illustrates an operation amount for the PWM circuit 25 in the control device according to the second embodiment of the present invention. It is a flowchart which shows the process sequence of CPU21 which calculates. The process of FIG. 6 is started at every cycle of performing the calculation based on Expression (14), that is, every control cycle of PWM control, and is executed by the CPU 21 according to a control program stored in the ROM 22 in advance.

  The configuration of the multipliers 31 and 32 in FIG. 5 and the configuration of the integrating unit including the adder 33 and Acc 34 are the same as those in FIG.

Before starting the repetitive calculation, the CPU 21 arithmetically shifts the constants a ₁ and a ₂ in the expression (14) to the left by a predetermined number of bits so that the precision as the operand is maximized. .

A ₁ and A ₂ shown in FIG. 5 are numerical values calculated in advance by the equation (11) as in the first embodiment, and are stored in the RAM 23. Thus, when each of A ₁ and A ₂ is viewed as a 16-bit signed fixed-point number from bit 0 (LSB) to bit 15 (MSB), it is treated as having a decimal point between bits 13 and 14. .

On the other hand, b ₀ , b _1, and b ₂ are coefficients to be arithmetically shifted to the left by J bits further than a ₁ and a ₂ as in the first embodiment, and B ₀ , B _1, and B shown in FIG. ₂ is calculated in advance by Expression (12) and stored in the RAM 23. B ₀ , B ₁ and B ₂ are treated as if there is a decimal point between the bits 25 and 26 virtually.

A _HL shown in FIG. 5 is calculated in advance by equation (13) as in the first embodiment, and is stored in the RAM 23. Each of A ₁ ′ and A ₂ ′ is calculated in advance by the following equation (15) and is stored in the RAM 23.

_{A 1 '= A 1 · 2} JM, A 2' = A 2 · 2 JM ··· (15)

In addition, _UL (n-1), _UL (n-2), E (n-1), E (n-2), _UH (n-1) and _UH (n-2) shown in FIG. ), 0 as an initial value is stored in the RAM 23 as in the first embodiment.

  Next, moving to FIG. 6, a process of repeatedly calculating Expression (14) by the calculator shown in FIG. 5 will be described. Since each of steps S31, S32, and S36 to S45 shown in FIG. 6 is the same as steps S11, S12, and S16 to S25 in FIG. 4 of the first embodiment, a part of these descriptions is provided. Omitted.

  When the processing of FIG. 6 is started, the CPU 21 sets the deviation of the digital current value converted by the A / D conversion circuit 26 from the target value, with I (n) calculated by the equation (2) as the target value. Calculate (S31), and store the calculated deviation in E (n) (S32). Also in the second embodiment, E (n) is normalized so that the absolute value becomes an appropriate value smaller than 1. That is, E (n) is treated as if bit 15 is a sign bit and there is a decimal point between bits 14 and 15.

Next, the CPU 21 multiplies the contents of A ₁ ′ and U _L (n−1) by the multiplication unit 31 and adds the multiplication result to Acc 34 by the addition unit 33 (S33). Similarly, the CPU 21 multiplies the contents of A ₂ ′ and U _L (n−2) by the multiplication unit 31, and adds the multiplication result to Acc 34 by the addition unit 33 (S34).

Next, the CPU 21 multiplies the contents of B ₀ and E (n), the contents of B ₁ and E (n−1), and the contents of B ₂ and E (n−2) by the multiplying unit 31, respectively. Is added to Acc34 by the adding unit 33 (S36 to S38).

Here, B ₀ , B ₁ and B ₂ are virtually 26 bits in the decimal part, and E (n), E (n−1) and E (n−2) are 15 bits in the decimal part. , Acc 34 in which these product sums are accumulated and stored has a virtual decimal part of 41 bits. That is, when Acc34 is viewed as a signed fixed-point number, there is a decimal point between bits 40 and 41 virtually.

Then, CPU 21 is an arithmetic shift in accordance with the contents of Acc34 the contents of the A _HL (S39). After performing this arithmetic right shift, the decimal point position of Acc34 is between bits 28 and 29.

Next, the CPU 21 multiplies the contents of A ₁ and U _H (n−1) and the contents of A ₂ and U _H (n−2) by the multiplication unit 31, respectively, and multiplies the multiplication results to Acc 34 by the addition unit 33. Add (S40-S41). At this time, U (n) is already stored in Acc34 as the calculation result of Expression (14).

Thereafter, the CPU 21 reads out the contents of U _H (n−1) and U _L (n−1) from the RAM 23 for the calculation in the next cycle, and reads U _H (n−2) and U _L (n− 2) (S42).

  In the second embodiment, U (n) is calculated as a value representing a duty with an absolute value smaller than 1. That is, in U (n), bit 15 is a sign bit and there is a decimal point between bits 14 and 15. On the other hand, since Acc 34 as the calculation result of step S41 has a decimal point between bits 28 and 29, 31 bits from bit 30 to bit 0 of Acc 34 may be extracted as U (n).

Therefore, the CPU 21 stores the contents of bits 30 to 15 and bits 14 to 0 of Acc 34 in U _H (n−1) and U _L (n−1) for calculation in the next cycle (S43). . In this case, the contents of bits 14-0 of Acc34 are stored right-justified in U _L (n-1).

  Thereafter, the CPU 21 stores the contents of E (n-1) in E (n-2) (S44), and further stores the contents of E (n) in E (n-1) (S45). Terminate the process. The output voltage of the converter 1 is controlled by the current mode control method by repeatedly repeating the above steps S31 to S45.

As described above, according to the second embodiment, before starting the calculation based on the difference equation of the equation (14) corresponding to the pulse transfer function represented by the equation (7), the coefficient of each of the deviation and the manipulated variable is calculated. b ₀ , b ₁ , b ₂ and a ₁ , a ₂ are previously stored in the RAM 23 as 16-bit fixed-point numbers, and the deviations E (n), E (n−1), E (n−2) and the manipulated variable are stored. An area for storing U (n), U (n−1), and U (n−2) as 16-bit and 31-bit fixed-point numbers is secured in the RAM 23. In this case, U (n-1) is in U _H (n-1) and U _L (n-1), and U (n-2) is in U _H (n-2) and U _L (n-2). , To be stored separately. For each calculation based on the difference equation of equation (14), the current deviation E (n) is first stored in the RAM 23 as a 16-bit fixed point number. Then, U _L (n-1) and _{A 1 ', U L (n} -2) and A _2, E (n) and _{B 0, E (n-1} ) and _{B 1, E (n-2} ) and B ₂ , U _H (n−1) and A ₁ , and U _H (n−2) and A ₂ are read from the RAM 23 and multiplied by the multiplier 31, and the manipulated variable U indicated by the calculation result of Expression (14) is obtained. (N) is substantially divided into U _H (n−1) and U _L (n−1) and stored as 31 (= 16 + 15) -bit fixed point numbers.
Accordingly, U (n) indicated by the operation result is succeeded to the next operation with an accuracy of 31 bits, although the multiplication unit 31 that multiplies the 16-bit multiplier and multiplicand is used.
Accordingly, it is possible to prevent a reduction in the calculation accuracy of the manipulated variable even though an operation with a relatively small number of bits is performed.

Further, according to the second embodiment, the multiplication results of the plurality of multiplication terms included in Expression (14) are accumulated in Acc34, and the upper 16 bits and the lower 15 bits of the 31 bits from the least significant bit in the accumulation result, respectively. Are defined as U _H (n−1) and U _L (n−1) in the calculation result of Expression (14).
Therefore, prior to the (n + 1) th calculation of Equation (14), U (n) can be substituted into U _H (n−1) and U _L (n−1) without any loss of digits.

  In the first and second embodiments, the present invention is applied to the control device that controls the output voltage of the converter 1 by the current mode control method, but may be applied to general control that performs feedback control. In particular, when the transfer characteristic of the control target is represented by a pulse transfer function, the present invention has a special effect when there is a large difference in the numerical value between the coefficients of the corresponding difference equation.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. In addition, the technical features described in each embodiment can be combined with each other.

DESCRIPTION OF SYMBOLS 1 Converter 11, 12 Switching element 13 Inductor 14 Resistor 15 Capacitor 2 Control part 21 CPU
22 ROM
23 RAM
25 PWM circuit 26, 27 A / D conversion circuit 28 Voltage loop controller 29 Current loop controller 31, 32 Multiplier 33 Adder 34 Acc
4 Battery 5 Load

Claims (5)

A control device that controls an operation amount input to a control target whose transfer characteristic is represented by a pulse transfer function based on a deviation of the control amount from a target value, and the operation amount based on a difference equation corresponding to the pulse transfer function In a method of iteratively calculating
A storage unit;
A multiplication unit for multiplying a fixed-point multiplier and multiplicand of N digits (N is an integer of 2 or more);
The storage unit stores in advance the coefficients of the deviation and the manipulated variable as N-digit fixed-point numbers, and each time the calculation based on the difference equation, the deviation and the manipulated variable are N digits and N + M digits (M is Stored as a fixed-point number (natural number smaller than N),
The multiplication unit performs the calculation based on the difference equation, the deviation and the coefficient of the deviation, the upper N digits of the manipulated variable and the manipulated variable coefficient, and the lower M digit of the manipulated variable and the manipulated variable coefficient. Each of the above is read out from the storage unit and multiplied, and the operation amount of the control device is calculated. Preparing an integration unit for integrating the multiplication results of the multiplication unit,
The difference equation is the following equation (1):
The M digits from the least significant position and the N digits following the M digits in the integration result of the integration unit are set as U _L (n) and U _H (n) in the calculation result of the formula (1), respectively. The operation amount calculation method of the control device according to claim 1.
U _H (n) + _UL (n) · 2 ^−M = b ₀ · E (n) + b ₁ · E (n-1) + ·· + bm · E (n−m) + a ₁ · U _H (n− 1) + a ₂ · U _H (n−2) + ·· + a _k • U _H (n−k) + {a ₁ • U _L (n−1) + a ₂ • U _L (n−2) +・ ・ + A _k・_UL (n−k)} 2 ^−M (1)
However,
n: integer m greater than or equal to 2, k: integer satisfying 1 ≦ m ≦ k ≦ n−1 E (n): deviation of control amount for the nth time U _H (n): nth manipulated variable U ( n) upper N digits U _L (n): lower M digits of the nth manipulated variable U (n) bm: coefficient of deviation a _k : coefficient of manipulated variable The manipulated variable input to the controlled object whose transfer characteristics are represented by a pulse transfer function is controlled based on the deviation of the controlled variable from the target value, and the manipulated variable is iteratively calculated by the differential equation corresponding to the pulse transfer function. In the control device
The coefficient of each of the deviation and the manipulated variable is stored as a fixed-point number of N digits (N is an integer of 2 or more), and the deviation and the manipulated variable are respectively represented by N and N + M digits (N + M ( A storage unit for storing M as a fixed-point number (a natural number smaller than N);
For each calculation based on the difference equation, the deviation and the coefficient of the deviation, the upper N digits of the manipulated variable and the manipulated variable coefficient, and the lower M digits of the manipulated variable and the manipulated variable coefficient are stored in the memory, respectively. A control unit comprising: a multiplication unit that reads out and multiplies from the unit. The control target includes a PWM generation unit that generates a PWM signal based on the calculated operation amount, and a voltage conversion unit that includes a switching element that switches according to the PWM signal generated by the PWM generation unit. The control device according to claim 3.   The control device according to claim 4, wherein the control amount is a current output from the voltage conversion unit.

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