JP6185325B2 - Switching power supply device and semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a switching power supply device and a semiconductor integrated circuit device, and more particularly to a technique effective for a power supply device that performs power supply control by digitally controlled negative feedback control.

  For example, a DC / DC converter is known as a switching power supply device. The DC / DC converter includes a power stage circuit including an inductor, a capacitor, and a switch element, for example, and a control system.

  In the power stage circuit, the magnetic flux energy of the inductor is charged / discharged by turning on / off the switch element, and the output voltage is smoothed by the capacitor. The control system operates as a power supply regulator by controlling the on / off operation of the switch element so that the output voltage smoothed by the capacitor becomes equal to the target value.

  At this time, the ON / OFF control speed of the switch element is called a switching frequency, and the higher the speed, the smaller the fluctuation in output due to charging / discharging of the inductor, the so-called ripple. Further, the ratio of the ON period of the switching element within one cycle of the switching frequency is called a time ratio, and the magnitude of the output can be adjusted by increasing or decreasing the time ratio.

  In the control system of the switching power supply device, negative feedback control is performed to adjust the time ratio so as to cancel the error between the output of the power stage circuit and the target value.

  In recent years, the method of negative feedback control in a control system is changing from an analog method to a digital method. For example, in the analog method, a negative feedback voltage obtained by amplifying, integrating, and differentiating the difference between the output voltage and the set voltage by an error amplifier circuit is generated, and this negative feedback voltage is compared with a sawtooth wave by an analog comparator to generate PWM ( Pulse Width Modulation) signal is generated.

  The duty ratio of the power MOS-FET (Metal Oxide Semiconductor Field Effect Transistor) of the switch circuit is controlled by the generated PWM signal. At this time, the output voltage is changed by changing the phase ratio by phase compensation by an error amplifier circuit, and negative feedback control is performed so that the output voltage becomes equal to the set voltage.

  On the other hand, in the digital system, for example, operations such as amplification, integration, and differentiation are replaced with digital signal processing represented by an IIR (Infinite Impulse Response) filter by a DSP (Digital Signal Processor).

  Specifically, the output voltage is converted into a digital signal by an ADC (Analog to Digital Converter), and digital signal processing is performed on the error value subtracted from the target value by the DSP.

  Then, negative feedback control is performed so that the output voltage becomes equal to the set voltage by controlling the time ratio of the power MOS-FET by a digital PWM circuit that generates a pulse width according to the signal processing result.

  According to this digital method, it is possible to adjust control parameters by software, and it is possible to realize a flexible power supply device design according to applications and functions. In addition, it is possible to suppress the influence of manufacturing variations of control characteristics and environmental fluctuations compared to the analog method.

  As negative feedback control by this type of digital method, for example, the control method is changed by software in accordance with fluctuations in input current, temperature, or output voltage, thereby improving output voltage accuracy and reducing ripples to reduce power consumption. There is a technology (see, for example, Patent Document 1).

  On the other hand, the digital method has a problem that a delay time not found in the analog method, for example, a conversion time by the ADC or a calculation time by the DSP becomes a delay element in the negative feedback loop.

  The delay on the negative feedback system becomes a factor to reduce the phase margin and restricts the negative feedback gain, which hinders output response. In general, output response and system stability are in a reciprocal relationship. Increasing the negative feedback gain improves output response but reduces phase margin. In the worst case, the control that should be negative feedback becomes positive feedback and oscillates. If the negative feedback gain is reduced to suppress oscillation, the output response will deteriorate, resulting in undershoot or overshoot during startup or when there is a large load fluctuation.

  As countermeasures, for example, a technique for improving output responsiveness by dynamically changing a negative feedback gain and a frequency characteristic according to an output voltage (for example, refer to Patent Document 2), or controlling according to an error between an output and a target value. There are some that dynamically change the amount to reduce overshoot without sacrificing the rise time (see, for example, Patent Document 3).

  By the way, as an example of the configuration of the above digital arithmetic unit, the data transfer between the ADC, DSP, and PWM is performed by the DMAC, so that the load on the CPU (Central Processing Unit) can be reduced, and the power consumption and the performance can be improved. There is a technique (see, for example, Patent Document 4).

Japanese Patent Laid-Open No. 11-289553 JP 2004-304961 A JP2012-110124A JP 2013-25590 A

  However, the above-described techniques of Patent Documents 2 to 3 focus on overcoming the delay time related to the arithmetic processing that occurs with digitization, and refer to a configuration that speeds up the digital arithmetic unit itself. is not.

  In general, the digital system has a larger physical circuit scale than the analog system, so that optimization is required to reduce the number of components and make the circuit as small as possible from the viewpoint of miniaturization and cost reduction. For this reason, as the configuration of the digital arithmetic unit of the control system, a fixed-point arithmetic unit, that is, an integer arithmetic unit, whose circuit scale is significantly smaller than that of the floating point arithmetic unit is suitable.

  However, in the case of a fixed-point arithmetic unit, particularly when the circuit scale is reduced, overflow due to insufficient bit length, so-called overflow or underflow, so-called loss of digits, etc. becomes a problem. None of the above-mentioned patent documents avoids overflow or underflow.

  In the case of Patent Document 4, the processing of the negative feedback control system can be speeded up by operating the system processing by the CPU and the digital filter operation by the DSP in parallel. The DSP is composed of a 16-bit fixed point arithmetic unit, and the accumulator for storing the product-sum operation result is 36 bits. If the product-sum operation is 16 times or less, the operation result is accurate without overflowing. Here, the product-sum operation within 16 times corresponds to within 8 taps in the IIR filter calculation.

  The register file as a memory area that can be allocated as a control parameter or variable is 16 bits. If data overflows when shifting data from the accumulator to the register file, that is, when the digit is aligned, the maximum positive value or the minimum negative It works to saturate to the value and the sign is accurate.

  However, the overflow processing in Patent Document 4 guarantees the sign of the operation, and does not take into account the digital filter calculation performed by programming a series of operation procedures. Therefore, the continuity of control related to recovery from a state where the output of the digital filter is stuck due to overflow or underflow has not been studied.

  An object of the present invention is to provide a technique capable of realizing highly accurate digital power supply control by a fixed-point arithmetic unit having a small bit length.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The switching power supply in one embodiment includes a DC / DC converter and a voltage control unit that controls a power supply voltage generated by the DC / DC converter based on an output signal output from the DC / DC converter.

  The DC / DC converter has a switch unit that performs switching based on the PWM signal, and converts a DC power supply voltage into an arbitrary DC voltage. The voltage control unit controls a power supply voltage generated by the DC / DC converter based on an output signal output from the DC / DC converter.

  The voltage control unit includes an A / D converter, a digital arithmetic unit, and a PWM generation unit. The A / D converter converts the voltage output from the DC / DC converter into digital data.

  Based on the digital data converted by the A / D converter, the digital arithmetic unit calculates a time ratio for turning on the switch unit, and outputs it as control digital data. The PWM generation unit generates a PWM signal for driving the switch unit based on the control digital data calculated by the digital arithmetic unit.

  The digital computing unit then synchronizes at least the sampling frequency of the A / D converter with error data obtained by subtracting the set command value from the digital data converted by the A / D converter, and the digital computation in the digital computing unit. The internal state data and the calculation result data which is the calculation result by the digital filter are respectively held and updated, and offset data to be added to the calculation result data is held.

  High-precision digital power supply control can be performed.

It is explanatory drawing which shows an example of a structure of the power supply device in this Embodiment 1. FIG. It is explanatory drawing which shows an example of a structure in DSP which the power supply device of FIG. 1 has. It is a block diagram which shows the calculation procedure of Formula 5 in IIR calculation. It is a list which shows an example of a DSP program. FIG. 5 is an explanatory diagram showing an example of register file allocation in the DSP program list of FIG. 4. It is a flowchart which shows the process example of the main program by CPU. It is a flowchart which shows an example of the process in the power supply control interruption routine validated by the process of step S103 of FIG. It is a flowchart which shows an example of the IIR restart process in the process of step S216 of FIG. It is explanatory drawing which showed an example of the change of the output voltage in the power stage at the time of load fluctuation | variation generate | occur | producing. It is explanatory drawing which shows an example of the change of the output voltage in the startup of a power stage. It is explanatory drawing which shows an example of the block diagram when the operation | movement of the arithmetic unit in DSP by this Embodiment 2 is implement | achieved by the logic circuit.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., the shape of the component is substantially the case unless it is clearly specified and the case where it is clearly not apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Overview>
The power supply apparatus 100 includes an inductor 112, a capacitor 115, and a MOSFET 113, and includes a power stage 110 that converts an input to a target output, and a control system 120 that drives the MOSFET 113 of the power stage 110.

  The control system 120 includes an ADC 121 that converts the output of the power stage 110 into a digital value, and a subtractor 122 and a DSP 123 that add the offset value to the IIR filter calculation result as a phase compensation unit to obtain the time ratio of the MOSFET 113. A digital calculator and a PWM generator 124 that drives the MOSFET 113 of the power stage 110 by converting the time ratio into a pulse signal are configured.

  The digital arithmetic unit executes IIR filter calculation in response to the sampling period of the ADC 121, and in parallel, the CPU 127 monitors the temporal change of the error value, and if the error value is within a predetermined allowable value, the command value When the allowable value is exceeded, the command value is maintained, and when the allowable value is exceeded for a predetermined allowable period, the command value is set to the output of the current power stage and the IIR. The internal state data of the Z buffer of the filter is cleared to zero and the offset value is updated based on the current duty ratio.

  Hereinafter, embodiments will be described in detail.

<Configuration example of power supply device>
FIG. 1 is an explanatory diagram showing an example of the configuration of the power supply device according to the first embodiment. FIG. 1 shows an example of a power supply apparatus 100 that boosts an input voltage and regulates an output voltage.

  The power supply device 100 is a power supply device provided in an electronic device such as a mobile phone or a notebook personal computer, for example, and generates a direct-current power source serving as an operation power supply voltage of the electronic device using a battery provided in the electronic device as an input voltage. Switching power supply that outputs the output.

  In addition to this, the power supply device 100 can also be applied to a power supply device of a power storage system that supplies power stored in a battery during a power failure or the like. In this case, the DC power supply voltage supplied from the battery is input to the power supply device 100.

  Then, for example, a DC voltage of about 200 V is generated by the power supply device 100 and supplied to an inverter circuit or the like connected to the output unit of the power supply device 100. In the inverter circuit, the supplied DC voltage of about 200 is converted into an AC power supply of about 100 V and supplied.

  The power supply apparatus 100 includes a power stage 110 and a control system 120 that is a voltage control unit. The power stage 110 includes an input power supply terminal 111, an inductor 112, a MOSFET 113, a diode 114, a capacitor 115, an output terminal 116, and resistors 117 and 118.

  The MOSFET 113, the diode 114, the resistors 117 and 118, and the control system 120 in the power stage 110 are, for example, circuits provided in a semiconductor integrated circuit device. The inductor 112 and the capacitor 115 in the power stage 110 are circuits provided outside the semiconductor integrated circuit device.

  Here, as an example, the MOSFET 113, the diode 114, and the resistors 117 and 118 of the power stage 110 are provided in the semiconductor integrated circuit device. However, these circuits are provided outside the semiconductor integrated circuit device. May be.

  A DC voltage is input to the input power supply terminal 111 from the outside. The inductor 112, the MOSFET 113, the diode 114, and the capacitor 115 constitute a general DC / DC converter circuit, and supplies a DC voltage to an external load connected through the output terminal 116. The diode 114 is a free wheel diode, that is, a free wheel diode. Although the DC / DC converter circuit is not particularly limited, FIG. 1 illustrates a boost converter that is a typical topology of a boost converter.

  In the power stage 110, the gate of the MOSFET 113 serving as a switch unit is driven by a gate signal GS which is a PWM signal output from the control system 120. Note that the gate signal GS is input to the gate of the MOSFET 113 via the driver 101 or the like as necessary.

  The resistor 117 and the resistor 118 are connected in series between the output terminals 116. The signals divided by the resistors 117 and 118 are output to the control system 120 as the output voltage monitor signal VM.

  The control system 120 includes an ADC 121, a subtractor 122, a DSP 123, a PWM generation unit 124, DMACs (Direct Memory Access Controllers) 125 and 126, a CPU 127, and the like. The subtractor 122 and the DSP 123 constitute a digital arithmetic unit.

  In the control system 120, the output voltage monitor signal VM is converted from an analog signal to digital data by the ADC 121, which is an A / D converter, and is subtracted from the command value Vref set in the command value data register 131 by the subtractor 122. Value data Eout is calculated.

  Then, the time ratio data Dout, which is control digital data phase-compensated by the DSP 123, is calculated, and the pulse width modulation is performed by the PWM generator 124, thereby generating the gate signal GS and controlling the power stage 110.

  Although not shown in the figure, the ADC 121 receives the carrier cycle start pulse signal from the PWM generation unit 124, holds the voltage level of the output voltage monitor signal VM at the edge of the carrier cycle start pulse signal, and outputs the output monitor. The digital data MDD is converted and output to the subtractor 122.

  At the same time, although not shown in the figure, a conversion end signal is output to the subtractor 122, and the ADC 121 asserts the conversion end signal. This conversion end signal is negated by the ADC 121 at the start of conversion.

  The ADC 121 receives a control signal output from the CPU 127 and operates in the same manner as the carrier cycle start pulse signal described above. Here, the control signal output by the CPU 127 is a signal that is asserted / negotiated by, for example, a bit operation on a function register mapped in the memory space of the CPU 127.

  In response to the assertion of the conversion end signal from the ADC 121, the subtracter 122 subtracts the output monitor digital data MDD from the command value Vref of the command value data register 131, and the result is an error value data calculation result register 130. Write to.

  At the same time, although not shown in the figure, a transfer request pulse signal is output to the DMAC 125. The command value data register 131 is configured to be rewritable by a program of the CPU 127 at least at a carrier frequency.

  The subtractor 122 is, for example, a 16-bit signed integer arithmetic unit, and the command value data register 131 and the error value data calculation result register 130 are configured with 16 bits.

  The DMAC 125 writes the contents of the error value data calculation result register 130 to the storage location of the error value data Ein of the DSP 123 at the edge of the transfer request pulse signal from the subtractor 122.

  In response to the writing of the error value data Ein, the DSP 123 executes an IIR calculation DFI, which is a digital filter calculation programmed in advance in the DSP 123.

  Then, the offset offset is added to the data data that is the result of the IIR calculation and written to the storage location of the time ratio calculation result data Dout. At the same time, a transfer request pulse signal is output to the DMAC 126 although omitted in the figure.

  In the present embodiment, when the program of the CPU 127 determines that it is necessary by monitoring the error value data Ein, an operation such as starting a routine different from the IIR calculation DFI programmed in advance in the DSP 123 is performed. The internal state data of the Z buffer group BFF that is the internal state of the IIR calculation is cleared to zero. The Z buffer group BFF is, for example, Z00 to Zkl. However, k = 0 to the number of taps of each section k−1, and 1 = 0 to the number of sections−1.

  Subsequently, data obtained by multiplying the content of the storage location of the duty ratio calculation result data Dout at that time by the coefficient m given by the CPU 127 is written to the storage location of the offset offset as the content of the new offset offset.

  Then, data obtained by subtracting the error value data Ein from the content of the command value data register 131 at that time is written as the content of the new command value data register 131. Thereafter, the program of the DSP 123 is configured to return to a state where the IIR calculation DFI can be activated in response to the error value data Ein being written.

  The DMAC 126 writes the contents of the address where the time ratio calculation result data Dout is stored in the time ratio data register 150 in the PWM generation unit 124 at the edge of the transfer request pulse signal from the DSP 123.

  The PWM generation unit 124 is configured by digital PWM, and uses a triangular wave having the same frequency as the switching frequency of the power stage 110 (hereinafter referred to as carrier frequency, and the cycle is referred to as carrier cycle) as a carrier wave, the time ratio data register 150. The gate signal GS is generated by pulse width modulation of the content of.

<Configuration example of DSP>
FIG. 2 is an explanatory diagram showing an example of the configuration of the DSP 123 included in the power supply apparatus 100 of FIG.

  As shown in FIG. 2, the DSP 123 includes a register file 201, a product-sum operation register 202, an arithmetic unit 203, a control storage 204, and a program execution control unit 205.

  The register file 201 is a data storage area that is a calculation target in the calculator 203. This register file 201 is composed of 16 16-bit registers, for example, and is a data storage area used for the operation of the arithmetic unit 203.

  The register file 201 can be accessed via the CPU interface 206 via the CPU 127 or the DMA interface 207 to other functional modules in the control system 120 such as the subtractor 122 and the PWM generator 124.

  When writing to the register file 201 competes at the same address or at the same time, the storage of the calculation result of the calculator 203 is given the highest priority. Next, the DMA interface 207 and the CPU interface 206 are configured so that the DMA interface 207 is prioritized and the low-priority access is written after the high-priority write finishes.

  The arithmetic unit 203 is a 16-bit fixed point arithmetic unit, that is, an integer arithmetic unit. The computing unit 203 is a 16-bit data stored in the register file 201 or a 36-bit multiply-accumulated bit expanded to the most significant bit (MSB) side in accordance with an operation instruction of the program stored in the control storage 204. The 36-bit data stored in the arithmetic register 202 is calculated and stored.

  The arithmetic instruction of the arithmetic unit 203 is not particularly limited, and includes an arithmetic addition / subtraction instruction, an arithmetic shift instruction, an arithmetic multiplication instruction, a product-sum operation instruction, a 36-bit 16-bit arithmetic shift instruction, and the like.

  The arithmetic addition / subtraction instruction adds and subtracts 16 bits of arbitrary two data on the register file 201 designated by the arithmetic instruction and stores the result in the designated register file 201. The arithmetic shift instruction arithmetically shifts arbitrary data on the register file 201 and stores it in the designated register file 201.

  The arithmetic multiplication instruction multiplies any two data on the register file 201 by 16 bits, sign-extends the resulting 32 bits, and stores the result in the product-sum operation register 202. The product-sum operation instruction multiplies two arbitrary data on the register file 201, sign-extends 32 bits of the result, adds 36-bit data on the product-sum operation register 202, and stores the result in the product-sum operation register 202. The 36-bit 16-bit arithmetic shift instruction arithmetically shifts 36-bit data on the product-sum operation register 202 and stores it in the designated register file 201.

  Note that the arithmetic unit 203 is constituted by, for example, a signed fixed point arithmetic unit, and management of the decimal point position is performed by, for example, a DSP program.

  When the result is stored by the above arithmetic addition / subtraction, arithmetic multiplication, or arithmetic shift operation, if the overflow occurs due to the bit length of the storage destination, the data of the maximum value of the code can be output in the operation step. Here, the maximum value of the sign is a maximum value when positive, and a minimum value when negative.

  In order to improve the calculation accuracy, although not particularly limited, for example, data rounded down by right shift calculation is rounded to the minimum bit (LSB: Least Significant Bit) of the output data (including carry from LSB) Can be performed in the calculation step.

  The control storage 204 is a memory that stores a DSP program, and is written by the CPU 127. The program execution control unit 205 includes a program execution control register CTL and a program counter register PC.

  This program execution control unit 205 controls the control storage from the program address set by the CPU 127 in the program counter register PC in advance by the bit operation in the program execution control register CTL via the CPU interface 206, that is, from the address of the control storage 204. Control is performed so that the program stored in the program 204 is executed.

  That is, the instruction in the control storage 204 stored at the address indicated by the program counter register PC is decoded. In the case of an arithmetic instruction, the arithmetic unit 203 is controlled by the instruction to increment the program counter register PC. In the case of a control instruction, the instruction is executed to update the program counter register PC. To execute the DSP program. In the case of a control command, NOP (Non OPeration) indicating that nothing is performed is transmitted to the arithmetic unit 203.

  The control instruction is not particularly limited, and includes, for example, a wait (wait) instruction, a goto (branch) instruction, an event (transfer request effective) instruction, and the like. The wait instruction continues to hold the program counter register PC until the data in the register file 201 specified by the instruction is updated, that is, until rewritten by access through the CPU interface 206 or the DMA interface 207.

  The goto instruction branches to the address specified by the instruction. The event command issues a transfer request pulse signal for giving the timing to the DMACs 125 and 126 that transfer data from the DSP 123 to other functional modules via the DMA interface 207.

  The configuration example in which the output voltage monitor signal VM of the power stage 110 is negatively fed back and the gate signal GS of the MOSFET 113 is digitally controlled has been described above.

<Detailed configuration and operation of power supply unit>
Next, the details and operation of the configuration for realizing the operation according to the present embodiment will be described.

  In the power stage 110, various combinations of circuit parameters constituting the boost converter can be considered. Here, for example, the input voltage giving the specification of the power supply device 100 to the input power supply terminal 111 is 50 V, the target value of the output voltage from the output terminal 116 is 200 V, the maximum output current is 2 A, and the switching frequency is 50 KHz. For example, the inductor 112 can be 0.4 mH, and the capacitor 115 can be 2700 μF.

  The ADC 121 in the control system 120 receives, for example, 0 V to 3.3 V, and the voltage level of the output voltage monitor signal VM in response to the edge of the carrier cycle start pulse signal output from the PWM generation unit 124 described in detail later. Hold. In addition, the output monitor digital data MDD is output after being converted into a digital value with a resolution of 10 bits in an operation time of 250 ns.

  The resistors 117 and 118, which are voltage dividing resistors of the power stage 110, can output the output voltage by changing the voltage between the output terminals 116 from 0V to include the target voltage 200V, for example, by setting the resistor 117 to 198 kΩ and the resistor 118 to WkΩ. The voltage level of the monitor signal VM is divided into a voltage range that can be converted by the ADC 121 of the control system 120.

  The subtractor 122, the DMAC 125, the DSP 123, and the DMAC 126 perform subtraction, IIR calculation, offset addition, and offset update in 10 μs that is 1/2 of the carrier period that is the reciprocal of the switching frequency after the output monitor digital data MDD is generated. I do.

  The switching power supply digital control system which makes the sampling cycle, the switching cycle, and the carrier cycle the same and minimizes the delay time related to the quantization is configured by updating the duty ratio data register 150 in the PWM generator 1244. To do. For this purpose, for example, the subtraction speed of the subtractor 122, the calculation / control instruction execution speed of the DSP 123, the instruction execution speed of the CPU 127, and the bus speed of the DMACs 125 and 126 are configured at 50 MHz.

  The subtractor 122 performs integer subtraction within 60 ns after the ADC 121 outputs the output monitor digital data MDD, and writes the result in the error value data calculation result register 130. For example, the 10-bit data of the output monitor digital data MDD is subjected to 16-bit signed integer calculation by adding 6 to the MSB side 6 bits as the LSB side of the 16-bit data.

  The DMAC 126 transfers the data in the error value data calculation result register 130 to the storage location of the error value data Ein in the DSP 123 within 80 ns.

  In the DSP 123, the error value data Ein, the duty ratio data Dout, the Z buffer group BFF, the offset offset, or the coefficient m in FIG. 1 are assigned to the register file 201 in FIG.

  The calculation related to the addition / update of the IIR calculation DFI and offset offset in FIG. 1 is performed by the CPU 127 operating the bits of the register in the program execution control unit 205 by the program stored in the control storage 204 in FIG. It is executed at a speed of 20 ns per calculation.

  The IIR calculation DFI is a calculation for realizing an operation as a phase compensator. The characteristics of the phase compensator are not particularly limited, but can generally be a 3P2Z type transfer function shown in Equation 1.

  In Equation 1, s is a Laplace operator, K is a negative feedback gain parameter, fz0 and fz1 are zero frequency parameters, and fp0 and fp1 are pole frequency parameters. For the power stage 110 having the above specifications, as the above parameters, for example,

By setting the crossover frequency fc, which is the cut-off frequency of the negative feedback loop, to approximately 360 Hz, the phase does not become 180 degrees, that is, a phase compensator in which the negative feedback does not become positive feedback can be obtained.

  The transfer function of Equation 1 can be converted to a discrete-time transfer function that is generally suitable for digital computation by performing Z conversion. By converting the 3P2Z type transfer function so that Z becomes a maximum quadratic element, an IIR calculation formula consisting of two sections can be obtained as shown in Formula 5.

  In Expression 5, Z represents a discrete-time data string, and Z to the power of −n indicates that the data is n samples before.

  FIG. 3 is a block diagram showing the calculation procedure of Equation 5 in the IIR calculation DFI.

In Equation 5 and FIG. 3, C ₀₂ is a coefficient of the second section (first stage), Z ₁₂ is a Z buffer of the second section, and a ₁₂ and b ₁₂ are coefficients of the second section.

Further, C ₀₁ is a coefficient of the first section (following stage), Z ₁₁ is a Z buffer of the first tap of the first section, and a ₁₁ and b ₁₁ are coefficients of the first tap of the first section. Z ₂₁ is the Z buffer of the second tap of the first section, and a ₂₁ and b ₂₁ are the coefficients of the second tap of the first section.

  The parameters in Equation 5 and FIG. 3 are the parameters of IIR if the sampling period is 20 μs as the parameter (Equation 2 to Equation 4) of the transfer function (Equation 1).

And

  As a result, the operation speed of the data data from the error value data Ein of FIG. 3, that is, the speed of updating n in FIG. It can be realized equivalently.

  For convenience of explanation, n in FIG. 3 is described to indicate that the discrete time is updated simultaneously every time one is advanced, and the variable with n need only hold the data of the current discrete time, There is no need for an array. In FIG. 3, past states n-1 and n-2 whose discrete times have been updated are held as internal state data in the Z buffer.

  In the DSP 123, the above-described IIR parameters (Expression 6 to Expression 13) are allocated to the register file 201 and written in advance by the CPU 127. Then, the offset offset is added to the data data of the calculation result of the IIR calculation DFI, and the result is output as the time ratio data Dout. It should be noted that intermediate data and the like when calculating the block diagram of FIG. 3 and adding or updating offsets are also assigned to the register file 201 as appropriate.

  The DSP 123 outputs the time ratio data Dout within 9.53 μs after the data is written in the error value data Ein by executing the above-described DSP program.

  The DMAC 126 transfers the time ratio data Dout on the register file 201 in the DSP 123 to the time ratio data register 150 in the PWM generator 124 within 80 ns.

  The PWM generator 124 in the control system 120 is configured to operate with a carrier wave with a switching frequency of 50 KHz (carrier cycle 20 μs). For example, the resolution is 1 ns, and if the carrier wave is a triangular wave, 14 bits that operate at 1 GHz. Consists of an up / down counter.

  By counting down from the initial value 10,000 to 0, counting up to 10,000 (0x2710), and counting down to 0 again, the operation as a 50 KHz triangular wave is realized.

  When the 14-bit up / down counter is less than the content of the time ratio data register 150, the gate signal GS is asserted to turn on the MOSFET 113 of the power stage 110, and the content of the 14-bit up / down counter is The gate signal GS is negated and the MOSFET 113 is turned off.

  As a result, the size of the time ratio data register 150 is modulated to a pulse width which is the ON period of the MOSFET 113 within the carrier period. Each time the 14-bit up / down counter value reaches 10,000 (0x2710), a carrier cycle start pulse signal for the ADC 121 is output.

<Example of DSP program processing>
Next, a processing example of the DSP program having the above configuration will be described.

  4 is a list showing an example of the DSP program, and FIG. 5 is an explanatory diagram showing an example of assignment of the register file 201 in the DSP program list of FIG.

  In the steps of the list in FIG. 4, “step” indicates the storage address of the control storage 204, and it is assumed that the operation is performed at the above-described calculation speed (20 μs per step).

  In addition, the format of the operation instructions (instructions other than the above-described control instructions) described in each step is not particularly limited, and operations that can be easily realized by the arithmetic unit construction technology in a general DSP are written in the C language. Shown according to the format.

  The variable SUM indicates the product-sum operation register 202 (36 bits), and the other variables are storage areas (16-bit data) on the register file 201 assigned as shown in FIG.

  The shift operation constant is 4-bit data stored in the control storage 204 together with the step. The control instruction executes the function described above, and the argument is a constant stored in the control storage 204 together with the control instruction of the step.

  In the initial state, the program counter register PC in the program execution control unit 205 points to step 0. When the DSP program is started by the bit operation of the program execution control register CTL in the program execution control unit 205 by the CPU 127, the program execution control unit 205 sequentially executes each step of the program in the list of FIG. 4 from step0. .

  In step 0 of the list of FIG. 4, the DSP 123 holds the program counter register PC as step 0 until data is written in the storage address (address 3) of the coefficient m.

  In response to the CPU 127 writing data to address 3 (coefficient m) of the register file 201, the program counter register PC is incremented and sequentially executes the program after step1.

  In the execution of step 1 to step 3, the internal state data of the Z buffer group BFF that holds the internal state of the IIR calculation DFI is cleared to zero. Then, the offset offset is updated in the execution of step 4 to step 5.

  At step 6, the DSP 123 holds the program counter register PC (holds the data write waiting state at address 2) in the same manner as step 3 for the storage address of the error value data Ein, and when the data at address 2 is written, Proceed to the program.

  Steps 7 to 24 are IIR calculation DFIs, which are obtained by programming the block diagram shown in FIG. As shown in FIG. 5, the variable x that shifts 4 bits to the left of step 7 is error value data Ein, and the fixed-point position is (integer bit.fractional bit) = (6.10). An operation is performed.

  That is, since it is 10 bits of the output of the ADC 121, the output voltage monitor signal VM is 3.3V, that is, the output of the power stage 110 is 1.0 with respect to 330V, more precisely 0x3FF / 0x400. Determine the location. The calculation of the negative feedback gain of the transfer function described above incorporates this feedback gain (1/330).

  In the IIR parameter data (Equation 6 to Equation 13) described above, the CPU 127 writes an initial value converted to an integer at the fixed-point position shown in FIG. 5 at addresses 7 to 14 of the register file 201 shown in FIG.

  By sequential execution of operations including digit alignment of step 8 to step 22, the temporal ratio normalized to 0.0 to 1.0 of the fixed point position (1.15) is stored in temp (address 3) as temporary data. Calculated.

  In step 23 to step 24, the time ratio is multiplied by the maximum value of the triangular wave 10,000 (0x2710) in the PWM generation unit 124 described above, and the scale is scaled to the data range to be output to the time ratio data Dout.

  Thereafter, an offset offset is added at step 25 and stored in the duty ratio data Dout (address 0), and the transfer request for the data stored at address 0 is made effective at step 26.

  Subsequently, at step 27, the program counter register PC branches unconditionally to step 6, and returns to the data write waiting state at the address 2. The update of the discrete time of the Z buffer is executed by operation instructions of step 12 and step 20 to step 21.

<CPU processing example>
Next, processing of a program in the CPU 127, that is, processing of a so-called CPU program will be described. The CPU 127 controls the operation of the entire control system including the DSP program based on the CPU program.

  FIG. 6 is a flowchart showing a processing example of the main program 500 by the CPU 127.

  First, the CPU 127 executes a hardware setting process (step S101). This hardware setting process is an operation setting process in the ADC 121, the subtractor 122, the DMACs 125 and 126, and the PWM generation unit 124, and is a program data writing process and an initial value writing process.

  The program data writing process is writing the program data of the list shown in FIG. 4 to the control storage 204 of the DSP 123. The initial value writing process is a process of writing the initial value shown in FIG.

  Subsequently, initialization of the variables in the program executed by the CPU 127 and initialization of the variables in the functional module for digital processing in the control system 120 are performed (step S102). In the processing of step S102, initialization of main variables and constants used as global variables among the variables and constants in the program in the CPU 127 is as follows.

  The target value is a digital conversion value of the output voltage monitor signal VM that becomes the target value of the output voltage of the power supply apparatus 100. 0x026C indicating an output voltage of 200 V is set.

  The command value Vref is a command value of an output voltage for the power stage 110 and is a variable value set in the command value data register 131. The initialization of the command value Vref is executed in the process of step S104 described later.

  The abnormal value is a digital conversion value of the output voltage monitor signal VM that is an output voltage defined by the power supply apparatus 100. For example, when the output voltage is 10% of 200V, 0x02AA indicating 220V is set.

  The allowable value is an allowable voltage with respect to an absolute value of the error value data Ein for detecting that the IIR calculation is stuck. For example, when the output voltage is 200V ± 5%, 0x001F indicating 10V is set.

  The convergence value is a convergence voltage with respect to the absolute value of the error value data Ein for determining whether or not the power stage is in a steady state in the IIR calculation. For example, when the output voltage is 200V ± 2%, and the ripple voltage is within 1% and is four times that, 0x000C indicating 4V is set.

ΔVref is a step amount for increasing the command value Vref to a target value at the time of start-up and restart from the stack. It is assumed that it is larger than the convergence value of the absolute value of the error value, for example, 5V.

  The convergence counter is a counter variable for determining that the power stage is in a steady state in the IIR calculation. In the initialization in the process of step S102, 0 is set.

  The convergence determination count value is a value of a convergence counter that determines that the power stage has converged to a steady state in IIR calculation, and is specified by the number of carrier cycles. For example, the variable is calculated in proportion to the command value Vref. Alternatively, for example, a constant of 20 (corresponding to 400 μs) may be set.

  The stack detection counter is a counter variable for detecting that the IIR calculation is stuck. In initialization of the processing in step S102, 0 is set.

  The stack determination count value is a value of a convergence counter that determines that the IIR calculation is stuck, and is specified by the number of carrier cycles. For example, 250 (corresponding to 5 ms) is set.

  The abnormality detection flag is a state variable that is set to “1” when the output voltage of the power supply apparatus 100 exceeds the abnormal value described above. In initialization of the processing in step S102, 0 is set.

  In the process of step S102, the time ratio data register 150 in the PWM generation unit 124, the error value data calculation result register 130 in the subtractor 122, and the command value data register 131 are initialized to zero (0x0000). In step S102, the program counter register PC in the program execution control unit 205 of the DSP 123 is initialized to zero (0x0000).

  Then, a power supply control interrupt enabling process is executed (step S103). This power control interrupt enabling process enables the interrupt for the power control interrupt routine to realize the switching power control method in the power supply apparatus 100 in the power control interrupt routine executed in the carrier cycle unit shown in FIG. .

  The interrupt for the power control interrupt routine can be, for example, a data transfer completion interrupt that generates an interrupt factor each time data transfer to the error value data Ein in the DMAC 125 is completed.

  Subsequently, the ADC 121, the subtractor 122, the DMAC 125, and the DMAC 126 are made operable (step S104). Thereafter, the ADC 121 is operated only once by asserting and negating the control signal from the CPU 127 to the ADC 121.

  As a result, the subtractor 122 and the DMAC 125 operate, and after the data is stored in the error value data Ein on the register file 201, the error value data Ein is read and set in the current command value data register 131. The command value Vref (initial value is arbitrary) is subtracted. Thus, the current output voltage is obtained, the obtained output voltage is set as the initial value of the command value Vref, and the initialized command value Vref is written in the command value data register 131.

  Then, the program execution control register CTL in the program execution control unit 205 of the DSP 123 is bit-operated to start execution of the DSP program shown in FIG. 4, and the coefficient m (address 3) in the register file 201 is zero (0x0000). Write.

  As a result, the ADC 121, the subtractor 122, and the DMACs 125 and 126 enter a signal waiting state for controlling the start of execution, and the DSP 123 performs error value data in the register file 201 for performing IIR calculation (step 6 and subsequent steps in FIG. 4). It enters a state of waiting for writing to Ein (address 2). Thereafter, by starting the execution of the PWM generation unit 124, the boost conversion from the soft start, which is a control for smoothing the rising of the output voltage, is started.

  The CPU 127 executes system monitoring processing (step S105). System monitoring processing is performed when, for example, signal control of the entire system such as stop given from the outside, or abnormal processing of abnormality detection such as overcurrent detection is performed, and an external stop request or an unrecoverable error is detected. The gate signal GS output from the PWM generator 124 is negated to stop the operation of the power supply apparatus 100 (step S106).

<Example of power control interrupt routine processing>
FIG. 7 is a flowchart showing an example of processing in the power control interrupt routine that is validated in the processing of step S103 in FIG.

  As described with reference to FIG. 6, the power control interrupt routine is called by an interrupt for each carrier cycle.

  In FIG. 7, the power supply control interrupt routine performs an abnormal process, IIR calculation stack detection, IIR restart process, and soft start process.

  First, the abnormality process will be described. The error value data Ein of the DSP 123 is read, and a value obtained by subtracting the error value data Ein from the current command value Vref, that is, an output voltage is calculated and compared with an abnormal value (step S201).

  If the subtraction value is equal to or greater than the abnormal value, that is, the output voltage is an abnormal voltage, the abnormality detection flag is set to “1” and the interrupt process is terminated (step S202). If the abnormality detection flag is “1”, the process is performed in step S105 in FIG. 6 and the operation of the power supply apparatus 100 is terminated.

  Next, stack detection and restart processing of IIR calculation DFI will be described.

  The absolute value of the error value data Ein read in the process of step S201 is compared with the allowable value (step S203). If the allowable value is exceeded, the convergence counter is cleared to zero (step S204), and the stack detection counter is incremented (step S205).

  Then, the stack detection counter is compared (step S206), and if it is less than the stack determination count value, the interrupt process is terminated. If the stack determination count value has been reached, it is determined that the stack state has been reached, the command value Vref is updated (step S207), the IIR calculation DFI is restarted (step S216), and then the stack detection counter Is cleared to zero (step S208), and the interrupt process is terminated.

  In the process of step S207, the CPU 127 obtains a digital value indicating the output voltage of the power stage 110 by subtracting the error value data Ein from the current command value Vref managed by the wide area variable, and updates the command value Vref. At this time, when the subtraction result exceeds the target value, the command value Vref is updated so as to become the target value.

<Example of IIR restart processing>
FIG. 8 is a flowchart showing an example of the IIR restart process in the process of step S216 of FIG.

  First, the execution of the DSP program is shifted to step 0 of FIG. 4 to wait for the writing of the coefficient m (step S301). Then, the command value Vref updated in the process of step S207 of FIG. 6 is written in the command value data register 131 of the subtractor 122 (step S302).

  Then, the value to be written to the coefficient m is normally set to 1.0 (0x7FFF) (step S303), and when the subtraction exceeds the target value in the process of step S207 in FIG. 7, it is smaller than 1.0 depending on the degree. (However, it is calculated to be 0.0 or more).

  By writing the coefficient to the coefficient m of the register file 201, the DSP 123 clears the internal state data of the Z buffer group BFF, which is the internal state of the IIR calculation DFI, to zero, and multiplies the current time ratio data Dout by the multiplier m to offset offset. After that, the execution wait state for IIR calculation after step 6 in FIG.

  Although the internal state of the IIR is cleared by the processing of steps S207 and S216, the error data Ein that is continuously input by setting the output voltage of the power stage 110 to the command value Vref becomes a data string starting from zero, and does not overflow. It can be calculated. Then, by adding the output of IIR to the output as an offset, the output to the time ratio data register 150 of the PWM generation unit 124 can be made continuous.

<Example of processing due to change in output voltage>
FIG. 9 is an explanatory diagram showing an example of a change in output voltage in the power stage 110 when a load change occurs.

  In FIG. 9, an overflow or underflow occurs in the IIR calculation in which the time ratio is greatly changed with a sudden load change from the steady state where the output voltage is controlled to be equal to the target value. Even when stacking is performed as indicated by the output voltage change 802 indicated by, it is possible to perform control for resuming the IIR calculation by eliminating the stack state so that the operation of the output voltage change 801 indicated by the solid line is performed. it can.

  Further, in the process of step S207 in FIG. 7, when the command value Vref is set to the current output voltage, the output voltage of the power stage 110 becomes an abnormal value due to overflow or underflow of IIR calculation by limiting it to a target value or less. Can be avoided in advance.

<Example of soft start processing>
Next, the soft start process will be described.

  In FIG. 7, the current command value Vref is compared with the target value, and if it is less than the target value, the soft start processing after the processing in step S210 is executed (step S209). The detection counter is cleared to zero (step S208), and the interrupt process is terminated.

  If it is not the target value, the absolute value of the error value data Ein read in the process of step S201 is compared with the convergence value (step S210). If the convergence value is exceeded, the stack detection and restart after the process of step S203 are performed. The same processing as the processing is performed. On the other hand, if the value is equal to or less than the convergence value, the convergence determination after the processing in step S211, the update of the command value Vref, and the soft start using the IIR restart process are performed.

  In the process of step S210, if the convergence value is exceeded, the convergence counter is incremented if the absolute value of the read error value data Ein is within the convergence value (step S211).

  Subsequently, it is determined whether or not the convergence counter is equal to or greater than the convergence determination count value (step S212). If the convergence counter is less than the convergence determination count value, the interrupt process is terminated. In the process of step S212, if the convergence counter has reached the convergence determination count value, it is determined that it has converged, and ΔVref is added to the current command value Vref to update the command value Vref (step S213). When the addition result of the process of step S213 exceeds the target value, the command value Vref is set as the target value.

  Then, the convergence counter is cleared to zero (step S214). After that, by performing the process of step S216, it is possible to suppress an increase in the Z buffer accompanying startup and avoid an overflow or underflow of IIR calculation.

  Even during the soft start period, if the error value data Ein deviates from the allowable value, in the execution of the repetitive power control interrupt routine, the same processing as the stack detection and restart processing is performed in the branch by the processing in step S203. Processing is performed.

  Also, at start-up, a sudden increase in duty ratio results in an excessive inrush current. In order to prevent this, for example, an interval counter is provided as a global variable. In the process of step S212, a determination for performing the process of step S213 is added at least after a necessary period has elapsed since the update of the command value Vref, and the increase in the command value Vref over time is limited.

  The interval counter is incremented each time the power control interrupt routine is called, and is cleared to zero together with the clearing of the convergence counter in the process of step S214. The interval determination count value for determining the passage of the necessary period is, for example, 500.

<Example of processing due to change in startup output voltage>
FIG. 10 is an explanatory diagram showing an example of a change in the output voltage at the startup of the power stage 110.

  In FIG. 10, when a bit length arithmetic unit optimized for steady-state control causes the Z buffer to overflow due to a large voltage change at start-up, the output voltage is changed to an output voltage change 903 indicated by a dotted line. Will end up.

  However, in the power stage 110, since the duty ratio can be increased while clearing the internal state data of the Z buffer that increases with the increase of the command value Vref to zero, the output voltage is indicated by a solid line without causing an overflow. It is possible to realize a soft start so that the change 901 occurs.

  In addition, when an overflow or underflow occurs in the IIR calculation due to a disturbance such as a temperature change during the soft start period and the output is stacked, the stack detection and the IIR restart process are executed by the IIR calculation. .

  As a result, the output voltage can be controlled such that the stack state is canceled and the IIR calculation is restarted so that the output voltage changes 902 indicated by the one-dot chain line in FIG. 10, for example.

  As described above, when the error value is within a predetermined allowable value, the soft start control of the startup can be realized by bringing the command value Vref close to the target value.

  Even if the bit length of the storage area of the variable related to the IIR calculation overflows (overflows) or drops (underflows) and the time ratio is not updated, the command value Vref is set to the current power stage 110. Set to the output value of. Then, the internal state data of the Z buffer of the IIR filter in the DSP 123 can be cleared to zero to return to a state where IIR calculation similar to that at the start-up is possible.

  The overflow (overflow) or underflow (underflow) is caused by fluctuations in circuit parameters caused by disturbances such as inrush current in the transient state of the power stage 110 at start-up and load fluctuations including steady state and temperature changes. This is caused by a large change in the ratio.

  At the same time, by setting the current duty ratio to the offset value, the duty ratio becomes a continuous operation, so that the duty ratio can be controlled without greatly deviating from linearity.

  In other words, according to the control technique of power supply apparatus 100 according to the present embodiment, when the time ratio is largely changed due to a change in circuit parameters, overflow or underflow of the digital arithmetic unit can be allowed. As a result, the integer part of the variable related to the IIR filter calculation can be set to the minimum bit length necessary for the calculation in the steady state of the power stage 110.

  This makes it possible to assign a large number of digits in the bit length of the memory storage area as a fractional part to the digital control of the power stage 110 in the steady state, and as a result, a fixed-point operation with a small bit length. It can be said that a high-precision digital power supply control technology is provided by the device.

(Embodiment 2)
<Overview>
In the second embodiment, an example of a digitally controlled switching power supply device in which the IIR calculation DFI is implemented as hardware will be described.

  In the first embodiment, the function of the arithmetic unit 203 in FIG. 3 is configured by DSP software. However, the arithmetic unit 203 can also be configured by hardware by a logic circuit.

<Configuration example of computing unit>
FIG. 11 is an explanatory diagram showing an example of a block diagram when the operation of the arithmetic unit 203 in the DSP 123 according to the second embodiment is realized by a logic circuit.

  In FIG. 11, a logic circuit that performs IIR calculation is given one control signal “modify” from the outside. When the control signal modify is asserted, the internal state data of the Z buffer is cleared to zero, and the offset is stored by multiplying the time ratio data Dout, which is the output of the IIR calculation DFI, by the coefficient m.

  The DSP 123 described in the first embodiment is replaced with a logic circuit that operates according to the block diagram shown in FIG. Then, in the process of step S216 which is the IIR restart process shown in FIG. 8, the process of step S301 is omitted, and after the process of step S303, the control signal “modify” of FIG. There is an execution step that only asserts.

  As a result, other circuit configurations, control of the CPU 127, operation of the control system 120, and effects can be realized as in the first embodiment. Furthermore, since the circuit can be optimized, the hardware can be made smaller.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In addition, this invention is not limited to above-described embodiment, Various modifications are included. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.

  Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

100 power supply device 110 power stage 111 input power supply terminal 112 inductor 113 MOSFET
114 Diode 115 Capacitor 116 Output terminal 117 Resistor 118 Resistor 120 Control system 121 ADC
122 Subtractor 123 DSP
124 PWM generation unit 130 Error value data calculation result register 131 Command value data register 150 Time ratio data register 201 Register file 202 Product-sum operation register 203 Calculator 204 Control storage 205 Program execution control unit 206 CPU interface 207 DMA interface CTL Program execution control Register PC Program counter register

Claims (6)

A DC / DC converter that has a switch unit that performs switching based on the PWM signal and converts a DC power supply voltage into an arbitrary DC voltage;
A voltage control unit that controls a power supply voltage generated by the DC / DC converter based on an output voltage output from the DC / DC converter;
With
The voltage controller is
An A / D converter that converts the voltage output from the DC / DC converter into digital data;
Based on the digital data converted by the A / D converter, a time ratio for turning on the switch unit is calculated and output as control digital data;
Based on the control digital data calculated by the digital arithmetic unit, a PWM generation unit that generates the PWM signal for driving the switch unit;
Have
The digital computing unit includes error data obtained by subtracting a command value set from digital data converted by the A / D converter in synchronization with at least the sampling frequency of the A / D converter, and digital data in the digital computing unit. The internal state data of the calculation and the calculation result data which is the calculation result by the digital filter are respectively held and updated, the offset data to be added to the calculation result data is held, and the digital data is changed according to the temporal change of the error data. The control digital data calculated by the arithmetic unit is held in the offset data so as to be added to the next calculation result data, the internal state data is cleared, and output from the A / D converter when cleared The error data is obtained by using the digital data to be the command value. To Rear, switching power supply device. The switching power supply device according to claim 1 ,
The digital computing unit adds the control digital data immediately before the calculation by the digital computing unit to the next calculation result data when the error data continuously exceeds a threshold value for a set period or longer. A switching power supply device that holds the offset data so as to be a value. The switching power supply device according to claim 2 ,
The switching unit according to claim 1, wherein the digital computing unit calculates at least one of the threshold value and the period in accordance with the digital data converted by the A / D converter or the magnitude of the command value. A power supply generated by the DC / DC converter based on an output voltage output from a DC / DC converter that has a switch unit that performs switching based on a PWM signal and converts a DC power supply voltage into an arbitrary DC voltage A voltage control unit for controlling the voltage;
The voltage controller is
An A / D converter that converts the voltage output from the DC / DC converter into digital data;
Based on the digital data converted by the A / D converter, a time ratio for turning on the switch unit is calculated and output as control digital data;
Based on the control digital data calculated by the digital arithmetic unit, a PWM generation unit that generates the PWM signal for driving the switch unit;
Have
The digital computing unit includes error data obtained by subtracting a command value set from digital data converted by the A / D converter in synchronization with at least the sampling frequency of the A / D converter, and digital data in the digital computing unit. The internal state data of the calculation and the calculation result data by the digital filter are respectively held and updated, the offset data to be added to the calculation result data is held, and the digital arithmetic unit calculates in accordance with the temporal change of the error data The control digital data is stored in the offset data so as to be added to the next calculation result data, the internal state data is cleared, and the digital output from the A / D converter when the data is cleared clearing the error data by the data and the command value, half Body integrated circuit device. The semiconductor integrated circuit device according to claim 4 .
The digital computing unit adds the control digital data immediately before the calculation by the digital computing unit to the next calculation result data when the error data continuously exceeds a threshold value for a set period or longer. A semiconductor integrated circuit device which holds the offset data so as to be a value. The semiconductor integrated circuit device according to claim 5 .
The semiconductor integrated circuit device, wherein the digital arithmetic unit calculates at least one of the threshold value and the period in accordance with the digital data converted by the A / D converter or the magnitude of the command value.

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