JP2016015378A - Silicon carbide semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device capable of reducing a forward resistance while keeping high breakdown voltage.SOLUTION: A p-type epitaxial region 3 has a trench TR having a side surface SS and a bottom part BS. An n-type epitaxial region 4 abuts the p-type epitaxial region 3 at the side surface SS and the bottom part BS of the trench TR, respectively. A semiconductor layer 2 covers both of a first main surface 3a of the p-type epitaxial region 3 and the n-type epitaxial region 4. A first electrode 16 is provided on the semiconductor layer 2. A second electrode 20 is provided on a second main surface 3b side of the p-type epitaxial region 3. The first main surface 3a of the p-type epitaxial region 3 is a silicon plane or a plane 8° off the silicon plane. The side surface SS of the trench TR is a plane more than 50° and less than 70° off the silicon plane.

Description

  The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly, to a silicon carbide semiconductor device including a p-type epitaxial region and an n-type epitaxial region and a manufacturing method thereof.

  In recent years, in order to enable a semiconductor device to have a high breakdown voltage, low loss, use under a high temperature environment, etc., silicon carbide is being adopted as a material constituting the semiconductor device. Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve high breakdown voltage of the semiconductor device, reduction of on-resistance, and the like. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

Y. Takeuchi, 4 others, “SiC migration enhanced embedded epitaxial (ME ³ ) growth technology”, Materials Science Forum Vols. 527-529, 2006, pp. 251-254 (Non-Patent Document 1) A method is described in which a p-type epitaxial layer is formed on the surface of a silicon carbide substrate having a groove and having an n-type conductivity and inside the groove. According to this method, since the p-type epitaxial layer grows so as to fill the trench, a p-type region to which an impurity such as aluminum is locally added can be formed.

Y.Takeuchi, 4 others, "SiC migration enhanced embedded epitaxial (ME3) growth technology", Materials Science Forum Vols. 527-529, 2006, pp. 251-254

  When a super junction structure is formed by the p-type region filling the groove and the n-type region of the silicon carbide substrate, a high breakdown voltage can be realized when a reverse voltage is applied due to the depletion layer caused by the pn junction. . However, according to the method described in the above document, since the impurity concentration of the p-type region cannot be sufficiently increased, the impurity concentration of the n-type region forming the pn junction cannot be sufficiently increased. Therefore, the forward resistance of the silicon carbide semiconductor device at the time of forward voltage application cannot be sufficiently reduced. As a result, it has been difficult to obtain a silicon carbide semiconductor device capable of reducing the forward resistance while maintaining a high breakdown voltage.

  The objective which concerns on 1 aspect of this invention is to provide the silicon carbide semiconductor device which can reduce a forward resistance, and its manufacturing method, maintaining a high proof pressure.

  A silicon carbide semiconductor device according to one embodiment of the present invention includes a p-type epitaxial region, an n-type epitaxial region, a semiconductor layer, a first electrode, and a second electrode. The p-type epitaxial region has a first main surface, a second main surface opposite to the first main surface, a side surface connected to the first main surface, and a bottom portion connected to the side surface. The trench is provided and is made of silicon carbide. The n-type epitaxial region is in contact with the p-type epitaxial region at each of the side surface and the bottom of the trench and is made of silicon carbide. The semiconductor layer covers both the first main surface of the p-type epitaxial region and the n-type epitaxial region. The first electrode is provided on the semiconductor layer. The second electrode is provided on the second main surface side of the p-type epitaxial region. The first main surface of the p-type epitaxial region is a silicon surface or a surface off by 8 ° or less from the silicon surface. The side surface of the trench is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface.

  A method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention includes the following steps. A p-type epitaxial region having a first main surface and a second main surface opposite to the first main surface and made of silicon carbide is formed. A trench having a side surface connected to the first main surface and a bottom portion connected to the side surface is formed on the first main surface of the p-type epitaxial region. An n-type epitaxial region made of silicon carbide is formed in contact with the p-type epitaxial region on both the side and bottom of the trench. A semiconductor layer covering both the first main surface of the p-type epitaxial region and the n-type epitaxial region is formed. A first electrode in contact with the semiconductor layer is formed. A second electrode is formed on the second main surface side of the p-type epitaxial region. The first main surface of the p-type epitaxial region is a silicon surface or a surface off by 8 ° or less from the silicon surface. The side surface of the trench is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface.

  According to one embodiment of the present invention, it is possible to provide a silicon carbide semiconductor device capable of reducing forward resistance while maintaining a high breakdown voltage, and a method for manufacturing the same.

1 is a partial perspective view schematically showing a configuration of a silicon carbide semiconductor device in a first embodiment of the present invention. It is a fragmentary sectional view in area | region II-II of FIG. It is an enlarged view of the area | region III of FIG. FIG. 4 is a partial cross-sectional view in a region IV-IV in FIG. 1. It is a figure which shows the relationship between the off angle from a silicon surface, an etching rate, and donor concentration. It is a flowchart which shows schematically the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is an A surface side partial sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention. It is an A surface side partial sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention. FIG. 5 is a partial cross-sectional view on the A surface side, schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention. FIG. 7 is a partial cross sectional view on the A side showing schematically a fourth step in the method for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention. FIG. 9 is a partial cross sectional view on the A surface side schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention. It is A surface side partial sectional drawing (A) and B surface side partial sectional view (B) of the 6th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. FIG. 8 is a partial cross-sectional view (A) on the A side and a partial cross-sectional view (B) on the B side of the seventh step of the method for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention. It is A surface side partial sectional view (A) and B surface side partial sectional view (B) of the 8th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is A surface side partial sectional view (A) and B surface side partial sectional view (B) of the 9th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is a B surface side fragmentary sectional view which shows roughly the 10th process of the manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is A surface side partial sectional drawing which shows schematically the 1st process of the 1st modification of the manufacturing method of the super junction structure of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is A surface side partial sectional drawing which shows schematically the 2nd process of the 1st modification of the manufacturing method of the super junction structure of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is A surface side partial sectional drawing which shows roughly the 1st process of the 2nd modification of the manufacturing method of the super junction structure of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is A surface side partial sectional drawing which shows schematically the 2nd process of the 2nd modification of the manufacturing method of the super junction structure of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is A surface side partial sectional drawing which shows schematically the 3rd process of the 2nd modification of the manufacturing method of the super junction structure of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is a fragmentary perspective view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is a fragmentary perspective view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 4 of this invention. FIG. 10 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a fifth embodiment of the present invention. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 6 of this invention.

[Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described.

  As a result of intensive studies on measures for realizing a silicon carbide semiconductor device capable of reducing the forward resistance while maintaining a high breakdown voltage, the inventors have obtained the following knowledge and found the present invention.

  First, the inventors paid attention to the plane orientation of silicon carbide and the elements constituting the plane. In crystallography, the plane orientation of silicon carbide and the ratio of carbon and silicon in each plane orientation can be calculated theoretically. The inventors experimentally obtained the ratio of carbon and silicon in each plane orientation by actually measuring the etching rate of silicon carbide. Referring to FIG. 5, the graph shown in FIG. 5 shows the actual measured values of the etching rate of silicon carbide in each plane orientation. Silicon is less chemically reactive than carbon. For this reason, the etching rate is low on a plane having a high silicon ratio, and the etching rate is high on a plane having a high carbon ratio. A surface having an off angle of 90 ° from the Si surface is a (11-20) surface. In the plane where the off angle from the Si plane is 90 °, the silicon ratio is equal to the carbon ratio. In FIG. 5, from the measured value of the etching rate, a surface having the same etching rate as the surface having an off angle of 90 ° from the Si surface is a surface having an off angle from the Si surface of about 47 °. I understood. In other words, it was found that the carbon ratio of the surface in the range where the off angle from the Si surface is larger than about 47 ° and smaller than 90 ° is higher than that of silicon. On the other hand, it was found that the carbon ratio of the surface in the range where the off angle from the Si surface is 0 ° or more and less than about 47 ° is lower than that of silicon.

  Next, the inventor theoretically calculated the donor concentration contained in silicon carbide based on the actually measured value of the etching rate of silicon carbide. Hereinafter, a method for calculating the donor concentration contained in silicon carbide from the actually measured value of the etching rate of silicon carbide will be described.

  Compared to the carbon surface, the silicon surface has the property of easily taking in p-type impurities such as aluminum or boron. A p-type impurity is likely to enter a position of a silicon atom surrounded by carbon. The p-type impurity functions as an acceptor when the p-type impurity enters the position of the silicon atom that is not occupied. On the other hand, compared with the silicon surface, the carbon surface has a property of easily taking in n-type impurities such as nitrogen or phosphorus. An n-type impurity is likely to enter a position of a carbon atom surrounded by silicon. The n-type impurity functions as a donor when the n-type impurity enters the position of the carbon atom that is not occupied. Therefore, the silicon carbide epitaxial region formed on the surface where the silicon ratio is higher than the carbon ratio has a low donor concentration, and the silicon carbide epitaxial region formed on the surface where the silicon ratio is lower than the carbon ratio. The region is believed to have a higher donor concentration. That is, the surface with a high silicon ratio has a low etching rate and a low donor concentration. On the other hand, the surface with a high carbon ratio has a high etching rate and a high donor concentration. Based on the above concept, assuming that the etching rate graph is the same as the donor concentration, the donor concentration was obtained by theoretical calculation.

  Referring to FIG. 5, the graph shown in FIG. 5 shows the calculated value of the donor concentration contained in silicon carbide in each plane orientation.

  From the calculated value of the donor concentration, when the off angle from the Si surface is about 68 °, the donor concentration of the n-type epitaxial region shows a maximum value, and when the off angle from the Si surface is about 120 °, the n-type epitaxial region The donor concentration was found to be minimal. Further, the donor concentration of the n-type epitaxial region formed on the surface that is greater than about 47 ° and less than 90 ° from the Si surface is the donor concentration of the n-type epitaxial region formed on the surface that is 90 ° off from the Si surface. It turned out to be higher. The inventors have found from the calculated value of the donor concentration that the optimum range of the donor concentration in the n-type epitaxial region is that the off angle from the Si plane is 50 ° or more and 70 ° or less.

  (1) A silicon carbide semiconductor device according to an aspect of the present invention includes a p-type epitaxial region 3, an n-type epitaxial region 4, a semiconductor layer 2, a first electrode 16, and a second electrode 20. . The p-type epitaxial region 3 has a first main surface 3a and a second main surface 3b opposite to the first main surface 3a, a side surface connected to the first main surface 3a, a side surface, A trench having a bottom portion connected to the trench is provided and is made of silicon carbide. N-type epitaxial region 4 is in contact with p-type epitaxial region 3 at each of the side surface and the bottom of the trench and is made of silicon carbide. The semiconductor layer 2 covers both the first main surface 3a of the p-type epitaxial region 3 and the n-type epitaxial region 4. The first electrode 16 is provided on the semiconductor layer 2. The second electrode 20 is provided on the second main surface 3 b side of the p-type epitaxial region 3. First main surface 3a of p-type epitaxial region 3 is a silicon surface or a surface that is off by 8 ° or less from the silicon surface. The side surface of the trench is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface.

  According to the silicon carbide semiconductor device according to (1) above, the side surface SS of the trench TR formed in the first main surface 3a of the p-type epitaxial region 3 is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface. By forming the n-type epitaxial region 4 on the side surface SS, the n-type impurity concentration in the n-type epitaxial region 4 on the side surface SS is reduced by 90 ° from the carbon surface or silicon surface of the side surface SS of the trench TR. The concentration of the n-type impurity in the n-type epitaxial region 4 formed on the surface can be made higher. By increasing the concentration of the n-type impurity in the n-type epitaxial region 4, the concentration of the p-type impurity in the p-type epitaxial region 3 in contact with the n-type epitaxial region 4 can be increased. As a result, the p-type impurity concentration in p-type epitaxial region 3 serving as a current path is increased, so that the forward resistance of silicon carbide semiconductor device 1 can be reduced. As a result, it is possible to reduce the forward resistance while increasing the breakdown voltage of silicon carbide semiconductor device 1 with the super junction structure formed by n type epitaxial region 4 and p type epitaxial region 3.

  (2) In the silicon carbide semiconductor device according to (1), preferably, n type epitaxial region 4 includes a first n type region 4c in contact with p type epitaxial region 3 at the bottom of the trench, and a p type epitaxial region at the side of the trench. 3 and a second n-type region 4d that is in contact with 3. The second n-type region 4d has a higher impurity concentration than the first n-type region 4c. As a result, the impurity concentration in the portion of the p-type epitaxial region 3 in contact with the second n-type region 4d is increased, the forward resistance can be reduced, and a low-loss semiconductor device is obtained.

(3) Preferably, in the silicon carbide semiconductor device according to (2) above, the impurity concentration of second n-type region 4d is not less than 5 × 10 ¹⁵ cm ^{−3 and not} more than 1 × 10 ¹⁸ cm ⁻³ . The forward resistance can be reduced by setting the impurity concentration of the second n-type region 4d to 5 × 10 ¹⁵ cm ⁻³ or more. Further, by setting the impurity concentration of the second n-type region 4d to 1 × 10 ¹⁸ cm ⁻³ or less, a high withstand voltage can be maintained.

  (4) Preferably in the silicon carbide semiconductor device according to any one of (1) to (3) above, the surface of n type epitaxial region 4 in contact with semiconductor layer 2 is the first main surface 3a of p type epitaxial region 3. Is formed along the extending direction. Thereby, a switching area | region can be ensured.

  (5) In the silicon carbide semiconductor device according to any one of (1) to (4), preferably, the side surface of the trench has a first main surface in a direction perpendicular to second main surface 3b of p-type epitaxial region 3. A first side surface portion SS1 within 0.2 μm from the surface 3a, a second side surface portion SS2 within 0.2 μm from the bottom of the trench in the direction perpendicular to the second main surface 3b of the p-type epitaxial region 3, and a first It has 3rd side part SS3 which connects side part SS1 and 2nd side part SS2. The variation of the plane orientation in the third side surface portion SS3 is within 3 °. Thereby, the concentration of the electric field can be relaxed.

  (6) Preferably, the silicon carbide semiconductor device according to any one of (1) to (5) further includes a gate insulating film 15. Semiconductor layer 2 is in contact with first main surface 3a of p-type epitaxial region 3 and n-type epitaxial region 4, drift region 12 having p-type, and base region having n-type in contact with drift region 12 13 and a source region 14 which is separated from drift region 12 by base region 13 and has p-type. Gate insulating film 15 is in contact with drift region 12, base region 13, and source region 14. The first electrode 16 is in contact with the source region 14. Thereby, the forward resistance can be reduced while increasing the breakdown voltage of silicon carbide semiconductor device 1 including gate insulating film 15.

  (7) Preferably, in the silicon carbide semiconductor device according to (6) above, a gate trench GT penetrating both source region 14 and base region 13 and reaching drift region 12 is provided on the surface of semiconductor layer 2. Yes. The gate insulating film 15 is in contact with the source region 14 and the base region 13 on the side surface of the gate trench, and is in contact with the drift region 12 at the bottom of the gate trench. Thereby, it is possible to reduce the forward resistance while increasing the breakdown voltage of silicon carbide semiconductor device 1 having gate trench GT.

  (8) Preferably in the silicon carbide semiconductor device according to any one of (1) to (5) above, the conductivity type of semiconductor layer 2 is n-type. The first electrode 16 is in ohmic contact with the semiconductor layer 2. Thereby, the forward resistance can be reduced while increasing the breakdown voltage of silicon carbide semiconductor device 1 in which first electrode 16 is in ohmic contact with semiconductor layer 2.

  (9) In the silicon carbide semiconductor device according to any one of (1) to (5), preferably, the conductivity type of semiconductor layer 2 is p-type. The first electrode 16 is in Schottky junction with the semiconductor layer 2. Thereby, the forward resistance can be reduced while increasing the breakdown voltage of silicon carbide semiconductor device 1 in which first electrode 16 is in Schottky junction with semiconductor layer 2.

  (10) In the silicon carbide semiconductor device according to any one of (1) to (5), preferably, semiconductor layer 2 is formed on first main surface 3a of p-type epitaxial region 3 and n-type epitaxial region 4. A drift region 12 in contact with p-type, a base region 13 in contact with drift region 12 and having an n-type, and an emitter region 14 having a p-type and separated from drift region 12 by base region 13. Yes. The silicon carbide semiconductor device is further in contact with the second main surface 3b of the p-type epitaxial region 3 and with the n-type collector region 19, the drift region 12, the base region 13 and the emitter region 14 in gate insulation. And a film 15. The first electrode 16 is in contact with the emitter region 14, and the second electrode 20 is in contact with the collector region 19. Thereby, the forward resistance can be reduced while increasing the breakdown voltage of silicon carbide semiconductor device 1 including emitter region 14 and collector region 19.

  (11) A method for manufacturing a silicon carbide semiconductor device according to an aspect of the present invention includes the following steps. A p-type epitaxial region 3 having a first main surface 3a and a second main surface 3b opposite to the first main surface 3a and made of silicon carbide is formed. A trench having a side surface connected to first main surface 3a and a bottom portion connected to the side surface is formed in first main surface 3a of p-type epitaxial region 3. N-type epitaxial region 4 made of silicon carbide is formed in contact with p-type epitaxial region 3 on both the side and bottom of the trench. Semiconductor layer 2 is formed to cover both first main surface 3a of p-type epitaxial region 3 and n-type epitaxial region 4. A first electrode 16 in contact with the semiconductor layer 2 is formed. A second electrode 20 is formed on the second main surface 3 b side of the p-type epitaxial region 3. First main surface 3a of p-type epitaxial region 3 is a silicon surface or a surface that is off by 8 ° or less from the silicon surface. The side surface of the trench is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface.

  According to the method for manufacturing a silicon carbide semiconductor device according to (11) above, side surface SS of trench TR formed in first main surface 3a of p-type epitaxial region 3 is turned off by 50 ° or more and 70 ° or less from the silicon surface. By forming the n-type epitaxial region 4 on the side surface SS, the concentration of the n-type impurity in the n-type epitaxial region 4 on the side surface SS is changed from the carbon surface or the silicon surface to the side surface SS of the trench TR. The n-type impurity concentration of the n-type epitaxial region 4 formed on the 90 ° off surface can be made higher. By increasing the concentration of the n-type impurity in the n-type epitaxial region 4, the concentration of the p-type impurity in the p-type epitaxial region 3 in contact with the n-type epitaxial region 4 can be increased. As a result, the p-type impurity concentration in p-type epitaxial region 3 serving as a current path is increased, so that the forward resistance of silicon carbide semiconductor device 1 can be reduced. As a result, it is possible to reduce the forward resistance while increasing the breakdown voltage of silicon carbide semiconductor device 1 with the super junction structure formed by n type epitaxial region 4 and p type epitaxial region 3.

  (12) Preferably in the method for manufacturing a silicon carbide semiconductor device according to (11) above, the step of forming the trench is such that the p-type epitaxial region 3 is thermally etched in an atmosphere containing at least one of chlorine and bromine. Is done. Thereby, trench TR can be formed effectively.

  (13) Preferably in the manufacturing method of the silicon carbide semiconductor device which concerns on said (12), the temperature of thermal etching is 700 degreeC or more and 1300 degrees C or less. When the temperature of the thermal etching is less than 700 ° C., the process time becomes long because the etching rate is slow. On the other hand, when the temperature of the thermal etching is higher than 1300 ° C., the etching rate is too fast, so that it is difficult to accurately control the shape of the trench TR. By setting the temperature of the thermal etching to 700 ° C. or higher and 1300 ° C. or lower, the shape of the trench TR can be accurately controlled while shortening the process time.

  (14) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any of (11) to (13) above, the step of forming n-type epitaxial region 4 uses a raw material containing nitrogen or phosphorus that functions as a dopant. Done. Thereby, the n-type epitaxial region 4 having a high impurity concentration can be formed.

  (15) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any of (11) to (14) above, the step of forming n-type epitaxial region 4 includes the step of forming a trench, followed by p-type epitaxial region 3 N-type epitaxial region 4 including a step of forming carbon mask 33 on first main surface 3a, a first portion located on the carbon mask, a second portion in contact with a side surface of the trench, and a bottom portion of the trench. And a step of removing the first portion of the n-type epitaxial region 4 on the carbon mask while leaving the second portion of the n-type epitaxial region 4. Thereby, each of first main surface 3a of p-type epitaxial region 3 and surface 4a of n-type epitaxial region 4 can be effectively planarized.

  (16) Preferably, in the method for manufacturing the silicon carbide semiconductor device according to (15), the step of forming the carbon mask includes a step of forming a resist region on the first main surface 3a of the p-type epitaxial region 3; And carbonizing the resist region. Thereby, the carbon mask 33 can be formed efficiently.

  (17) Preferably, in the method for manufacturing a silicon carbide semiconductor device according to (15) above, the step of forming the carbon mask includes the step of forming the silicon on the first main surface 3a of the p-type epitaxial region 3 after the step of forming the trench. Is selectively etched to leave carbon. Thereby, the carbon mask 33 can be formed efficiently.

  (18) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any one of (11) to (14) above, the step of forming n-type epitaxial region 4 includes the step of forming a trench, followed by a step of forming p-type epitaxial region 3. Forming the n-type epitaxial region 4 in contact with the first main surface 3a, the side surface of the trench, and the bottom of the trench, and leaving the portion of the n-type epitaxial region 4 in contact with each of the side and bottom of the trench And chemical mechanical polishing is performed on the n-type epitaxial region 4 until the first main surface 3a is exposed. Thereby, each of first main surface 3a of p-type epitaxial region 3 and surface 4a of n-type epitaxial region 4 can be effectively planarized.

  (19) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any one of (11) to (14) above, the step of forming n-type epitaxial region 4 includes the step of forming a trench, followed by a step of forming p-type epitaxial region 3. Forming n-type epitaxial region 4 in contact with first main surface 3a, the side surface of the trench, and the bottom of the trench, forming a mask layer 32 over the entire surface of n-type epitaxial region 4, and n Etching the mask layer 32 until a part of the surface of the epitaxial region 4 is exposed, and using the mask layer 32 remaining on the surface of the n-type epitaxial region 4 until the first main surface 3a is exposed. A step of etching the epitaxial region 4 and a step of removing the mask layer 32 after etching the n-type epitaxial region 4 are included. Thereby, each of first main surface 3a of p-type epitaxial region 3 and surface 4a of n-type epitaxial region 4 can be effectively planarized.

(20) Preferably in the method for manufacturing a silicon carbide semiconductor device according to any one of (11) to (19), n-type epitaxial region 4 includes first n-type region 4c in contact with p-type epitaxial region 3 at the bottom of the trench. And a second n-type region 4d in contact with the p-type epitaxial region 3 on the side surface of the trench. The second n-type region 4d has a higher impurity concentration than the first n-type region 4c. Thereby, the impurity concentration of the portion of the p-type epitaxial region 3 in contact with the second n-type region 4d can be increased.
[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

(Embodiment 1)
First, the configuration of MOSFET as silicon carbide semiconductor device according to the first embodiment of the present invention will be described.

  Referring to FIG. 1, MOSFET 1 according to the first embodiment includes a silicon carbide substrate 10, a gate insulating film 15, a gate electrode 27, an interlayer insulating film 21, a source electrode 16 (first electrode), and a drain. It mainly has an electrode 20 (second electrode). Silicon carbide substrate 10 has a third main surface 10a and a fourth main surface 10b opposite to the third main surface 10a. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 11 constituting fourth main surface 10b, a super junction structure 5 provided on silicon carbide single crystal substrate 11, and a semiconductor provided on super junction structure 5. Layer 2 mainly. The silicon carbide single crystal is made of, for example, hexagonal silicon carbide, and preferably has polytype 4H. Silicon carbide single crystal substrate 11 has impurities such as aluminum and has p-type. Third main surface 10a of silicon carbide substrate 10 is, for example, a plane that is off by about 8 ° or less from the {0001} plane or {0001} plane, and preferably about 8 ° or less from the (0001) plane or (0001) plane. It is a surface that has been turned off.

  Referring to FIG. 2, super junction structure 5 mainly has a p-type epitaxial region 3 and an n-type epitaxial region 4. The p-type epitaxial region 3 is an epitaxial layer made of silicon carbide, and has a first main surface 3a and a second main surface 3b opposite to the first main surface 3a. P-type epitaxial region 3 contains a p-type impurity such as aluminum or boron, and has p-type conductivity. The first main surface 3a of the p-type epitaxial region 3 is provided with a trench TR having a side surface SS connected to the first main surface 3a and a bottom portion BS connected to the side surface SS. Bottom portion BS of trench TR is, for example, a plane substantially parallel to first main surface 3a. Side surface SS of trench TR is inclined with respect to bottom portion BS. N type epitaxial region 4 is an epitaxial layer made of silicon carbide, and is in contact with p type epitaxial region 3 at each of side surface SS and bottom portion BT of trench TR. N type epitaxial region 4 includes an n type impurity such as nitrogen or phosphorus, and has an n type conductivity type. Back surface 4b of n-type epitaxial region 4 is in contact with p-type epitaxial region 3 at bottom BT of trench TR. In other words, n type epitaxial region 4 is provided so as to fill the inside of trench TR. First main surface 3a of p-type epitaxial region 3 is a silicon surface or a surface that is off by 8 ° or less from the silicon surface. Side surface SS of trench TR is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface. The silicon surface is the (0001) surface. The off direction may be the <11-20> direction or the <1-100> direction.

  As shown in FIGS. 1, 2, and 4, the p-type epitaxial regions 3 and the n-type epitaxial regions 4 are alternately arranged along the direction in which the gate electrode 27 extends. That is, the longitudinal direction of each of the p-type epitaxial region 3 and the n-type epitaxial region 4 intersects the longitudinal direction of the gate electrode 27 substantially perpendicularly. A plurality of p-type epitaxial regions 3 and n-type epitaxial regions 4 are provided along the longitudinal direction of the gate electrode 27. A p-type drift region 12 is provided on the p-type epitaxial region 3. On the n-type epitaxial region 4, a connection region 17 having n-type is provided. The longitudinal direction of each of drift region 12 and connection region 17 intersects the longitudinal direction of gate electrode 27 substantially perpendicularly. A plurality of drift regions 12 and connection regions 17 are provided along the longitudinal direction of the gate electrode 27.

Next, the details of the configuration near the trench TR will be described.
Referring to FIG. 3, n-type epitaxial region 4 includes a first n-type region 4c in contact with p-type epitaxial region 3 at bottom BS of trench TR and a second n-type region in contact with p-type epitaxial region 3 on side surface SS of trench TR. Region 4d. The second n-type region 4d has a higher impurity concentration than the first n-type region 4c. The concentration of the n-type impurity included in the second n-type region 4d is, for example, not less than 5 × 10 ¹⁵ cm ^{−3 and not} more than 1 × 10 ¹⁸ cm ⁻³ . The concentration of the p-type impurity contained in the portion of the p-type epitaxial region 3 in contact with the second n-type region 4d is, for example, 5 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. The concentration of the n-type impurity included in the second n-type region 4d is substantially the same as the concentration of the p-type impurity included in the p-type epitaxial region 3. Preferably, surface 4a of n-type epitaxial region 4 in contact with connection region 17 is formed along the direction in which first main surface 3a of p-type epitaxial region 3 extends. The surface 4a of the n-type epitaxial region 4 is formed along the direction in which the first main surface 3a of the p-type epitaxial region 3 extends. It means that the distance between the surface 4a of the n-type epitaxial region 4 and the first main surface 3a of the p-type epitaxial region 3 is within 0.5 μm in the vertical direction. Surface 4 a of n type epitaxial region 4 is connected to first main surface 3 a of p type epitaxial region 3. In a cross-sectional view (a visual field viewed along a direction parallel to the second main surface 3 b), the boundary surface 3 a between the p-type epitaxial region 3 and the drift region 12 is a boundary between the n-type epitaxial region 4 and the connection region 17. It is formed along the surface 4a. In a cross-sectional view, the first n-type region 4c is provided between the second n-type region 4d and the bottom BS of the trench TR.

  In the cross-sectional view, a plurality of trenches TR are periodically provided along the longitudinal direction of the gate electrode 27. In a plan view (a visual field viewed along a direction perpendicular to the second main surface 3b), the shape of the bottom BS of each of the plurality of trenches TR is, for example, rectangular. The longitudinal direction of the bottom BS of the trench TR intersects the longitudinal direction of the gate electrode 27 substantially perpendicularly. In cross-sectional view, the pitch P of the plurality of trenches TR is, for example, not less than 1.3 μm and not more than 23 μm, and preferably not less than 8.2 μm and not more than 23 μm. In cross-sectional view, the depth H of the trench TR is, for example, not less than 0.8 μm and not more than 15 μm, and preferably not less than 1 μm and not more than 15 μm. In cross-sectional view, the width W1 of the bottom BS of the trench TR is, for example, 0.1 μm or more and 5 μm or less, and the width W2 of the opening of the trench TR is, for example, 1 μm or more and 18 μm or less.

  In cross-sectional view, the side surface SS of the trench TR has a first side surface portion SS1 within 0.2 μm from the first main surface 3a in the direction perpendicular to the second main surface 3b of the p-type epitaxial region 3, and the p-type epitaxial region. A second side surface portion SS2 within 0.2 μm from the bottom of the trench in a direction perpendicular to the second main surface 3b of the region 3, and a third side surface portion SS3 connecting the first side surface portion SS1 and the second side surface portion SS2. Have Preferably, the variation in the plane orientation in the third side surface portion SS3 is within 3 °. The variation in the plane orientation means that the difference between the portion having the maximum angle in the third side surface portion SS3 and the portion having the minimum angle in the third side surface portion SS3 is 3 ° or less in a sectional view. . For example, the cross section of the trench TR is observed by SEM (scanning electron microscope), and the angle of each region obtained by dividing the third side surface portion SS3 of the trench TR into 10 equal parts is measured with respect to the maximum value of the angle. When the value excluding the minimum value is 3 ° or less, it is determined that the variation in the plane orientation of the third side surface portion SS3 is 3 ° or less.

  With reference to FIG. 3, the relationship between the off-angle from the Si surface (silicon surface) and the donor concentration in the n-type epitaxial region will be described.

  As described above, the relationship between the off-angle from the Si surface (silicon surface) and the donor concentration in the n-type epitaxial region is considered to be a curve indicated by a solid line. That is, the n-type impurity concentration (that is, donor concentration) in the n-type epitaxial region has a minimum value when the off angle is 0 ° (that is, Si surface), and has a maximum value when the off angle is about 68 °. When the off angle is larger than about 68 °, the concentration of the n-type impurity is reduced, and shows a minimum value when the off angle is about 120 °. When the off angle is larger than about 120 °, the concentration of the n-type impurity increases, and shows a maximum value when the off angle is 180 ° (that is, the C plane). When the off angle from the Si surface is about 68 °, the carbon ratio is higher than the silicon ratio, and when the off angle from the Si surface is about 120 °, the carbon ratio is higher than the silicon ratio. Low. When the off angle from the Si plane is 90 °, in other words, in the case of the (11-20) plane, the silicon ratio is the same as the carbon ratio.

  As shown in FIG. 5, the side surface SS of the trench TR formed in the first main surface 3a of the p-type epitaxial region 3 is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface, and n on the side surface SS. By forming the type epitaxial region 4, the n type impurity concentration of the n type epitaxial region 4 on the side surface SS is formed on the surface where the side surface SS of the trench TR is 90 ° off from the carbon surface or the silicon surface. The concentration of the n-type impurity in the type epitaxial region 4 can be made higher. Preferably, side surface SS of trench TR is a surface turned off by 55 ° or more and 70 ° or less from the silicon surface, and more preferably a surface turned off by 60 ° or more and 70 ° or less from the carbon surface.

Referring to FIGS. 1, 2, and 4 again, semiconductor layer 2 covers both first main surface 3 a of p-type epitaxial region 3 and n-type epitaxial region 4. Specifically, the semiconductor layer 2 is in contact with the first main surface 3 a of the p-type epitaxial region 3 and the surface 4 a of the n-type epitaxial region 4. The semiconductor layer 2 includes a drift region 12 having p-type, a base region 13 in contact with the drift region 12 and having n-type, and a source region 14 having p-type and separated from the drift region 12 by the base region 13. And a connection region 17 having an n-type. Drift region 12 is in contact with first main surface 3 a of p type epitaxial region 3. Drift region 12 is a p-type impurity region containing a p-type impurity such as aluminum. The impurity concentration of drift region 12 is preferably lower than the impurity concentration of silicon carbide single crystal substrate 11. The concentration of p-type impurities such as aluminum included in drift region 12 is, for example, 3 × 10 ¹⁵ cm ⁻³ or more and 2 × 10 ¹⁶ cm ⁻³ or less. The thickness of drift region 12 is, for example, about 15 μm.

  As shown in FIG. 2, drift region 12 has a region sandwiched between gate insulating film 15 and p type epitaxial region 3. As shown in FIG. 4, drift region 12 has a region sandwiched between base region 13 and p type epitaxial region 3. Connection region 17 is an n-type impurity region containing an n-type impurity such as nitrogen. As shown in FIG. 2, connection region 17 has a region sandwiched between gate insulating film 15 and n-type epitaxial region 4. As shown in FIG. 1, connection region 17 has a region sandwiched between contact region 18 and n-type epitaxial region 4. That is, the connection region 17 electrically connects the contact region 18 and the n-type epitaxial region 4. As a result, the n-type epitaxial region 4 is electrically connected to the source electrode 16.

Base region 13 is an n-type impurity region containing an n-type impurity such as phosphorus. The base region 13 is provided on the drift region 12. The concentration of n-type impurities such as phosphorus included in the base region 13 may be higher than the concentration of p-type impurities such as aluminum included in the drift region 12. The concentration of n-type impurities such as phosphorus included in the base region 13 is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less.

Source region 14 is a p-type impurity region containing a p-type impurity such as aluminum. The source region 14 is provided on the base region 13 so as to be separated from the drift region 12 by the base region 13. The concentration of the p-type impurity such as aluminum included in the source region 14 is, for example, 1 × 10 ¹⁹ cm ⁻³ or more and 2 × 10 ²⁰ cm ⁻³ or less. Contact region 18 is an n-type impurity region containing an n-type impurity such as phosphorus. The contact region 18 passes through the source region 14 and is connected to the base region 13. The impurity concentration of the contact region 18 is higher than the impurity concentration of the base region 13. The concentration of n-type impurities such as phosphorus included in the contact region 18 is, for example, 5 × 10 ¹⁸ cm ⁻³ or more and 2 × 10 ²⁰ cm ⁻³ or less. Each of source region 14 and contact region 18 constitutes third main surface 10a of silicon carbide substrate 10.

  A gate trench GT that penetrates both the source region 14 and the base region 13 and reaches the drift region 12 is provided on the surface of the semiconductor layer 2 (that is, the third main surface 10a of the silicon carbide substrate 10). Gate trench GT is connected to third main surface 10a of silicon carbide substrate 10, side surface SW that penetrates source region 14 and base region 13 to drift region 12, and bottom portion BT located in drift region 12. And have. The gate insulating film 15 is in contact with the source region 14, the base region 13, and the drift region 12 on the side surface SW of the gate trench GT, and is in contact with the drift region 12 at the bottom of the gate trench. On the base region 13 in contact with the side surface SW, the channel CH (see FIG. 4) of the MOSFET 1 is formed. Side SW may be perpendicular to third main surface 10a of silicon carbide substrate 10 or may be inclined.

  The gate insulating film 15 is in contact with the drift region 12, the base region 13, and the source region 14 on the side surface SW of the gate trench GT, and is in contact with the drift region 12 at the bottom BT of the gate trench GT. Gate insulating film 15 includes, for example, silicon dioxide.

  The gate electrode 27 is provided on the gate insulating film 15 inside the gate trench GT. The gate electrode 27 is in contact with each of the source region 14, the base region 13, and the drift region 12 through the gate insulating film 15. The gate electrode 27 is made of a conductive material such as polysilicon containing impurities.

  The source electrode 16 is provided on the semiconductor layer 2. Specifically, source electrode 16 is in contact with source region 14 and contact region 18 on third main surface 10a of silicon carbide substrate 10. The source electrode 16 includes, for example, TiAlSi. The source electrode 16 is preferably in ohmic contact with each of the source region 14 and the contact region 18 of the semiconductor layer 2. The interlayer insulating film 21 is in contact with the gate insulating film 15 and the gate electrode 27 so as to cover the gate trench GT. The interlayer insulating film 21 insulates between the gate electrode 27 and the source electrode 16. The drain electrode 20 is provided on the second main surface 3 b side of the p-type epitaxial region 3. Specifically, drain electrode 20 is in contact with silicon carbide single crystal substrate 11 at fourth main surface 10 b of silicon carbide substrate 10. The drain electrode 20 is made of a material containing, for example, TiAlSi. Drain electrode 20 is preferably in ohmic contact with n-type silicon carbide single crystal substrate 11.

  Note that side surface SS of trench TR may penetrate p type epitaxial region 3 and reach silicon carbide single crystal substrate 11. In this case, bottom portion BS of trench TR is located on silicon carbide single crystal substrate 11. When side surface SS of trench TR reaches silicon carbide single crystal substrate 11, drift region 12 is electrically connected to silicon carbide single crystal substrate 11 through n type epitaxial region 4. In this case, silicon carbide single crystal substrate 11, drift region 12, and source region 14 have n-type conductivity, and base region 13 and contact region 18 have p-type conductivity. You may do it.

  Next, a method for manufacturing MOSFET 1 as the silicon carbide semiconductor device according to the first embodiment of the present invention will be described. In addition, in description of a figure, A surface side partial sectional drawing means the partial sectional view by the side of A surface of FIG. 1, B surface side partial sectional drawing is a partial cross section by the side of B surface of FIG. Means the figure.

  First, a p-type epitaxial region forming step (S10: FIG. 6) is performed. Referring to FIG. 7, silicon carbide single crystal substrate 11 having an upper surface and a lower surface is prepared. The upper surface preferably has an off angle of 8 ° or less from the {0001} plane, and more preferably has an off angle of 4 ° or less. In this case, the {0001} plane is more preferably a (0001) plane. Silicon carbide single crystal substrate 11 is made of, for example, a hexagonal silicon carbide single crystal having polytype 4H.

Next, p type epitaxial region 3 is formed on the upper surface of silicon carbide single crystal substrate 11 by epitaxial growth. The p-type epitaxial region 3 is formed by, for example, a CVD (Chemical Vapor Deposition) method. As the source gas, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) can be used. In epitaxial growth, a p-type epitaxial region 3 made of silicon carbide is formed by introducing a p-type impurity such as aluminum (Al) or boron (B) into silicon carbide. Thus, p type epitaxial region 3 having first main surface 3a and second main surface 3b opposite to first main surface 3a and made of silicon carbide is formed. Second main surface 3 b of p type epitaxial region 3 is in contact with the upper surface of silicon carbide single crystal substrate 11.

  Next, a trench formation step (S20: FIG. 6) is performed. For example, etching mask 30 having an opening is formed on first main surface 3 a of p-type epitaxial region 3. Referring to FIG. 8, a plurality of etching masks 30 are periodically provided at regular intervals in a sectional view. The etching mask 30 can be formed, for example, by forming a silicon oxide film by thermally oxidizing the first main surface 3a of the p-type epitaxial region 3, and then patterning the silicon oxide film.

Next, etching having a physical action is performed on the first main surface 3a of the p-type epitaxial region 3 provided with the etching mask 30. Thereby, in the opening of the etching mask 30, a part of the p-type epitaxial region 3 is removed by etching, whereby a recess is formed in the first main surface 3a. The recess has a side wall surface substantially perpendicular to the first main surface 3a and a bottom surface substantially parallel to the first main surface 3a. As the etching having a physical action, reactive ion etching (RIE) is preferable, and inductively coupled plasma (ICP) RIE is more preferable. As a reactive gas for RIE, SF ₆ or a mixed gas of SF ₆ and O ₂ can be used.

  Next, thermal etching is performed on the first main surface 3a of the p-type epitaxial region 3 in which the etching mask 30 is provided and the recess is formed. For example, the first main surface 3a of the p-type epitaxial region 3 is thermally etched using a halogen gas such as chlorine gas or bromine gas. Thereby, a trench TR having a side surface SS connected to the first main surface 3a and a bottom portion BS connected to the side surface SS is formed (see FIG. 9). Bottom portion BS of trench TR may be located in p type epitaxial region 3 or may be located in silicon carbide single crystal substrate 11. When bottom portion BS of trench TR is located in silicon carbide single crystal substrate 11, trench TR is formed so as to penetrate p type epitaxial region 3. Preferably, trench TR is formed by thermally etching p type epitaxial region 3 in an atmosphere containing at least one of chlorine and bromine. Preferably, in a cross-sectional view, a plurality of trenches TR are formed periodically with a constant interval. In cross-sectional view, the pitch P of the plurality of trenches TR is, for example, not less than 1.3 μm and not more than 23 μm. In a cross-sectional view, the depth H of the trench TR is, for example, 7 μm or more and 15 μm or less (see FIG. 3). First main surface 3a of p-type epitaxial region 3 is a silicon surface or a surface off by 8 ° or less from the silicon surface, and preferably a surface off by 4 ° or less from the silicon surface. Side surface SS of trench TR is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface. Preferably, side surface SS of trench TR is a surface turned off by 55 ° or more and 70 ° or less from the carbon surface, and more preferably a surface turned off by 60 ° or more and 70 ° or less from the carbon surface.

  The gas used for the thermal etching may contain oxygen gas in addition to chlorine gas or bromine gas, and may further contain a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas, helium gas or the like can be used. For example, in a mixed gas atmosphere of chlorine gas and oxygen gas, first main surface 3a of p type epitaxial region 3 is thermally etched at 800 ° C., for example. Preferably, the temperature of the p-type epitaxial region 3 in the thermal etching is 700 ° C. or higher and 1300 ° C. or lower.

Next, an n-type epitaxial region forming step (S30: FIG. 6) is performed. Referring to FIG. 10, n type epitaxial region 4 is formed to be in contact with first main surface 3a of p type epitaxial region 3 and to fill trench TR. In a cross-sectional view, the surface 4a of the n-type epitaxial region 4 periodically changes in height so as to be higher on the first main surface 3a of the p-type epitaxial region 3 and lower on the bottom BS of the trench TR. You may do it. N type epitaxial region 4 is formed by, for example, a CVD method. As the source gas, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) can be used. In epitaxial growth, n-type epitaxial region 4 is formed by introducing n-type impurities such as nitrogen (N) or phosphorus (P) into silicon carbide. That is, the step of forming the n-type epitaxial region 4 is performed using a raw material containing nitrogen or phosphorus that functions as a dopant. The raw material containing nitrogen or phosphorus may be a liquid phase or a gas phase. The raw material containing nitrogen or phosphorus is, for example, ammonia (NH ₃ ) or phosphine (PH ₃ ).

  Next, a planarization process is performed. For example, the surface 4a of the n-type epitaxial region 4 is planarized by performing chemical mechanical polishing (CMP) on the surface 4a of the n-type epitaxial region 4. A portion of n-type epitaxial region 4 is removed until first main surface 3a of p-type epitaxial region 3 is exposed. A part of the p-type epitaxial region 3 may be removed together with the n-type epitaxial region 4. Thereby, each of first main surface 3a of p type epitaxial region 3 and surface 4a of n type epitaxial region 4 is planarized (see FIG. 11). Surface 4a of n-type epitaxial region 4 is formed along the direction in which first main surface 3a of p-type epitaxial region 3 extends. As described above, after the step of forming trench TR, n-type epitaxial region 4 in contact with first main surface 3a of p-type epitaxial region 3, side surface SS of trench TR, and bottom portion BS of trench TR is formed. After that, with respect to the n-type epitaxial region 4 until the first main surface 3a of the p-type epitaxial region 3 is exposed, leaving a portion of the n-type epitaxial region 4 in contact with each of the side surface SS and the bottom BS of the trench TR. Chemical mechanical polishing is performed. Thereby, n type epitaxial region 4 made of silicon carbide is formed in contact with p type epitaxial region 3 on both side surface SS and bottom portion BS of trench TR.

As shown in FIG. 3, the n-type epitaxial region 4 includes a first n-type region 4c in contact with the p-type epitaxial region 3 at the bottom BS of the trench TR and a second n-type region in contact with the p-type epitaxial region 3 at the side surface SS of the trench TR. Region 4d. The second n-type region 4d has a higher impurity concentration than the first n-type region 4c. That is, the concentration of the n-type impurity such as nitrogen contained in the second n-type region 4d is higher than the concentration of the n-type impurity such as nitrogen contained in the first n-type region 4c. Preferably, the impurity concentration of the second n-type region 4d is not less than 5 × 10 ¹⁵ cm ^{−3 and not} more than 1 × 10 ¹⁸ cm ⁻³ . As described above, the super junction structure 5 in which the p-type epitaxial regions 3 and the n-type epitaxial regions 4 are alternately arranged along the direction parallel to the second main surface 3b of the p-type epitaxial region 3 in a cross-sectional view. Is formed.

Next, a semiconductor layer forming step (S40: FIG. 6) is performed. The semiconductor layer 2 is formed so as to cover both the first main surface 3 a of the p-type epitaxial region 3 and the surface 4 a of the n-type epitaxial region 4. Specifically, it is formed by, for example, a CVD method. As the source gas, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) can be used. In epitaxial growth, a p-type impurity such as aluminum (Al) or boron (B) is introduced into silicon carbide, so that drift region 12 made of silicon carbide and having p-type is formed. Referring to FIGS. 12A and 12B, drift region 12 is formed to cover both first main surface 3a of p-type epitaxial region 3 and surface 4a of n-type epitaxial region 4. The

  Next, the connection region 17 is formed. Referring to FIGS. 13A and 13B, for example, a portion of drift region 12 on first main surface 3a of p-type epitaxial region 3 is covered, and an opening is formed on surface 4a of n-type epitaxial region 4. An ion implantation mask (not shown) is provided. An n-type impurity such as phosphorus is ion-implanted into the drift region 12 using the ion implantation mask. Thereby, a connection region 17 is formed on the surface 4a of the n-type epitaxial region 4. Drift region 12 is left on first main surface 3 a of p-type epitaxial region 3.

  Next, the base region 13 is formed. Referring to FIGS. 14A and 14B, base region 13 having n-type is formed while n-type impurities such as nitrogen are introduced into silicon carbide by, for example, epitaxial growth. Base region 13 is formed to cover both drift region 12 and connection region 17.

  Next, the source region 14 is formed. For example, a p-type impurity such as aluminum is ion-implanted into the entire surface of base region 13 to form source region 14 in contact with base region 13. Source region 14 constitutes third main surface 10a of silicon carbide substrate 10. Note that the source region 14 may be formed by using epitaxial growth with addition of impurities instead of ion implantation.

  Next, the contact region 18 is formed. Referring to FIGS. 15A and 15B, for example, an n-type impurity such as phosphorus is ion-implanted into a part of the surface of source region 14 so that source region 14 and base region 13 are A contact region 18 is formed in contact with the connection region 17 through each of them. Contact region 18 may be formed in contact with drift region 12.

  Next, activation annealing for activating the impurities implanted into the semiconductor layer 2 is performed. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere. As described above, the p-type drift region 12, the n-type base region 13 provided on the drift region 12, the p-type source region 14 provided on the base region 13, and the source region 14 are penetrated. Thus, the semiconductor layer 2 is formed which is in contact with the base region 13 and includes an n-type contact region. Source region 14 and contact region 18 constitute third main surface 10a of silicon carbide substrate 10.

  Next, a gate trench formation step is performed. For example, etching mask 31 having an opening is formed on third main surface 10a of silicon carbide substrate 10. The opening is formed corresponding to the position of the gate trench GT (FIG. 1). Referring to FIG. 11, etching mask 31 is formed in contact with contact region 18 and source region 14 on third main surface 10a. Etching mask 31 can be formed, for example, by forming a silicon oxide film by thermally oxidizing third main surface 10a of silicon carbide substrate 10 and then patterning the silicon oxide film.

Next, etching having a physical action is performed on third main surface 10a of silicon carbide substrate 10 provided with etching mask 31. As a result, the source region 14, the base region 13, and a part of the connection region 17 of the drift region 12 are removed by etching in the opening of the etching mask 31, so that a gate trench is formed in the third main surface 10 a. A GT is formed (see FIG. 16). Gate trench GT has a side surface SW substantially perpendicular to third main surface 10a and a bottom portion BT substantially parallel to third main surface 10a. As the etching having a physical action, reactive ion etching (RIE) is preferable, and inductively coupled plasma (ICP) RIE is more preferable. As a reactive gas for RIE, SF ₆ or a mixed gas of SF ₆ and O ₂ can be used.

  Next, a gate oxide film forming step is performed. Gate insulating film 15 is formed to cover third main surface 10a of silicon carbide substrate 10 and each of side surface SW and bottom portion BT of gate trench GT. More specifically, the gate insulating film 15 is formed on the side surface SW of the gate trench GT, in contact with the drift region 12, the base region 13, and the source region 14, and in contact with the drift region 12 at the bottom BT of the gate trench GT. The The gate insulating film 15 is formed by, for example, thermal oxidation. Preferably, by oxidizing silicon carbide substrate 10 at 1300 ° C. or lower, gate insulating film 15 is formed in contact with each of side surface SW and bottom portion BT of gate trench GT. The gate insulating film 15 may be in contact with the connection region 17 on each of the side surface SW and the bottom portion BT of the gate trench GT.

  After the gate oxide film is formed, NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed. The temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between the gate insulating film 15 and the base region 13. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate insulating film 15. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between the gate insulating film 15 and the base region 13 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

  Next, a gate electrode formation step is performed. Referring to FIG. 1, gate electrode 27 is formed on gate insulating film 15. For example, the gate electrode 27 is formed by depositing a conductor or impurity doped polysilicon on the gate insulating film 15. Gate electrode 27 is formed to fill the inside of trench TR. Next, the interlayer insulating film 21 is formed on the gate electrode 27 and the gate insulating film 15. Next, etching is performed so that an opening is formed in the interlayer insulating film 21. Through the opening, source region 14 and contact region 18 are exposed from interlayer insulating film 21 on third main surface 10a of silicon carbide substrate 10.

  Next, a first electrode formation step (S50: FIG. 6) is performed. Referring to FIG. 1, a first electrode (source electrode 16) in contact with semiconductor layer 2 is formed. Specifically, source electrode 16 in contact with source region 14 and contact region 18 is formed on third main surface 10a of silicon carbide substrate 10. The source electrode 16 is made of a material containing, for example, TiAlSi. Next, silicon carbide substrate 10 on which source electrode 16 is formed is heated to about 1000 ° C., for example, so that source electrode 16 is in ohmic contact with source region 14 of silicon carbide substrate 10.

  Next, a second electrode formation step (S60: FIG. 6) is performed. A second electrode (drain electrode 20) is formed on the second main surface 3b side of the p-type epitaxial region 3. Specifically, drain electrode 20 made of, for example, a material containing TiAlSi is formed on fourth main surface 10b of silicon carbide single crystal substrate 11. Next, drain electrode 20 that is in ohmic contact with silicon carbide single crystal substrate 11 is formed by heating drain electrode 20 by laser annealing, for example. Thus, the manufacture of MOSFET 1 shown in FIG. 1 is completed.

Next, a first modification of the method for manufacturing the super junction structure 5 will be described.
First, as shown in FIG. 9, a trench TR having a side surface SS connected to the third main surface 10a of the p-type epitaxial region 3 and a bottom portion BS connected to the side surface SS is formed by thermal etching. Next, the etching mask 30 is removed by an arbitrary method.

  Next, a carbon mask 33 is formed on first main surface 3 a of p type epitaxial region 3. For example, a resist region is first formed on the entire surface of p type epitaxial region 3. The resist region is formed to be in contact with first main surface 3a of p-type epitaxial region 3, each of side surface SS and bottom portion BT of trench TR, and fill trench TR. Next, patterning is performed on the resist region. For example, a resist region on the first main surface 3a of the p-type epitaxial region 3 is left by selectively removing a portion of the resist region formed in the trench TR. Next, the resist region formed on the first main surface 3a of the p-type epitaxial region 3 is carbonized. Thereby, a carbon mask 33 is formed on the first main surface 3a of the p-type epitaxial region 3 (see FIG. 17). Carbon mask 33 may be formed by selectively etching silicon on first main surface 3a of p-type epitaxial region 3 to leave carbon after forming trench TR. For example, the first main surface 3a of the p-type epitaxial region 3 is selectively etched by performing thermal etching on the p-type epitaxial region 3 having the trench TR formed in the first main surface 3a. Then, a carbon layer in contact with the side surface SS of the trench TR and the bottom portion BS of the trench TR is formed. Next, a carbon mask 33 is formed on first main surface 3a of p type epitaxial region 3 by selectively removing the carbon layer in contact with side surface SS and bottom portion BS of trench TR, for example, by RIE. It is also possible (see FIG. 17).

Next, an n-type epitaxial region forming step (S30: FIG. 6) is performed. N type epitaxial region 4 is formed by, for example, a CVD method. As the source gas, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) can be used. In epitaxial growth, n-type epitaxial region 4 is formed by introducing n-type impurities such as nitrogen (N) or phosphorus (P) into silicon carbide. Referring to FIG. 18, n type epitaxial region 4 includes a first portion 4e located on carbon mask 33, a side portion SS of trench TR, and a second portion 4f in contact with bottom portion BS of trench TR. Second portion 4f of n-type epitaxial region 4 is formed so as to fill the inside of trench TR.

  Next, an intermediate substrate in which the first portion 4e of the n-type epitaxial region 4 is formed on the carbon mask 33 and the second portion 4f of the n-type epitaxial region 4 is formed in the trench TR is an oxidation furnace (not shown). ). In the oxidation furnace, the carbon mask 33 is baked to carbon dioxide, so that the first portion 4e of the n-type epitaxial region 4 on the carbon mask 33 together with the carbon mask 33 becomes the first main surface of the p-type epitaxial region 3. 3a is removed from above. That is, by oxidizing the carbon mask 33 at a high temperature, the first portion 4e of the n-type epitaxial region 4 on the carbon mask 33 is removed while leaving the second portion 4f of the n-type epitaxial region 4 inside the trench TR. The As described above, as shown in FIG. 11, n-type epitaxial region 4 is arranged inside trench TR formed in first main surface 3 a of p-type epitaxial region 3, and first type of p-type epitaxial region 3 is arranged. N type epitaxial region 4 is formed such that main surface 3a is exposed from n type epitaxial region 4.

Next, a second modification of the method for manufacturing the super junction structure 5 will be described.
First, referring to FIG. 10, after trench TR is formed in first main surface 3a of p-type epitaxial region 3, it is in contact with first main surface 3a of p-type epitaxial region 3, and trench TR is filled. Thus, n type epitaxial region 4 in contact with side surface SS of trench TR and bottom portion BS of trench TR is formed. In a cross-sectional view, the surface 4a of the n-type epitaxial region 4 periodically changes in height so as to be higher on the first main surface 3a of the p-type epitaxial region 3 and lower on the bottom BS of the trench TR. You may do it. N type epitaxial region 4 is formed by, for example, a CVD method. As the source gas, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) can be used. In epitaxial growth, n-type epitaxial region 4 is formed by introducing n-type impurities such as nitrogen (N) or phosphorus (P) into silicon carbide. That is, the step of forming the n-type epitaxial region 4 is performed using a raw material containing nitrogen or phosphorus that functions as a dopant.

  Next, referring to FIG. 19, mask layer 32 is formed on the entire surface 4 a of n type epitaxial region 4. The mask layer 32 is a resist, for example. Next, the entire surface of the mask layer 32 is etched. Mask layer 32 is etched until part of surface 4a of n-type epitaxial region 4 is exposed. Thereby, the portion of mask layer 32 located above first main surface 3a of p-type epitaxial region 3 is removed, and the portion of mask layer 32 located above bottom portion BS of trench TR is left (FIG. 20). reference).

  Next, referring to FIG. 21, n-type epitaxial region 4 is formed using mask layer 32 remaining on surface 4 a of n-type epitaxial region 4 until first main surface 3 a of p-type epitaxial region 3 is exposed. Etched. Thereby, the portion of n type epitaxial region 4 on first main surface 3a of p type epitaxial region 3 is removed. A part of the n-type epitaxial region 4 directly under the mask layer 32 may be removed by the etching. After the n-type epitaxial region 4 is etched, the mask layer 32 is removed from the surface 4 a of the n-type epitaxial region 4. As described above, as shown in FIG. 9, n-type epitaxial region 4 is arranged inside trench TR formed in first main surface 3 a of p-type epitaxial region 3, and first type of p-type epitaxial region 3 is provided. N type epitaxial region 4 is formed such that main surface 3a is exposed from n type epitaxial region 4.

  Next, functions and effects of the silicon carbide semiconductor device and the method for manufacturing the same according to the first embodiment will be described.

  According to MOSFET 1 according to the first embodiment, side surface SS of trench TR formed in first main surface 3a of p-type epitaxial region 3 is a surface off from 50 ° to 70 ° from the silicon surface. By forming the n-type epitaxial region 4 on the SS, the concentration of the n-type impurity in the n-type epitaxial region 4 on the side surface SS is reduced on the surface where the side surface SS of the trench TR is 90 ° off from the carbon surface or the silicon surface. The concentration of the n-type impurity in the n-type epitaxial region 4 formed in the above can be made higher. By increasing the concentration of the n-type impurity in the n-type epitaxial region 4, the concentration of the p-type impurity in the p-type epitaxial region 3 in contact with the n-type epitaxial region 4 can be increased. As a result, the p-type impurity concentration in p-type epitaxial region 3 serving as a current path is increased, so that the forward resistance of silicon carbide semiconductor device 1 can be reduced. As a result, it is possible to reduce the forward resistance while increasing the breakdown voltage of the MOSFET 1 with the super junction structure formed by the n-type epitaxial region 4 and the p-type epitaxial region 3.

  According to MOSFET 1 according to the first embodiment, n-type epitaxial region 4 includes first n-type region 4c in contact with p-type epitaxial region 3 at bottom BS of trench TR, and p-type epitaxial region 3 at side surface SS of trench TR. And a second n-type region 4d in contact with. The second n-type region 4d has a higher impurity concentration than the first n-type region 4c. As a result, the impurity concentration in the portion of the p-type epitaxial region 3 in contact with the second n-type region 4d is increased, the forward resistance can be reduced, and the MOSFET 1 has a low loss.

Furthermore, according to MOSFET 1 according to the first embodiment, the impurity concentration of second n-type region 4d is not less than 5 × 10 ¹⁵ cm ^{−3 and not} more than 1 × 10 ¹⁸ cm ⁻³ . The forward resistance can be reduced by setting the impurity concentration of the second n-type region 4d to 5 × 10 ¹⁵ cm ⁻³ or more. Further, by setting the impurity concentration of the second n-type region 4d to 1 × 10 ¹⁸ cm ⁻³ or less, a high withstand voltage can be maintained.

  Furthermore, according to MOSFET 1 according to the first embodiment, the surface of n type epitaxial region 4 in contact with semiconductor layer 2 is formed along the direction in which first main surface 3a of p type epitaxial region 3 extends. . Thereby, a switching area | region can be ensured.

  Furthermore, according to MOSFET 1 according to the first embodiment, the side surface of the trench is a first side surface portion within 0.2 μm from first main surface 3a in the direction perpendicular to second main surface 3b of p-type epitaxial region 3. SS1, the second side surface portion SS2 within 0.2 μm from the bottom of the trench in the direction perpendicular to the second main surface 3b of the p-type epitaxial region 3, and the first side surface portion SS1 and the second side surface portion SS2 are connected. And a third side surface portion SS3. The variation of the plane orientation in the third side surface portion SS3 is within 3 °. Thereby, the concentration of the electric field can be relaxed.

  Further, the MOSFET 1 according to the first embodiment further includes the gate insulating film 15. Semiconductor layer 2 is in contact with first main surface 3a of p-type epitaxial region 3 and n-type epitaxial region 4, drift region 12 having p-type, and base region having n-type in contact with drift region 12 13 and a source region 14 which is separated from drift region 12 by base region 13 and has p-type. Gate insulating film 15 is in contact with drift region 12, base region 13, and source region 14. The first electrode 16 is in contact with the source region 14. Thereby, the forward resistance can be reduced while increasing the breakdown voltage of silicon carbide semiconductor device 1 including gate insulating film 15.

  Furthermore, according to MOSFET 1 according to the first embodiment, the surface of semiconductor layer 2 is provided with gate trench GT that penetrates both source region 14 and base region 13 and reaches drift region 12. The gate insulating film 15 is in contact with the source region 14 and the base region 13 on the side surface of the gate trench, and is in contact with the drift region 12 at the bottom of the gate trench. Thereby, it is possible to reduce the forward resistance while increasing the breakdown voltage of silicon carbide semiconductor device 1 having gate trench GT.

  According to the method for manufacturing MOSFET 1 according to the first embodiment, side surface SS of trench TR formed in first main surface 3a of p-type epitaxial region 3 is a surface that is off by 50 ° or more and 70 ° or less from the silicon surface. By forming the n-type epitaxial region 4 on the side surface SS, the n-type impurity concentration in the n-type epitaxial region 4 on the side surface SS is reduced by 90 ° from the carbon surface or silicon surface of the side surface SS of the trench TR. The concentration of the n-type impurity in the n-type epitaxial region 4 formed on the surface can be made higher. By increasing the concentration of the n-type impurity in the n-type epitaxial region 4, the concentration of the p-type impurity in the p-type epitaxial region 3 in contact with the n-type epitaxial region 4 can be increased. As a result, the p-type impurity concentration in p-type epitaxial region 3 serving as a current path is increased, so that the forward resistance of silicon carbide semiconductor device 1 can be reduced. As a result, it is possible to reduce the forward resistance while increasing the breakdown voltage of silicon carbide semiconductor device 1 with the super junction structure formed by n type epitaxial region 4 and p type epitaxial region 3.

  Further, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming the trench is performed by thermally etching p type epitaxial region 3 in an atmosphere containing at least one of chlorine and bromine. Thereby, trench TR can be formed effectively.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the temperature of thermal etching is 700 ° C. or higher and 1300 ° C. or lower. When the temperature of the thermal etching is less than 700 ° C., the process time becomes long because the etching rate is slow. On the other hand, when the temperature of the thermal etching is higher than 1300 ° C., the etching rate is too fast, so that it is difficult to accurately control the shape of the trench TR. By setting the temperature of the thermal etching to 700 ° C. or higher and 1300 ° C. or lower, the shape of the trench TR can be accurately controlled while shortening the process time.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming n-type epitaxial region 4 is performed using a raw material containing nitrogen or phosphorus that functions as a dopant. Thereby, the n-type epitaxial region 4 having a high impurity concentration can be formed.

  Furthermore, according to the method of manufacturing MOSFET 1 according to the first embodiment, the step of forming n-type epitaxial region 4 includes the step of forming a carbon mask 33 on first main surface 3a of p-type epitaxial region 3 after the step of forming a trench. Forming an n-type epitaxial region 4 including a step of forming, a first portion located on the carbon mask, a second portion in contact with a side surface of the trench, and a bottom of the trench; Removing the first portion of the n-type epitaxial region 4 on the carbon mask while leaving the second portion. Thereby, each of first main surface 3a of p-type epitaxial region 3 and surface 4a of n-type epitaxial region 4 can be effectively planarized.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming the carbon mask includes the step of forming a resist region on first main surface 3a of p-type epitaxial region 3, and carbonizing the resist region. Process. Thereby, the carbon mask 33 can be formed efficiently.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming the carbon mask selectively etches silicon on first main surface 3a of p type epitaxial region 3 after the step of forming the trench. This is done by leaving carbon. Thereby, the carbon mask 33 can be formed efficiently.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming n-type epitaxial region 4 includes the step of forming the trench, the first main surface 3a of p-type epitaxial region 3, and the side surface of the trench. And a step of forming n-type epitaxial region 4 in contact with the bottom of the trench, and a portion of n-type epitaxial region 4 in contact with each of the side and bottom of the trench, while leaving the first main surface 3a exposed. A step of performing chemical mechanical polishing on the mold epitaxial region 4. Thereby, each of first main surface 3a of p-type epitaxial region 3 and surface 4a of n-type epitaxial region 4 can be effectively planarized.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming n-type epitaxial region 4 includes the step of forming the trench, the first main surface 3a of p-type epitaxial region 3, and the side surface of the trench. A step of forming n-type epitaxial region 4 in contact with the bottom of the trench, a step of forming mask layer 32 on the entire surface of n-type epitaxial region 4, and a part of the surface of n-type epitaxial region 4 is exposed. Etching the mask layer 32 until the first main surface 3a is exposed using the mask layer 32 remaining on the surface of the n-type epitaxial region 4, and n-type epitaxial And a step of removing the mask layer 32 after etching the region 4. Thereby, each of first main surface 3a of p-type epitaxial region 3 and surface 4a of n-type epitaxial region 4 can be effectively planarized.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, n-type epitaxial region 4 includes first n-type region 4c in contact with p-type epitaxial region 3 at the bottom of the trench, and p-type epitaxial region 3 on the side of the trench. And a second n-type region 4d in contact therewith. The second n-type region 4d has a higher impurity concentration than the first n-type region 4c. Thereby, the impurity concentration of the portion of the p-type epitaxial region 3 in contact with the second n-type region 4d can be increased.

(Embodiment 2)
Next, the structure of MOSFET as a silicon carbide semiconductor device according to the second embodiment of the present invention will be described. The MOSFET according to the second embodiment differs from the MOSFET according to the first embodiment mainly in that the side surface SW of the gate trench GT is inclined with respect to the bottom BT, and the other structures are the same as in the first embodiment. This is almost the same as the MOSFET according to FIG. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. The following description will focus on differences from the MOSFET structure according to the first embodiment.

  Referring to FIG. 22, side surface SW of gate trench GT is inclined with respect to bottom portion BT. An angle formed between the side surface SW of the gate trench GT and a surface parallel to the bottom portion BT is, for example, 50 ° to 70 °. The side surface SW of the gate trench GT may be a surface that is off by 50 ° or more and 70 ° or less with respect to the <11-20> direction from the carbon surface. Gate insulating film 15 is in contact with source region 14 on third main surface 10a of silicon carbide substrate 10, and is in contact with source region 14, base region 13, and drift region 12 on side surface SW of gate trench GT. The bottom region BT of GT is in contact with the drift region 12. In the sectional view, a plurality of gate trenches GT may be provided. In cross-sectional view, the intervals between the plurality of gate trenches GT may be larger than the intervals between the plurality of trenches TR in the super junction structure 5.

  The gate electrode 27 is provided on the gate insulating film 15. Gate electrode 27 is in contact with third main surface 10a of silicon carbide substrate 10, side surface SS of trench TR, and bottom portion BT of trench TR via gate insulating film 15. That is, the gate electrode 27 is formed so as to run over the third main surface 10a from the side surface SS of the trench TR. The interlayer insulating film 21 is in contact with the gate electrode 27 inside the gate trench GT. The gate electrode 27 is made of polysilicon containing impurities, for example.

  Next, a method for manufacturing a MOSFET as a silicon carbide semiconductor device according to the second embodiment of the present invention will be described. The MOSFET according to the second embodiment is different from the MOSFET manufacturing method according to the first embodiment in that thermal etching is used when forming the gate trench GT, and other steps are related to the first embodiment. This is almost the same as the MOSFET manufacturing method. Hereinafter, a method for forming the gate trench GT will be described.

  Referring to FIG. 16, for example, RIE is performed on third main surface 10 a of silicon carbide substrate 10 provided with etching mask 31, so that source region 14, base region 13, drift region 12 is removed by etching, thereby forming a gate trench GT having a side surface SW connected to the third main surface 10a and a bottom portion BT connected to the side surface SW.

  Next, thermal etching is performed on third main surface 10a of silicon carbide substrate 10 provided with etching mask 31. For example, third main surface 10a of silicon carbide substrate 10 is thermally etched using a halogen gas such as chlorine gas or bromine gas. Thereby, the side surface SS of the gate trench GT is etched, and the side surface SW of the gate trench GT is formed to be inclined with respect to the bottom portion BT so that the opening of the gate trench GT is expanded. Preferably, the side surface SW of the trench TR is inclined with respect to the bottom portion BT by thermally etching the semiconductor layer 2 in an atmosphere containing at least one of chlorine and bromine. The gas used for the thermal etching may contain oxygen gas in addition to chlorine gas or bromine gas, and may further contain a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas, helium gas or the like can be used. For example, in a mixed gas atmosphere of chlorine gas and oxygen gas, third main surface 10a of silicon carbide substrate 10 is thermally etched at 800 ° C., for example. Preferably, the temperature of silicon carbide substrate 10 in the thermal etching is 700 ° C. or higher and 1300 ° C. or lower, more preferably 800 ° C. or higher and 900 ° C. or lower. As described above, in third main surface 10a of silicon carbide substrate 10, gate having source region 14, side surface SW that passes through base region 13 and reaches drift region 12, and bottom portion BT located in drift region 12. A trench GT is formed.

(Embodiment 3)
Next, the structure of MOSFET as a silicon carbide semiconductor device according to the third embodiment of the present invention will be described. The MOSFET according to the third embodiment is different from the MOSFET according to the first embodiment in that the gate trench GT is not mainly formed on the third main surface 10a of the silicon carbide substrate 10, and the other structures are as follows. This is almost the same as the MOSFET according to the first embodiment. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. The following description will focus on differences from the MOSFET structure according to the first embodiment.

  Referring to FIG. 23, MOSFET 1 according to the third embodiment is a planar MOSFET, gate trench GT is not formed in third main surface 10a of silicon carbide substrate 10, and gate insulating film 15 is carbonized. It is formed on third main surface 10a of silicon substrate 10. When viewed from a direction perpendicular to the third major surface 10a, the gate electrode 27 may have a long shape having a longitudinal direction and a short direction. The longitudinal direction of each of n type epitaxial region 4 and p type epitaxial region 3 may be substantially parallel to the longitudinal direction of gate electrode 27. N-type epitaxial region 4 is electrically connected to source electrode 16.

  Gate insulating film 15 is formed in contact with third main surface 10a of silicon carbide substrate 10 so as to extend from the upper surface of one source region 14 to the upper surface of the other source region 14. Gate insulating film 15 is in contact with each of source region 14, base region 13, and drift region 12 on third main surface 10 a of silicon carbide substrate 10. Gate electrode 27 is arranged in contact with gate insulating film 15 so as to extend from one source region 14 to the other source region 14. Gate electrode 27 is provided on gate insulating film 15 so as to sandwich gate insulating film 15 between silicon carbide substrate 10. The gate electrode 27 is formed above the source region 14, the base region 13 and the drift region 12 via the gate insulating film 15. Interlayer insulating film 21 is provided at a position facing third main surface 10a of silicon carbide substrate 10. Specifically, the interlayer insulating film 21 is provided in contact with each of the gate electrode 27 and the gate insulating film 15 so as to cover the gate electrode 27. The interlayer insulating film 21 electrically insulates the gate electrode 27 and the source electrode 16 from each other.

(Embodiment 4)
Next, the structure of an IGBT (Insulated Gate Bipolar Transistor) as a silicon carbide semiconductor device according to the fourth embodiment of the present invention will be described.

Referring to FIG. 24, IGBT 1 according to the fourth embodiment mainly includes silicon carbide substrate 10, gate electrode 27, gate insulating film 15, interlayer insulating film 21, emitter electrode 16, and collector electrode 20. Have. Silicon carbide substrate 10 mainly includes super junction structure 5, semiconductor layer 2, and collector region 19. The super junction structure 5 according to the fourth embodiment is substantially the same as the super junction structure 5 described in the first embodiment. The semiconductor layer 2 mainly has a drift region 12, a base region 13, an emitter region 14, and a contact region 18. Preferably, semiconductor layer 2 is a silicon carbide layer. Drift region 12 is in contact with first main surface 3a of p-type epitaxial region 3 and n-type epitaxial region 4, and has p-type. Base region 13 is in contact with drift region 12 and has an n-type. Emitter region 14 is separated from drift region 12 by base region 13 and has p-type. The contact region 18 passes through the emitter region 14 and contacts the base region 13. The thickness of drift region 12 is, for example, about 100 μm. The concentration of the p-type impurity such as aluminum included in the drift region 12 is, for example, about 5 × 10 ¹⁴ cm ^{−3 to} 1 × 10 ¹⁵ cm ⁻³ .

  Collector region 19 is in contact with second main surface 3b of p type epitaxial region 3 and has n type. The collector electrode 20 is in contact with the collector region 19. The collector region 19 is provided between the p-type epitaxial region 3 and the collector electrode 20. The third main surface 10a of the silicon carbide substrate 10 may be provided with a gate trench GT having a side surface SW connected to the third main surface 10a and a bottom portion BT connected to the side surface SW. Gate insulating film 15 is in contact with emitter region 14 at third main surface 10a of silicon carbide substrate 10, is in contact with drift region 12, base region 13 and emitter region 14 at side surface SW of gate trench GT, and The bottom region BT of the gate trench GT is in contact with the drift region 12. Emitter electrode 16 is in contact with each of emitter region 14 and contact region 18 on third main surface 10a of silicon carbide substrate 10. Preferably, emitter electrode 16 is in ohmic contact with emitter region 14, and collector electrode 20 is in ohmic contact with collector region 19.

  According to the IGBT according to the fourth embodiment, the semiconductor layer 2 is in contact with the first main surface 3a of the p-type epitaxial region 3 and the n-type epitaxial region 4, and has a drift region 12 having p-type and a drift region. 12 and a base region 13 having an n-type and an emitter region 14 having a p-type and separated from the drift region 12 by the base region 13. The silicon carbide semiconductor device is further in contact with the second main surface 3b of the p-type epitaxial region 3 and with the n-type collector region 19, the drift region 12, the base region 13 and the emitter region 14 in gate insulation. And a film 15. The emitter electrode 16 is in contact with the emitter region 14, and the collector electrode 20 is in contact with the collector region 19. Thereby, it is possible to reduce the forward resistance while increasing the breakdown voltage of the IGBT 1 including the emitter region 14 and the collector region 19.

  Next, the configuration of a PN diode as a silicon carbide semiconductor device according to the fifth embodiment of the present invention will be described.

  Referring to FIG. 25, PN diode 1 according to the fifth embodiment mainly includes silicon carbide substrate 10, first electrode 16, and second electrode 20. Silicon carbide substrate 10 mainly includes semiconductor layer 2, super junction structure 5, and silicon carbide single crystal substrate 11. Semiconductor layer 2 is made of, for example, silicon carbide and includes an n-type impurity such as nitrogen. The conductivity type of the semiconductor layer 2 is n-type. The semiconductor layer 2 is provided in contact with each of the first main surface 3 a of the p-type epitaxial region 3 and the surface 4 a of the n-type epitaxial region 4. The first electrode 16 is in ohmic contact with the semiconductor layer 2. The first electrode 16 includes, for example, TiAlSi.

  Silicon carbide single crystal substrate 11 is provided in contact with second main surface 3 b of p type epitaxial region 3. Silicon carbide single crystal substrate 11 contains a p-type impurity such as aluminum and has p-type conductivity. Second electrode 20 is provided in contact with fourth main surface 10b of silicon carbide substrate 10. Second electrode 20 includes, for example, TiAlSi, and is in ohmic contact with silicon carbide single crystal substrate 11 of silicon carbide substrate 10.

  The super junction structure 5 included in the PN diode 1 of the fifth embodiment is substantially the same as the super junction structure 5 described in the first embodiment. Super junction structure 5 is arranged between silicon carbide single crystal substrate 11 and semiconductor layer 2.

  According to the PN diode 1 according to the fifth embodiment, the conductivity type of the semiconductor layer 2 is n-type. The first electrode 16 is in ohmic contact with the semiconductor layer 2. Thereby, the forward resistance can be reduced while increasing the breakdown voltage of the PN diode 1 in which the first electrode 16 is in ohmic contact with the semiconductor layer 2.

(Embodiment 6)
Next, the configuration of a Schottky barrier diode as a silicon carbide semiconductor device according to the sixth embodiment of the present invention will be described.

  Referring to FIG. 26, Schottky barrier diode 1 according to the sixth embodiment mainly includes silicon carbide substrate 10, first electrode 16, and second electrode 20. Silicon carbide substrate 10 mainly includes semiconductor layer 2, super junction structure 5, and silicon carbide single crystal substrate 11. Semiconductor layer 2 is made of, for example, silicon carbide and contains p-type impurities such as aluminum. The conductivity type of the semiconductor layer 2 is p-type. The semiconductor layer 2 is provided in contact with each of the first main surface 3 a of the p-type epitaxial region 3 and the surface 4 a of the n-type epitaxial region 4. The first electrode 16 is in Schottky junction with the semiconductor layer 2. The first electrode 16 is made of, for example, titanium (Ti), nickel (Ni), titanium nitride (TiN), gold (Au), molybdenum (Mo), tungsten (W), hafnium (Hf), zirconium (Zr), tantalum ( Ta) or platinum (Pt).

  Silicon carbide single crystal substrate 11 is provided in contact with second main surface 3 b of p type epitaxial region 3. Silicon carbide single crystal substrate 11 contains a p-type impurity such as aluminum and has p-type conductivity. Second electrode 20 is provided in contact with fourth main surface 10b of silicon carbide substrate 10. Second electrode 20 includes, for example, TiAlSi, and is in ohmic contact with silicon carbide single crystal substrate 11 of silicon carbide substrate 10.

  The super junction structure 5 included in the Schottky barrier diode 1 of the sixth embodiment is substantially the same as the super junction structure 5 described in the first embodiment. Super junction structure 5 is arranged between silicon carbide single crystal substrate 11 and semiconductor layer 2.

  According to the Schottky barrier diode 1 according to the sixth embodiment, the conductivity type of the semiconductor layer 2 is p-type. The first electrode 16 is in Schottky junction with the semiconductor layer 2. Thereby, the forward resistance can be reduced while increasing the breakdown voltage of the Schottky barrier diode 1 in which the first electrode 16 is in Schottky junction with the semiconductor layer 2.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Silicon carbide semiconductor device (MOSFET, IGBT, PN diode, Schottky barrier diode)
2 Semiconductor layer 3 n-type epitaxial region 3a First main surface (boundary surface)
3b Second main surface 4 p-type epitaxial region 4a surface (boundary surface)
4b Back surface 4c First p-type region 4d Second p-type region 4e First portion 4f Second portion 5 Super junction structure 10 Silicon carbide substrate 10a Third main surface 10b Fourth main surface 11 Single crystal substrate 12 Drift region 13 Base region 14 Emitter region (source region)
15 Gate insulating film 16 First electrode (emitter electrode, source electrode)
17 connection region 18 contact region 19 collector region 20 second electrode (collector electrode, drain electrode)
21 Interlayer insulating film 27 Gate electrode 30, 31 Etching mask 32 Mask layer 33 Carbon mask BS, BT Bottom GT Gate trench P Pitch SS, SW Side surface SS1 First side surface portion SS2 Second side surface portion SS3 Third side surface portion TR Trench W1, W2 width

Claims (20)

A trench having a first main surface, a second main surface opposite to the first main surface, a side surface connected to the first main surface, and a bottom portion connected to the side surface. A p-type epitaxial region provided and made of silicon carbide;
An n-type epitaxial region in contact with the p-type epitaxial region at each of the side surface and the bottom of the trench and made of silicon carbide;
A semiconductor layer covering both the first main surface of the p-type epitaxial region and the n-type epitaxial region;
A first electrode provided on the semiconductor layer;
A second electrode provided on the second main surface side of the p-type epitaxial region,
The first main surface of the p-type epitaxial region is a silicon surface or a surface off by 8 ° or less from the silicon surface,
The silicon carbide semiconductor device, wherein the side surface of the trench is a surface that is off by 50 ° or more and 70 ° or less from a silicon surface. The n-type epitaxial region includes a first n-type region in contact with the p-type epitaxial region at the bottom of the trench, and a second n-type region in contact with the p-type epitaxial region at the side surface of the trench,
2. The silicon carbide semiconductor device according to claim 1, wherein said second n-type region has a higher impurity concentration than said first n-type region. 3. The silicon carbide semiconductor device according to claim 2, wherein an impurity concentration of said second n-type region is not less than 5 × 10 ¹⁵ cm ^{−3 and not} more than 1 × 10 ¹⁸ cm ⁻³ .   4. The surface of the n-type epitaxial region in contact with the semiconductor layer is formed along a direction in which the first main surface of the p-type epitaxial region extends. 5. The silicon carbide semiconductor device according to item. The side surface of the trench includes a first side surface portion within 0.2 μm from the first main surface in a direction perpendicular to the second main surface of the n-type epitaxial region, and the first side surface of the n-type epitaxial region. A second side surface portion within 0.2 μm from the bottom of the trench in a direction perpendicular to the main surface of the second surface, and a third side surface portion connecting the first side surface portion and the second side surface portion,
The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein a variation in a plane orientation in the third side surface portion is within 3 °. The semiconductor layer is
A drift region having a p-type in contact with the first main surface of the p-type epitaxial region and the n-type epitaxial region;
A base region in contact with the drift region and having an n-type;
A source region separated from the drift region by the base region and having a p-type, and
A gate insulating film in contact with the drift region, the base region, and the source region;
The silicon carbide semiconductor device according to claim 1, wherein the first electrode is in contact with the source region. On the surface of the semiconductor layer, a gate trench that penetrates both the source region and the base region and reaches the drift region is provided,
The silicon carbide semiconductor device according to claim 6, wherein the gate insulating film is in contact with the source region and the base region on a side surface of the gate trench, and is in contact with the drift region at a bottom of the gate trench. The conductivity type of the semiconductor layer is n-type,
The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the first electrode is in ohmic contact with the semiconductor layer. The conductivity type of the semiconductor layer is p-type,
The silicon carbide semiconductor device according to claim 1, wherein the first electrode is in Schottky junction with the semiconductor layer. The semiconductor layer is
A drift region having a p-type in contact with the first main surface of the p-type epitaxial region and the n-type epitaxial region;
A base region in contact with the drift region and having an n-type;
An emitter region that is separated from the drift region by the base region and has a p-type, and
A collector region in contact with the second main surface of the n-type epitaxial region and having an n-type; and
A gate insulating film in contact with the drift region, the base region, and the emitter region;
6. The silicon carbide semiconductor device according to claim 1, wherein said first electrode is in contact with said emitter region, and said second electrode is in contact with said collector region. Forming a p-type epitaxial region having a first main surface and a second main surface opposite to the first main surface and made of silicon carbide;
Forming a trench having a side surface connected to the first main surface and a bottom portion connected to the side surface on the first main surface of the p-type epitaxial region;
Forming an n-type epitaxial region made of silicon carbide and in contact with the p-type epitaxial region on both the side surface and the bottom of the trench;
Forming a semiconductor layer covering both the first main surface of the p-type epitaxial region and the n-type epitaxial region;
Forming a first electrode in contact with the semiconductor layer;
Forming a second electrode on the second main surface side of the p-type epitaxial region,
The first main surface of the p-type epitaxial region is a silicon surface or a surface off by 8 ° or less from the silicon surface,
The method for manufacturing a silicon carbide semiconductor device, wherein the side surface of the trench is a surface that is off by 50 ° or more and 70 ° or less from a silicon surface.   12. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the step of forming the trench is performed by thermally etching the p-type epitaxial region in an atmosphere containing at least one of chlorine and bromine.   The method for manufacturing a silicon carbide semiconductor device according to claim 12, wherein a temperature of the thermal etching is 700 ° C. or higher and 1300 ° C. or lower.   14. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the step of forming the n-type epitaxial region is performed using a raw material containing nitrogen or phosphorus functioning as a dopant. The step of forming the n-type epitaxial region includes
After the step of forming the trench, forming a carbon mask on the first main surface of the p-type epitaxial region;
Forming the n-type epitaxial region including a first portion located on the carbon mask, a second portion in contact with the side surface of the trench, and the bottom of the trench;
And removing the first portion of the n-type epitaxial region on the carbon mask while leaving the second portion of the n-type epitaxial region. The manufacturing method of the silicon carbide semiconductor device of description. The step of forming the carbon mask includes:
Forming a resist region on the first main surface of the p-type epitaxial region;
The method for manufacturing a silicon carbide semiconductor device according to claim 15, further comprising: carbonizing the resist region. The step of forming the carbon mask includes:
16. The manufacturing of a silicon carbide semiconductor device according to claim 15, which is performed by selectively etching silicon on the first main surface of the p-type epitaxial region to leave carbon after the step of forming the trench. Method. The step of forming the n-type epitaxial region includes
After the step of forming the trench, forming the n-type epitaxial region in contact with the first main surface of the p-type epitaxial region, the side surface of the trench, and the bottom of the trench;
Chemical mechanical polishing is performed on the n-type epitaxial region until the first main surface is exposed, leaving a portion of the n-type epitaxial region in contact with each of the side surface and the bottom of the trench. The manufacturing method of the silicon carbide semiconductor device of any one of Claims 11-14 containing this. The step of forming the n-type epitaxial region includes
After the step of forming the trench, forming the n-type epitaxial region in contact with the first main surface of the p-type epitaxial region, the side surface of the trench, and the bottom of the trench;
Forming a mask layer over the entire surface of the n-type epitaxial region;
Etching the mask layer until a portion of the surface of the n-type epitaxial region is exposed;
Etching the n-type epitaxial region using the mask layer remaining on the surface of the n-type epitaxial region until the first main surface is exposed;
The method for manufacturing a silicon carbide semiconductor device according to claim 11, further comprising: removing the mask layer after etching the n-type epitaxial region. The n-type epitaxial region includes a first n-type region in contact with the p-type epitaxial region at the bottom of the trench, and a second n-type region in contact with the p-type epitaxial region at the side surface of the trench,
20. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein said second n-type region has an impurity concentration higher than that of said first n-type region.

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