JP2016009878A - Imaging device, imaging system and imaging method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high-speed processing of correction data to correct an image in an imaging device.SOLUTION: An imaging device has a pixel array having plural arranged pixels each of which outputs a signal corresponding to radiation or light, a data processor 262 for embedding offset correction data for performing offset correction on image data into a predetermined bit out of plural bits constituting the image data corresponding to a predetermined pixel in the image data based on the signal output from the pixel array, and a transfer controller 266 for transferring the image data having the offset correction data embedded therein to an image processor for performing image processing by using the offset correction data.

Description

  The present invention relates to an imaging apparatus, an imaging system, and an imaging method.

  In an imaging apparatus, a CCD or a CMOS image sensor is used as a sensor for detecting radiation. The characteristics of the sensor are affected by the temperature change of the sensor panel itself on which the sensor is arranged or a peripheral circuit for operating the sensor. Then, since the dark current of the sensor changes due to the temperature change, a difference between the image and the offset value caused by the dark current occurs, causing deterioration in the image quality of the radiation image.

  The invention described in Patent Document 1 discloses a method for correcting an offset amount caused by a dark current for each pixel of a captured image. Specifically, a method of correcting the image data of the imaging device for each pixel based on correction data measured in advance is performed.

  The invention described in Patent Document 2 discloses a method for correcting image data of an imaging device based on image information recorded in a header. Specifically, the imaging device adds a header to the image data at the time of image transfer, and records image information and the like in the header. The transferred header information is extracted by software in the image processing apparatus, and image processing is performed.

Japanese Patent Laid-Open No. 7-236093 JP-A-7-231418

  However, in the image pickup apparatus, the offset amount due to the dark current for each pixel changes due to a temperature change of the image pickup apparatus during shooting even during the same accumulation time. Therefore, it is necessary to correct the offset of the image data following the temperature change of the imaging device.

  Therefore, as in the invention described in Patent Document 2, when image information is transmitted using a header, the header structure is complicated. In a complicated header structure, the processing time for extracting and decoding the header information increases. Therefore, when image information is added to the header of each image data, there is a problem that the amount of transfer data increases and the frame rate decreases.

  Therefore, an object of the present invention is to process correction data for correcting an image at high speed in an imaging apparatus.

  In order to solve the above problems, an imaging apparatus according to the present invention includes a pixel array in which a plurality of pixels that output signals corresponding to radiation or light are arranged, and image data based on signals output from the pixel array. A data processing unit that embeds offset correction data for offset correction of the image data in predetermined bits of a plurality of bits constituting pixel data corresponding to the predetermined pixel, and image data in which the offset correction data is embedded. A transfer control unit that transfers the image to an image processing unit that performs image processing using the offset correction data.

  The present invention can provide an imaging apparatus capable of processing correction data for correcting an image at high speed.

It is a block diagram which shows the radiation imaging system in 1st embodiment. It is a figure which shows the pixel in 1st embodiment. It is a figure which shows the temperature sensor in 1st embodiment. It is a figure which shows the pixel array in 1st embodiment. It is a block diagram which shows the function of the control part in 1st embodiment. It is a figure which shows the process which acquires temperature data from the temperature sensor in 1st embodiment. It is a figure which shows the process of the image data read from the sensor panel in 1st embodiment. It is a figure which shows the process which embeds the offset correction data in 1st embodiment in the least significant bit of image data. It is a figure which shows the process which extracts offset correction data from the image data in which offset correction data was embedded in 1st embodiment. It is a figure which shows the offset correction process in 1st embodiment. It is a figure which shows the process which embeds the offset correction data in 1st embodiment in the low-order bit part of the head pixel of each area | region of image data.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing an example of a block diagram of a radiation imaging system in the first embodiment of the present invention.

  First, the overall configuration of the radiation imaging system will be described with reference to FIG. FIG. 1 is an example of a block diagram of a radiation imaging system showing the present embodiment.

  The radiation imaging system 1 includes a radiation imaging apparatus 100, an image processing unit 101 that performs image processing and system control, a display unit 102 that includes a display, a radiation control unit 103, and a radiation source 104 that generates radiation. When performing radiation imaging, the image processing unit 101 can synchronously control the radiation imaging apparatus 100 and the radiation control unit 103. Radiation (X-rays, α-rays, β-rays, γ-rays, etc.) transmitted through the subject is detected by the radiation imaging apparatus 100 and subjected to predetermined processing by the image processing unit 101 and the like, and image data of the subject is generated. The The image data is displayed on the display unit 102 as a radiation image. The radiation imaging system 1 in the present embodiment corresponds to the imaging system in the present invention.

  Next, the overall configuration of the radiation imaging apparatus 100 will be described. The radiation imaging apparatus 100 includes a sensor panel 105 and a control unit 109. A data processing unit 262 (not shown in FIG. 1) and a transfer control unit (not shown in FIG. 1) 266 are included in the control unit 109. The sensor panel 105 has a plurality of pixels that output signals corresponding to radiation or light. The data processing unit 262 embeds offset correction data for offset correction of image data. The image data is data based on a signal output from the sensor panel 105. Then, the transfer control unit 266 transfers the image data in which the offset correction data is embedded to an image processing unit that performs image processing on the image data. Here, the pixel data is data defining the luminance value and density value of a pixel, which is data of one pixel constituting image data. The radiation imaging apparatus 100 in the present embodiment corresponds to the imaging apparatus in the present invention. Hereinafter, each part will be described in detail.

  The sensor panel 105 is configured by tiling (two-dimensional arrangement) a plurality of pixel arrays 120 on a plate-like base. The pixel array 120 is composed of, for example, a semiconductor substrate. With such a configuration, a large sensor panel 105 can be formed. A plurality of pixels are arranged for each pixel array 120. Further, here, a configuration in which the semiconductor substrate is tiled so that the pixel array 120 forms 12 columns × 2 rows is illustrated, but the configuration is not limited thereto. In the present embodiment, the pixel array 120 is one of the regions obtained by dividing the region where the plurality of pixels are arranged in the sensor panel 105 into a plurality of regions. Hereinafter, the pixel array 120 will be described as a region separated for each semiconductor substrate in the sensor panel 105.

  On the pixel array 120, for example, a scintillator (not shown) that converts radiation into light may be provided. A plurality of photoelectric conversion elements (sensors) are arranged on the side opposite to the radiation incident side of the scintillator. For each sensor, a conversion element that performs photoelectric conversion such as MIS type or PIN type is used. Thereby, an electric signal based on the irradiated radiation dose is obtained. That is, in the present embodiment, a conversion element that generates electric charge according to radiation can be configured by each sensor and the corresponding scintillator. In addition, the said conversion element may convert a radiation into an electric charge directly.

  The signal reading unit 20 includes at least a signal amplification unit 107 including a differential amplifier and an AD conversion unit 108 that converts an analog signal into a digital signal (AD conversion). The signal reading unit 20 can read a signal of a pixel selected by a row scanning circuit 203 and a column scanning circuit 204 described later. A plurality of electrodes for inputting / outputting signals or supplying power are arranged on the upper and lower sides of the sensor panel 105. The electrode is connected to an external circuit, and for example, a flying lead type printed wiring board (not shown) is used for the connection. The signal from the pixel array 120 is read by the signal reading unit 20 through the electrodes. A control signal from the control unit 109 is input to the pixel array 120 via an electrode.

  The control unit 109 communicates control commands with the image processing unit 101, performs synchronization signal communication, and outputs image data to the image processing unit 101. The control unit 109 controls the pixel array 120 or each unit, and performs drive control and operation mode control of each pixel and temperature sensor. Further, the control unit 109 synthesizes the image data (digital data) of each pixel array 120 AD-converted by the AD conversion unit 108 of the signal reading unit 20 into one image data, and outputs it to the image processing unit 101. . Furthermore, the control unit 109 can control to read temperature data from the temperature sensor 127 for each frame during a period in which signals are read from the pixels 202 to be read for one frame in the pixel array 120. The control unit 109 can calculate the temperature of the sensor panel 105 or the temperature change amount of the sensor panel 105 from the acquired data of the temperature sensor 127. The control unit 109 can also generate offset correction data from the calculated data of the temperature sensor 127 and embed it in the image data.

  The image processing unit 101 has a function of performing image processing of image data using offset correction data. The image processing unit 101 can perform offset correction by subtracting image data for offset (offset image data) from one acquired image data. The pixel array 120 generates a dark current even during a period when radiation for imaging is not irradiated. For this reason, the pixel array 120 has an offset value in the image data. The image processing unit 101 has image data acquired in a state where no radiation is irradiated for a predetermined period as image data for offset of the pixel array 120. Then, the image processing unit 101 can perform offset correction by subtracting image data for offset from image data acquired in a period different from the predetermined period.

  Control commands or control signals and image data are exchanged between the control unit 109 and the image processing unit 101 via various interfaces. The image processing unit 101 outputs setting information or shooting information such as an operation mode and various parameters to the control unit 109 via the control interface 110. Further, the control unit 109 outputs device information such as an operation state of the radiation imaging apparatus 100 to the image processing unit 101 via the control interface 110. Further, the control unit 109 outputs image data obtained by the radiation imaging apparatus 100 to the image processing unit 101 via the image data interface 111. Further, the control unit 109 notifies the image processing unit 101 that the radiation imaging apparatus 100 is ready for imaging using the READY signal 112. In addition, the image processing unit 101 notifies the control unit 109 of the timing of radiation irradiation start (exposure) in response to the READY signal 112 from the control unit 109 using the external synchronization signal 113. Further, the control unit 109 outputs a control signal to the radiation control unit 103 to start radiation irradiation while the exposure permission signal 114 is enabled.

  The temperature sensor 127 is arranged in each pixel array 120 constituting the sensor panel 105 in order to acquire the temperature of the sensor panel 105. The temperature sensor 127 and the pixel array 120 are connected by a common wiring. In addition, although the position of the temperature sensor 127 is made into the surface edge part, it is not restricted to this. It can be arranged at any position on the surface of the pixel array 120 as long as no radiation or light is incident thereon. At least the pixel array 120 and the temperature sensor 127 are arranged on a common semiconductor substrate. Furthermore, the temperature sensor 127 may be arranged in a region different from the pixel array 120 on the semiconductor substrate. Note that the configuration in which the pixel array 120 and the temperature sensor 127 are formed on a common semiconductor substrate is included in the configuration in which the pixel array 120 and the temperature sensor 127 are formed on the common semiconductor substrate.

  The cooling panel 133 has a function of cooling the sensor panel 105. It is possible to reduce the temperature change of the sensor panel 105 and suppress fluctuations in the characteristics of the sensor panel. The cooling panel 133 is made of a material having high thermal conductivity so that the entire surface of the sensor panel 105 has a uniform temperature.

  The cooling device 131 has a function of controlling the temperature of the cooling panel 133 to be constant. The cooling hose 132 is connected to the cooling device 131 and the cooling panel, and has a function as a path for circulating the coolant. The cooling device 131 can be maintained at 27 ° C., for example, by circulating a temperature-controlled cooling liquid.

  Next, an example of a pixel will be described with reference to FIG. FIG. 2 is an equivalent circuit diagram illustrating an example of a circuit configuration of one pixel 202 that forms the pixel array 120.

  As shown in FIG. 2, each of the plurality of pixels may include, for example, a first portion ps1, a second portion ps2, and a third portion ps3. Note that the control unit 109 can control whether or not the transistors M1 to M13 which are transistors included in each part are conductive.

  The first portion ps1 may include a photodiode PD, transistors M1 to M3, a floating diffusion capacitor CFD (hereinafter referred to as FD capacitor CFD), and a sensitivity switching capacitor CFD1. The photodiode PD is a photoelectric conversion element, and can generate a charge corresponding to radiation or light. The photodiode PD converts light generated by the above-described scintillator into an electric signal in accordance with the irradiated radiation. The photodiode PD may be one that can directly detect radiation and generate charges. Then, a charge corresponding to the radiation or light is generated in the photodiode PD, and the voltage of the FD capacitor CFD corresponding to the generated charge is output to the second portion ps2. The sensitivity switching capacitor CFD1 is used to switch the sensitivity of the pixel 202 to radiation, and is connected to the photodiode PD via the transistor M1 (switching element). When the control unit 109 activates the WIDE signal, the transistor M1 is turned on, and the voltage of the combined capacitance of the FD capacitor CFD and the capacitor CFD1 is output to the second portion ps2. Thus, in the pixel 202, the sensitivity to radiation is changed depending on whether or not the capacitor CFD1 is used. Further, the transistor M2 initializes the charge of the photodiode PD when the PRES signal is activated, and resets the voltage output to the second portion ps2. If the sensitivity switching function is not provided, M1 and CFD1 are not included in ps1.

  The second part ps2 may include transistors M3 to M7, a clamp capacitor CCL, and a constant current source. The transistor M3, the transistor M4, and a constant current source (for example, a transistor having a current mirror configuration) are connected in series so as to form a current path. When the enable signal EN input to the gate of the transistor M3 is activated by the control unit 109, the transistor M4 that receives the voltage from the first portion ps1 is activated. In this way, a source follower circuit is formed, and a voltage corresponding to the voltage from the first portion ps1 is output. At the subsequent stage, a clamp circuit including transistors M5 to 7 and a clamp capacitor CCL is provided. Specifically, one terminal n1 of the clamp capacitor CCL is connected to a node between the transistors M3 and M4 of the first part ps1, and the other terminal n2 is connected to the transistor M5 functioning as a clamp switch. It is connected. The transistors M6, M7, and the constant current source are directly connected to form a current path, and the other terminal n2 is connected to the gate of the transistor M7. With this configuration, the influence of kTC noise (so-called reset noise) generated in the photodiode PD of the first portion ps1 can be reduced. Specifically, a voltage corresponding to the voltage from the first portion ps1 at the time of reset is input to the terminal n1 of the clamp capacitor CCL. Further, when the clamp signal PCL is activated, the transistor M5 becomes conductive, and the clamp voltage VCL is input to the terminal n2 of the clamp capacitor CCL. In this manner, the potential of the terminal n2 is clamped as a noise component, and the change in voltage due to subsequent generation and accumulation of charges in the photodiode PD is output as a signal component. The enable signal EN is also input to the gate of the transistor M6, and the enable signal EN is activated, so that the transistor M7 is activated. In this way, a source follower circuit is formed, and a voltage corresponding to the gate voltage of the transistor M7 is output to the third portion ps3.

  The third part ps3 may include transistors M8, M10, M11, and M13, analog switches SW9 and SW12, and capacitors CS and CN. The third part ps3 corresponds to the holding part in the present invention. The holding unit includes a signal holding unit and a reference signal unit. The signal holding unit has a function of holding a signal corresponding to the amount of charge generated in the photoelectric conversion element. Specifically, it has M8, M10, SW9, and a capacitor CS. The reference signal unit has a function of holding a reference signal that serves as a reference for the amount of generated charges. Specifically, it has M9, M11, SW12, and a capacitor CN.

  The transistor M8 and the capacitor CS form a sample and hold circuit, and function as a signal holding unit that holds an output value from the second portion ps2. First, an operation for holding a signal in the signal holding unit will be described. Specifically, the control unit 109 switches the state (conductive state or non-conductive state) of the transistor M8 using the control signal TS1, thereby allowing the signal (signal according to the light component) obtained from the second part ps2 to be capacitance. Hold in CS, that is, perform sampling. Further, the transistor M10 functions as an amplifier by its source follower operation, and thereby the signal is amplified. The amplified signal is output from the terminal S by making the analog switch SW9 conductive using the control signal VSR. Next, an operation in which the reference signal is held by the reference holding unit will be described. Similarly, the transistors M11 and M13, the analog switch SW12, and the capacitor CN can hold a reference signal.

  Next, the configuration of the temperature sensor in the first embodiment will be described in detail with reference to FIG. FIG. 3 is a diagram showing an example of the configuration of the temperature sensor in the first embodiment.

  First, the overall configuration of the temperature sensor will be described. The temperature sensor 127 in FIG. 3 includes at least one or a plurality of diodes. Furthermore, a signal amplifying unit that amplifies the signal of the diode and a signal holding unit that holds a signal output from the signal amplifying unit are provided. Further, the temperature sensor 127 includes a reference holding unit that holds a reference signal that serves as a reference for the temperature of the pixel array 120. The temperature sensor 127 further includes a second signal amplification unit that amplifies a reference signal that serves as a reference for the temperature of the pixel array 120, and a reference holding unit that holds a signal output from the second signal amplification unit. Have. Each configuration will be specifically described below.

  First, the diode of the temperature sensor 127 will be described. D1 to D4 are PN junction diodes. The material of the diode is composed of a silicon semiconductor. The following forward voltage and temperature characteristics will be described in the case of using a PN junction type diode made of a silicon semiconductor. The relationship between the current I flowing through the PN junction diode and the applied voltage V is expressed by Equation (1).

  Here, q is a unit charge, n is an ideal factor, k is a Boltzmann constant, T is a temperature, and Io is a saturation current. As an example of the characteristic based on Equation (1), the PN junction diode functions as a temperature sensor having a forward voltage characteristic of about 0.6 V at room temperature and a forward voltage of about −2.5 mV / ° C. In this embodiment, four stages of diodes are connected in series to have a forward voltage of about 2.4 V and an output characteristic of about −10 mV / ° C. at room temperature. Since the output of the temperature sensor can be within the same output range as that of the sensor shown in FIG. 2, it can be read out using the signal reading unit 20 shown in FIG. .

  Next, the signal amplification unit will be described. The signal amplifying unit includes at least one transistor (M23). M23 is a transistor that operates as a source follower, and has a function of performing signal amplification of a signal corresponding to the forward voltage VF of the diode output from the temperature sensor as the temperature signal S.

  Next, the second signal amplification unit will be described. M29 as a second signal amplifying unit is a transistor that operates as a source follower, and has a function of performing signal amplification of the reference signal VCL output from the N terminal of the temperature sensor as the reference signal N.

  Next, the signal holding unit will be described. The signal holding unit includes at least M24 and CS, and constitutes a temperature sensor signal sample hold circuit. M24 is a sample and hold transistor (sample and hold switch S). CS is a temperature sensor signal hold capacitor. Further, a signal amplifying transistor M26 may be provided. M26 operates as a source follower and functions as a transistor for amplifying the temperature sensor signal.

  Next, the reference holding unit will be described. The reference holding unit includes at least M30 and CN, and constitutes a sample hold circuit for storing a reference signal. M30 is a sample and hold transistor (sample and hold switch N). CN is a reference signal hold capacitor. Further, a signal amplifying transistor M32 may be provided. M32 operates as a source follower and functions as a transistor for amplifying the reference signal.

  Next, the transfer switch will be described. M25 is a transfer switch S for outputting the temperature sensor signal amplified in M26 to the S signal output line. M31 is a transfer switch N for outputting the reference signal amplified in M32 to the N signal output line.

  Next, each signal related to the control of the temperature sensor 127 and an operation based on the signal will be described. Each signal described below is input from the control unit 109.

  First, the EN signal will be described. The EN signal is input from the control unit 109 and has a function of controlling the operation state of each transistor. The EN signal is connected to the gates of a constant current selection switch for diode (M21), a constant current selection switch for diode signal amplifier (M22), and a constant current selection switch for reference voltage amplifier (M28). When the EN signal is at a high level, these selection switches M21, M22, and M28 are turned on. When the EN signal is at a high level, a constant current flows through the diodes D1 to D4 connected in series, and a signal corresponding to the forward voltage VF of the diode is output as a signal output of the temperature sensor from the activated transistor M23.

  The PCL signal is a signal for controlling the reference voltage selection switch M27. When the EN signal is at a high level, the reference voltage selection switch M27 is turned on when the PCL signal is at a high level, and the reference signal VCL is amplified and output from the transistor M29 that has been activated.

  The TS signal is a sample-and-hold control signal that is a signal output of the temperature sensor. By setting the TS signal to a high level and turning M24 on, the diode forward voltage VF is applied to the capacitor CS through M23. Next, when the signal TS is set to a low level and the M24 is turned on, the holding of the temperature sensor signal in the sample hold circuit is completed.

  The TN signal is a sample hold control signal for the reference signal VCL, and the reference signal VCL amplified through M29 is applied to the capacitor CN by setting the TN signal to a high level and turning M30 on. Next, the signal TN is set to the low level and the M30 is turned off, whereby the holding of the reference signal VCL in the sample and hold circuit is completed.

  After the sample hold of the capacitors CS and CN, M26 and M32 are turned on, and the held signals can be read without destruction until they are sampled and held again.

  The TSEL signal is a temperature sensor selection signal and controls the on / off state of the transfer switch S (M25) and the transfer switch N (M31). Then, the temperature sensor signal hold capacitor (CS) signal S and the reference voltage VCL hold capacitor (CN) signal N are output.

  The pixel array 120 in the first embodiment will be described with reference to FIG. FIG. 4 is a diagram illustrating a configuration example of the pixel array 120. As shown in FIG. 4, the pixel array 120 includes a plurality of pixels 202 arranged in m pieces in the vertical direction on the long side and n pieces in the horizontal direction on the short side. In the pixel array 120, a plurality of sensors are arranged in a matrix. In this embodiment, one set of column signal lines among the column signal lines 206 and 207 is used in common between the temperature sensor 127 and the pixel array 120.

  Each signal of the pixel array 120 and the temperature sensor 127 is read by the signal reading unit 20 through a common wiring. In this embodiment, the image forming apparatus further includes a row scanning circuit that scans a plurality of sensors of the pixel array 120 in units of rows, and the row scanning circuit scans a predetermined row of sensors and a temperature sensor in common.

  The drive unit 210 includes a row scanning circuit 203 for driving each pixel 202 and a column scanning circuit 204 for reading a signal from each pixel 202.

  The row scanning circuit 203 and the column scanning circuit 204 are constituted by shift registers, for example, and operate based on a control signal from the control unit 109. The row scanning circuit 203 inputs a control signal to each pixel 202 via the row signal line 205, and drives each pixel 202 in units of rows based on the control signal. For example, the row scanning circuit 203 functions as a row selection unit, and selects a pixel 202 to be read out for a plurality of pixels at a predetermined selection cycle for each row. The column scanning circuit 204 functions as a column selection unit, selects each pixel 202 for each column based on the control signal, and sequentially outputs a signal from each pixel 202 at a predetermined readout cycle. When the row selection signal V0 is enabled, the temperature sensor 127 outputs the output of the temperature sensor 127 to the reference signal output terminal N and the signal output terminal S. V0 is a row dedicated to the temperature sensor.

  The pixel array 120 further has VST, HST, CLKV, and CLKH as input terminals. The input terminal VST is a terminal to which a row scanning start signal VST is input. The input terminal CLKV is a terminal to which the row scanning clock signal CLKV is input. The input terminal CLKH is a terminal to which the column scanning clock signal CLKH is input. The input terminal HST is a terminal to which a column scanning start signal HST is input.

  The row scanning circuit 203 selects a plurality of pixels for each row, and sequentially scans the pixels in the row direction, which is the sub-scanning direction, in synchronization with the row scanning clock CLKV. The column scanning circuit 204 sequentially selects the column signal lines of the pixels in the row selected by the row scanning circuit 203 for each pixel in synchronization with the column scanning clock signal CLKH. When the row signal line 205 that is an output line of the row scanning circuit 203 is enabled, a signal and a reference signal are output via the column signal lines 206 and 207. When the column scanning circuit 204 sequentially selects the signals output to the column signal lines 206 and 207, the signals of the respective pixels are sequentially output to the analog voltage output lines 208 and 209.

  Further, the pixel array 120 has a chip select terminal CS, a signal output terminal S, and a reference signal output terminal N. The chip select terminal CS is a terminal for making it possible to read a signal from the pixel array 120. The signal output terminal SIG is a terminal for reading a signal held in the capacitor CS of each pixel 202, and the reference signal output terminal N is held in the capacitor CN.

  Next, the configuration of the control unit 109 will be described with reference to FIG. First, functions of each unit of the control unit 109 will be described. The control unit 109 includes at least a data processing unit 262 and a transfer control unit 266.

  The communication control unit 261 has a function of performing communication with the image processing unit 101 and controlling the radiation imaging apparatus 100 using a control command transmitted from the image processing unit 101. The control command is acquired via the control interface 110. The data processing unit 262 controls the sensor panel 105 based on the transmitted control command, and acquires image data from the sensor panel 105. Then, image data rearrangement processing and offset correction data are embedded in the image data. Acquisition of image data is performed via the sensor control bus 251 and the data processing bus 256. The sensor control bus 251 is a bus that exchanges various signals for driving the sensor panel 105 and the temperature sensor 127. The data processing bus 256 is a bus that acquires a signal from the AD conversion unit 108. Note that the data processing unit 262 can perform control for determining whether or not temperature data is embedded in the image data.

  The temperature data processing unit 264 performs data processing on the temperature data read from the temperature sensor 127. The line buffer memory 265 stores image data read from the sensor panel 105 and rearranged. The line buffer memory 265 has one or a plurality of line buffer memories. The transfer control unit 266 transfers the image data stored in the line buffer memory to the image processing unit 101 via the image data interface 118. The frame buffer 267 temporarily stores the pixel rows on which the image data has been rearranged in the order of transfer.

  The temperature correction data memory 268 stores temperature correction data for correcting the inherent offset amount of each temperature sensor 127 configured in the sensor panel 105. This is performed for each pixel array 120 in which the temperature sensor 127 is configured in the sensor panel 105.

  The conversion table memory 269 includes a temperature conversion lookup table 270 and an 8b / 10b conversion table 271. The temperature conversion lookup table 270 converts the temperature data after temperature correction. The 8b / 10b conversion table 271 performs 8b / 10b conversion on the converted temperature data.

  Next, a method for acquiring offset correction data from temperature data read from the temperature sensor 127 will be described with reference to FIG.

  First, the temperature data group 301 and the image data group 302 are input to the data processing unit 262. A temperature data group 301 and an image data group 302 indicate data rows of temperature data and image data in AD conversion regions B1 to B8 that have been AD converted, respectively. The data processing unit 262 stores the temperature data group 301 in the register 303 included in the data processing unit 262. The temperature data group 301 is arranged and stored in series when stored in the register 303.

  The sensor panel 105 includes a sensor panel upper stage 224 and a sensor panel lower stage 225. The sensor panel upper stage 224 is composed of blocks B1 to B4. The sensor panel lower part 225 is configured by blocks B5 to B8. Each block includes a pixel array 120. Arrows in the sensor panel 105 indicate the main scanning direction 252 and the sub-scanning direction 253 for reading out pixel signals in the sensor panel 105.

  As shown in FIG. 6, the temperature data of the sensor panel upper stage 224 is aligned in the order of T0, T1, and T2 for each pixel array 120. Further, the aligned temperature data is aligned in the register 303 so as to be in the order of B1 to B4 in units of blocks. On the other hand, the temperature data of the lower part 225 of the sensor panel is aligned in the register 303 in order of T2, T1, and T0 in the order of T2, T1, and T0 in order of B4 of the upper block and in the order of B8 to B5. The Therefore, the sensor panel upper step 224 and the sensor panel lower step 225 in the data processing unit 262 are different. This is because the main scanning direction of the sensor panel 105 is different between the sensor panel upper step 224 and the sensor panel lower step 225.

  The above rearrangement process is sequentially performed in parallel with the input of the temperature data to the data processing unit 262. The rearrangement of the temperature data in the register 303 is completed when the input of the temperature data group 301 to the data processing unit 262 is completed.

  Next, the temperature data processing unit 264 performs correction processing on the rearranged temperature data. The temperature data correction processing unit 304 reads the temperature data sequentially input and the temperature correction data corresponding to the temperature data from the temperature correction data memory 268, and performs the temperature data correction process.

  The offset component of the temperature sensor 127 included in the temperature data is corrected by the correction process. Further, the temperature data processing unit 264 converts the corrected 16-bit temperature data into 8-bit offset correction data used in the offset correction processing of the captured image. The temperature data conversion processing unit 305 refers to the temperature data conversion lookup table 270 and converts the 16-bit temperature data sequentially transferred from the temperature data correction processing unit 304 into 8-bit offset correction data. The 8-bit offset correction data is used to switch a plurality of correction data prepared for offset correction. Therefore, the 8-bit offset correction data does not have to be temperature information. For example, the 8-bit offset correction data may be a number corresponding to the correction step set in advance according to the offset variation characteristic depending on the temperature of the sensor panel 105 in one-to-one correspondence.

  The temperature data processing unit 264 then converts the 8-bit offset correction data into 10-bit offset correction data with reference to the 8b / 10b conversion table 271 at the 8b / 10b conversion processing unit 306. The offset correction data is converted by the conversion so that the continuous low or high state becomes 3 bits or less. The temperature data conversion lookup table 270 and the 8b / 10b conversion table 271 may be integrated as one lookup table and used for data conversion. Note that the conversion processing time is shortened by integrating the two lookup tables.

  The register 309 is a register provided in the data processing unit 262, and sequentially stores offset correction data that has been subjected to temperature data correction processing, temperature data conversion processing, and 8b / 10b conversion processing by a pipeline method. In the register 309, the offset correction data subjected to the 8b / 10b conversion processing from the temperature data is arranged in the same order as the register 303.

  The offset correction data group 308 is a converted 10-bit offset correction data group of the sensor panel upper stage 224. The offset correction data group 307 is a converted 10-bit offset correction data group of the lower part 225 of the sensor panel.

  Although the temperature data is converted into 256-step data, which is 8-bit temperature data, using the temperature data conversion lookup table 270, the present invention is not limited to this. When the temperature range used by the temperature sensor 127 is narrow, or when the offset component of the temperature data is stable, the number of bits of the temperature data can be appropriately converted.

  For example, when it is desired to increase the correction step for offset correction, the temperature range for acquiring offset correction data can be set to 8 bits or less. If the temperature data is 32 steps, it can be converted into 5-bit temperature data using the temperature data conversion lookup table 270. Further, when the temperature data step is 8 or 4 steps, the offset correction data can be 3 bits or 2 bits.

  When the temperature data is 3 bits or less, there is no need to limit the number of consecutive lows or highs as in the 8b / 10b conversion, and the offset correction data may be stored in the register 309 as it is. Therefore, although 8b / 10b conversion was performed, it is not restricted to this. When the number of bits of the temperature data is small, conversion may be performed using a conversion table in which the continuous low or high state is 3 bits or less.

  Next, image data rearrangement processing read from the sensor panel 105 will be described with reference to FIG. First, the processing of image data read by the control unit 109 from the sensor panel upper stage unit 224 will be described with reference to FIG.

  FIG. 7 is a conceptual diagram of the processing of image data read from the sensor panel upper stage 224. A data group 320 indicates a data group of one line of image data read from the sensor panel upper stage 224. In FIG. 7, n is the number of pixels in the main scanning direction. m is the number of pixels in the sub-scanning direction.

  In the radiation imaging apparatus 100, the eight blocks B1 to B8 of the sensor panel upper stage 224 and the sensor panel lower stage 225 are driven at the same timing. The AD-converted image data of each block is input to the data processing unit 262 in parallel.

  As shown in FIG. 7, in the pixel data processing of the upper part 224 of the sensor panel, first, the pixels in the first row inputted in parallel from the four blocks B1 to B4 are rearranged.

  The data group 320 is a total of 12n pixels of the first row 3n pixels 4 blocks of each block upper stage P0 (1,1) to P2 (n, 1). The data group 320 is stored in the first upper line buffer area 265-1 so as to be continuous address data. Next, the arrangement of the image data in the first upper line buffer 265-1 will be described. First, the pixel P0 (1, 1) to the pixel P2 (n, 1) of the block B1 are stored in order. Hereinafter, the image data of blocks B2 to B4 are also stored in order.

  When the rearrangement of the data in the first row is completed, the pixel P0 (1,1) in the block B1 to the pixel P2 (n, 1) in the block B4 are transferred to the data processing unit 262.

  Similarly, in the second and subsequent image data, the pixel P0 (1,2) to the pixel P2 (n, 2) of the block B1 are sequentially stored in the second upper line buffer 265-2. Hereinafter, the image data of blocks B2 to B4 are also stored in order.

  From the pixel P0 (1,2) of the block B1 where the rearrangement of the data of the second row is completed, the pixel P2 (n, 2) of the block B4 is transferred to the data processing unit 262.

  Thereafter, similarly, the first upper line buffer 265-1 and the second upper line buffer 265-2 are alternately used to rearrange the image data of each row. The transfer to the data processing unit 262 is repeated, and the process up to the last readout line of the sensor panel upper stage unit 224 is completed.

  The processing of the pixel data of the sensor panel lower stage 225 is performed in parallel with the process of the sensor panel upper stage 224. The rearrangement of the image data in the lower part 225 of the sensor panel is similarly performed. The rearrangement of the image data in the lower part 225 of the sensor panel is performed by alternately using the first lower line buffer 265-3 and the second lower line buffer 265-4. The rearranged image data is repeatedly transferred to the data processing unit 262.

  The data processing unit 262 embeds the offset correction data groups 307 and 308 in at least one bit among the bits constituting the predetermined pixel in the image data. The temperature data embedding process will be described later. Then, the transfer control unit 266 transfers the image data in which the offset correction data is embedded to the image processing unit 101 that performs image processing of the image data using the offset correction data. Image data waiting for transfer in the data transfer unit 266 is temporarily saved in the frame buffer 267.

  Next, a process for embedding bits of offset correction data in predetermined pixels of image data will be described with reference to FIG. Hereinafter, a case where the data processing unit 262 embeds offset correction data in a plurality of continuous pixels in a predetermined row will be described in detail.

  In FIG. 8, an arrow 351 indicates the direction of processing for embedding offset correction data in the least significant bit. In this example, the least significant bit of the pixel data is predetermined as a bit in a range in which an offset of a signal output from the sensor can be included. Image data 352 indicates data for one pixel. Bit 353 indicates one bit in one pixel data. The image data 352 is composed of 1 byte of the most significant bit (MSB) from Bit 0 to Bit 15 with LSB as the least significant bit.

  An address 354 indicates an address when reading image data of each block when reading data from the sensor panel 105. An address 355 indicates an address when image data is transferred from the control unit 109 to the image processing unit 101. As shown in FIG. 8, the address 354 and the address 355 have a one-to-one correspondence.

  The offset correction data embedding process will be described in detail below. First, offset correction data corresponding to the image data of each pixel array 120 of the sensor panel upper stage 224 is sequentially read from the offset correction data group 308.

  The offset correction data embedding process is performed in a pipeline manner, starting with the image data D (1, 1) as the head, and sequentially performing the byte data one byte at a time until the last image data D (12n, 1). As described with reference to FIG. 6, the register 309 stores offset correction data groups 308 and 307 of the sensor panel 105.

  The offset correction data 356 is offset correction data of an image data row starting with D (1, 1) in the offset correction data group 308. Similarly, the offset correction data 357 is offset correction data of an image data row starting with D (n + 1, 1).

  The data processing unit 262 reads the 10-bit offset correction data 356 from the register 309 and decomposes the bits. Then, the bit-decomposed data includes the least significant bit Bit0 to the most significant bit Bit9 in order from the least significant bit of the image data from D (1,1) to D (10,1). It is sequentially replaced with bit Bit0. Similarly, the bit-decomposed data 357 is sequentially replaced with the least significant bit Bit0 of each of the image data from D (n + 1, 1) to D (n + 10, 1) in the flow of image data processing. Then, the remaining offset correction data is sequentially read from the register 309, and bit decomposition and replacement processing are performed.

  Through the above processing, the offset correction data is embedded bit by bit in the least significant bit of the image data of 10 pixels starting from the address D (1,1) to D (11n + 1,1) of the image data row.

  Addresses D (1,1) to D (11n + 1,1) are the leading pixel addresses of each pixel array 120 in the image data row transferred first in the upper stage of the sensor panel. For this reason, offset correction data is embedded in the head portion of each pixel array 120 of the transferred image data.

  The embedded image data flows in the direction of the arrow 351 for each byte, and the data processing timing is adjusted by the data processing unit 262 and transferred.

  As described above, the process for embedding the offset correction data in the upper part 224 of the sensor panel has been described above.

  Note that the bit for which the offset correction data embedding process is performed is not limited to the least significant bit. The data processing unit 262 can determine a bit for embedding the offset correction data within a range that does not affect the image quality even if a part of the pixels is replaced. For example, the data processing unit 262 can determine the number of bits in which the offset correction data is embedded according to the noise level of the image data. Here, the noise level is caused by, for example, external noise, a pixel array, a peripheral circuit thereof, or the like. In this case, a lot of offset correction data can be embedded within a range that does not affect the image quality. Therefore, for example, the data processing unit 262 may embed not only the lowest bit Bit0 but also Bit1. In order to ensure image quality, it is preferable that 12 bits out of at least 16 bits are used for the image. The data processing unit 262 is preferably embedded in a predetermined range of bits including at least one bit from the least significant bit of the pixel data of the predetermined pixel of the image data to the fourth bit. In this case, more offset correction data can be embedded within a range that does not affect the image quality. Furthermore, the data processing unit 262 can embed the image data in an area including any of the first pixel, the first row, and the first column in the image data. Further, although the offset correction data has been described as an example of the data to be embedded, not only the offset correction data but also image processing data including other environment information can be embedded. If there is only one type of image processing data for one frame, it is only necessary to embed the image processing data only at the beginning of the frame.

  As described above, the data processing unit 262 embeds the offset correction data in the pixels at the positions common to the plurality of regions in the plurality of regions in the image data. The plurality of regions are determined corresponding to one AD converter in the AD conversion unit 108, but are not limited thereto. For example, the offset correction data may be embedded in pixels located at a common position in a plurality of regions for each pixel array 120.

  Next, processing for transferring image data performed by the transfer control unit 266 will be described. The transfer control unit 266 sequentially transfers the image data of the sensor panel upper stage unit 224 to the image processing unit 101 via the image data interface 111 line by line. The image data of the lower sensor panel 225 is temporarily stored in the frame buffer 267 while the image data of the upper sensor panel 224 is being transferred. After the last image data of the sensor panel upper stage 224 is transferred, the image data is sequentially read from the frame buffer 267 and transferred to the image processing unit 101.

  As described above, the radiation imaging apparatus 100 can process and transfer the offset correction data at high speed while reading the image data. Furthermore, since the offset correction data is embedded in some pixels of the image data, the amount of data transferred from the imaging device can be reduced. Since the offset correction data is embedded in the image data in a range that does not affect the image quality, the offset correction data can be transferred while ensuring the image quality.

  Next, processing for extracting offset correction data from image data performed by the image processing unit will be described with reference to FIG. FIG. 9 is a conceptual diagram illustrating processing for extracting offset correction data from an image data row in which offset correction data is embedded. Each process is performed by the image processing unit 100. The image processing unit 100 includes an 8b / 10b reverse conversion table 404, a segment base data memory 409, an 8b / 10b reverse conversion processing unit 421, and a data conversion processing unit 422.

  In FIG. 9, an arrow 423 indicates the direction of processing for extracting the offset correction data from the image data in which the offset correction data is embedded in the least significant bit.

  The offset correction data 424 extracts the bits embedded in the least significant bit Bit0 of each of the image data from D (1,1) to D (10,1), and is synthesized into 10-bit data. The offset correction data 425 is obtained by performing extraction processing similar to the offset correction data 424 on the image data from D (n + 1, 1) to D (n + 10, 1).

  The 8b / 10b reverse conversion processing unit 421 performs 8b / 10b reverse conversion. The data conversion processing unit 422 converts the 8-bit offset correction data subjected to the 8b / 10b inverse conversion into the segment base memory.

  In the offset correction data extraction processing, each image data row is processed in a pipeline manner by image data D (1, 1) to D (12n, 1) one by one in order.

  In the image data from D (1,1) to D (10,1), offset correction data is embedded in the least significant bits. Therefore, the image processing unit 100 extracts the least significant bits for each piece of image data, and combines the bits with 10-bit offset correction data 424. The processed image data is transferred to the next process in the direction of arrow 423. The combined offset correction data 424 is transferred to the 8b / 10b inverse transform processing unit 421. The 8B / 10B reverse conversion processing unit 421 converts the offset correction data 424 into 8-bit offset correction data with reference to the 8b / 10b reverse conversion processing table 405 and transfers the data to the data conversion processing unit 422 in the next stage.

  The data conversion processing unit 422 refers to the data conversion table 406, converts the segment base address indicating the first pixel of the offset image data corresponding to the offset correction data, and stores the segment base address in the segment base data memory.

  Since offset correction data is not embedded in the image data from D (11, 1) to D (n, 1), the image data is transferred to the next process in the direction of the arrow 423 without performing the conversion process.

  Similarly, the image data D (n + 1, 1) to D (n + 10, 1) are subjected to offset correction data extraction processing, and the segment base address is stored in the segment base data memory 409. Determination and processing are performed in the same manner as described above from image data D (n + 11, 1) to D (12n, 1).

  Similarly, the 8b / 10b reverse conversion table 405 and the data conversion table 406 may be integrated as one lookup table to create a segment base address. By integrating the look-up table, the conversion processing time is reduced.

  As described above, the offset correction data embedded at the head of each image data is extracted, converted into the segment base address, and stored in the segment base data memory 409.

  An offset correction process performed on the image data by the image processing unit 101 will be described with reference to FIG. By the offset processing, a plurality of offset image data stored in the offset image data memory 408 can be switched based on the segment base address associated with each region.

  Through the processing performed in FIG. 9, the segment base data memory 409 stores segment base addresses corresponding to a plurality of areas until the image processing of image data per frame (one frame) is completed. .

  The offset image data selection processing unit 456 switches the segment base address for each of a plurality of areas, and switches offset image data to be referenced for offset correction.

  The offset image data memory 408 stores offset image data. Reference numerals 471 to 476 denote pixel positions of the offset image data indicated by the segment base address, and are the head addresses of the offset image data corresponding to the offset correction data. The offset image data 1 to N correspond to the offset correction data on a one-to-one basis.

  Then, the offset correction processing unit 453 performs offset correction of the image data using the image data and the offset correction data. Further, the gain correction processing unit 454 may perform gain correction on the image data subjected to offset correction.

  As described above, the image data input to the image processing unit 101 is subjected to offset correction pipeline processing considering temperature fluctuations by extracting offset correction data at the head of the image and accessing the offset image data.

  A second embodiment will be described. The first embodiment is different from the first embodiment in that it is embedded in a plurality of bits constituting pixel data of a predetermined pixel. Hereinafter, a process of embedding offset correction data in a plurality of bits of pixel data of the first pixel of image data will be described with reference to FIG.

  The offset correction data 501 is offset correction data of an image data row starting with D (1, 1) in the offset correction data group 308. Similarly, the offset correction data 502 is offset correction data of an image data row starting with D (n + 1, 1). The offset correction data 503 is offset correction data of an image data row starting with D (3n + 1, 1). The offset correction data 504 is a lower bit portion of the first pixel of the image data starting with D (1, 1).

  First, the offset correction data 356 is read from the register 309 and bit-decomposed. Here, the offset correction data 356 is 10 bits.

  In the offset correction data 356, each bit from the least significant bit Bit0 to the most significant bit Bit9 is sequentially changed to the least significant bit Bit0 of the image data from D (1,1) to D (10,1). Replaced. Reference numeral 356 denotes offset correction data of an image data row starting with D (1, 1) in the offset correction data group 308. Similarly, reference numeral 357 denotes offset correction data of an image data row starting with D (n + 1, 1).

  As described above, since the offset correction data is embedded only in the first pixel in one image data, the processing for embedding and extracting in the image data can be reduced. In addition, a pixel outside the range used as a captured image in the image data can be set as the first pixel. In this case, the image data can be prevented from being deteriorated in image quality by embedding the offset correction data. Each embodiment of the present invention can also be realized by a computer or a control computer executing a program (computer program). Further, a means for supplying a program to a computer, for example, a computer-readable recording medium such as a CD-ROM recording such a program or a transmission medium such as the Internet for transmitting such a program is also applied as an embodiment of the present invention. be able to. The above program can also be applied as an embodiment of the present invention. The above program, recording medium, transmission medium, and program product are included in the scope of the present invention.

  Although the present invention has been described in detail based on the embodiments, the present invention is not limited to these specific embodiments, and various forms within the scope of the present invention are within the scope of the present invention. included. Furthermore, the above-described embodiment is merely an embodiment of the present invention, and an invention that can be easily imagined from the above-described embodiment is also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 100 Imaging device 101 Image processing part 105 Sensor panel 120 Pixel array 202 Pixel 262 Data processing part 266 Transfer control part

Claims (18)

A pixel array in which a plurality of pixels that output signals corresponding to radiation or light are arranged;
A data processing unit for embedding offset correction data for offset correction of the image data in predetermined bits of a plurality of bits constituting pixel data corresponding to predetermined pixels in the image data based on the signal output from the pixel array When,
A transfer control unit that transfers the image data in which the offset correction data is embedded to an image processing unit that performs image processing using the offset correction data;
An imaging device comprising: A temperature sensor disposed in the pixel array for obtaining data relating to the temperature of the pixel array;
The imaging apparatus according to claim 1, wherein the offset correction data is determined based on temperature data of the pixel array acquired by the temperature sensor. The predetermined pixel has a top pixel of the image data,
The imaging apparatus according to claim 1, wherein the data processing unit embeds the offset correction data in a plurality of bits including at least the least significant bit or the least significant bit of the leading pixel.   The imaging according to any one of claims 1 to 3, wherein the data processing unit embeds the offset correction data in a plurality of continuous pixel data in a predetermined row or column of the image data. apparatus.   The data processing unit embeds the offset correction data in a pixel at a common position in each of the plurality of regions in the plurality of regions in the image data. The imaging apparatus according to item 1.   The imaging apparatus according to claim 5, wherein the position common to each of the plurality of regions includes at least one of a leading pixel, a leading row, and a leading column. A plurality of the pixel arrays;
7. The offset correction data is embedded in pixels in the plurality of areas corresponding to the plurality of pixel arrays, respectively, and in a common position in each pixel array. Imaging device. An AD converter having a plurality of AD converters for converting an analog signal output from the pixel array into a digital signal;
The imaging apparatus according to claim 7, wherein the AD conversion unit converts the analog signal into a digital signal by one AD converter corresponding to each of the plurality of regions.   9. The imaging apparatus according to claim 1, wherein the data processing unit determines the number of bits in which the offset correction data is embedded according to a noise level of the image data.   The data processing unit embeds the offset correction data in predetermined bits including at least one bit from the least significant bit to the fourth bit of pixel data of a predetermined pixel of the image data. The imaging device according to any one of 1 to 9.   11. The imaging apparatus according to claim 1, wherein the data processing unit embeds the offset correction data in pixels located at a common position in a plurality of continuous image data.   The imaging apparatus according to claim 1, wherein the data processing unit determines whether or not the offset correction data is embedded in the image data.   An image processing unit that performs image processing of the image data using the offset correction data on the image data in which the offset correction data is embedded The imaging device according to any one of claims 1 to 13,
An image pickup system comprising: an image processing unit that acquires image data in which the offset correction data is embedded from the image pickup device and performs image processing on the image data using the offset correction data. The imaging system according to claim 14,
The image processing unit, wherein the image processing unit performs image processing on the image data by switching the offset correction data for each of a plurality of regions. The imaging system according to claim 14 or 15,
The image processing unit
An imaging system, wherein the processing for acquiring the image data and the image processing are performed in parallel. A pixel array in which a plurality of pixels that output signals corresponding to radiation or light are arranged;
An imaging method of an imaging apparatus, comprising: a data processing unit that processes image data; and a transfer control unit that transfers image data processed by the data processing unit,
Offset correction data for the data processing unit to offset-correct the image data to predetermined bits in a plurality of bits constituting pixel data corresponding to predetermined pixels in the image data based on signals output from the pixel array Data processing step of embedding,
A transfer step in which the transfer control unit transfers the image data in which the offset correction data is embedded to an image processing unit that performs image processing using the offset correction data;
An imaging method comprising:   A computer program for executing the imaging method according to claim 17 on a computer.

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