JP2016009782A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fuse that can be easily cut off.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a conductive film pattern above a semiconductor substrate; forming a first insulating layer covering the conductive film pattern; etching the first insulating layer to form a groove to the first insulating layer, the conductive film pattern being disposed on the bottom of the groove; and forming, on the conductive film pattern, a conductive layer, which includes copper and has a side face in contact with a side face of the groove, to form a fuse including the conductive film pattern and the conductive layer.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  There is a fuse provided in the semiconductor device. For example, the fuse is used for a process of separating a defective element from an integrated circuit and replacing it with a normal element (see Patent Document 1).

  There are various types of fuses provided in a semiconductor device. In recent years, a fuse formed of copper (Cu) has attracted attention (see Patent Documents 1 to 4). This type of fuse can be formed simultaneously with the copper wiring (see Patent Documents 1 and 2). A fuse formed of Cu is cut by applying current or irradiating laser (see Patent Documents 1 to 4).

  A fuse that is cut by applying a current is called an electric fuse. Electrical fuses formed from Cu are often cut by electromigration. In order to facilitate the cutting of the fuse, a technique has been reported in which a metal cap (for example, a Co film) on a copper wiring that suppresses electromigration is not provided on the fuse (see Patent Document 2).

  By the way, regarding the formation of copper, research on the adhesion between Rh, Ir, Pd, Ta, Mo, Ru, Co, Os and Cu has been reported (Non-patent Document 1). In addition, research on electroless plating of copper on a Pd atomic layer has been reported (Non-Patent Document 2).

JP 2009-124060 A JP 2008-108956 A US 2009/0045484 A1 JP 2011-49252 A

Shao-Feng Ding, Hai-Sheng Lu, Fei Chen, Yu-Long Jiang, Guo-Pig Ru, David Wei Zhang, and Xin-Ping Qu, "Density Functional Theory Study of Cu Adhesion on Rh, Ir, Pd, Ta, Mo, Ru, Co, and Os Surfaces ", Japanese Journal of Applied Physics 50, 105701-5, 2011. Young-soon Kim, Gregory A. Ten Eyck, Dexian Ye, Christopher Jezewski, Tansel Karabacak, Hyung-shik Shin, Jay J. Senkevich, and Toh-Ming Lu, "Atomic Layer Deposition of Pd on TaN for Cu Electroless Plating", Journal of The Electrochemical Society, 152 (6), C376-C381, 2005.

  Since Cu wiring is generally formed so as to suppress electromigration and ensure reliability, it may be difficult to cut when Cu wiring is used as an electrical fuse.

  In order to solve the above problem, according to one aspect of the present manufacturing method, a step of forming a conductive film pattern above a semiconductor substrate, a step of forming a first insulating layer covering the conductive film pattern, Etching the first insulating layer to form a groove in which the conductive film pattern is disposed at the bottom in the first insulating layer; and copper on the conductive film pattern, and a side surface of the groove is a side surface of the groove There is provided a method for manufacturing a semiconductor device, comprising forming a conductive layer in contact with each other and forming a fuse including the conductive film pattern and the conductive layer.

  The disclosed method provides an electrical fuse that is significantly easier to cut.

FIG. 1 is an example of a longitudinal sectional view of a semiconductor device including an electrical fuse formed simultaneously with a copper wiring. FIG. 2 is an example of a longitudinal sectional view of a semiconductor device including the electrical fuse of the embodiment. FIG. 3 is a block diagram illustrating an example of the semiconductor device of the embodiment. FIG. 4 is a longitudinal sectional view for explaining an example of the method for manufacturing the semiconductor device of the embodiment. FIG. 5 is a longitudinal sectional view for explaining an example of the method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a longitudinal sectional view for explaining an example of the method for manufacturing the semiconductor device of the embodiment. FIG. 7 is a longitudinal sectional view for explaining an example of the method for manufacturing the semiconductor device of the embodiment. FIG. 8 is a longitudinal sectional view for explaining an example of a method for manufacturing a semiconductor device according to the embodiment. FIG. 9 is a longitudinal sectional view for explaining an example of the method for manufacturing the semiconductor device of the embodiment. FIG. 10 is a longitudinal sectional view for explaining an example of the method for manufacturing the semiconductor device of the embodiment. FIG. 11 is a flowchart for explaining a procedure for recording unused SRAM information in the fuse ROM. FIG. 12 is an example of a block diagram of the fuse ROM. FIG. 13 is a table showing an example of unused SRAM information. FIG. 14 is a diagram for explaining the state of the blown fuse.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. In addition, the same code | symbol is attached | subjected to the corresponding part even if drawings differ, and the description is abbreviate | omitted.

  The fuse formed of Cu is formed simultaneously with the copper wiring as described above. FIG. 1 is an example of a longitudinal sectional view of a semiconductor device including an electric fuse 1 formed simultaneously with a copper wiring. FIG. 2 is an example of a longitudinal sectional view of a semiconductor device including the electric fuse 2 of the embodiment. 1 and 2 show a part of a longitudinal sectional view of a semiconductor device having electric fuses 1 and 2.

  The electric fuse 1 in FIG. 1 is formed by the following procedure, for example.

  First, a semiconductor element (not shown) is formed on the surface of the semiconductor substrate 4. Next, a first interlayer insulating film 6 a is formed on the semiconductor substrate 4. A groove (not shown) corresponding to a copper wiring (not shown) and a groove 8a corresponding to the electric fuse 1 are formed in the first interlayer insulating film 6a. After the formation of these grooves, a barrier metal film (for example, TaN film) and a seed film (for example, Cu film) for suppressing the diffusion of Cu are formed on the first interlayer insulating film 6a, for example, PVD (Physical Vapor Deposition, For example, it is formed by sputtering.

  Thereafter, a Cu film filling the groove (not shown) corresponding to the copper wiring (not shown) and the groove 8a corresponding to the electric fuse 1 is grown on the seed film by electrolytic plating. A portion outside the groove of the grown Cu film is removed by CMP (Chemical Mechanical Polishing) to form a conductive layer 15 (hereinafter referred to as a Cu conductive layer) inside the groove 8a.

  By this CMP, the barrier metal film outside the groove 8a is etched, and the barrier metal layer 10a is formed inside the groove 8a. Further, the seed film outside the groove 8a is etched by this CMP, and the seed layer 12 is formed inside the groove 8a. As a result, a metal film 16 in which the barrier metal layer 10a and the seed layer 12 are stacked is formed to cover the bottom surface and side surfaces of the conductive layer 15.

  Thus, a copper wiring (not shown) and the electric fuse 1 are formed.

  Thereafter, a barrier insulating layer 14a (for example, a silicon carbonitride film) for preventing diffusion of Cu is formed on the electric fuse 1, the copper wiring (not shown), and the first interlayer insulating film 6a. A second interlayer insulating film 6b is further formed on the barrier insulating layer 14a.

  As a method for forming the electric fuse 1, a barrier metal film and a Cu film are deposited on the first interlayer insulating film 6a without forming the groove 8a, and the barrier metal film and the Cu film are formed by dry etching (etching). It is also conceivable to form the electric fuse 1. However, it is difficult to form (etch) the Cu film by dry etching.

  Therefore, the trench 8a formed in the first interlayer insulating film 6a is filled with Cu, and the portion grown outside the trench 8a is removed by CMP to form the electrical fuse 1. For this reason, the lower surface and the side surface of the Cu conductive layer 15 of the electric fuse 1 are in contact with the metal film 16 in which the barrier metal layer 10a and the seed layer 12 are laminated.

  The barrier metal layer 10a is provided in order to suppress diffusion of Cu that degrades elements on the semiconductor substrate 4. Since the barrier metal film (that is, the barrier metal layer 10a before CMP) has high adhesion to the Cu film, the Cu film suppresses peeling from the first interlayer insulating film 6a by the force applied during CMP.

  Electromigration is a phenomenon in which atoms in a metal to which an electric current is applied exchange momentum with electrons and move gradually toward the anode, resulting in defects (voids) in the vicinity of the cathode. Metal atoms exchanging momentum with electrons move through gaps between microcrystals contained in the metal (that is, grain boundaries), metal free surfaces, and the like. The path through which metal atoms pass is called a diffusion path.

  As in the conductive layer 15 of the electrical fuse 1 in FIG. 1, there is no free surface in the metal (for example, Cu) surrounded by other materials. In the metal in such a state, the metal atom moves along the interface between the metal surrounding the metal and the metal instead of the free surface. The ease of movement of metal atoms at the interface varies depending on the material surrounding the metal.

  When the metal is in contact with the insulator, a microscopic gap is generated at the interface between the metal and the insulator. Such a gap becomes a diffusion path. On the other hand, when the metal is in contact with another metal, it is difficult to form a diffusion path at the interface between the metals.

  In the embodiment, as shown in FIG. 2, a conductive layer 20 containing Cu is formed on the conductive film pattern 18 disposed at the bottom of the groove 8b by, for example, plating. Then, the conductive layer 20 whose entire side surface is in contact with the insulator (in FIG. 2, the first insulating layer 6a) is formed. Therefore, the area where the conductive layer 20 is in contact with the insulator is larger than the area where the conductive layer 15 of the electric fuse 1 in FIG. 1 is in contact with the insulator. Therefore, according to the embodiment, cutting by electromigration becomes much easier.

  The conductive layer 20 may be grown by CVD (Chemical Vapor Deposition). Plating and CVD do not grow a metal such as Cu on the insulating film. Therefore, the conductive layer 20 containing Cu grows on the conductive film pattern 18 in the trench 8b and does not grow on the surface of the first interlayer insulating film 6a.

(1) Overall Structure FIG. 3 is a block diagram illustrating an example of the semiconductor device 22 according to the embodiment.

  The semiconductor device 22 includes, for example, a CPU (Central Processing Unit, not shown), a ROM (Read Only Memory, not shown), a plurality of SRAMs 24a to 24c (Static Random Access Memory), and peripheral circuits (not shown). System LSI (Large Scale Integration). The semiconductor device 22 further includes a spare SRAM 24d (hereinafter referred to as a redundant SRAM), a fuse ROM 26, and a redundant selection control unit 28. The fuse ROM 26 is a one time programmable read only memory having the electric fuse 2 described with reference to FIG.

(2) Manufacturing Method FIGS. 4 to 10 are longitudinal sectional views for explaining an example of a method for manufacturing the semiconductor device 22 according to the embodiment.

(2-1) Formation of conductive film pattern (see FIGS. 4A to 4B)
First, as shown in FIG. 4A, an STI (Shallow Trench Isolation) 29 on a semiconductor substrate 4 (for example, a silicon substrate) and a semiconductor element 30 (for example, a metal oxide semiconductor (MOS) field effect transistor) surrounded by the STI 29 And form. Next, an insulating layer 32b (for example, a silicon oxide film) is formed to 200 nm to 500 nm (for example, 300 nm) on the semiconductor substrate 4 by PECVD (Plasma Enhanced Chemical Vapor Deposition), for example.

  A barrier metal film 34 containing at least one element of Ti, Ta, and Co is formed on the insulating layer 32b by, for example, PVD (for example, sputtering) in a range of 5 nm to 15 nm (preferably 10 nm). The barrier metal film 34 is preferably a titanium nitride film (TiN film), a tantalum nitride film (TaN film), or a cobalt nitride film (CoN film).

  Thereafter, a conductive film 36 (for example, Ru film, Co film, Pd film, Os film, Mo film, Rh film, Ir film) having a thickness of 5 nm to 15 nm (preferably 10 nm) is further formed on the barrier metal film 34. Form. The conductive film 36 may be formed by any of PECVD (Plasma-Enhanced Chemical Vapor Deposition), PEALD (Plasma-Enhanced Atomic Layer Deposition), and PVD (for example, sputtering).

  Next, on the conductive film 36, a silicon oxide film 38 having a thickness of about 30 nm, an antireflection film 40a having a thickness of about 30 nm (for example, a silicon nitride film (SiN film), the same applies hereinafter), and a photo film having a thickness of about 130 nm. A resist film is formed. Thereafter, the photoresist film is formed by photolithography to form a photoresist film pattern (hereinafter referred to as a resist pattern) 42 a corresponding to the electric fuse 2.

  The antireflection film 40a, the silicon oxide film 38, the conductive film 36, and the barrier metal film 34 are etched by dry etching through the resist pattern 42a. Thereby, as shown in FIG. 4B, a conductive film pattern 44 and a pattern 46 of the barrier metal film 34 (hereinafter referred to as a barrier metal pattern) are formed. Thereafter, the antireflection film 40a is removed.

  As a result, the conductive film pattern 44 is formed above the semiconductor substrate 4.

  Incidentally, a conductive film containing at least one element selected from the group consisting of Ru, Co, Pd, Os, Mo, Rh, and Ir (hereinafter referred to as Ru, etc.) (in particular, a Ru film, a Co film, a Pd film, Os film, Mo film, Rh film, Ir film) and Cu lattice constant mismatch (see Non-Patent Document 1) are small. Specifically, the lattice constant mismatch between the conductive film containing Ru and the like and Cu is smaller than the lattice constant mismatch between Pd (see Non-Patent Document 2) and Cu capable of electroless plating of Cu.

  For this reason, the conductive layer 20 containing Cu can be easily grown on the conductive film containing Ru or the like by plating or CVD. Therefore, the conductive film pattern 44 preferably includes at least one element selected from the group consisting of Ru, Co, Pd, Os, Mo, Rh, and Ir.

  The formation of the barrier metal film 34 can be omitted (see FIG. 2). However, the adhesion between the conductive film (for example, Ru film) and the insulating film (for example, silicon oxide film) is improved by providing a barrier metal film between the conductive film and the insulating film. Therefore, it is preferable not to omit the formation of the barrier metal film 34.

  The barrier metal film 34 suppresses the diffusion of Cu contained in the conductive layer 20 (see FIG. 2). Therefore, when the formation of the barrier metal film 34 is omitted, it is preferable to form a barrier insulating film (for example, a silicon carbonitride film) that prevents Cu diffusion instead of the barrier metal film 34.

  When the size of the conductive film pattern 44 is sufficiently large, the formation of the antireflection film 40a can be omitted (the same applies to photolithography described later).

(2-2) Formation of insulating layer (see FIG. 4C)
Next, a silicon oxide film having a thickness of 150 nm to 450 nm (for example, 300 nm) is deposited on the semiconductor substrate 4 on which the conductive film pattern 44 is formed, for example, by PECVD. Thereafter, the deposited silicon oxide film is planarized by CMP (Chemical Mechanical Polishing). At this time, the silicon oxide film is planarized so that the distance between the planarized silicon oxide film and the conductive film pattern 44 is, for example, 75 nm to 25 nm (for example, 50 nm). Thereby, as shown in FIG. 4C, a first insulating layer 32a (interlayer insulating film) covering the conductive film pattern 44 is formed.

In the above example, the first insulating layer 32a and the insulating layer 32b below the conductive film pattern 44 (hereinafter referred to as the second insulating layer) are insulating layers having a silicon oxide film (for example, a SiO ₂ film). . However, the first insulating layer 32a and the second insulating layer 32b may be insulating layers having an insulating film other than the silicon oxide film (for example, a silicon carbonitride film (SiCN film)).

(2-3) Formation of vias (see FIGS. 5A to 6A)
Next, an antireflection film 40b (see FIG. 5A) having a thickness of about 30 nm and a photoresist film having a thickness of about 130 nm are formed on the surface of the first insulating layer 32a. Thereafter, the photoresist film is formed by photolithography to form a resist pattern 42b having an opening 48a corresponding to the contact hole 47 (see FIG. 5B).

  Through the resist pattern 42b, the antireflection film 40b, the first insulating layer 32a, and the second insulating layer 32b are etched by dry etching to form a contact hole 47 that reaches the semiconductor element 30 (see FIG. 5B). Form. Thereafter, the antireflection film 40b is removed.

  Next, as shown in FIG. 5C, a barrier metal film 50 for wiring (for example, a titanium nitride film (TiN film), a tantalum nitride film (TaN film)) is formed on the semiconductor substrate 4 in which the contact holes 47 are formed. , Cobalt nitride film (CoN film, etc.) and conductive film 52 for wiring (for example, tungsten film) are deposited by, for example, PVD or CVD.

  Thereafter, the conductive film 52 and the barrier metal film 50 are removed by CMP to form a wiring 54a (hereinafter referred to as a via) in the contact hole as shown in FIG.

(2-4) Formation of groove (see FIGS. 6B to 7C)
Next, as shown in FIG. 6B, a protective film 56 (for example, a silicon carbonitride film) having a thickness of 15 nm to 45 nm (for example, 30 nm) is formed on the first insulating layer 32a and the via 54a by, for example, PECVD. To form. The protective film 56 is an insulating film that protects the via 54a from oxidation.

  On the protective film 56, an antireflection film 40c (see FIG. 6C) having a thickness of about 30 nm and a photoresist film having a thickness of about 130 nm are formed. Thereafter, this photoresist film is formed by photolithography to form a resist pattern 42c having an opening 48b corresponding to the electric fuse 2.

  Through the resist pattern 42c, the antireflection film 40c, the protective film 56, the first insulating layer 32a, and the silicon oxide film 38 are etched by dry etching, and as shown in FIG. Expose the surface. Thereby, the groove 8c is formed in the first insulating layer 32a. Thereafter, the antireflection film 40c is removed.

  Next, as shown in FIG. 7B, an insulating film 58 (for example, a silicon carbonitride film) that suppresses diffusion of Cu is deposited on the semiconductor substrate 4 from which the conductive film pattern 44 is exposed, for example, by PECVD. At this time, the insulating film 58 covers the side surface of the first insulating layer 32a formed by dry etching.

  The insulating film 58 is etched by dry etching until the conductive film pattern 44 is exposed as shown in FIG. Then, a groove 8b having a third insulating layer 32c (for example, a silicon carbonitride film) different from the first insulating layer 32a is formed on the side surface.

  As described above, the groove 8b in which the conductive film pattern 44 is disposed at the bottom is formed in the first insulating layer 32a.

(2-5) Formation of conductive layer (see FIG. 8A)
Next, as shown in FIG. 8A, a conductive film containing copper having a thickness of, for example, 25 nm to 75 nm (preferably 50 nm) is formed on the conductive film pattern 44 by electroless plating or CVD (chemical vapor deposition method). Layer 62 is grown. At this time, the conductive layer 62 is selectively formed on the conductive film pattern 44 having high adhesion because it has low adhesion to the protective film 56 that is an insulating film. The conductive layer 62 is an example of the conductive layer 20 described with reference to FIG.

  The conductive layer 62 may include at least one of impurity elements composed of Ni, Sn, Ag, Co, Ge, and Si. The ratio of the impurity element to Cu is preferably 10 atomic% or less.

  Thus, the conductive layer 62 containing copper and having a side surface in contact with the side surface of the groove 8b (see FIG. 7C) is formed on the conductive film pattern 44. Specifically, for example, as shown in FIG. 8A, a conductive layer 62 in contact with the third insulating layer 32c is formed. As a result, an electric fuse 64 including the conductive layer 62, the conductive film pattern 44, and the barrier metal pattern 46 is formed.

  The conductive film pattern 44 is an example of the conductive film pattern 18 described with reference to FIG. The electric fuse 64 is an example of the electric fuse 2 described with reference to FIG.

  The conductive layer 62 is preferably formed so as not to protrude from the groove 8b (that is, stay in the groove 8b). The barrier metal pattern 46 can be omitted as described above.

(2-6) Formation of upper surface barrier insulating layer (see FIG. 8B)
As shown in FIG. 8B, a fourth insulating layer 32d (for example, a silicon carbonitride film) in contact with the upper surface of the conductive layer 62 is formed on the semiconductor substrate 4 on which the fuse 64 is formed by, for example, PECVD.

  The third insulating layer 32c (see FIG. 8A) and the fourth insulating layer 32d are barrier insulating layers (for example, insulating films having a silicon carbonitride film) that suppress diffusion of Cu. When the reliability required for the semiconductor element 30 is not high, the formation of the third insulating layer 32c and the fourth insulating layer 32d can be omitted.

(2-7) Formation of wiring layer (see FIGS. 9 to 10)
An interlayer insulating film 66 (for example, a silicon oxide film) is formed on the semiconductor substrate 4 on which the fourth insulating layer 32d is formed. In the interlayer insulating film 66, a plurality of contact holes reaching at least both ends of the via 54a and the fuse 64 and a groove for connecting the contact holes (hereinafter referred to as a wiring groove) are formed.

  A barrier metal film (for example, a tantalum nitride film (TaN film)) and a seed film (for example, Cu film) are formed by, for example, PVD (for example, sputtering) on the interlayer insulating film 66 in which the contact holes and wiring grooves are formed. To do.

  Thereafter, a Cu film filling the contact hole and the wiring groove is grown on the seed film by, for example, electrolytic plating. A portion of the grown Cu film outside the trench is removed by CMP to form a via 54b and a wiring 70. By this CMP, the barrier metal film outside the trench is removed, and the barrier metal layer 10b covering the bottom surface and the side surface of the via 54b and the wiring 70 is formed.

  For example, the barrier insulating layer 14b is formed on the interlayer insulating film 66 in which the via 54b and the wiring 70 are formed. Thus, the wiring layer 72a is formed.

  Thereafter, one or more wiring layers (not shown) are further formed on the wiring layer 72 a according to the structure of the semiconductor device 22.

  Finally, as shown in FIG. 10, external electrode pads 74 are formed on the uppermost wiring layer 72b. The external electrode pad 74 is connected to the semiconductor element 30 and / or the electric fuse 64 through wirings and / or vias formed in the first insulating layer 32a, the second insulating layer 32b, and the wiring layers 72a and 72b. The uppermost wiring layer 72b is covered with a passivation film 76 such as polyimide.

  Thus, the semiconductor device 22 of the embodiment is formed.

(3) Structure near the fuse As shown in FIG. 10, the semiconductor device 22 of the embodiment is formed on the semiconductor substrate 4, the first insulating layer 32a formed on the semiconductor substrate 4, and the first insulating layer 32a. Groove 8b (see FIG. 7C).

  The semiconductor device 22 further includes a conductive film pattern 44 disposed at the bottom of the groove 8b and a conductive film pattern 44 (preferably in the groove 8b), and has a side surface in contact with the side surface of the groove 8b and containing copper. An electric fuse 64 having a conductive layer 62 is provided.

  In the semiconductor device 22 of the embodiment, since the side surface of the conductive layer 62 containing copper is in contact with the insulator (in the example shown in FIG. 10, the third insulating layer 32c), the side surface is the metal film 16 (see FIG. 1). Electromigration is much more likely to occur than the conductive layer 15 in contact with the electrode. Therefore, the electric fuse 64 of the embodiment is easier to cut than the fuse 1 described with reference to FIG.

(4) Usage -Record of unused SRAM information-
FIG. 11 is a flowchart for explaining a procedure for recording unused SRAM information to be described later in the fuse ROM 26 (see FIG. 3). FIG. 12 is an example of a block diagram of the fuse ROM 26.

  As shown in FIG. 12, the fuse ROM 26 includes, for example, a first electric fuse 2a and a second electric fuse 2b. The first electric fuse 2a and the second electric fuse 2b are the electric fuses 64 described with reference to FIGS.

  The fuse ROM 26 further includes a first MOS field effect transistor 100a and a second MOS field effect transistor 100b. The source and drain of the first MOS field effect transistor 100a are connected to the ground plane 102 and one end of the first electric fuse 2a, respectively. Similarly, the source and drain of the second MOS field effect transistor 100b are connected to the ground plane 102 and one end of the second electric fuse 2b, respectively.

  The fuse ROM 26 further includes a cutting power supply circuit 110 to which the other end of the first electric fuse 2a and the other end of the second electric fuse 2b are connected. The cutting power supply circuit 110 is a circuit that outputs a current supplied from an external power supply.

  The fuse ROM 26 further includes a first cutting determination circuit 104a and a second cutting determination circuit 104b. The first disconnection determination circuit 104a is connected to both ends of the first electric fuse 2a and the first signal line 106a. Similarly, the second disconnection determination circuit 104b is connected to both ends of the second electric fuse 2b and the second signal line 106b. Each of the first signal line 106a and the second signal line 106b is connected to the redundancy selection control unit 28 (see FIG. 3).

  The fuse ROM 26 further includes a disconnection control circuit 108 connected to the gate of the first MOS field effect transistor 100a and the gate of the second MOS field effect transistor 100b.

  The unused SRAM information is information indicating an SRAM (hereinafter, referred to as an unused SRAM) that is determined not to be used among the SRAMs 24a to 24c. The unused SRAM information is determined by the procedure shown in FIG.

  First, the SRAMs 24a to 24c are tested using, for example, an IC (Integrated Circuit) tester (S2).

  If a defective SRAM is detected as a result of the test, the detected defective SRAM is determined as an SRAM that does not use (S4).

  Thereafter, unused SRAM information is created and recorded in the fuse ROM 26 (S6).

  Specifically, the unused SRAM information is, for example, a bit string. FIG. 13 is a table showing an example of unused SRAM information. The first column of FIG. 13 shows the second digit of unused SRAM information (hereinafter referred to as the second bit). The second column of FIG. 13 shows the first digit of unused SRAM information (hereinafter referred to as the first bit). In the third column of FIG. 13, unused SRAM is shown. For example, the unused SRAM corresponding to the unused SRAM information “01” is the first SRAM 24a. Unused SRAM information “00” indicates that there is no unused SRAM.

  The unused SRAM information is recorded in the fuse ROM 26 as follows, for example. FIG. 14 is a diagram illustrating the state of the cut electric fuse.

  First, unused SRAM information is input to the cutting control circuit 108 (see FIG. 12). Then, the disconnection control circuit 108 applies a voltage corresponding to the input unused SRAM information to the gate of the first MOS field effect transistor 100a. Similarly, the disconnection control circuit 108 applies a voltage corresponding to the input unused SRAM information to the gate of the second MOS field effect transistor 100b. Thereafter, the cutting control circuit 108 makes the cutting power supply circuit 110 ready to supply current.

  For example, when the first bit of the input unused SRAM information is “1”, the disconnection control circuit 108 applies a voltage higher than the threshold value to the gate of the first MOS field effect transistor 100a. Then, the first MOS field effect transistor 100a becomes conductive, and current is supplied from the cut power supply circuit 110 to the first electric fuse 2a. This current supply causes electromigration, and a void 74 (see FIG. 14) is generated in the conductive layer 62 of the first electric fuse 2a. As a result, the cathode side of the first electric fuse 2a is cut (disconnected).

  When the first bit of the inputted unused SRAM information is “0”, the disconnection control circuit 108 applies a voltage lower than the threshold value to the gate of the first MOS field effect transistor 100a. In this case, since the first MOS field effect transistor 100a is in a non-conductive state, no current is supplied to the first electric fuse 2a. Accordingly, the first electric fuse 2a is not cut.

  As described above, information corresponding to the first bit of the unused SRAM information is recorded in the first electric fuse 2a. Similarly, information corresponding to the second bit of the unused SRAM information is recorded in the second electric fuse 2b.

  The unused SRAM information is recorded in the fuse ROM 26 by the above procedure (S2 to S6). When the semiconductor device 22 (see FIG. 3) is restarted after recording the unused SRAM information, the fuse ROM 26 outputs the unused SRAM information to the first signal line 106a and the second signal line 106b.

  Specifically, the first disconnection determination circuit 104a determines whether or not the first electrical fuse 2a is disconnected. When determining that the first electrical fuse 2a is disconnected, the first disconnection determination circuit 104a outputs a high level signal to the first signal line 106a. On the other hand, when it is determined that the first electrical fuse 2a is not disconnected, the first disconnection determination circuit 104a outputs a low level signal to the first signal line 106a. Similarly, the second cut determining circuit 104b outputs a signal (high level signal or low level signal) corresponding to the state (cut or not cut) of the second electric fuse 2b to the second signal line 106b.

―Information processing of semiconductor devices―
When the semiconductor device 22 (see FIG. 3) is activated and information is input, the CPU (not shown) of the semiconductor device 22 processes the input information and outputs the result. At that time, the CPU accesses the SRAMs 24a to 24c via the redundancy selection control unit 28 (see FIG. 3).

  Specifically, the CPU transmits the memory address to the redundancy selection control unit 28 via the address bus 112a. Then, the redundancy selection control unit 28 refers to the fuse ROM 26 and determines whether or not the SRAM corresponding to the memory address (hereinafter referred to as the corresponding SRAM) is an unused SRAM.

  When the corresponding SRAM is not an unused SRAM, the redundancy selection control unit 28 connects the corresponding SRAM to the data bus 112b. When the corresponding SRAM is an unused SRAM, the redundancy selection control unit 28 connects the redundancy SRAM 24d to the data bus 112b.

  Thereafter, the CPU records data in the SRAM connected to the data bus 112b or reads data from the SRAM connected to the data bus 112b. FIG. 3 also shows a control bus 112c.

  The embodiment is illustrative and not restrictive.

  For example, the semiconductor device of the embodiment is a system LSI having an electrical fuse. However, the semiconductor device according to the embodiment may be a semiconductor device other than the system LSI. For example, the semiconductor device of the embodiment may be a PROM (Programmable Read Only Memory) having an electrical fuse.

The third insulating film and the fourth insulating film in the embodiment are silicon carbonitride films. However, the first insulating film and the second insulating film may be insulating films other than the silicon carbonitride film (for example, a silicon carbide (SiC _x ) film).

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
Forming a conductive film pattern above the semiconductor substrate;
Forming a first insulating layer covering the conductive film pattern;
Etching the first insulating layer to form a groove in the first insulating layer, the conductive film pattern being disposed at the bottom;
Forming a conductive layer containing copper and having a side surface in contact with the side surface of the groove on the conductive film pattern, and forming a fuse including the conductive film pattern and the conductive layer. .

(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the conductive film pattern includes at least one element selected from the group consisting of Ru, Co, Pd, Os, Mo, Rh, and Ir.

(Appendix 3)
In the step of forming the conductive film pattern,
Forming a barrier metal film containing at least one element of Ti, Ta and Co on a second insulating layer different from the first insulating layer;
Forming a conductive film corresponding to the conductive film pattern on the barrier metal film;
3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film and the barrier metal film are etched to form the conductive film pattern and the barrier metal film pattern.

(Appendix 4)
4. The appendix 1 to claim 3, wherein the groove has a third insulating layer on a side surface different from the first insulating layer, and the side surface of the conductive layer is in contact with the third insulating layer. Semiconductor device manufacturing method.

(Appendix 5)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 4, further comprising a step of forming a fourth insulating layer in contact with an upper surface of the conductive layer.

(Appendix 6)
The first insulating layer includes a silicon oxide film;
The second insulating layer has a silicon oxide film;
The third insulating layer has a silicon carbonitride film,
6. The method of manufacturing a semiconductor device according to appendix 5, wherein the fourth insulating layer includes a silicon carbonitride film.

(Appendix 7)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the conductive layer is formed by electroless plating or chemical vapor deposition.

(Appendix 8)
A semiconductor substrate;
A first insulating layer formed on the semiconductor substrate;
A groove formed in the first insulating layer;
A semiconductor device comprising: a conductive film pattern disposed at a bottom of the groove; and a fuse disposed on the conductive film pattern and having a side surface in contact with the side surface of the groove and a conductive layer containing copper.

(Appendix 9)
9. The semiconductor device according to appendix 8, wherein the conductive film pattern includes at least one element selected from the group consisting of Ru, Co, Pd, Os, Mo, Rh, and Ir.

(Appendix 10)
A second insulating layer disposed under the first insulating layer;
The barrier metal film pattern including at least one element of Ti, Ta, and Co, disposed between the second insulating layer and the conductive film pattern, Semiconductor device.

(Appendix 11)
The groove has a third insulating layer different from the first insulating layer on a side surface,
11. The semiconductor device according to claim 8, wherein a side surface of the conductive layer is in contact with the third insulating layer.

(Appendix 12)
The semiconductor device according to any one of appendices 8 to 11, further comprising a fourth insulating layer in contact with an upper surface of the conductive layer.

(Appendix 13)
The first insulating layer includes a silicon oxide film;
The second insulating layer has a silicon oxide film,
The third insulating layer has a silicon carbonitride film,
13. The semiconductor device according to appendix 12, wherein the fourth insulating layer includes a silicon carbonitride film.

2 ... electric fuse 4 ... semiconductor substrates 8a, 8b ... groove 18 ... conductive film pattern 20 ... conductive layer 22 ... semiconductor device 32a ... first insulating layer 32b ... Second insulating layer 32c ... third insulating layer 32d ... fourth insulating layer 34 ... barrier metal film 36 ... conductive film 44 ... conductive film pattern 46 ... barrier metal film pattern 62 ... Conductive layer 64 ... Electric fuse

Claims (6)

Forming a conductive film pattern above the semiconductor substrate;
Forming a first insulating layer covering the conductive film pattern;
Etching the first insulating layer to form a groove in the first insulating layer, the conductive film pattern being disposed at the bottom;
Forming a conductive layer containing copper and having a side surface in contact with the side surface of the groove on the conductive film pattern, and forming a fuse including the conductive film pattern and the conductive layer. . The method for manufacturing a semiconductor device according to claim 1, wherein the conductive film pattern includes at least one element selected from the group consisting of Ru, Co, Pd, Os, Mo, Rh, and Ir. The semiconductor device according to claim 1, wherein the groove has a third insulating layer different from the first insulating layer on a side surface, and the side surface of the conductive layer is in contact with the third insulating layer. Production method. A semiconductor substrate;
A first insulating layer formed on the semiconductor substrate;
A groove formed in the first insulating layer;
A semiconductor device comprising: a conductive film pattern disposed at a bottom of the groove; and a fuse disposed on the conductive film pattern and having a side surface in contact with the side surface of the groove and a conductive layer containing copper. The semiconductor device according to claim 4, wherein the conductive film pattern includes at least one element selected from the group consisting of Ru, Co, Pd, Os, Mo, Rh, and Ir. The groove has a third insulating layer different from the first insulating layer on a side surface,
The semiconductor device according to claim 4, wherein a side surface of the conductive layer is in contact with the third insulating layer.

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