JP2016009728A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve switching capacity at a corner part.SOLUTION: A semiconductor device comprises: a semiconductor substrate; a first electrode which contacts a surface of the semiconductor substrate; a second electrode which contacts the surface in an outer peripheral region; and a third electrode which contacts a rear face of the semiconductor substrate. The semiconductor substrate has a p-type region connected to the first electrode and the second electrode, and an n-type region which extends from a region on the underside of the p-type region across a region between the p-type region and an end face of the semiconductor substrate. The p-type region in the outer peripheral region has a straight line part and a corner part and a ratio of an area of the contacting part of the second electrode to an area of the p-type region exposed on the surface in the outer peripheral region is larger at the corner part than at the straight line part.

Description

  The technology disclosed in this specification relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device in which a diode is formed in an active region. In this semiconductor device, the anode region of the diode has an L portion extending to the outer peripheral side from the contact portion of the anode electrode.

JP 09-232597 A

  Like the L portion described above, the p-type region extending to the outer peripheral side from the contact portion of the electrode can be used not only for the diode but also for an IGBT or MOSFET. As described above, the semiconductor device having the p-type region extending to the outer peripheral side has a problem that the electric field is easily concentrated in the vicinity of the corner portion of the p-type region extending to the outer peripheral side, and the switching tolerance is low in the corner portion.

  The semiconductor device of the present invention contacts the surface in a semiconductor substrate, a first electrode in contact with the surface of the semiconductor substrate, and an outer peripheral region between a contact portion of the first electrode and an end face of the semiconductor substrate. And a third electrode in contact with the back surface of the semiconductor substrate in a range extending from the cell region overlapping the contact portion of the first electrode to the outer peripheral region. The semiconductor substrate extends from the cell region to the outer peripheral region, and is connected to the first electrode and the second electrode, and the p-type region extends from the lower region of the p-type region. And an n-type region extending over the region between the end faces of the semiconductor substrate and in contact with the p-type region. The p-type region in the outer peripheral region has a straight portion where the outer peripheral end extends linearly when the surface is viewed in plan, and a corner portion where the outer peripheral end extends in a curved shape when the surface is viewed in plan. The ratio of the area of the contact portion of the second electrode to the area where the p-type region is exposed on the surface in the outer peripheral region is larger than the linear portion at the corner portion.

  The n-type region may be in direct contact with the third electrode, or a p-type region may be interposed between the n-type region and the third electrode. The first electrode and the second electrode may be connected to each other or may be separated from each other. The “cell region overlapping with the contact portion of the first electrode” is a region overlapping with the contact portion of the first electrode when the semiconductor substrate is viewed in plan from the surface side. The “outer peripheral end” means an end on the end face side.

  In this configuration, when a high electric field is generated in the p-type region in the outer peripheral region, a current generated by the high electric field flows from the p-type region toward the second electrode. Since a higher electric field is generated in the corner portion than in the straight portion, the current flowing in the corner portion is higher than that in the straight portion. However, in this semiconductor device, since the ratio of the area of the contact portion of the second electrode in the corner portion is large, the current density in the corner portion can be reduced. This improves the switching tolerance of the corner portion.

1 is a plan view of a semiconductor device 10 of Example 1. FIG. FIG. 2 is a longitudinal sectional view of a semiconductor device 10 taken along line II-II in FIG. 1. The enlarged view of the peripheral p-type area | region 82. FIG. FIG. 3 is a longitudinal sectional view corresponding to FIG. 2 of a semiconductor device of Example 2. The longitudinal cross-sectional view corresponding to FIG. 2 of the semiconductor device of a modification. The longitudinal cross-sectional view corresponding to FIG. 2 of the semiconductor device of a modification.

First, features of the semiconductor device of Example 1 are listed. The following features are all independently useful.
(Feature 1) The cell region is surrounded by a p-type region in the outer peripheral region. The contact portion of the second electrode extends so as to surround the cell region. The width of the contact portion of the second electrode is wider than the straight portion at the corner portion.
(Feature 2) An IGBT or MOSFET in which a channel is formed in a p-type region is formed in the cell region.
(Feature 3) A diode having a p-type region as an anode is formed in the cell region.

  As illustrated in FIG. 1, the semiconductor device 10 according to the first embodiment includes a semiconductor substrate 12. Two emitter electrodes 14, a gate pad 16, and an outer peripheral electrode 18 are formed on the upper surface 12 a of the semiconductor substrate 12. In addition, although electrodes and insulating films other than these are also formed on the upper surface 12a of the semiconductor substrate 12, illustration thereof is omitted for easy viewing of the drawing. The two emitter electrodes 14 are formed side by side at the center of the semiconductor substrate 12. Hereinafter, a region that overlaps with a contact portion of the emitter electrode 14 (a contact portion between the emitter electrode 14 and the semiconductor substrate 12) when the upper surface 12a of the semiconductor substrate 12 is viewed in plan as shown in FIG. That is, the cell region 40 is a substantially central portion of the semiconductor substrate 12. A region located between the contact portion of the emitter electrode 14 and the end surface 12 b of the semiconductor substrate 12 when the upper surface 12 a of the semiconductor substrate 12 is viewed in plan is called an outer peripheral region 80. The gate pad 16 is formed next to the two emitter electrodes 14. The outer peripheral electrode 18 is formed on the upper surface 12 a in the outer peripheral region 80. The outer peripheral electrode 18 extends around the two emitter electrodes 14 (that is, the cell region 40).

  As shown in FIG. 2, an emitter region 44, a body region 46, a drift region 48, a collector region 50, and a gate electrode 54 are formed in the semiconductor substrate 12 in the cell region 40.

  A plurality of trenches are formed in the upper surface 12 a of the semiconductor substrate 12 in the cell region 40. The inner surface of each trench is covered with a gate insulating film 56. A gate electrode 54 is disposed inside each trench. Each gate electrode 54 is insulated from the semiconductor substrate 12 by a gate insulating film 56. The upper surface 12 a of each gate electrode 54 is covered with an insulating film 58. Each gate electrode 54 is insulated from the emitter electrode 14 by an insulating film 58.

  A plurality of emitter regions 44 are formed in an island shape in a range exposed on the upper surface 12 a of the semiconductor substrate 12. Each emitter region 44 is formed in a range in contact with the gate insulating film 56. Each emitter region 44 is n-type and has a high impurity concentration. Each emitter region 44 is ohmically connected to the emitter electrode 14.

  Body region 46 is p-type. The body region 46 is formed between the two emitter regions 44 and below the emitter region 44. The body region 46 is exposed on the upper surface 12 a of the semiconductor substrate 12 between the two emitter regions 44. The body region 46 has a high p-type impurity concentration at the position of the upper surface 12 a of the semiconductor substrate 12. The body region 46 is ohmically connected to the emitter electrode 14. The body region 46 is formed in a range shallower than the lower end of the gate electrode 54. The body region 46 below the emitter region 44 has a low p-type impurity concentration. The body region 46 is in contact with the gate insulating film 56 below the emitter region 44.

  A drift region 48 is formed below the body region 46. The drift region 48 is n-type. The n-type impurity concentration in the drift region 48 is low. The drift region 48 is separated from the emitter region 44 by the body region 46. The drift region 48 is formed across the cell region 40 and the outer peripheral region 80. The drift region 48 extends to the end face 12 b of the semiconductor substrate 12.

  A collector region 50 is formed below the drift region 48. The collector region 50 is p-type. The collector region 50 has a high p-type impurity concentration. Collector region 50 is separated from body region 46 by drift region 48. The collector region 50 is formed from the cell region 40 to the outer peripheral region 80. The collector region 50 extends to the end surface 12 b of the semiconductor substrate 12. The collector region 50 is exposed on the lower surface 12 c of the semiconductor substrate 12.

  A collector electrode 20 is formed over the entire lower surface 12 c of the semiconductor substrate 12. The collector electrode 20 is ohmically connected to the collector region 50.

  An IGBT is formed in the cell region 40 with the above-described configuration.

  In the semiconductor substrate 12 in the outer peripheral region 80, a peripheral p-type region 82, three guard rings 84, and an outer peripheral end n-type region 88 are formed.

  The peripheral p-type region 82 is p-type and is in contact with the body region 46. That is, the peripheral p-type region 82 is a p-type region continuous from the body region 46. The body region 46 and the peripheral p-type region 82 can also be regarded as one p-type region. Peripheral p-type region 82 has a lower p-type impurity concentration than body region 46. The peripheral p-type region 82 is exposed on the upper surface 12 a of the semiconductor substrate 12 in the outer peripheral region 80. A drift region 48 is formed below and to the sides of the peripheral p-type region 82. The upper surface 12 a in the outer peripheral region 80 is covered with an insulating film 81. However, an opening 18a is partially formed in the insulating film 81 above the peripheral p-type region 82, and the outer peripheral electrode 18 is formed in the opening 18a. The outer peripheral electrode 18 is connected to the peripheral p-type region 82 in the opening 18a. That is, the opening 18 a is a contact portion where the outer peripheral electrode 18 and the peripheral p-type region 82 are in contact. The contact portion 18a of the outer peripheral electrode 18 extends so as to make a round around the cell region 40, similarly to the outer peripheral electrode 18 shown in FIG.

  FIG. 3 shows the arrangement of the peripheral p-type region 82 and the contact portion 18a when viewed from the upper surface 12a side of the semiconductor substrate 12. FIG. 3 shows an enlarged view of the vicinity of the corner 14a of the emitter electrode 14 shown in FIG. As shown in FIG. 3, the outer peripheral end 14 b of the emitter electrode 14 extends linearly at a position away from the corner 14 a of the emitter electrode 14. At a position adjacent to the outer peripheral end 14 b of the linear emitter electrode 14, the outer peripheral end 82 a of the peripheral p-type region 82 extends linearly in parallel with the outer peripheral end 14 b of the emitter electrode 14. Hereinafter, the portion having the linear outer peripheral edge 82a in the peripheral p-type region 82 is referred to as a straight portion 83a. On the other hand, at the corner portion 14a of the emitter electrode 14, the outer peripheral end 14b of the emitter electrode 14 extends in a curved shape (for example, an arc shape). At a position adjacent to the outer peripheral end 14 b of the curved emitter electrode 14, the outer peripheral end 82 a of the peripheral p-type region 82 extends in a curved shape (for example, an arc shape) in parallel with the outer peripheral end 14 b of the emitter electrode 14. Hereinafter, a portion having the curved outer peripheral edge 82a in the peripheral p-type region 82 is referred to as a corner portion 83b. In the straight portion 83a, the contact portion 18a extends linearly along the straight portion 83a. In the straight portion 83a, the contact portion 18a has a certain width W1. In the corner portion 83b, the contact portion 18a extends in a curved shape (for example, an arc shape) along the corner portion 83b. In the corner portion 83b, the width of the contact portion 18a is wider as the position is farther from the straight portion 83a. In the corner portion 83b, the contact portion 18a has a width W2 at the widest portion. The width W2 is about twice the root of the width W1. Further, the distance from the outer peripheral end 18b of the contact portion 18a to the outer peripheral end 82a of the peripheral p-type region 82 is a constant distance W3 in both the corner portion 83b and the straight portion 83a. The configuration shown in FIG. 3 is formed in all four corner portions.

  As shown in FIG. 2, a gate wiring 87 is formed on the insulating film 81 above the peripheral p-type region 82. The gate wiring 87 is formed between the emitter electrode 14 and the outer peripheral electrode 18. The gate wiring 87 connects each gate electrode 54 and the gate pad 16.

  The guard ring 84 is a p-type region. Three guard rings 84 are formed at intervals on the outer peripheral side of the peripheral p-type region 82. Each guard ring 84 is exposed on the upper surface 12 a of the semiconductor substrate 12. Although not shown, each guard ring 84 extends around the cell region 40. The guard ring 84 closest to the peripheral p-type region 82 is separated from the peripheral p-type region 82 by the drift region 48. The three guard rings 84 are separated from each other by the drift region 48. An opening is formed in the insulating film 81 above each guard ring 84. Each guard ring 84 is connected to the electrode 86 through an opening.

  The outer peripheral end n-type region 88 is n-type and has an n-type impurity concentration higher than that of the drift region 48. The outer peripheral end n-type region 88 is exposed on the upper surface 12 a and the end surface 12 b of the semiconductor substrate 12. The outer peripheral end n-type region 88 is separated from the guard ring 84 by the drift region 48. An opening is formed in the insulating film 81 above the outer peripheral end n-type region 88. The outer peripheral end n-type region 88 is connected to the electrode 90 through an opening.

  Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is used, the same potential as that of the emitter electrode 14 is applied to the outer peripheral electrode 18. A higher potential than the emitter electrode 14 is applied to the collector electrode 20. In this state, when a potential equal to or higher than the threshold is applied to the gate electrode 54, a channel is formed in the body region 46 in a range in contact with the gate insulating film 56, and the IGBT is turned on. That is, electrons flow from the emitter electrode 14 to the collector electrode 20 through the emitter region 44, the channel, the drift region 48, and the collector region 50. Further, holes flow from the collector electrode 20 to the emitter electrode 14 through the collector region 50, the drift region 48, and the body region 46. Therefore, a current flows from the collector electrode 20 to the emitter electrode 14. Thereafter, when the potential of the gate electrode 54 is lowered below the threshold value, the channel disappears and the current stops. That is, the IGBT is turned off. Then, a depletion layer spreads from the peripheral p-type region 82 into the drift region 48 in the outer peripheral region 80. The guard ring 84 promotes the depletion layer to extend toward the end face 12 b side of the semiconductor substrate 12. For this reason, the depletion layer extends to the outer peripheral edge n-type region 88.

  When turning off the IGBT, a high voltage is applied to the IGBT due to the influence of the inductance of the circuit to which the semiconductor device 10 is connected. In particular, when the depletion layer extends in the outer peripheral region 80, a high electric field is generated in the outer peripheral region 80. When such a high electric field is generated, impact ions are generated in the outer peripheral region 80. The generated impact ions flow into the outer peripheral electrode 18. In addition, the electric field generated in the corner portion 83b of the peripheral p-type region 82 and the drift region 48 in the periphery thereof (hereinafter referred to as the vicinity of the corner portion 83b) causes the linear portion 83a of the peripheral p-type region 82 and the drift region 48 in the periphery thereof (hereinafter referred to as the vicinity). Higher than the electric field generated in the vicinity of the straight line portion 83a). In the configuration of the first embodiment, the electric field generated in the vicinity of the corner portion 83b is about twice the route of the electric field generated in the vicinity of the straight portion 83a. For this reason, more impact ions are generated in the vicinity of the corner portion 83b than in the vicinity of the straight portion 83a. The number of impact ions generated in the vicinity of the corner portion 83b is approximately twice the route of the number of impact ions generated in the vicinity of the straight portion 83a. Thus, more impact ions are generated in the vicinity of the corner portion 83b than in the vicinity of the straight portion 83a. In the semiconductor device 10 of the first embodiment, the contact portion 18a is wider at the corner portion 83b than at the straight portion 83a. For this reason, even if more impact ions flow into the contact portion 18a (that is, the outer peripheral electrode 18) in the vicinity of the corner portion 83b, the current density in the contact portion 18a of the corner portion 83b is not so high. In particular, in the first embodiment, impact ions about twice the route of the straight portion 83a flow in the corner portion 83b, whereas the width W2 of the contact portion 18a of the corner portion 83b is equal to the width W1 of the contact portion 18a of the straight portion 83a. The route is doubled. For this reason, even in the corner portion 83b where the electric field tends to concentrate, the current density can be suppressed to the same level as the straight portion 83a. For this reason, in the semiconductor device 10, the switching tolerance of the corner part 83b is high. As a result, the switching tolerance of the entire semiconductor device 10 can be improved.

  In the semiconductor device 10, the collector region 50 can be replaced with a high concentration n-type region. In this case, the element formed in the cell region 40 is not an IGBT but a MOSFET. Even if the MOSFET is formed in the cell region 40, according to the configuration of the contact portion 18a described above, the switching tolerance of the corner portion 83b can be improved.

  In the semiconductor device according to the second embodiment illustrated in FIG. 4, a diode is formed in the cell region 40. That is, in Example 2, the anode region 47, the drift region 48, and the cathode region 51 are formed in the cell region 40.

  The anode region 47 is p-type. The anode region 47 is exposed on the upper surface 12 a of the semiconductor substrate 12. The anode region 47 is ohmically connected to the anode electrode 14 on the upper surface 12a.

  The drift region 48 is configured in the same manner as the drift region 48 of the first embodiment.

  The cathode region 51 is n-type and has an n-type impurity concentration higher than that of the drift region 48. The cathode region 51 is formed below the drift region 48. The cathode region 51 is also formed in the outer peripheral region 80. The cathode region 51 is exposed on the lower surface 12 c of the semiconductor substrate 12. The cathode region 51 is ohmically connected to the cathode electrode 20 on the lower surface 12c.

  In Example 2, the electrode 14 at the center of the upper surface 12a functions as an anode electrode, and the electrode 20 on the lower surface 12c functions as a cathode electrode.

  Further, the outer peripheral region 80 of the second embodiment is configured in the same manner as the outer peripheral region 80 of the first embodiment shown in FIGS.

  Next, the operation of the semiconductor device of Example 2 will be described. When the semiconductor device 10 of the second embodiment is used, the same potential as that of the anode electrode 14 is applied to the outer peripheral electrode 18. When a forward voltage (a voltage at which the anode electrode 14 has a higher potential than the cathode electrode 20) is applied between the anode electrode 14 and the cathode electrode 20, the diode is turned on. That is, holes flow from the anode electrode 14 to the cathode electrode 20 through the anode region 47, the drift region 48, and the cathode region 51. Further, electrons flow from the cathode electrode 20 to the anode electrode 14 through the cathode region 51, the drift region 48, and the anode region 47. Therefore, a current flows from the anode electrode 14 to the cathode electrode 20. Thereafter, when a reverse voltage is applied between the anode electrode 14 and the cathode electrode 20, a depletion layer spreads from the peripheral p-type region 82 to the drift region 48 in the outer peripheral region 80. The guard ring 84 promotes the depletion layer to extend toward the end face 12 b side of the semiconductor substrate 12. For this reason, the depletion layer extends to the outer peripheral edge n-type region 88. When the depletion layer extends in the outer peripheral region 80, a high electric field is generated in the outer peripheral region 80. When such a high electric field is generated, impact ions are generated in the outer peripheral region 80. The generated impact ions flow into the outer peripheral electrode 18. Also in the semiconductor device of Example 2, the electric field generated near the corner portion 83b is larger than the electric field generated near the straight portion 83a. For this reason, the number of impact ions generated near the corner portion 83b is larger than the number of impact ions generated near the straight portion 83a. Also in the semiconductor device of the second embodiment, the contact portion 18a is wider at the corner portion 83b than at the straight portion 83a. For this reason, the current density in the corner portion 83b is not so high during the reverse recovery operation. For this reason, also in the semiconductor device 10 of Example 2, the switching withstand capability of the corner portion 83b is high.

  Further, when the diode performs the reverse recovery operation, holes existing in the drift region 48 in the outer peripheral region 80 are discharged from the peripheral p-type region 82 to the outer peripheral electrode 18. At this time, since holes flow into the corner portion 83b from the drift region 48 around the corner portion 83b, the flow rate of holes is larger in the corner portion 83b than in the straight portion 83a. However, since the contact portion 18a is wider in the corner portion 83b than in the straight portion 83a, the current density in the corner portion 83b is not so high during the reverse recovery operation. Thus, in the configuration of the second embodiment, an increase in current density at the corner portion 83b due to the concentration of holes flowing from the drift region 48 into the corner portion 83b can be suppressed.

  In the first and second embodiments described above, the current concentration at the corner portion 83b is suppressed by increasing the width of the contact portion 18a at the corner portion 83b. However, as long as the ratio of the area of the contact portion 18a to the area where the peripheral p-type region 82 is exposed on the upper surface 12a is larger than the straight portion 83a at the corner portion 83b, the contact portion 18a is arranged in any way. Good. If the area ratio is set in this way, current concentration in the corner portion 83b can be suppressed. That is, when the area of the upper surface 12a of the corner portion 83b is S1, the area of the contact portion 18a of the corner portion 83b is S2, the area of the upper surface 12a of the straight portion 83a is S3, and the area of the contact portion 18a of the straight portion 83a is S4. And S2 / S1> S4 / S3 need only be satisfied.

  In the first and second embodiments described above, the guard ring 84 is formed in the outer peripheral region 80. However, instead of the guard ring 84, the peripheral p-type region 82 is extended to the outer peripheral side as shown in FIG. May be. The peripheral p-type region 82 extended in this way functions as a RESURF layer.

  In the first embodiment described above, the emitter electrode 14 is separated from the outer peripheral electrode 18. However, if it is not necessary to arrange the gate wiring 87 between them, the contact portion 18a of the outer peripheral electrode 18 and the contact portion of the emitter electrode 14 are not connected as shown in FIG. The electrodes 18 may be connected to each other. In the second embodiment, the anode electrode 14 and the outer peripheral electrode 18 may be connected to each other in the same manner.

  Further, both the diode and the IGBT may be formed in the cell region 40. In the cell region 40, both a diode and a MOSFET may be formed.

  In addition, the electrode 14 of Examples 1 and 2 is an example of the 1st electrode of a claim, the electrode 18 of Examples 1 and 2 is an example of the 2nd electrode of a claim, and the electrode 20 of Example 1, 2 Is an example of the third electrode of the claims, the regions 46 and 82 of Examples 1 and 2 are examples of the p-type region of the claims, and the region 48 of Examples 1 and 2 is the n-type region of the claims. It is an example.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor device 12: Semiconductor substrate 14: Emitter electrode 16: Gate pad 18: Peripheral electrode 18a: Contact portion 20: Collector electrode 40: Cell region 44: Emitter region 46: Body region 48: Drift region 50: Collector region 54: Gate electrode 80: outer peripheral region 82: peripheral p-type region 83a: linear portion 83b: corner portion 84: guard ring 87: gate wiring 88: outer peripheral end n-type region

Claims (4)

A semiconductor device,
A semiconductor substrate;
A first electrode in contact with the surface of the semiconductor substrate;
A second electrode in contact with the surface in an outer peripheral region between a contact portion of the first electrode and an end face of the semiconductor substrate;
A third electrode in contact with the back surface of the semiconductor substrate in a range extending from the cell region overlapping the contact portion of the first electrode to the outer peripheral region;
Have
The semiconductor substrate is
A p-type region extending from the cell region to the outer peripheral region and connected to the first electrode and the second electrode;
An n-type region extending from a lower region of the p-type region to a region between the p-type region and the end face of the semiconductor substrate and in contact with the p-type region;
Have
The p-type region in the outer peripheral region has a straight portion where the outer peripheral end extends linearly when the surface is viewed in plan, and a corner portion where the outer peripheral end extends in a curved shape when the surface is viewed in plan ,
The ratio of the area of the contact portion of the second electrode to the area where the p-type region is exposed on the surface in the outer peripheral region is larger than the straight portion at the corner portion,
Semiconductor device. The cell region is surrounded by the p-type region in the outer peripheral region;
The contact portion of the second electrode extends so as to surround the cell region;
A width of the contact portion of the second electrode is wider than the straight portion at the corner portion;
The semiconductor device according to claim 1.   3. The semiconductor device according to claim 1, wherein an IGBT or a MOSFET in which a channel is formed in the p-type region is formed in the cell region. The semiconductor device according to claim 1, wherein a diode having the p-type region as an anode is formed in the cell region.

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