JP2015519744A - Integrated circuit design - Google Patents

Abstract

A method of forming a hybrid split gate type semiconductor. According to an embodiment of the method of the present invention, a plurality of first trenches are formed in a semiconductor substrate to a first depth. A plurality of second trenches are formed in the semiconductor substrate to the second depth. The plurality of first trenches are parallel to the plurality of second trenches. Further, some of the plurality of first trenches are alternately adjacent to some of the plurality of second trenches. [Selection] Figure 1

Description

Related projects

  [0001] This application is a part of co-pending and co-owned US patent application Ser. No. 12 / 603,028, “Split Gate Semiconductor device Curved Gate Oxide Profile” filed Oct. 21, 2009 by Gao et al. It is a continuation application and claims its priority. This application is a continuation-in-part of co-pending and co-owned US patent application Ser. No. 12 / 869,554 “Structures and Methods of Fabricating Split Gate MIS Devices” filed Aug. 26, 2010 by Terrill et al. Insist on that priority. This application is related to US patent application Ser. No. 13 / 460,600 filed Apr. 30, 2012, which claims its priority and the disclosure of which is incorporated herein by reference. All such applications are incorporated herein by reference in their entirety.

  [0002] Embodiments of the invention relate to the field of integrated circuit design and manufacture. Embodiments of the present invention relate more particularly to hybrid split gate semiconductor systems and methods.

  [0003] Split-gate power MOSFETs (metal oxide semiconductor field effect transistors) are understood to be advantageous over non-split-gate power MOSFETs. However, conventional split gate power MOSFETs do not substantially benefit from reduced process geometry, such as reduced gate pitch. In general, sub-micron cell pitch scaling is desirable for higher channel density, which reduces channel resistance per unit area. However, such scaling may undesirably reduce the mesa width per unit area and may increase the resistance of the drift region. In addition, as the density of the gate and shield electrodes increases, the gate charge and output capacitance can be deleteriously increased.

  [0004] Accordingly, there is a need for systems and methods for hybrid split gate semiconductor devices. In addition, there is a need for a hybrid split gate semiconductor device system and method with improved performance with finer, eg, smaller, gate pitch dimensions. There is a further need for a hybrid split gate semiconductor device system and method that is compatible and complementary to existing systems and methods of integrated circuit design, manufacturing, and testing. Embodiments of the present invention seek to meet these needs.

  [0005] In one embodiment according to the present technology, a semiconductor device includes a vertical channel region, a gate at a first depth on a first side of the vertical channel region, and a first side of the vertical channel region. A shield structure at a second depth and a hybrid gate at a first depth on a second side of the vertical channel region. There is no gate or electrode in the region below the hybrid gate on the second side of the vertical channel region.

  [0006] According to another embodiment of the present technology, the structure comprises a first elongated structure disposed directly under the surface of the semiconductor substrate. The first elongate structure comprises a gate structure at a first depth below the surface and a shield structure at a second depth below the surface. The structure further includes a second elongated structure formed immediately below the surface and having a hybrid gate structure at a first depth. There is no separate gate or electrode structure in this second elongated structure. The first and second elongated structures may be parallel.

  [0007] According to yet another embodiment of the present technology, a structure is formed to a first plurality of first trenches formed to a first depth in a semiconductor substrate and to a second depth in the semiconductor substrate. A second plurality of second trenches. The first trenches are parallel to the second trenches, and the first trenches alternate with the second trenches. The first trench may be filled with a first material including a first polysilicon and a second polysilicon on the first polysilicon.

  [0008] According to an embodiment of the method of the present technology, a plurality of first trenches are formed in a semiconductor substrate to a first depth. A plurality of second trenches are formed in the semiconductor substrate to the second depth. The plurality of first trenches are parallel to the plurality of second trenches. Further, some of the plurality of first trenches are alternately adjacent to some of the plurality of second trenches.

  [0009] According to another method embodiment of the present technology, a plurality of trenches are formed in a semiconductor substrate to a first depth. Some of the plurality of trenches are parallel to each other. Further, every other trench of the plurality of trenches is masked, and the depth of the unmasked trenches of the plurality of trenches is increased to the second depth. Further, the mask for deepening may be formed by a pattern layer of pad oxide.

  [0010] According to yet another method embodiment of the present technology, a vertical trench metal oxide semiconductor field effect transistor (MOSFET) device with a plurality of parallel filled trench structures is formed. The parallel filled trench structures are spaced apart by a pitch distance of 0.6 μm or less, and each of the parallel filled trench structures includes a MOSFET gate structure.

  [0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the following description, serve to explain the principles of the invention. Unless otherwise noted, the drawings are not drawn to scale.

It is sectional drawing of the trench part of a hybrid split gate type semiconductor device. It is a figure which concerns on the manufacturing method of a hybrid split gate type semiconductor. It is a figure which concerns on the manufacturing method of a hybrid split gate type semiconductor. It is a figure which concerns on the manufacturing method of a hybrid split gate type semiconductor. It is a figure which concerns on the manufacturing method of a hybrid split gate type semiconductor. It is a figure which concerns on the manufacturing method of a hybrid split gate type semiconductor. It is a figure which concerns on the manufacturing method of a hybrid split gate type semiconductor.

  [0014] Reference will now be made in detail to various embodiments of the invention to a method of forming a hybrid split gate semiconductor, as illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that it is not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one skilled in the art will understand that the invention may be practiced without these specific details. In other instances, detailed descriptions of well-known methods, procedures, components, and circuits are omitted so as not to obscure aspects of the present invention unnecessarily.

Notation and nomenclature
[0015] Some portions of the detailed descriptions that follow are presented as symbolic representations of operations on data bits that can be executed on computer memory, such as procedures, steps, logic blocks, processes, operations, etc. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. As used herein and generally, procedures, computer-executed steps, logic blocks, processes, operations, etc. are considered a consistent series of steps or instructions that lead to a desired result. Each step requires physical manipulation of physical quantities. Typically, these quantities are not necessarily so, but take the form of electrical or magnetic signals that can be stored, moved, combined, compared, or manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

  [0016] However, it should be noted that all of these terms and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specified in the discussion below, throughout the present invention, "attachment", "treatment", "separation", "formation", "dope", "filling", "etching", "rough surface" , Access, implementation, generation, adjustment, creation, execution, continuation, indexing, processing, operation, transformation, calculation ”,“ Determining ”,“ measuring ”,“ collecting ”,“ start-up ”, etc., the discussion uses the data represented as physical (electronic) quantities in registers and memory to manipulate computer system memory, It should be understood that it refers to the operation and processing of a computer system or similar electronic computing device that translates into a register, or other such data storage, transmission, or other data that is also represented as a physical quantity in a display device. .

  [0017] The drawings are not drawn to scale, and may show only a portion of a structure as well as the various layers that form the structure. Further, the manufacturing processes and operations may be performed in conjunction with the processes and operations discussed herein. That is, some process operations may exist before, during, and / or after the operations shown and described herein. It is important that embodiments in accordance with the present invention can be implemented in connection with these other (possibly conventional) processes and operations without significant confusion. In general, embodiments according to the present invention may replace and / or supplement a portion of a conventional process without significantly affecting the surrounding processes and operations.

  [0018] As used herein, the letter “n” represents an n-type dopant and the letter “p” represents a p-type dopant. A plus sign “+” or a minus sign “−” is used to indicate that the dopant concentration is relatively high or relatively low, respectively.

  [0019] As used herein, the term "channel" is used in a generally accepted manner. That is, in the FET, current moves through the channel from the source connection to the drain connection. The channel can be composed of either n-type or p-type semiconductor material. Thus, FETs are defined as either n-channel or p-channel devices. Some drawings are discussed in the context of n-channel devices, specifically n-channel power MOSFETs. However, the embodiment according to the present invention is not limited to this. That is, the features described herein can also be used in p-channel devices. The discussion regarding n-channel devices can be easily replaced with p-channel devices by using corresponding p-type dopants and materials instead of n-type dopants and materials, and vice versa.

  [0020] The term "trench" has two different but related meanings in semiconductor technology. In general, when referring to a process, such as etching, the term trench means or is used to refer to a cavity of material, such as a hole or groove. Also, in general, the length of such a hole is much larger than its width or depth. However, when referring to a semiconductor structure or device, the term trench is a solid vertical structure that is disposed directly under the surface of the substrate, has a complex configuration different from the substrate, and is adjacent to the channel of a field effect transistor (FET). Is used to mean or refer to. This structure comprises, for example, a FET gate. Thus, a trench semiconductor device typically comprises a mesa structure that is not a trench and a portion, eg, half, of two “trench” as adjacent structures.

  [0021] Although a semiconductor structure, commonly referred to as a "trench", can be formed by etching the trench and then filling the trench, the structural terminology is used herein with respect to embodiments of the invention. However, it should be understood that such processes are not implied and are not limited to such processes.

Method of forming hybrid split gate type semiconductor
[0022] FIG. 1 is a cross-sectional view of a trench portion of a hybrid split gate semiconductor device 100 according to an embodiment of the present invention. The hybrid split gate semiconductor device 100 includes a source electrode 110 in contact with a semiconductor material, for example, a mesa 101 of silicon. By doping the mesa 101, regions of the vertical trench metal oxide semiconductor field effect transistor, for example, the source regions 170 and 171, the body region 180, and the drift region 150 are formed. The figure shows exemplary conductivity types. For example, the source regions 170 and 171 may be n +, the body region 180 may be p, and the drift region 150 may be n or n +. In some embodiments, mesa 101 may include an epitaxially formed material. The hybrid split gate semiconductor device 100 further includes a drain region (not shown), usually at the bottom of the substrate, for example, below the mesa 101 of FIG.

  [0023] The hybrid split gate semiconductor device 100 also includes a gate 130 and a shield electrode 140 forming a split gate. Gate 130 is electrically coupled to a gate electrode (not shown). Shield electrode 140 is electrically coupled to source electrode 110. The gate 130 and the shield electrode 140 are separated by an oxide 121, such as a gate oxide.

  [0024] According to an embodiment of the present invention, the hybrid split gate semiconductor device 100 further comprises a hybrid gate 160. Hybrid gate 160 is electrically coupled to gate 130. The hybrid gate 160 is also separated from the mesa 101 by an oxide 120, such as a gate oxide.

  [0025] It should be understood that many trench power semiconductors include multiple rows of trenches, and the gates of many trenches are often coupled together. Embodiments according to the present invention are well adapted to such a configuration.

  [0026] According to an embodiment of the present invention, the hybrid split gate semiconductor device 100 comprises one gate on one side of the mesa, eg, the hybrid gate 160 on the left side of the mesa 101, as shown in FIG. Further, as shown in FIG. 1, a split gate structure is provided on the other side of the mesa, for example, a gate 130 and a shield electrode 140 are provided on the right side of the mesa 101.

  [0027] It should be understood that conventional split gate devices include split gates, eg, gate and shield electrodes, on both sides of the substrate mesa. According to embodiments of the present invention, the hybrid split gate semiconductor device 100 does not have split gate structures on both sides of the mesa, in contrast to conventional split gate devices. Rather, the hybrid split gate semiconductor device 100 does not have a second or shield electrode on one side of the mesa, for example, the left side of the mesa 101, as shown in FIG.

  [0028] According to the prior art, process miniaturization or trench pitch reduction often does not provide any benefit or adversely affects the performance of split gate trench MOSFETs (metal oxide semiconductor field effect transistors). There are even cases. For example, reducing the trench pitch can increase the channel width at a given die area, and it is advantageous to reduce channel resistance. However, when the trench pitch is reduced in this way, for example, the density of the shield electrode is increased, and the output capacitance may be increased harmfully.

  [0029] According to an embodiment of the present invention, the pitch of the shield electrodes is half of the total gate pitch. For example, for each shield electrode, eg, shield electrode 140, there are two gates, eg, gate 130 and hybrid gate 160. In this novel aspect, the channel resistance may be reduced by reducing the trench pitch while limiting the increase in output capacitance. For example, because each device has only one shield electrode, the channel resistance decreases more rapidly than the gate capacitance increases, leading to an overall improvement of such devices compared to the prior art. Another advantage of alternately removing every other shield electrode is current conduction due to mesa widening. Such mesa widening may reduce the total resistance of the power MOSFET.

  [0030] Power MOSFETs are often characterized by their “Figure of Merit”. The figure of merit refers to the product of the device channel resistance multiplied by the gate charge. In general, a device with a low figure of merit is more desirable.

[0031] Table 1 below shows results that demonstrate some of the advantages of the present invention.

  [0032] Each column in Table 1 corresponds to three exemplary test versions for a vertical trench MOSFET. The column labeled “Low Density Split Gate” refers to a device in a conventional split gate configuration designed for nominal 25V operation with a pitch of 0.8 μm. The column labeled “High Density Split Gate” refers to a device in a conventional split gate configuration designed for nominal 25V operation with a pitch of 0.6 μm. In particular, “high density split gate” devices are constructed with a denser, for example closer 0.6 μm pitch, compared to the 0.8 μm pitch in the case of “low density split gate” devices. The column labeled “High Density Hybrid Split Gate” refers to a device in a novel hybrid gate configuration designed for nominal 25V operation at a pitch of 0.6 μm, according to an embodiment of the present invention.

[0033] The term “resistance” in Table 1 refers to the “on” resistance of a MOSFET for a device with an active area of 1 mm ² and a gate bias of 4.5V. The term “gate charge” in Table 1 refers to the gate charge required to drive the gate terminal to 4.5V and turn on the gate in a device with an active area of 1 mm ² .

[0034] The term "output charge" in Table 1 refers to the charge associated with charging / discharging the source output capacitance of the drain when the MOSFET is switched from an on state to an off state, and is 1 mm ² active It is measured by nano coulomb for the region.

  [0035] The term "performance index" in Table 1 refers to the product of the device channel resistance multiplied by the gate charge, and is an indicator of the combination of its conduction loss and switching loss. For example, for a “low density split gate” device, the figure of merit is RDS2A * QG4.5 = 5.21 * 6.77 = 35.27. In general, a device with a low figure of merit is more desirable.

  [0036] It should be understood that "high density split gate" devices are generally less desirable than large "low density split gate" devices. For example, between these two devices, although many of the parameters are similar, the gate charge and output charge are significantly different. As a result, smaller pitch “high density split gate” devices are less desirable due to their higher figure of merit.

  [0037] In contrast, according to embodiments of the present invention, a "high density hybrid split gate" device is more resistant than both a "low density split gate" device and a "high density split gate" device. Has improved. It should be understood that the resistance has been significantly improved compared to conventional “low density split gate” devices, for example by approximately 20%.

  [0038] FIGS. 2A-2F illustrate a method of manufacturing a hybrid split gate semiconductor according to an embodiment of the present invention. 2A shows a first trench mask 220 applied to the pad oxide 230 applied to the substrate 210, according to an embodiment of the present invention. The substrate 210 may comprise a bulk material and / or one or more epitaxial layers.

  [0039] In accordance with an embodiment of the present invention, FIG. 2B illustrates a plurality of multiple layers in the substrate 210 via the pad oxide 230, eg, by a reactive ion etching (RIE) process, based on the first trench mask 220. A state where trenches 241 to 245 are formed is shown. It should be understood that in forming trenches 241-245, oxide 230 and substrate 210 may be etched separately. In some embodiments, the substrate 210 may include an epitaxially grown material. It should be understood that embodiments in accordance with the present invention are well suited to any suitable trench formation method. The trenches 241 to 245 are formed to a depth d1 below the surface of the substrate 210.

  [0040] In accordance with an embodiment of the present invention, FIG. 2C shows a second trench mask 250 applied over every other trench, eg, trenches 241, 243, 245. FIG. Optionally, the second trench mask 250 may fill the trench that it covers, eg, trenches 241, 243, 245. It should be understood that the trenches 242, 244 are not covered by the trench mask 250 and remain exposed.

  [0041] In accordance with an embodiment of the present invention, FIG. 2D shows the trenches 242 and 244 being etched to a deeper depth d2 below the surface of the substrate 210 to form deep trenches 252 and 254. FIG. The trenches 252 and 254 are etched by, for example, a reactive ion etching (RIE) process based on the pattern of the second trench mask 250 and the pad oxide 230. It should be understood that embodiments in accordance with the present invention are well suited to any suitable method of forming such trenches.

  [0042] According to embodiments of the present invention, the pad oxide 230 when the trenches 242 and 244 are etched can form a self-aligned mask for etching the trenches 253 and 254, so that the trench mask 250 is not necessarily used. Need not be aligned with the edges of the unexposed trenches 242, 244. For example, when the trenches 241 to 245 are formed, both the oxide 230 and the substrate 210 are etched, but it is not necessary to etch the oxide 230 in order to etch the trenches 242 and 244 deeper. A mask for etching the trenches 252 and 254 can be formed.

  [0043] In accordance with an embodiment of the present invention, FIG. 2E shows a first polysilicon 261 deposited in trenches 241, 243, 245 and deep trenches 252, 254. FIG. As will be described in detail below, the first polysilicon 261 will form the split or shield electrode of the hybrid split gate semiconductor device. In an etch back process, the poly p1 is etched away from all trenches to a depth of approximately d1. It should be understood that such a recess etch removes all the poly p1 261 from the trenches 241, 243, 245 and leaves the poly p1 261 only at the bottom of the deep trenches 252, 254.

  [0044] According to an embodiment of the present invention, FIG. 2F shows a second polysilicon 262 deposited in all trenches 241, 252, 243, 254, 245. FIG. At least deep trenches 252 and 254 may be formed with an oxide prior to filling with second polysilicon 262 to separate first polysilicon p1 161 from second polysilicon p2 262. . As discussed further below, the second polysilicon 262 forms a standard gate, eg, a top gate or “unshielded” electrode of a split gate semiconductor and a hybrid gate of a hybrid split gate semiconductor device. become.

  [0045] US patent application Ser. No. 12 / 603,028, “Split Gate Semiconductor device with Curved Gate Oxide Profile” filed Oct. 21, 2009 by Gao et al. And Terrill et al. US patent application Ser. No. 12 / 869,554, “Structures and Methods of Fabrication Split Gate MIS Devices,” is incorporated herein by reference in its entirety for additional details regarding the formation of split gate semiconductor devices. It is shown. Embodiments according to the present invention are compatible with the processes and materials described in these referenced applications.

  [0046] Referring to FIGS. 1 and 2F, polysilicon p2 262 in trench 254 forms a gate, eg, gate 130. The polysilicon p1 261 in the trench 254 forms a shield electrode, for example, a shield electrode 140. The polysilicon p2 262 in the trench 243 forms a hybrid gate, for example, the hybrid gate 160. Between trenches 254, 243, a portion of substrate 210 that may include bulk and / or epitaxial material forms a mesa, eg, mesa 101.

  [0047] It should be understood that the internal structure of the deep trench 254 and itself and the internal structure of the trench 245 and itself also form a hybrid split gate semiconductor device. In this configuration, the split gate is on the left side and includes, for example, a shield electrode formed by polysilicon p1 261 in deep trench 254 and a gate formed by polysilicon p2 262 in deep trench 254. The hybrid gate is on the right side, and is formed by, for example, polysilicon p2 262 in the trench 245. For example, a hybrid split gate semiconductor device formed by trench 245 and deep trench 254 and its own structure may be seen as a mirror image of hybrid split gate semiconductor device 100, as shown in FIG.

  [0048] Doping the regions between the trenches forms regions of the vertical trench metal oxide semiconductor field effect transistor, eg, source regions 170, 171, body region 180, and drift region 150, as shown in FIG. It should be understood that this may be done. Such doping may be performed before or after formation of the trench, and may be performed at different stages of processing. For example, the body region 180 and the drift region 150 may be doped before any trench formation, while the source regions 170, 171 may be doped after the trench formation and filling. Embodiments in accordance with the present invention are well suited to any sequence and / or process for doping various regions of a hybrid split gate semiconductor device.

  [0049] Embodiments in accordance with the present invention provide systems and methods for hybrid split gate semiconductor devices. In addition, embodiments according to the present invention provide systems and methods for hybrid split gate semiconductor devices with improved performance at finer gate pitch dimensions. Furthermore, embodiments according to the present invention provide systems and methods for hybrid split gate semiconductor devices that are compatible and complementary to existing systems and methods for integrated circuit design, manufacturing, and testing. provide.

  [0050] Various embodiments of the invention have been described above. While the invention has been described in certain embodiments, it should be understood that it is not to be construed as limited to such embodiments, but is to be construed in accordance with the following claims.

  [0051] All elements, parts, and steps described herein are preferably included. As will be appreciated by those skilled in the art, it should be understood that any of these elements, parts, or steps may be replaced with other elements, parts, or steps, or may all be deleted.

[0052] Concepts This specification discloses at least the following concepts.

Concept 1. Forming a plurality of first trenches in a semiconductor substrate to a first depth;
Forming a plurality of second trenches in the semiconductor substrate to a second depth,
The plurality of first trenches are parallel to the plurality of second trenches;
The method wherein the further trenches of the plurality of first trenches are alternately adjacent to some of the plurality of second trenches.

  Concept 2. The method of concept 1, further comprising filling the plurality of first trenches with a first polysilicon.

  Concept 3. The method of concept 2, further comprising the step of masking the plurality of first trenches prior to the filling step.

  Concept 4. 4. The method of concept 2 or 3, further comprising the step of filling the plurality of first trenches with a second polysilicon over the first polysilicon.

  Concept 5. 5. The method of concept 4, further comprising forming an oxide in the plurality of first trenches that separates the first and second polysilicon.

  Concept 6. 4. The concept 3 further comprising the step of filling the plurality of second trenches with the second polysilicon at substantially the same depth as the second polysilicon in the plurality of first trenches. Method.

  Concept 7. 7. The method of any one of concepts 1-6, further comprising doping a region between the plurality of first and second trenches to form a body region.

Concept 8. Forming a plurality of trenches in a semiconductor substrate to a first depth, wherein some of the plurality of trenches are parallel to each other; and
Masking every other trench of the plurality of trenches;
Increasing the depth of the unmasked trenches of the plurality of trenches to a second depth.

  Concept 9. 9. The method of concept 8, wherein the deep step mask is formed by a patterned layer of pad oxide.

  Concept 10. 10. The method of concept 8 or 9, further comprising filling the unmasked trenches of the plurality of trenches with a first polysilicon.

  Concept 11. 11. The method of any one of concepts 8 to 10, further comprising forming an oxide in the unmasked trench on the first polysilicon.

  Concept 12. 12. The method of concept 11, further comprising filling the plurality of trenches with a second polysilicon.

  Concept 13. The method of any one of concepts 8-12, further comprising forming a pad oxide on the semiconductor substrate.

  Concept 14. 14. The method according to any one of concepts 8-13, further comprising doping the region between the trenches to form a plurality of source regions.

Concept 15. Forming a vertical trench metal oxide semiconductor field effect transistor (MOSFET) with a plurality of parallel filled trench structures;
The parallel filled trench structures are separated by a pitch distance of 0.6 μm or less,
A method wherein each of the parallel filled trench structures comprises the gate structure of the MOSFET

Concept 16. The forming step is
A first sub-step of forming a first plurality of first trenches in a semiconductor substrate to a first depth;
Forming a second plurality of second trenches in the semiconductor substrate to a second depth; and
16. The method of concept 15, wherein the first trenches alternate with the second trenches.

Concept 17. The second sub-step to be formed is
A sub-substep for masking the first trench;
17. The method of concept 16, comprising a sub-substep of increasing the depth of the second trench to the second depth.

  Concept 18. 18. The method of concepts 16 or 17, wherein the forming step further comprises a substep of filling the first trench with a first polysilicon.

  Concept 19. 19. The method of concept 18, wherein the forming step further comprises a substep of filling the first and second trenches with a second polysilicon.

  Concept 20. 20. The method of any of concepts 15-19, wherein the forming step includes a substep of doping a region between the parallel filled trench structures to form a body region.

Claims (20)

Forming a plurality of first trenches in a semiconductor substrate to a first depth;
Forming a plurality of second trenches in the semiconductor substrate to a second depth,
The plurality of first trenches are parallel to the plurality of second trenches;
A method wherein further trenches of the plurality of first trenches are alternately adjacent to some of the plurality of second trenches.   The method of claim 1, further comprising filling the plurality of first trenches with a first polysilicon.   The method of claim 2, further comprising masking the plurality of first trenches prior to the filling step.   3. The method of claim 2, further comprising filling the plurality of first trenches with a second polysilicon over the first polysilicon.   The method of claim 4, further comprising forming an oxide in the plurality of first trenches that separates the first and second polysilicon.   4. The method of claim 3, further comprising: filling the plurality of second trenches with the second polysilicon at substantially the same depth as the second polysilicon in the plurality of first trenches. the method of.   The method of claim 1, further comprising doping a region between the plurality of first and second trenches to form a body region. Forming a plurality of trenches in a semiconductor substrate to a first depth, wherein some of the plurality of trenches are parallel to each other;
Masking every other trench of the plurality of trenches;
Increasing the depth of the unmasked trenches of the plurality of trenches to a second depth.   9. The method of claim 8, wherein a mask for the deepening step is formed by a patterned layer of pad oxide.   9. The method of claim 8, further comprising filling an unmasked trench of the plurality of trenches with a first polysilicon.   The method of claim 8, further comprising forming an oxide in the unmasked trench on the first polysilicon.   The method of claim 11, further comprising filling the plurality of trenches with a second polysilicon.   The method of claim 8, further comprising forming a pad oxide on the semiconductor substrate.   The method of claim 8, further comprising doping a region between the trenches to form a plurality of source regions. Forming a vertical trench metal oxide semiconductor field effect transistor (MOSFET) device with a plurality of parallel filled trench structures;
The parallel filled trench structures are spaced apart by a pitch distance of 0.6 μm or less;
A method wherein each of the parallel filled trench structures comprises a gate structure of the MOSFET. The forming step comprises:
A first sub-step of forming a first plurality of first trenches in a semiconductor substrate to a first depth;
Forming a second plurality of second trenches in the semiconductor substrate to a second depth; and
The method of claim 15, wherein the first trench alternates with the second trench. The second sub-step of forming comprises:
A sub-substep for masking the first trench;
And a sub-substep of increasing the depth of the second trench to the second depth.   The method of claim 16, wherein the forming step further comprises a sub-step of filling the first trench with a first polysilicon.   The method of claim 18, wherein the forming step further comprises a sub-step of filling the first and second trenches with a second polysilicon.   The method of claim 15, wherein the forming step includes a sub-step of doping a region between the parallel filled trench structures to form a body region.

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