JP2015508616A - Network system configured to resolve forward error correction in data mode - Google Patents

Abstract

One embodiment provides a method for resolving a forward error correction (FEC) protocol. The method includes: requesting by a network node element during an auto-negotiation period between a network node element and a link partner to resolve at least one FEC mode during the data mode period; Determining at least one channel quality parameter of the at least one channel of the communication link between in the data mode period by the network node element and based on at least one of the at least one channel quality parameter Determining whether to enable or disable at least one FEC mode in a data mode period by a network node element, and Ation period and data mode period, Ethernet is defined by (R) communication protocol, auto-negotiation period occurs before the data mode period. [Selection] Figure 1

Description

  This application claims benefits based on US Provisional Patent Application No. 61 / 670,099 (filing date: July 10, 2012). The entire contents of the provisional application are incorporated herein by reference.

  The present disclosure relates to a network system configured to resolve forward error correction. In particular, the present invention relates to a network system configured to solve the enablement of forward error correction in the data mode.

  Some conventional Ethernet network systems optionally further support a forward error correction (FEC) protocol to achieve packet integrity. The FEC protocol may be useful in channels with very low quality. The FEC protocol places a heavy load on the processor. When the FEC protocol is enabled, the system performance and latency are usually deteriorated, and the total power demand of the network node increases. According to the conventional Ethernet method, the FEC protocol is enabled during the auto-negotiation period between link partners. However, the auto-negotiation period usually does not keep track of the actual quality of the channel between link partners. Instead, conventional network systems measure channel quality in a link training sequence that is performed after the auto-negotiation period and before the data mode period. When enabled, conventional network systems cannot achieve dynamic adjustments to the FEC state. Thus, while the channel quality parameter can change during data mode operation, conventional network systems cannot dynamically enable / disable the FEC protocol in data mode, so conventional Ethernet A network system may unnecessarily degrade system performance and latency, unnecessarily increase the total power demand of the network segment, and / or unnecessarily degrade packet integrity.

The features and advantages of the claimed subject matter will become apparent from the following detailed description of the dependent embodiments. The following description should be read in conjunction with the accompanying drawings. The attached drawings are as follows.
1 is a diagram illustrating a network system according to various embodiments of the present disclosure. FIG. FIG. 3 is a diagram illustrating an example of a base page 120 ′ according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of a sequence order set 130 ′ according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of a training frame 138 ′ according to an embodiment of the present disclosure. 5 is a diagram illustrating an example of a coefficient update field 162 ′ according to an embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of a status report field 164 ′ according to an embodiment of the present disclosure. FIG. 5 is a flowchart of an operation according to an embodiment of the present disclosure. 6 is a flowchart of an operation according to another embodiment of the present disclosure. 6 is a flowchart of an operation according to another embodiment of the present disclosure. 6 is a flowchart of an operation according to another embodiment of the present disclosure. The following <DETAILED DESCRIPTION> refers to example embodiments, but many alternatives, modifications and variations will be apparent to those skilled in the art.

  The present disclosure relates generally to network systems (and methods) configured to enable and / or disable at least one FEC protocol during a data mode period (also referred to herein as a “link up state”). During the auto-negotiation period, the respective FEC functions of the node element and the link partner are specified, and the node element requests to resolve the specified FEC function in the link up state. In the data mode period, determine at least one channel quality parameter of at least one channel of the communication link between the network controller and the link partner. At least one FEC mode may be enabled or disabled based on the channel quality determined in the data mode. Multiple FEC modes may be enabled or disabled during the data mode period. For communication links having multiple channels, link quality may be determined for each channel, and each node element may enable multiple different FEC functions asynchronously based on individual channel quality measurement results.

  FIG. 1 is a diagram illustrating a network system 100 according to various embodiments of the present disclosure. Network system 100 generally comprises at least one network node element 102 and at least one link partner 118. Network node element 102 and link partner 118 are configured to communicate with each other via communication link 126. The network node element 102 and the link partner 118 may communicate with each other via the link 126 using an Ethernet communication protocol. The Ethernet (registered trademark) communication protocol may be able to realize communication using a transmission control protocol / Internet protocol (TCP / IP). The Ethernet (registered trademark) protocol is an Ethernet (registered trademark) standard published by the Institute of Electrical and Electronics Engineers (IEEE), “IEEE 802.3 standard” published in March 2002, and / or after this standard. It may be compliant with or conforming to a published version, for example, the IEEE 802.3 standard for Ethernet (registered trademark) published in 2012. Link partner 118 and / or node element 102 may represent a computer node element (eg, a host server system), a switch, a router, a hub, a network storage device, a network attached device, a non-volatile memory (NVM) storage device, and the like. Link partner 118 may perform similar configurations and operations as node 102. Further details will be described below.

  Node 102 typically includes a network controller 104 that is configured to communicate with link partner 118 using the Ethernet communication protocol described above. The network controller 104 is also typically in the order defined when a link is first established with the link partner 118 (eg, when a new link is established with the link partner at system initialization, etc.). It is configured to perform various operations. Such an operation may include, for example, an auto-negotiation period during which various functions of the node 102 and link partner 118 are exchanged. After the auto-negotiation period, there is a link training period that determines the quality of the communication link 126, and after the link training period, a link up state or data mode in which data frames / packets are exchanged between the node 102 and the link partner 118; Become. The auto-negotiation period, link training period, and data mode period may be defined in the IEEE 802.3 communication protocol described above.

  The network controller 104 includes a PHY circuit 106 that is generally configured to connect the node 102 and the link partner 118 via a communication link 126. The PHY circuit 106 is, for example, 10GBASE-KR, 40GBASE-KR4, 40GBASE-CR4, 100GBASE-CR10, 100GBASE-CR4, 100GBASE-KR4 and / or 100GBASE-KP4, and / or the above IEEE802.3 Ethernet (registered trademark). ) May be compliant or compatible with the above IEEE 802.3 Ethernet communication protocol, including other PHY circuits that are compliant with the communication protocol and / or compliant with future developed communication protocols . The PHY circuit 106 is configured to transmit data packets and / or data frames to the link partner 118 via the link 126 and data packets and data from the link partner 118 via the link 126. And / or a receiving circuit (Rx) 110 configured to receive the data frame. Of course, the PHY circuit 106 is further configured to perform analog-to-digital and digital-to-analog conversion, data encoding and decoding, analog parasitic cancellation (eg, crosstalk cancellation) and received data recovery. Encoding / decoding circuitry (not shown). The Rx circuit 110 may include a phase locked loop circuit (PLL, not shown) configured to adjust the timing of data reception from the link partner 118. The communication link 126 may include a media dependent interface including, for example, a copper twin-axial cable, a backplane wiring on a printed wiring board, and the like. According to some embodiments, communication link 126 may include multiple logical channels and / or, for example, that implement separate connections between Tx and Rx 108/110 of node 102 and Rx and Tx of link partner 118, respectively. Alternatively, a plurality of physical channels (eg, differential pair channels) may be included.

  The network controller 104 further includes a forward error correction (FEC) module 112 that is configured to perform forward error correction processing on packets that the network controller 104 transmits and receives. Generally, according to the above IEEE 802.3 Ethernet communication protocol (eg, clause 74 or clause 91), the FEC process encodes the transmitted data stream into FEC frames (eg, calculates parity check symbols). Including in a FEC-encoded frame) and performing a data integrity check (eg, recalculating parity for the received FEC frame and comparing it to the received parity symbol) and error correction; And decoding the received data stream. FEC is typically used when the quality of the communication link 126 falls below a threshold (eg, bit error ratio (BER) threshold, etc.) and other integrity checks (eg, CRC) performed on a packet-by-packet basis. , Hash, etc.). The FEC module 112 may be configured to perform a plurality of FEC processes including a plurality of FEC protocols or FEC modes, as defined by the IEEE 802.3 Ethernet communication protocol described above. For example, the FEC module 112 may be configured to perform “mild” FEC mode processing in which error correction (coding gain) and latency are set to a minimum or low threshold. As another example, the FEC module 112 may perform “severe” FEC mode processing in which the coding gain is set to a maximum threshold or a high threshold. The “mild” FEC mode is generally less expensive than the “severe” FEC mode at the cost of increased packet errors and reduced error correction and error detection (thus lower latency and power). It may be). As another example, the FEC module 112 may include multiple FEC modes and on a given medium (eg, backplane copper wiring or copper twinaxial cable) utilized for the communication link 126. It may be configured to operate in an appropriate FEC mode that is optimized accordingly. FEC utilizes coding gain to improve link budget and BER performance on a given channel. The link budget is composed of a plurality of electrical parameters that define the link 126, such as insertion loss, return loss, pulse response, and the like. Generally, when an FEC method is selected, there are incompatible factors such as latency, power, error correction and error detection functions, and ease of implementation. “Heavy” FEC codes are generally more sophisticated in error correction and error detection than “light” FEC codes, but at the expense of power, latency, and ease of implementation. The amount of FEC coding gain may be selected to meet the lowest link budget and lowest BER performance for a given medium.

  The network controller 104 further includes an auto-negotiation module 114 that is configured to perform auto-negotiation processing between the node 102 and the link partner 118. The auto-negotiation process may be defined by the above-described IEEE 802.3 Ethernet (registered trademark) communication protocol. In general, the module 114 is configured to notify the link partner 118 of a predetermined set of functions of the node 102. The predetermined set of functions may be, for example, PHY function, maximum link speed, next page, remote fault, acknowledgment, FEC and / or as defined by the IEEE 802.3 Ethernet communication protocol above. An FEC mode function, a pause function, and the like may be included. Similarly, the link partner 118 is configured to notify the node 102 of a predetermined set of functions of the link partner 118. The exchange of functions between the node 102 and the link partner 118 is executed within a predetermined automatic negotiation period. Module 114 may be configured to format a link codeword base page (base page) 120 to define the function of node 102. The base page 120 is defined by the above-mentioned IEEE 802.3 Ethernet (registered trademark) communication protocol, and has a data structure (for example, a 48-bit frame) having a predetermined bit used to notify a predetermined function of the node 102. It is. According to the teachings of the present disclosure, bits conventionally used to define the FEC function (eg, bit 46) and bits conventionally used to request FEC mode enable during auto-negotiation ( For example, bit 47) may be reassigned. In contrast to the conventional Ethernet communication protocol, the module 114 may be configured to modify the base page 120 to specify support for multiple FEC modes. For example, with respect to the FEC protocol and / or FEC mode, the base page 120 includes two bits (eg, bit 46 and bit 47) that are used to identify the FEC function and / or FEC mode that the network controller 104 supports. May be modified. For example, if bit 46 and bit 47 are set to 0, it means that node 102 is not configured to perform FEC processing. If bit 46 is set to 0 and bit 47 is set to 1, it means that node 102 is configured to operate in a first FEC mode (eg, a “mild” FEC mode). However, if bit 46 is set to 1 and bit 47 is set to 0, node 102 is configured to operate in a second FEC mode (eg, a “severe” FEC mode). And when bit 46 and bit 47 are both set to 1, node 102 operates in first and / or second FEC modes (eg, “mild” FEC mode and “severe” FEC mode). It is configured as follows. Of course, the module 114 may be configured to modify additional bits of the base page 120 to support other / additional FEC modes.

  FIG. 1A is a diagram illustrating an example of a base page 120 ′ according to an embodiment of the present disclosure. The base page 120 ′ of the present embodiment is used for a PHY circuit defined by the above Ethernet (registered trademark) communication protocol including, for example, 10BASE-KR, 40BASE-KR4, 40BASE-CR4, and / or 100GBASE-CR10. It may be done. An example of the base page 120 'shows bits 0-47. In particular, it shows that bit 46 is set to 0 and bit 47 is set to 1. That is, the node 102 is configured to operate in the “mild” FEC mode. Of course, the base page 120 'is only an example, and the base page 120' can be modified in accordance with the teachings described herein.

  According to the conventional Ethernet communication protocol, the quality of the communication link 126 is not determined during a predetermined auto-negotiation period, but the FEC function and / or FEC mode enablement is specified by the base page 120. And enabling the FEC function and / or FEC mode during a predetermined auto-negotiation period. In contrast to the conventional Ethernet communication protocol, according to the teachings described herein, the module 114 further includes certain FEC functions and data functions (link up state) and not in the auto-negotiation period. The base page 120 is configured to indicate a request to resolve the enablement of the FEC mode. Thus, according to the teachings described herein, the FEC state may be dynamically resolved during the data mode period. The term “resolution” as used herein means to enable or disable FEC processing and / or to enable or disable FEC mode. This determination may be made based on channel quality parameters. The base page 120 is an “unused” data field defined in the IEEE 802.3 Ethernet communication protocol described above (for example, one specified in the Ethernet communication protocol but not used) A plurality of bits).

  According to an embodiment, the module 114 is configured to format the base page 120 with a request flag, for example, by setting one or more bits of the unused data field of the base page 120. As an example, the base page 120 may include a 16-bit unused portion (eg, bits 30-45). To support at least two different FEC modes, module 114 may be configured to utilize bit 44 and bit 45 as the FEC request flag. Thus, for example, if both bits 44 and 45 are set to 0, it may mean that node 102 cannot resolve FEC in the data mode period or has no function. If bit 44 is set to 0 and bit 45 is set to 1, node 102 is requesting to dynamically resolve FEC during the data mode period, and only the first FEC mode is supported It may mean that If bit 44 is set to 1 and bit 45 is set to 0, node 102 is requesting to dynamically resolve FEC in the data mode period, and the first FEC mode and the second It may mean that the FEC mode is supported. Of course, these are just examples of the types of flags that can be set in the base page 120, and in other embodiments, other predetermined bit orders may be used to define the FEC mode request. In still other embodiments, the number of bits used in the unused portion of the base page 120 may depend on the number of predetermined FEC modes (as defined by the Ethernet communication protocol). For this reason, when an additional FEC mode is supported, an additional bit may be set in an unused portion of the base page 120. According to yet another embodiment, in addition to dynamically resolving FEC in data mode, the FEC protocol may be resolved in the auto-negotiation period (defined by the Ethernet communication protocol). The formatted base page 120 is transmitted to the link partner 118, and a similar base page (not shown) is transmitted from the link partner 118 to the node 102.

  Node 102 and link partner 118 are configured to delay the resolution of the FEC mode at the same time until the data mode period, for example by exchanging acknowledgments, by the expiration of a timer, by a training protocol that reaches the fault state, etc. As good as According to some embodiments, the FEC mode required by the node 102 may be different from the FEC mode required by the link partner 118. According to such an embodiment, node 102 and link partner 118 may confirm such a condition, and each may enable a different FEC processing mode (eg, as described in more detail below, but asymmetric FEC). Mode enable). Needless to say, other parameters such as the maximum link speed, the pause function, the next page, the remote fault, the type of PHY including confirmation response, etc. may be constructed during the auto-negotiation period. Assuming that the link partner 118 has the same configuration as that of the node 102, the same processing as described above may be executed by the link partner 118.

  The network controller 104 further includes a link training module 116 that is configured to perform a link training process between the node 102 and the link partner 118. In general, the link training process may be used to determine at least one channel quality parameter for at least one channel of communication link 126. Examples of channel quality parameters include bit error ratio (BER), signal noise ratio (SNR), crosstalk, environmental noise, linearity, impulse response, and the like. The link training module 116 is configured to execute a link training process during the link training period as defined by the IEEE 802.3 Ethernet communication protocol. The link training period occurs after the auto-negotiation period. In operation, during the link training period, the node 102 and the link partner 118 each select a signal and / or packet and / or frame selected to at least partially determine at least one channel quality parameter. Is configured to communicate. The link training process may be defined by the above-mentioned IEEE 802.3 Ethernet (registered trademark) communication protocol. For example, the frame training is acquired between the node 102 and the link partner 118, and the transmission coefficient is set to the channel characteristic. Tx feed-forward equalization (FFE) handshake process for adaptation, node 102 and link partner 118 providing coefficient update information to the transmitter so that the transmitter can adjust the transmit equalizer coefficient to the optimal value appropriate for the particular channel. Digital signal processing convergence for “training” each of the Rx circuits to the corresponding Tx circuit. The module 116 is also configured to analyze the quality of the received signal on a given channel using various techniques to generate one or more channel quality parameters (described below).

  An analysis of the quality of the received signal on a given channel may be performed using customized techniques and / or predetermined techniques. For example, link training module 116 may be configured to control various circuits of node 102 for the purpose of performing a link side loopback procedure to determine at least one channel quality parameter. As another example, system 100 may be configured to specify a master / slave relationship between node 102 and link partner 118 during an auto-negotiation period. Then, during the link training period, the master may be configured to instruct the slave to loop back (or generate a designated character) after a predetermined test timeout period has elapsed. Specify transition using the channel and start loopback processing on the master side. As another example, link training module 116 may be configured to generate an “eye test” template to determine whether the test signal received by the Rx circuit is of sufficient quality. As another example, the link training module 116 may be configured to generate a Tx circuit on / off sequence to determine channel crosstalk parameters. As yet another example, link training module 116 may be configured to obtain information from attached media, such as non-volatile storage media or mass storage media. As yet another example, link training module 116 performs a time domain reflectometry (TDR) test to determine signal reflectivity on a given channel between node 102 and link partner 118. It may be configured as follows. Of course, the above is merely one example of a technique used to perform link quality analysis, and the link training module 116 may use the above techniques, and / or other predetermined techniques and / or customized / special Technology may be used. The selection of one or more such techniques may be based on, for example, the network system environment, a specific PHY circuit, a known channel quality limit value, and the like.

  The network controller 104 further includes a physical coding sublayer (PCS) module 128 that is configured to perform data mode processing between the node 102 and the link partner 118. The data mode processing is performed, for example, by transmitting data packets / data frames during the link up state (data mode period) between the node 102 and the link partner 118 as defined in the Ethernet communication protocol described above. It may include interacting. The PCS module 128 generally includes other layers or modules (eg, an arbitration sublayer, a MAC module, etc., described below) as the underlying communication link 126 and as defined in the Ethernet communication protocol above. Protect from specific characteristics of the PHY specification. The PCS module 128 may include a transmit channel and a receive channel, and each channel may operate in a normal mode or a test pattern mode. The interface between the PCS and the RS may be compliant with the above Ethernet standard, for example, including CGMII (100 Gb), XGMII (10 Gb) and / or XLGMII (40 Gb) interface communication protocols Good. When communicating with the RS, the PCS module 128 may utilize a synchronous data path in which packet boundaries are provided by transmission control signals (eg, TXCn = 1) and reception control signals (eg, RXCn = 1). The PCS module 128 may provide the functionality necessary to map packets between formats such as XGMII, CGMII and / or XLGMII and PMA service interface formats. When the transmission channel is in normal mode, the PCS module 128 transmission process generates blocks based on the TXD <31: 0> and TXC <3: 0> signals at interfaces such as XGMII, CGMII and / or XLGMII. You can keep doing it. The PCS module 128 may then pack the resulting bits into a format appropriate for the media. When the reception channel is in the normal mode, the PCS module 126 may realize block synchronization based on, for example, a 2-bit synchronization header. The PCS module 126 may further set a sync_status flag to indicate whether the PCS module 126 has acquired synchronization. Of course, other processing and features of the PCS module 128 may be defined by the Ethernet communication protocol described above.

  The network controller 104 is further configured to provide an addressing and channel access control protocol for communication with the link partner 118 as defined in the Ethernet communication protocol above, and a medium access control (MAC). Module 136 (eg, MAC module 136 may be a layer 2 device). The MAC module 136 defines a data transmission / reception method that does not depend on a medium. While the PHY circuit 106 is generally unique to the medium (ie, copper cable or backplane), the MAC module 136 may operate regardless of the type of medium connected. The MAC module 136 performs data encapsulation (transmission / reception), framing (frame boundary demarcation, frame synchronization), addressing (processing of source and destination addresses), and error detection (detection of physical medium transmission errors). It may be configured as follows. The CSMA / CD MAC sublayer makes every effort to acquire the medium and transfer a serial stream of bits to the physical layer. Needless to say, other operations and features of the MAC module 136 may be defined by the Ethernet communication protocol described above.

  The network controller 104 is further configured to adapt the bit serial protocol of the MAC module 136 to the parallel format of the PCS module 128 as defined in the Ethernet communication protocol above. Module 134 is included.

  The MAC module 136 may provide data to the RS module 134 one bit at a time as a serial stream. The RS module 134 may incorporate an appropriate number of bits specified by the PHY circuit 106 so that information can be transmitted and received according to the IEEE specification of the PHY circuit 106. The interface between the MAC module 136 and the RS module 134 may include a physical layer signaling (PLS) interface, as defined by the Ethernet communication protocol described above. Needless to say, other processes and features of the RS module 134 may be defined by the Ethernet communication protocol described above.

  To enable FEC state and / or dynamic resolution of the FEC mode during the data mode period, the network controller 104 further monitors at least one channel of the link 126 during the data mode period and generates at least one channel quality parameter. A channel quality monitoring module 122 configured to: According to some embodiments, module 122 received from link partner 118 in data mode to determine at least one channel quality parameter for at least one channel of the link between node 102 and link partner 118. It is configured to analyze signal quality. For example, to analyze the quality of a given channel, module 122 may perform one or more of the customized / predetermined techniques described above with respect to link training module 116 (eg, “eye test”). It may be configured. According to other embodiments, to analyze the quality of a given channel, the module 122 can generate a channel pulse response using signal recovery techniques from a given medium (eg, non-volatile media or storage media). Processing such as obtaining information and / or monitoring a physical coding sublayer bad synchronization header error counter may be performed. Of course, the above is merely one example of a technique used to perform link quality analysis, and the link training module 116 may use the above techniques, and / or other predetermined techniques and / or customized / special Various techniques may be used. When selecting one or more of the above techniques, it may be based on, for example, the network system environment, a specific PHY circuit, a known channel quality limit value, and the like. Module 122 may be configured to analyze the quality of the received signal in a data mode, for example, continuously or discretely (eg, over a predetermined period of time) based on, for example, processing overhead, bandwidth, and the like. Module 122 may further be configured to track channel quality parameters over a given period of time so that changes in channel quality conditions for a given channel / link can be monitored.

  During the data mode, module 122 may determine at least one channel quality parameter for at least one channel of link 126 indicating that changing the FEC state improves packet flow rate or data integrity. For example, the module 122 may use the channel if the FEC mode is enabled in the auto-negotiation period (as defined in the conventional Ethernet communication protocol) and / or already enabled in the data mode period. A channel that indicates that a change in the current FEC mode state (eg, “severe” FEC to “mild” FEC) improves the bandwidth while maintaining packet integrity within an acceptable range due to improved quality Quality parameters may be generated during the data mode period. As another example, module 122 may improve packet quality and disable packet current state within an acceptable range by disabling the current FEC mode state (eg, “mild” FEC to FEC off). A channel quality parameter indicating that the bandwidth is improved while maintaining may be generated in the data mode period. As another example, the module 122 may enable FEC (if not already enabled during the auto-negotiation period) and / or increase the coding gain of the current FEC mode state due to degraded channel quality. A channel quality parameter indicating that packet integrity is improved by performing (for example, changing from “mild” FEC to “severe” FEC) may be generated in the data mode period. At least one channel quality parameter (eg, bit error ratio (BER), signal to noise ratio (SNR), crosstalk, environmental noise, linearity, impulse response, etc.) is determined by module 122 and is in the FEC state during the data mode. May be used to solve the problem. This will be described in more detail below.

  The channel quality monitoring module 122 may be configured to determine a channel quality parameter for each channel. Alternatively, the channel quality parameter may be determined for the entire communication link. For example, a given PHY specification may define the number of channels between node 102 and link partner 118. By determining the channel quality parameter for each channel, it may be seen that a particular channel has a higher quality than other channels. Thus, module 122 may be further configured to enable a plurality of different FEC modes for a plurality of different channels based at least in part on the channel quality parameter of each channel. Determining channel quality parameters for each channel may also allow multiple asynchronous FEC modes to operate between node 102 and link partner 118. For example, there are two channels between the node 102 and the link partner 118, and the Rx circuits of both the node 102 and the link partner 118 each have two FEC modes (eg, “mild” FEC mode and “severe”). Assume that FEC mode is supported. After determining the channel quality for each of these two channels, it may be found that the Rx channel of node 102 is of higher quality than the Rx channel of the link partner. As described in more detail below, the PCS module 128 may enable the first FEC mode for the Rx channel (the link partner 118 may enable the first FEC mode for the corresponding Tx channel), and similarly Link partner 118 may enable the second FEC mode for the Rx channel associated with link partner 118 (node 102 may enable the second FEC mode for the corresponding Tx channel). Thus, for a given link 126 with multiple channels, multiple FEC modes may be utilized for each channel based on channel quality parameters. Of course, this is just one example of an asynchronous enable in FEC mode implemented by the teachings of this disclosure.

  As described above, the channel quality monitoring module 122 may be configured to determine a channel quality parameter for each channel, or the channel quality parameter may be determined for the entire communication link. For example, a given PHY specification may define the number of channels between node 102 and link partner 118. By determining the channel quality parameter for each channel, it may be seen that a particular channel has a higher quality than other channels. Thus, the channel quality monitoring module 122 may be further configured to enable different FEC modes for each channel based at least in part on the channel quality parameters of each channel. Determining channel quality parameters for each channel may also allow multiple asynchronous FEC modes to operate between the node 102 and the link partner 118. For example, there are two channels between the node 102 and the link partner 118, and the Rx circuits of both the node 102 and the link partner 118 each have two FEC modes (eg, “mild” FEC mode and “severe” FEC mode). ) Is supported. After determining the channel quality for each of these two channels, it may be seen that the Rx channel of node 102 is of higher quality than the Rx channel of the link partner. The channel quality monitoring module 122 may enable the first FEC mode for the Rx channel (and the link partner 118 may enable the first FEC mode for the corresponding Tx channel), as well as the link partner 118. May enable the second FEC mode for the Rx channel associated with link partner 118 (node 102 may enable the second FEC mode for the corresponding Tx channel). Thus, for a given link 126 with multiple channels, multiple FEC modes may be used for each channel based on the channel quality parameters. Of course, this is just one example of an asynchronous enable in FEC mode that can be implemented in accordance with the teachings of the present disclosure.

<Resolve FEC state during data mode using ordered set and PCS control code>
According to one embodiment of the present disclosure, the FEC state may change (resolve) during the data mode using ordered sets and PCS control codes. The PCS module 128 may be configured to determine whether to enable or disable at least one FEC mode based at least in part on the at least one channel quality parameter during the data mode. The PCS module may be configured to exchange in-band control code 132 with link partner 118 during the data mode. The PCS module 114 may be configured to generate transmission codes to improve the transmission characteristics of information transferred on the link 126 and to support control characters and data characters. The control code 132 may generally be a well-defined data structure with specific bits including control characters and data characters, as defined by the IEEE 802.3 Ethernet communication protocol described above. Control characters and data characters are encoded to create an in-band control code that defines an Ethernet packet at the interface from the MAC, or to indicate “idle” or “error”.

  In accordance with the teachings of the present disclosure, the PCS module 128 can change the FEC state (eg, in FEC and / or FEC mode) in addition to the control codes defined in the IEEE 802.3 Ethernet communication protocol described above. A control code indicating a request for (enable or disable) is generated. Based on the channel quality parameter of the at least one channel, the PCS module 128 may generate and send an FEC enable / disable request signal to the link partner 118. The FEC enable / disable request signal specifies a request to use a specific FEC mode (which may be specified in the base page 120) and / or a request to disable the current FEC mode. As good as The link partner 118 may have a similar configuration and may accept a request to change the FEC state (eg, via an acknowledgment signal).

  To prevent data failure between the node 102 and the link partner 118 when the FEC mode is enabled or disabled during the data mode, and to keep the link in an active state, the PCS module 128 further May be configured to notify the RS module 136 to pause data packet forwarding while the new FEC mode is enabled or disabled, and the new FEC mode is activated or disabled The RS module may be notified to resume data packet transfer. The PCS module 128 is configured to notify the RS module 134 using the sequence order set 130. The PCS module 128 is configured to format the sequence order set 130 to instruct the RS module to initiate a pause or resume of data flow processing. The sequence order set 130 is generally defined by the IEEE 802.3 Ethernet communication protocol and provides a fixed data structure (eg, a 4-byte sequence), while the conventional IEEE 802.3 Ethernet communication protocol. (Clause 81) implements only the link suspend and resume commands for the 10 Gigabit PHY protocol. In contrast to the traditional Ethernet communication protocol, module 128 has been identified to support link suspend and resume for other types of PHYs, such as 40 Gigabit and 100 Gigabit PHY protocols. The sequence order set 130 may be modified to do so. As an example, the 8-byte sequences that make up the sequence order set 130 may include additional data structures to allow the MAC module 136 to break links for multiple PHY protocols including, for example, 40 Gigabit and 100 Gigabit protocols. (For example, except that lane 0 is set to a sequence value and lane 3 is set to a value of 0x03, all lanes 1 to 7 are set to a value of 0x0). According to another embodiment, the other sequence order set is PCS for the purpose of informing the RS module 134 about link suspension and link resumption processing as defined by the IEEE 802.3 Ethernet communication protocol. It may be used by module 128.

  FIG. 1B is a diagram illustrating an example of a sequence order set 130 ′ according to an embodiment of the present disclosure. The sequence order set 130 ′ of this embodiment may be used for link interruption notification used for 40 GbE and 100 GbE (IEEE802.3, clause 81) link interruption.

  When the PCS module 128 notifies the RS module 134 about link suspension or resumption, the RS module may communicate with the MAC module 136 to enable these processes. The PLS interface between the RS module 134 and the MAC module 136 may use a primitive notification protocol outlined in the above IEEE 802.3 Ethernet communication protocol. For example, the 10 gigabit PHY of clause 46 of the IEEE 802.3 Ethernet communication protocol is such that the PLS_carrier.com allows the MAC module 136 to pause and resume data transmission / reception. Primitive signals called indications may be used (e.g., used in the Energy Efficient Ethernet (EEE) protocol). In accordance with the teachings of the present disclosure, the RS module 134 may allow the PLS_carrier.m to allow the MAC module 136 to pause data transmission for other types of PHYs, including, for example, 40 Gigabit and 100 Gigabit protocols. It is configured to modify indication primitives. Therefore, the RS module 134 uses the notification protocol defined in the IEEE 802.3 Ethernet (registered trademark) communication protocol clause 81 so that the RS module 134 can instruct the MAC module 136 to suspend and resume data transmission. It may be corrected. According to other embodiments, other PLS primitives may include RS module 134 and MAC module 136 to enable link suspend and link resumption processing as defined by the IEEE 802.3 Ethernet communication protocol. May be used.

  In operation, the channel quality monitoring module 122 determines at least one channel quality parameter for at least one channel, and the at least one channel quality parameter changes the FEC state (eg, enables or disables FEC). And / or change the FEC mode), module 122 may notify module 128 to initiate a change of the FEC state. In response, the module 128 may format the sequence order set 130 to instruct the MAC module 136 to suspend the link 126 to allow for temporary suspension of data transmission and reception, as described above. Module 128 may also format in-band control code 132 as described above and exchange these control code 132 with link partner 118 to resolve the new FEC state. When node 102 and link partner 118 build a new FEC state, PCS module 128 may format sequence order set 130 to instruct MAC module 136 to resume data transmission and reception, as described above. By using the in-band control code 132 and the sequence order set 130, as described above, the link between the link partner 118 remains active and a link failure occurs between the node 102 and the link partner 118. Without allowing the node 102 to dynamically enable and / or disable the FEC state during the data mode. These processes may have significant advantages over conventional methods in terms of processing overhead, throughput rate, and / or packet integrity. Of course, the link partner 118 may be configured to operate similarly.

<Resolve FEC state during data mode using "fast" link retraining>
According to another embodiment of the present disclosure, the FEC state may be changed (resolved) during the data mode using a “fast” link retraining protocol. As described in the previous embodiment, instead of using an additional control code that identifies the FEC state to resolve the FEC state between the node 102 and the link partner 118 during the data mode, this embodiment Utilizes a “fast” link retraining process to resolve the FEC state during data mode. This embodiment may be used, for example, when the signal quality of a given channel / link degrades to such an extent that the in-band control code (eg, control code 132 described above) is not detected by the link partner during the data mode. It may be used when quality deteriorates due to environmental conditions such as temperature, voltage, and crosstalk. Thus, according to this embodiment, the network controller 104 further includes at least a determination result (module 122) of at least one channel quality parameter of at least one channel between the node 102 and the link partner 118 during the data mode period. A “fast” link retraining module 124 configured to initiate a “fast” link retraining process may be included to resolve the FEC state based in part. The term “fast”, when used in this context, is generally defined as a link training process that takes less time than the link training performed by the link training module 116 described above. Such “fast” processing may be performed when the link is in the link up state (data mode). “Fast” link retraining protocols are generally defined by the IEEE 802.3 Ethernet communication protocol.

  In order to enable communication between the node element 102 and the link partner 118 under noisy conditions or link degradation, the high speed link retraining module 124 links to momentarily suspend data. It is configured to format the link break code 140 to notify the partner 118. In one example, a link break code may include a type of signal repetition known to be highly transmissible under noisy or degraded conditions. For example, such a signal may include a zero symbol repetition after a PAM2 sequence repetition, and so on.

  The module 124 may also be configured to format the training frame 138 to allow training processing and to resolve a predetermined FEC protocol and / or FEC mode during the data mode. The training frame 138 is a data structure that is defined to include, for example, a defined fixed 4-octet frame marker, as defined by the IEEE 802.3 Ethernet communication protocol described above. The training frame 138 typically includes fields called a frame marker field, a coefficient update field, a status report field, and a training pattern field. FIG. 1C is a diagram illustrating an example of a training frame 138 ′ according to an embodiment of the present disclosure. The training frame includes a plurality of octets representing a frame marker field 160, a coefficient update field 162, a status report field 164 and a training pattern field 166. In contrast to the training frame defined in the IEEE 802.3 Ethernet communication protocol described above, according to the teachings of this embodiment, the unused data field of the coefficient update field and / or status report field is: The FEC mode enable flag may be formatted to indicate at least one FEC mode for at least one communication channel. For example, the coefficient update field of training frame 138 includes a plurality of unused bits, one or more of these unused bits being a module to set a flag to indicate the FEC mode of at least one channel. 124 may be formatted. FIG. 1D is a diagram illustrating an example of a coefficient update field 162 ′ according to an embodiment of the present disclosure. As another example, the status report field of training frame 138 includes a plurality of unused bits, and one or more of these unused bits are flagged to indicate FEC mode for at least one channel. May be formatted by module 124 to set FIG. 1E is a diagram illustrating an example of a status report field 164 ′ according to an embodiment of the present disclosure. Of course, in some other embodiments, other portions of the training frame 138 may be formatted with the FEC enable flag. The training frame 138 may be exchanged between the node 102 and the link partner 118 during the data mode period (eg, using in-band communication technology).

  In operation, the channel quality monitoring module 122 determines at least one channel quality parameter for at least one channel, and the at least one channel quality parameter changes the FEC state (eg, enables or disables FEC and / or If the change in FEC mode means that packet integrity and / or data throughput is improved, the module 122 suspends the link 126 to allow the suspension of data transmission and reception as described above. The module 124 may be notified to format the sequence order set 130 to instruct the MAC module 136 to Also, as module 128 formats link break code 140 to notify link partner 118 to momentarily suspend data flow and to initiate “fast” link retraining on the link partner side. Good. The PCS module 128 may notify the module 124 to initiate a “fast” link retraining process on at least one channel of the link between the node 102 and the link partner 118. The module 124 may exchange the formatted training frame 138 with the link partner 118 to format the training frame 138 and initiate a “fast” link retraining process, as described above. When node 102 and link partner 118 build a new FEC state, module 124 informs link partner 118 to resume data flow using the “fast” link retraining process and link break code, as described above. The link interruption code 140 may be formatted. Thus, the node 102 dynamically enables the FEC state during the data mode without causing a link failure between the node 102 and the link partner 118 while the link between the link partner 118 remains active. And / or can be disabled. These processes may have significant advantages over conventional methods in terms of processing overhead, throughput rate, and / or packet integrity. Of course, the link partner 118 may be configured to operate similarly.

  The example embodiments described above provide various in-band signaling techniques for changing the FEC mode / state between the node 102 and the link partner 118 during the data mode. In other embodiments, other in-band signaling schemes may be used. For example, node 102 may be configured to generate CGMII TXT and TXD lane encoding signals encoded with a modified word set. Alternatively or in addition, the node 102 may use a modified command set in a low power idle wake event as specified in the Energy Efficient Ethernet (EEE) communication protocol. It may be configured to generate. Of course, these are merely examples of in-band signaling techniques utilized by the present invention to change the FEC mode / state during the data mode, and other techniques may be recognized by those skilled in the art. . All such techniques are intended to be within the scope of this disclosure in this context.

  FIG. 2 is a flowchart 200 illustrating a process according to an embodiment of the present disclosure. Specifically, the flowchart 200 is for explaining the processing of the node element in the automatic negotiation period. The process of the present embodiment includes formatting 202 a link codeword base page during an auto-negotiation period with a link partner with a request to resolve at least one forward error correction (FEC) mode during the data mode period. Including. The data mode period occurs after the auto-negotiation period, and the data mode period generally defines a link up state in which nodes and link partners exchange data packets. The processing further includes transmitting 204 a link codeword base page to the link partner. The process further includes determining 206 whether the link partner can resolve the FEC mode during the data mode period. If the link partner is unable to resolve the FEC mode in the data mode period, the process may further include enabling a particular FEC mode 208 in the auto-negotiation period (and / or link training period). If the link partner can resolve the FEC mode in the data mode period, the auto-negotiation period may be completed 210 without enabling the FEC mode during the auto-negotiation period. Alternatively, the auto-negotiation period may be completed by enabling a specific FEC mode in the auto-negotiation period and / or the link training period.

  FIG. 3 is a flowchart 300 illustrating a process according to another embodiment of the present disclosure. Specifically, flowchart 300 illustrates one example embodiment of processing of a node element during a data mode period. Processing according to this embodiment includes determining 302 at least one channel quality parameter of at least one channel of a communication link between a network node element and a link partner during a data mode period. The process may further include determining 304 whether the at least one channel quality parameter indicates a need to enable or disable at least one supported FEC mode. For example, if the FEC mode is already enabled (eg, during auto-negotiation period, link training period and / or data mode period), the channel quality parameter may be set if the current FEC mode is disabled and / or If another FEC mode is enabled, it may indicate that the channel has acceptable packet integrity. Alternatively, if the FEC mode is not currently enabled, the channel quality parameter may indicate that enabling at least one FEC mode improves packet integrity because the channel has degraded. If the at least one channel quality parameter indicates a need to enable or disable at least one FEC mode (304), the process may further include selecting 306 an appropriate mode for the at least one channel. Process 306 assumes that the channel quality parameter indicates the need to enable at least one FEC mode. This process may be omitted if the channel quality parameter indicates that all FEC modes are disabled. Processing may further include 308 suspending data flow at the node element. The process may further include exchanging 310 in-band control code with the link partner to enable or disable at least one FEC mode. The process further includes resuming 312 data flow to and from the link partner by the node element when the FEC mode is enabled or disabled. Processing may continue at 302 (shown at 313). If the at least one channel quality parameter does not indicate the need to enable or disable at least one FEC mode (304), processing may continue at 302 (shown at 305).

  FIG. 4 is a flowchart 400 describing a process according to another embodiment of the present disclosure. Specifically, flowchart 400 illustrates another example embodiment of node element processing during a data mode period. Processing according to this embodiment includes determining 402 at least one channel quality parameter of at least one channel of a communication link between a network node element and a link partner during a data mode period. The processing may further include determining 404 whether the at least one channel quality parameter indicates a need to enable or disable at least one supported FEC mode. For example, if FEC mode is already enabled (eg, during auto-negotiation period, link training period and / or data mode period), the channel quality parameter may be set when current FEC mode is disabled and / or When another FEC mode is enabled, the channel may indicate that it has acceptable packet integrity. Alternatively, if the FEC mode is not currently enabled, the channel quality parameter may indicate that enabling at least one FEC mode improves packet integrity because the channel has degraded. If the at least one channel quality parameter indicates a need to enable or disable at least one FEC mode (404), the process may further include selecting 406 an appropriate mode for the at least one channel. . Process 406 may assume that the channel quality parameter indicates the need to enable at least one FEC mode, and this process may be used if the channel quality parameter indicates that all FEC modes are disabled. It may be omitted. The processing may further include suspending data flow 408 at the node element. The process may further include initiating a “fast” link retraining sequence between the node element and the link partner to enable or disable at least one FEC mode 410. The process further includes resuming 412 data flow to and from the link partner by the node element when the FEC mode is enabled or disabled. Processing may continue at 402 (shown at 413). If the at least one channel quality parameter does not indicate the need to enable or disable at least one FEC mode (404), processing may continue at 402 (shown at 405).

  FIG. 5 is a flowchart 500 for describing processing according to another embodiment of the present disclosure. Specifically, flowchart 500 illustrates the processing of the node elements during the auto-negotiation period and the data mode period. The process according to this embodiment includes requesting 502 in an auto-negotiation period by a network node element to resolve at least one FEC mode in a subsequent data mode period. The auto-negotiation period and the data mode period are determined by the Ethernet (registered trademark) communication protocol, and the auto-negotiation period occurs before the data mode period. The processing may further include determining 504 at least one channel quality parameter of at least one channel of the communication link between the network node element and the link partner during the data mode period. The processing further determines whether to enable or disable at least one FEC mode to be utilized by the network node element based at least in part on the at least one channel quality parameter during the data mode period. 506 may be included.

  Although the flowcharts of FIGS. 2, 3, 4 and 5 illustrate processes according to various embodiments, all of the processes illustrated in FIGS. 2, 3, 4 and / or 5 are required for other embodiments. It should be understood that this is not the case. Also, in other embodiments of the present disclosure, the processes shown in FIGS. 2, 3, 4 and / or 5 and / or other processes described herein are specifically illustrated in any of the drawings. It is fully contemplated herein that it can be combined in ways not shown, and such embodiments may have more or fewer processes than those illustrated in FIG. 2, FIG. 3, FIG. 4 and / or FIG. Thus, claims relating to features and / or processes not exactly shown in one drawing are intended to be within the scope and content of this disclosure.

  The above is given as an example of a system architecture and method, and the present disclosure can be modified. For example, node 102 and / or link partner 118 may further include a host processor, chipset circuitry, and system memory. The host processor may include one or more processor cores and may be configured to execute system software. The system software may include, for example, operating system code (eg, OS kernel code) and local area network (LAN) driver code. The LAN driver code may be configured to at least partially control the processing of the network controller 104. The system memory may include an I / O memory buffer that is configured to store one or more data packets that the network controller 104 transmits and receives. The chipset circuit may generally include a “north bridge” circuit (not shown) that controls communication between the processor, the network controller 104, and the system memory.

  Node 102 and / or link partner 118 may further include an operating system (OS, not shown) that manages system resources and controls, for example, tasks performed on node 102. For example, the OS may be implemented using Microsoft Windows (registered trademark), HP-UX, Linux (registered trademark), or UNIX (registered trademark), but may use another operating system. According to some embodiments, the OS is a virtual machine monitor (or hypervisor) that provides an abstraction layer for the underlying hardware for various operating systems (virtual machines) running on one or more processing units. It may be replaced with (visor). An operating system and / or virtual machine may implement one or more protocol stacks. The protocol stack may execute one or more programs that process the packets. An example of a protocol stack is a TCP / IP (Transport Control Protocol / Internet Protocol) protocol stack that includes one or more programs that handle (eg, process or generate) packets sent and received over a network. Alternatively, the protocol stack may be included in a dedicated subsystem, such as the TCP offload engine and / or the network controller 104. The TCP offload engine circuit is configured to provide, for example, packet forwarding, packet segmentation, packet reconstruction, error checking, transmission acknowledgment, transmission retry, etc. without involving the host CPU and / or host software. It may be good.

  The system memory includes one or more of the following types of memory: semiconductor firmware memory, programmable memory, non-volatile memory, read only memory, electrically programmable memory, random access memory, flash memory, magnetic disk memory and / or optical disk memory As good as In addition or alternatively, the system memory may include other types of computer readable memory and / or later developed computer readable memory.

  Embodiments of the processes described herein include one or more storage media that store, individually or in combination, instructions that perform a method when implemented by one or more processors. It may be realized by a system including the above. The processor may include, for example, a processing unit and / or programmable circuit in the network controller 104 and / or other processing unit or programmable circuit. Thus, processing according to the methods described herein is assumed to be distributed across multiple physical devices, eg, multiple processing structures that reside at different physical locations. The storage medium can be any kind of tangible and non-transitory storage medium, such as floppy disk, optical disk, compact disk read only memory (CD-ROM), compact disk rewritable (CD-RW) and magneto-optical. Any type of disk including disks, semiconductor devices such as read only memory (ROM), random access memory (RAM) such as dynamic RAM and static RAM, erasable programmable read only memory (EPROM), electrically erasable programmable read It may include only memory (EEPROM), flash memory, magnetic card or optical card, or any type of storage medium suitable for storing electronic instructions.

  The term “circuit” as used in any embodiment herein, for example, a hardwired circuit, a programmable circuit, a state machine circuit, and / or instructions that are executed in a programmable circuit, alone or in combination. Firmware to be stored may be included. The term “module” as used herein may include circuitry and / or code and / or instruction sets (eg, software, firmware, etc.), alone or in combination.

  Accordingly, the present disclosure provides an example of a network node element that includes a network controller configured to communicate with a link partner using an Ethernet communication protocol. The network controller is further configured to request during the auto-negotiation period to resolve at least one forward error correction (FEC) mode during the data mode period. The auto-negotiation period and the data mode period are determined by the Ethernet (registered trademark) communication protocol, and the auto-negotiation period occurs before the data mode period. The network node element further determines at least one channel quality parameter of at least one channel of the communication link between the network controller and the link partner during the data mode period, and determines at least one channel quality parameter during the data mode period. Based at least in part, is configured to determine whether to enable or disable at least one FEC mode utilized by the network node element.

  The present disclosure further provides a system comprising one or more storage media storing instructions that, when executed by one or more processors, perform the following processing individually or in combination. As the processing to be performed, between the network node element and the link partner, the requesting process during the auto-negotiation period between the node element and the link partner to resolve at least one FEC mode during the data mode period. Enabling at least one FEC mode based at least in part on the process of determining at least one channel quality parameter of at least one channel of the communication link in a data mode period and at least one channel quality parameter; or The auto negotiation period and the data mode period are defined by the Ethernet (registered trademark) communication protocol, and the auto negotiation period is the decimation period. Occur before the Tamodo period.

  The present disclosure further provides a method for resolving a forward error correction (FEC) protocol. The method includes the step of requesting by the network node element in an auto-negotiation period between the network node element and the link partner to resolve at least one FEC mode in the data mode period. The auto negotiation period and the data mode period are defined by the Ethernet (registered trademark) communication protocol, and the auto negotiation period occurs before the data mode period. The method further includes determining, by the network node element, at least one channel quality parameter of at least one channel of the communication link between the network node element and the link partner in the data mode period; and by the network node element Determining whether to enable or disable at least one FEC mode utilized by the network node element based at least in part on the at least one channel quality parameter during the data mode period;

  The terms and expressions used herein are explanatory terms and are not intended to be limiting. Even if such terms and expressions are used, equivalents (or portions thereof) of the illustrated and described features ) Is not intended to be excluded, and it should be appreciated that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

  Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments can be combined with each other and can be changed and modified as will be understood by those skilled in the art. The present disclosure is therefore to be considered to include such combinations, modifications, and variations.

Claims (33)

A network node element comprising a network controller that communicates with a link partner using an Ethernet communication protocol,
The network controller further includes
Requesting in an auto-negotiation period to resolve at least one forward error correction (FEC) mode in the data mode period;
Determining at least one channel quality parameter of at least one channel of a communication link between the network controller and the link partner during the data mode period;
Determining, in the data mode period, whether to enable or disable at least one FEC mode utilized by the network node element based at least in part on the at least one channel quality parameter;
The auto-negotiation period and the data mode period are defined by an Ethernet (registered trademark) communication protocol, and the auto-negotiation period occurs before the data mode period.   The network node element according to claim 1, wherein the channel quality parameter is selected from the group consisting of bit error rate (BER), signal-to-noise ratio (SNR), crosstalk, environmental noise, linearity and impulse response.   The network node element according to claim 1 or 2, wherein the network controller further formats a link codeword base page with a flag indicating the request to resolve at least one FEC mode in the data mode period.   4. The network controller of claim 1, further comprising suspending data flow between the network node element and the link partner while the at least one FEC mode is enabled or disabled. 5. The network node element according to item.   The network node element according to claim 4, wherein the network controller further resumes the data flow between the network node element and the link partner after the at least one FEC mode is enabled or disabled. The network controller further determines, in the data mode period, whether to enable or disable at least one FEC mode utilized by the network node element based at least in part on the at least one channel quality parameter. Run multiple fast link retraining processes to determine,
The plurality of high-speed link retraining processes are defined by the Ethernet (registered trademark) communication protocol, and more than a plurality of link training processes executed in a link training period defined by the Ethernet (registered trademark) communication protocol. The network node element according to claim 1, wherein a load on the processor is small.   The network node element according to claim 6, wherein the network controller further formats a coefficient update field with at least one flag indicating a plurality of FEC mode functions of the network controller.   The network node element according to claim 6 or 7, wherein the network controller further formats a status report field with at least one flag indicating a plurality of FEC mode functions of the network controller.   The at least one FEC mode includes a first FEC mode and a second FEC mode, and the first FEC mode has a smaller coding gain than the second FEC mode. 2. The network node element according to item 1.   The network node element according to any one of claims 1 to 9, wherein the Ethernet (registered trademark) communication protocol is compliant with the Institute of Electrical and Electronics Engineers 802.3 Ethernet (registered trademark) communication protocol.   The network controller further formats the plurality of in-band control code signals with a plurality of FEC mode functions of the network controller and selects the plurality of FEC modes in the data mode to select at least one FEC mode to enable or disable. The network node element according to claim 1, wherein an in-band control code signal is exchanged with the link partner. A method for solving a forward error correction (FEC) protocol comprising:
Requesting by a network node element in an auto-negotiation period between said network node element and a link partner to resolve at least one FEC mode in a data mode period;
Determining at least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner in the data mode period by the network node element;
Based at least in part on the at least one channel quality parameter, the network node element determines in the data mode period whether to enable or disable at least one FEC mode utilized by the network node element. With steps and
The auto negotiation period and the data mode period are defined by an Ethernet communication protocol, and the auto negotiation period occurs before the data mode period.   The method of claim 12, wherein the channel quality parameter is selected from the group consisting of bit error rate (BER), signal-to-noise ratio (SNR), crosstalk, environmental noise, linearity, and impulse response.   14. The method according to claim 12 or 13, further comprising the step of formatting a link codeword base page by the network node element with a flag indicating the request to resolve at least one FEC mode in the data mode period.   15. The method of claim 12, further comprising suspending data flow between the network node element and the link partner by the network node element while the at least one FEC mode is enabled or disabled. The method according to any one of the above.   16. The method of claim 15, further comprising resuming the data flow between the network node element and the link partner by the network node element after the at least one FEC mode is enabled or disabled. . To determine in the data mode period whether to enable or disable at least one FEC mode utilized by the network node element based at least in part on the at least one channel quality parameter. Further comprising performing a training process by the network node element;
The plurality of high-speed link retraining processes are defined by the Ethernet (registered trademark) communication protocol, and more than a plurality of link training processes executed in a link training period defined by the Ethernet (registered trademark) communication protocol. The method according to any one of claims 12 to 16, wherein the load on the processor is small.   The method of claim 17, further comprising formatting a coefficient update field with the network node element with at least one flag indicating a plurality of FEC mode functions of a network controller.   19. A method according to claim 17 or 18, further comprising the step of formatting a status report field with at least one flag indicating a plurality of FEC mode functions of a network controller by the network node element.   The at least one FEC mode includes a first FEC mode and a second FEC mode, and the first FEC mode has a lower coding gain than the second FEC mode. 2. The method according to item 1.   21. A method according to any one of claims 12 to 20, wherein the Ethernet communication protocol is compliant with the Institute of Electrical and Electronics Engineers 802.3 Ethernet communication protocol.   A plurality of in-band control code signals are formatted by the network node element in a plurality of FEC mode functions of a network controller and the plurality of in-band control code signals are selected to select at least one FEC mode to be enabled or disabled. The method according to any one of claims 12 to 21, further comprising the step of interacting with a link partner in the data mode. On the computer,
Requesting in an auto-negotiation period between the network node element and the link partner to resolve at least one FEC mode in the data mode period;
Determining at least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner in the data mode period;
Determining, in the data mode period, whether to enable or disable at least one FEC mode based at least in part on the at least one channel quality parameter;
The auto negotiation period and the data mode period are defined by an Ethernet (registered trademark) communication protocol, and the auto negotiation period occurs before the data mode period.   The program of claim 23, wherein the channel quality parameter is selected from the group consisting of bit error rate (BER), signal to noise ratio (SNR), crosstalk, environmental noise, linearity and impulse response.   25. The program according to claim 23 or 24, further causing the computer to execute a procedure for formatting a link codeword base page with a flag indicating the request for resolving at least one FEC mode in the data mode period.   26. The computer further comprising causing a procedure to suspend data flow between the network node element and the link partner while the at least one FEC mode is enabled or disabled. The program according to any one of the above.   27. The computer of claim 26, further comprising causing the computer to perform a procedure to resume the data flow between the network node element and the link partner after the at least one FEC mode is enabled or disabled. program. In addition to the computer,
Based at least in part on the at least one channel quality parameter, a plurality of fast speeds to determine in the data mode period whether to enable or disable at least one FEC mode utilized by the network node element. Run the procedure to perform the link retraining process,
The plurality of high-speed link retraining processes are defined by the Ethernet (registered trademark) communication protocol, and more than a plurality of link training processes executed in a link training period defined by the Ethernet (registered trademark) communication protocol. 28. The program according to claim 23, wherein a load on the processor is small.   29. The program according to claim 28, further causing the computer to execute a procedure for formatting a coefficient update field with at least one flag indicating a plurality of FEC mode functions of the network controller.   30. The program according to claim 28 or 29, further causing the computer to execute a procedure for formatting a status report field with at least one flag indicating a plurality of FEC mode functions of the network controller.   31. The any one of claims 23 to 30, wherein the at least one FEC mode includes a first FEC mode and a second FEC mode, and the first FEC mode has less coding gain than the second FEC mode. The program according to item 1.   The program according to any one of claims 23 to 31, wherein the Ethernet (registered trademark) communication protocol is compliant with the Institute of Electrical and Electronics Engineers 802.3 Ethernet (registered trademark) communication protocol.   The computer further formats the plurality of inband control code signals with a plurality of FEC mode functions of a network controller and links the plurality of inband control code signals to select at least one FEC mode to be enabled or disabled. The program according to any one of claims 23 to 32, for executing a procedure of exchanging with a partner in the data mode.

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