JP2015231042A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that secures a high frequency characteristic while securing high heat radiation performance.SOLUTION: A principal surface 50 as an element mount face of a heat spreader 22 is configured to be sloped, so that a high frequency characteristic can be secured while securing high heat radiation performance.

Description

  The present invention relates to a semiconductor device including a heat spreader on which a semiconductor element is mounted.

  Conventionally, efforts have been made to increase heat dissipation in the mounting of Si-IGBT. For example, there are a method of dissipating heat from both sides of the semiconductor element and a method of using a heat spreader. An example of reducing the thermal resistance of a power semiconductor element using a heat spreader is disclosed in Patent Document 1 and is shown in FIG. FIG. 8 is a side view showing a configuration of a conventional semiconductor device.

  As shown in FIG. 8, in the conventional semiconductor device, the power semiconductor element 1 is mounted on the heat spreader 122 installed in the wiring 105 on the insulating layer 23 on the base plate 20 in order to reduce the thermal resistance. A wiring 105 through which a large current flows and the power semiconductor element 1 are electrically connected by a wire 104. Similarly, the gate pad and source pad of the power semiconductor element 1 are electrically connected to the wiring 106b serving as the gate pattern and the wiring 107b serving as the source pattern via the wires 108a and 108b.

  Heat generated from the power semiconductor element 1 is diffused through the heat diffusion region 200 of the heat spreader 122, and is expanded from the area of the power semiconductor element 1 by the heat diffusion region 200 having an angle of 45 ° and transmitted to the insulating layer 23. It is done. As described above, the heat spreader 122 extends the heat radiation area to the insulating layer 23 to transmit heat, thereby reducing the thermal resistance.

JP 2007-180267 A

  However, for example, in order to increase the current density in the SiC-MOSFET, it is necessary to increase the thickness of the heat spreader 122 by an amount corresponding to the reduction in the semiconductor element area. However, if the heat spreader 122 is increased, the wiring 105, 106a, and 106b are increased. The wires 104, 108a and 108b to be connected must be set longer by the height of the heat spreader 122. When the wire becomes long in this way, parasitic inductance is generated in the gate / source wiring and the wiring through which the main current flows in the power circuit, which is not suitable for high-frequency operation. In order to enable high-frequency operation, it is necessary to set the heat spreader 122 thin due to restrictions on parasitic inductance. However, if the heat spreader 122 is thin, it may not be possible to sufficiently diffuse the heat. Therefore, in the general heat spreader shape, there is a problem that high frequency characteristics and heat dissipation have a trade-off relationship.

  In order to solve the above problems, an object of the present invention is to ensure high frequency characteristics while ensuring high heat dissipation.

  In order to achieve the above object, a semiconductor device of the present invention is provided with a base plate, an insulating layer formed on the base plate, a conductive pattern formed on the insulating layer, and the conductive pattern. A heat spreader and a semiconductor element mounted on the heat spreader, wherein the heat spreader has a main surface inclined with respect to a surface on which the insulating layer of the base plate is formed, and the semiconductor element has the main surface It is mounted on.

  According to the present invention, high frequency characteristics can be ensured while ensuring high heat dissipation.

1A and 1B are diagrams illustrating a configuration of a semiconductor device according to a first embodiment, where FIG. 1A is a schematic cross-sectional view, and FIG. Plan view showing a structure of a semiconductor device in the first embodiment 2A and 2B are diagrams showing a heat spreader in the semiconductor device according to the first embodiment, where FIG. FIG. 2 is a diagram illustrating the dependence of the thermal expansion magnification on the angle of the heat spreader in the power semiconductor device according to the first embodiment, where (a) a diagram relating to the angle α and (b) a diagram relating to the angle θ. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the semiconductor device for three-phase electric power in Embodiment 1, Comprising: (a) Configuration figure, (b) Circuit diagram FIG. 4 is a diagram illustrating a configuration of a semiconductor device according to a second embodiment, where (a) a schematic cross-sectional view and (b) a main part perspective view. Plan view showing a structure of a semiconductor device in the second embodiment Side view showing the configuration of a conventional semiconductor device

(Embodiment 1)
First, the semiconductor device according to the first embodiment will be described with reference to FIGS.
1A and 1B are diagrams showing a configuration of a semiconductor device according to Embodiment 1, in which FIG. 1A is a schematic cross-sectional view, and FIG. FIG. 2 is a plan view showing the configuration of the semiconductor device according to the first embodiment. 1A is a schematic cross-sectional view taken along the line AA ′ of FIG. FIG. 3 is a diagram showing the configuration of the heat spreader and the heat dissipation area in the semiconductor device of the first embodiment. FIG. 4 is a diagram showing the dependence of the thermal expansion magnification on the inclination angle of the heat spreader in the power semiconductor device of the first embodiment. FIG. 5 is a diagram showing a configuration of the three-phase power semiconductor device according to the first embodiment.

The configuration of the power semiconductor device of the present invention will be described with reference to FIGS. The power semiconductor device is an example of a semiconductor device, and the power semiconductor element is an example of a semiconductor element.
As shown in FIGS. 1 and 2, the insulating layer 23 is formed on the base plate 20, and the conductive wiring pattern 5 is formed thereon. On the heat spreader 22 mounted on a part of the conductive wiring pattern 5, the power semiconductor element 1 is mounted. The semiconductor device of the present embodiment is characterized in that the surface of the heat spreader 22 on which the power semiconductor element 1 is mounted is inclined with respect to the element mounting surface of the base plate 20. The conductive wiring pattern 5 is an example of a conductive pattern.

  The power semiconductor device of the present invention is provided with at least a pair of gate terminal 6a and source terminal 7a, and the power semiconductor element 1 is provided with a gate pad 6c and a source pad 7c. On the base plate 20, a gate pattern 6b and a source pattern 7b are formed. The gate terminal 6a is electrically connected to the gate pattern 6b by the wiring 8b, and the gate pad 6c is electrically connected to the gate pattern 6b by the gate wiring 8a, whereby the gate terminal 6a and the gate pad 6c are electrically connected. Connected. The source terminal 7a is electrically connected to the source pattern 7b by the wiring 9b, and the source pad 7c is electrically connected to the source pattern 7b by the source wiring 9a, whereby the source terminal 7a and the source pad 7c are electrically connected. Connected. The source electrode 7 d of the power semiconductor element 1 is electrically connected to the conductive wiring pattern 5 by a plate-like lead 4. Here, the connection between the lead 4 and the source electrode 7d of the power semiconductor element 1 and the connection between the lead 4 and the conductive wiring pattern 5 are joined by solder. In addition, you may use the joining by an ultrasonic wave for these joining. FIG. 2 shows an example in which three power semiconductor elements 1 are mounted in parallel, and the wiring length is optimized to the shortest distance by using plate-like leads 4. The drain electrode of each power semiconductor element 1 is connected to the power terminal 15 and the output terminal 17 via the conductive wiring pattern 5 at the center and the upper part of FIG. 2, and the source electrode of each power semiconductor element 1 is 2 are electrically connected to the output terminal 17 and the ground terminal 16 via the conductive wiring pattern 5 at the center and lower part of the drawing. A snubber capacitor 24 for reducing wiring inductance is mounted between the power terminal 15 and the ground terminal 16 via the conductive wiring pattern 5.

  In the heat spreader 22, as shown in FIG. 1, when the surface on which the power semiconductor element 1 is mounted is referred to as a main surface 50 and the opposite side is referred to as a sub surface 51, an angle formed between the main surface 50 and the sub surface 51. It is preferable to set θ to about 135 °. The main surface 50 is an element mounting surface. Here, the sub surface 51 is a surface that is continuous with the main surface 50 on the upper side of the main surface 50 that is far from the base plate 20. This is because the heat generated from the power semiconductor element 1 conducts heat so as to spread in the direction of 45 ° in the heat spreader 22, so that the angle θ formed by the main surface 50 and the sub surface 51 is set to be larger than 135 °. This is because the installation area of the heat spreader 22 becomes large and the arrangement becomes difficult, and in addition, a region where heat is not diffused in the heat spreader 22 is formed, so that the efficiency of reducing the thermal resistance is lowered. If the angle θ formed by the main surface 50 and the sub surface 51 is set to be smaller than 135 °, it is not desirable because the heat resistance increases as the heat dissipation area decreases as shown in FIG. When the heat spreader 22 is made of copper, it is appropriate to set the angle θ to 135 ° because copper does not have thermal diffusion anisotropy.

  FIG. 1B shows a mounting example of the heat spreader 22 mounted on the conductive wiring pattern 5. FIG. 1B shows a mounting example in which three power semiconductor elements 1 are mounted on the heat spreader 22. Here, the heat spreader 22 is a triangular prism, but this is not necessarily the case. If the main surface 50 and the sub surface 51 are provided, there is no practical problem even if, for example, the quadrangular prism has a trapezoidal cross section.

  When the heat spreader 22 is a triangular prism, the shape cut at the cross section 26 in FIG. 1B is a triangle, and as shown in FIG. 3A, the main surface on which the power semiconductor element 1 of the heat spreader 22 is mounted. An angle formed by 50 and a bottom surface 52 which is a surface in contact with the conductive wiring pattern 5 is defined as α. The bottom surface 52 is a surface that is continuous with the main surface 50 on the lower side of the main surface 50 that is closer to the base plate 20. FIG. 3B is a plan view of the heat spreading area on the conductive wiring pattern 5 as seen from directly above, where the heat generated from the power semiconductor element 1. Assuming that the heat generated in the power semiconductor element 1 is dissipated so as to spread in a 45 ° obliquely lower range from the main surface 50 on which the power semiconductor element 1 is mounted, the heat is generated at the bottom surface 52 of the heat spreader 22. The effective area to radiate heat is defined as a heat radiation area 53. Here, since the main surface 50 on which the power semiconductor element 1 is mounted is inclined with respect to the bottom surface 52 of the heat spreader 22, the heat dissipation region 53 to be radiated has a trapezoidal shape. As the angle α increases, the heat dissipation region 53 expands to increase the heat dissipation area in the direction parallel to the base plate 20, and the thermal expansion effect increases. A value obtained by dividing the area of the heat radiation region 53 by the area of the power semiconductor element 1 is defined as a thermal expansion factor F. As the value of F increases, the heat reaching the insulating layer 23 is dispersed, and the value of the thermal resistance in the insulating layer 23 under the heat spreader 22 decreases. If the thermal resistance of the insulating layer 23 having the highest thermal conductivity in the breakdown of the overall thermal resistance is reduced, the overall thermal resistance is lowered, which is advantageous.

  As described above, in the present embodiment, the main surface 50 of the heat spreader 22 is inclined with respect to the mounting surface of the base plate 20, and the power semiconductor element 1 is mounted on the inclined main surface 50 of the heat spreader 22. With this configuration, the heat spreader 22 is thinner at the lower side of the slope of the power semiconductor element 1 than at the upper side of the slope. Therefore, in the heat radiation area 53 shown in FIG. 3B, the heat spread is reduced where the thickness of the heat spreader 22 is reduced, and the heat spread is increased on the opposite side. In the present embodiment, by configuring in this way, it is possible to increase the heat diffusion region as the whole heat spreader 22 and improve the heat radiation efficiency without increasing the thickness of the entire heat spreader 22.

  At the same time, in the configuration of the present embodiment, since the gate pad 6c and the source pad 7c are disposed below the slope of the heat spreader 22, the difference in height between the power semiconductor element 1 and the base plate 20 below the slope is reduced. The length of the wire connecting them can be shortened. Therefore, parasitic inductance is suppressed and high frequency operation is possible. The distance from the power semiconductor element 1 to the bottom surface below the slope of the heat spreader 22 is different from the distance from the bottom surface above the slope, and the distribution of the thermal resistance inside the heat spreader 22 occurs between them. The thermal conductivity of the insulating layer 23 disposed on the lower side of the heat spreader 22 is 10 W / mK, whereas the heat conductivity of the heat spreader 22, for example, copper is 198 W / mK, Is smaller than the thermal resistance in the insulating layer 23. Therefore, the distribution of thermal resistance due to the difference between the thickness above the slope of the heat spreader 22 and the thickness below the slope is not a problem in practice.

Further, as the optimum value of the inter-chip distance, which is the distance between the plurality of power semiconductor elements 1 to be mounted, the horizontal dimension and the vertical dimension of the power semiconductor element 1 are a and b, respectively, as shown in FIG. When the angle α between the inclined surface and the bottom surface of the heat spreader 22 is defined, it is desirable to dispose the power semiconductor elements 1 with an interval greater than or equal to a value given by the following formula (1). When the heat diffusion angle of heat conduction is 45 °, as shown in FIG. 3B, the heat radiation region 53 on the plane that expands depending on the inclination angle α of the heat spreader 22 is adjacent to the power semiconductor. This is a condition for maintaining the heat dissipation efficiency without overlapping the thermal diffusion region of the element 1.

Minimum distance between chips = a × tan (α) / tan (45 ° −α) (1)

FIG. 4 shows a calculation result of the dependence of the thermal expansion magnification F on the angles α and θ. FIG. 4A shows a calculation result of the thermal diffusion magnification F when the angle θ is fixed to 135 ° and the angle α is changed. If the angle α is set to 32 °, the thermal expansion factor F is about 6 times that when no inclination is provided, and even if the SiC device is increased to the maximum current density, it has sufficient heat dissipation characteristics. That is, even if the current density is 6 times that of Si-IGBT, the thermal resistance can be maintained at the same level or lower. If the angle α is set to be larger than 32 °, the thermal expansion magnification F can be further increased and the thermal resistance can be lowered. In this case, however, the power semiconductor element 1 is mounted on a steep slope, and the mounting is reduced. It becomes difficult. Therefore, the upper limit of the angle α is preferably 32 °, which can reduce the thermal resistance to an appropriate value even in the future maximum current density of the SiC device. Further, assuming that the current capability of the current SiC-MOSFET is about 1.5 times (about 6 times is expected in the future), the lower limit of the angle α is estimated to be about 20 °. In this range, it is possible to ideally reduce the thermal resistance.

  FIG. 4B shows calculation results indicating changes in the thermal expansion magnification F when the angle α is set to 32 ° and the angle θ is changed. As the angle θ is increased, the thermal expansion magnification F is increased. However, if the angle θ is set to 135 ° or more, the area of the base plate 20 on which the heat spreader 22 is installed increases, and the circuit configuration itself cannot be reduced in size. Therefore, when the processing accuracy of the inclination angle θ of the heat spreader 22 is considered to be about 10%, the angle θ is desirably smaller than 140 °. If the current density capability of the current SiC-MOSFET is about 1.5 times (about 6 times is expected in the future), the lower limit of the angle θ is estimated to be about 105 °. Therefore, as the ranges of α and θ, the ranges of the following formulas (2) and (3) can be said to be preferable conditions.

20 <α ≦ 32 ° (2)

105 ° <θ <140 ° (3)

Next, specific dimension examples of the optimum configuration are shown below.

  It is assumed that the size of the power semiconductor element 1 is 5 × 4.2 mm □, and three chips (power semiconductor element 1) are arranged in parallel as shown in FIG. That is, the horizontal dimension a is 5 mm and the vertical dimension b is 4.2 mm. The inclination angle α of the main surface 50 of the heat spreader 22 on which the power semiconductor element 1 is mounted is 32 °, and the angle θ formed between the main surface 50 and the sub surface 51 is 135 °. At this time, from the above formula (1), the minimum inter-chip distance is 13.5 mm, so it is preferable to arrange the chips in parallel at an interval of about 15 mm. By adopting this configuration, the thermal expansion ratio F is about 6 times, and a configuration in which the thermal resistance is not deteriorated even when the current density of the power semiconductor element 1 is 6 times that of the SiC-MOSFET is provided. Is possible. Further, according to this configuration, the gate wiring can be mounted with a short length, and the wiring inductance between the GS can be kept low and the main current wiring inductance can be greatly reduced. As a result, the thermal expansion factor F and the gate / source wiring length can be designed independently, and the trade-off relationship between high-frequency operation and heat dissipation can be eliminated. In addition, since a sufficient space can be secured between the drain-side electrode of the power semiconductor element 1 and the gate / source wire, the parasitic capacitance generated in the gate wiring can be suppressed low, and noise can be reduced. It can be a strong structure. As a result, it is possible to optimize the inductance between GD and DS while ensuring sufficient heat dissipation of the device, and to enable high-frequency operation while suppressing an increase in the junction temperature of the power semiconductor element 1. As a result, it is possible to achieve downsizing and energy saving of equipment such as a power converter.

  FIG. 5A shows a configuration example of the power semiconductor device 30 for realizing a three-phase output. The three-phase output power semiconductor device 30 in the first embodiment includes a power terminal 15, a ground terminal 16, an output terminal 17, a gate terminal 6a, and a source terminal 7a, and a snubber capacitor 24 is incorporated therein.

  FIG. 5B shows a schematic circuit diagram when the power semiconductor device 30 is assembled into a practical circuit. In this circuit, a DC power supply 45 is connected via a smoothing capacitor 43. A snubber capacitor 42 is connected in the immediate vicinity of the power terminal 15 and the ground terminal 16 as necessary. When the power semiconductor element 1 is a SiC-MOSFET, the snubber capacitor 24 is also disposed inside the power semiconductor device 30 for the purpose of high-frequency operation. The output 35 of the power semiconductor device 30 is connected to a load. The control signal generated in the control signal generation board 40 is amplified in voltage and current in the drive board 39 and transmitted as a drive signal to the power semiconductor element 1. In this way, the DC power source is converted into AC power.

(Embodiment 2)
Next, the semiconductor device according to the second embodiment will be described with reference to FIGS.

  6A and 6B are diagrams showing the configuration of the semiconductor device according to the second embodiment. FIG. 6A is a schematic cross-sectional view, and FIG. FIG. 7 is a plan view showing the configuration of the semiconductor device according to the second embodiment. FIG. 6A is a B-B ′ sectional view of FIG. 7.

6 and 7 are examples of realization when a half-bridge circuit is configured using the power semiconductor device of the second embodiment.
The power semiconductor device according to the first embodiment has a configuration in which no return diode is mounted. However, when the output in power conversion increases, it may be necessary to mount a freewheeling diode. In such a case, as shown in FIG. 6, the power semiconductor device structure of the second embodiment may be used.

  In the power semiconductor device of the second embodiment, an insulating layer 23 is formed on a base plate 20, and a conductive wiring pattern 5 is formed thereon. It includes a transistor 201 and a diode 202 which are examples of power semiconductor elements, and is mounted on a heat spreader 222 mounted on the conductive wiring pattern 5. The heat spreader 222 has a trapezoidal cross section. In the heat spreader 222, the main surface (first main surface) that is an inclined surface on which the transistor 201 is mounted and the main surface (second main surface) that is an inclined surface on which the diode 202 is mounted. Surface). As shown in FIG. 6A, the angles η and ζ formed by the upper surface of the heat spreader 222, the surface on which the transistor 201 is mounted, and the surface on which the diode 202 is mounted are set to the same conditions as the angle θ as described above. It is preferable to do this. Here, the upper surface of the heat spreader 222 corresponds to a sub surface, and is a surface continuous with the two main surfaces at the upper side of the main surface. The source pads and anode pads of the transistor 201 and the diode 202 are electrically connected to the conductive wiring pattern 5 by leads 204. Here, the source 204 and the anode pad of the lead 204, the transistor 201, and the diode 202 are connected by solder bonding or ultrasonic bonding.

  As described above, also in the second embodiment, by making the element mounting surface of the heat spreader 222 an inclined surface, the heat spreader 222 as a whole can be increased in heat diffusion area without increasing the thickness of the heat spreader 222, thereby improving the heat dissipation efficiency. Is possible. At the same time, the step with the base plate 20 is reduced below the slope, the wire length can be shortened, parasitic inductance is suppressed, and high-frequency operation is possible.

  The transistor 201 and the diode 202 are preferably arranged in a staggered arrangement in plan view. In this way, one of the transistor 201 and the diode 202 is radiated between the other chips, and the dead space between the chips in the radiating region 53 is effectively utilized as shown in FIG. Can do.

  FIG. 6B shows a mounting example of the heat spreader 222 mounted on the conductive wiring pattern 5. This is a mounting example in which three chips of transistors 201 and two chips of diodes 202 are mounted on a heat spreader 222.

  In each of the above embodiments, the power semiconductor device on which the power semiconductor element is mounted has been described as an example. However, the power semiconductor device can be applied to a semiconductor device on which another semiconductor element is mounted, and both high heat dissipation and high frequency characteristics can be achieved. Can be achieved.

  In addition, the arrangement, shape, and number of terminals, conductive wiring patterns, and pads can be arbitrarily configured according to the use of the semiconductor element or the semiconductor device. At this time, by arranging the semiconductor element so that the pad of the semiconductor element related to the high frequency operation is below the slope of the heat spreader, the wire length can be shortened, the parasitic inductance can be suppressed, and the high frequency operation can be realized.

  The present invention makes it possible to ensure high frequency characteristics while ensuring high heat dissipation by making the element mounting surface of the heat spreader into an inclined surface, and to a semiconductor device or the like equipped with a heat spreader on which a semiconductor element for power or the like is mounted. Useful.

DESCRIPTION OF SYMBOLS 1 Power semiconductor element 4,204 Lead 5 Conductive wiring pattern 6a Gate terminal 6b Gate pattern 6c Gate pad 7a Source terminal 7b Source pattern 7c Source pad 7d Source electrode 8a Gate wiring 8b, 9b, 105, 106a, 106b, 107b Wiring 9a Source wiring 15 Power terminal 16 Ground terminal 17 Output terminal 20 Base plate 22, 122, 222 Heat spreader 23 Insulating layer 24, 42 Snubber capacitor 26 Cross section 30 Power semiconductor device 35 Output 39 Drive substrate 40 Control signal generation substrate 43 Smoothing capacitor 45 DC power supply 50 Main surface 51 Sub surface 52 Bottom surface 53 Heat dissipation region 104, 108a, 108b Wire 200 Thermal diffusion region 201 Transistor 202 Diode

Claims (7)

A base plate;
An insulating layer formed on the base plate;
A conductive pattern formed on the insulating layer;
A heat spreader provided on the conductive pattern;
A semiconductor element mounted on the heat spreader,
The heat spreader has a main surface inclined with respect to a surface on which the insulating layer of the base plate is formed,
The semiconductor element is mounted on the main surface.
Semiconductor device. A wire that electrically connects the conductive pattern and the pad of the semiconductor element;
The pad of the semiconductor element is disposed below the slope of the heat spreader,
The semiconductor device according to claim 1. The semiconductor element is a power semiconductor element, and a source electrode that is one of the pads and one of the conductive patterns are connected by a plate-like lead.
The semiconductor device according to claim 1. When the angle formed between the main surface and the sub surface continuous with the main surface on the side far from the base plate is θ, the angle θ satisfies the relationship of 105 ° <θ <140 °.
The semiconductor device according to claim 1. When the angle formed between the main surface and the bottom surface continuous with the main surface on the side close to the base plate is α, the angle α satisfies a relationship of 20 ° <α ≦ 32 °.
The semiconductor device according to claim 1. The main surface is composed of a first main surface and a second main surface,
A transistor is disposed as the semiconductor element on the first main surface, and a diode is disposed as the semiconductor element on the second main surface.
The semiconductor device according to claim 1. The transistors and the diodes are staggered in a plan view.
The semiconductor device according to claim 6.

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