JP2015225228A - Optimization method of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optimization method of a liquid crystal display device that can improve display definition.SOLUTION: A normally black mode drive method of a liquid crystal display device including a first substrate having a pixel electrode and a common electrode, a second substrate facing the first substrate, and a positive type liquid crystal layer held between the first substrate and the second substrate, and displaying a black when a liquid crystal application voltage to be applied to the liquid crystal layer is the lowest is configured to: measure a first VT characteristic indicative of transmittance of the liquid crystal display device relative to the liquid crystal application voltage when a positive-polarity voltage higher than common potential relative to the pixel electrode; measure a second VT characteristic indicative of transmittance of the liquid crystal display device relative to the liquid crystal application voltage when a negative-polarity voltage lower than the common potential relative to the pixel electrode; and set a maximum liquid crystal application voltage in which maximum transmittance in the first VT characteristic and maximum transmittance in the second VT characteristic are almost equal to a white display voltage.

Description

  Embodiments described herein relate generally to a method for optimizing a liquid crystal display device.

  In recent years, liquid crystal display devices using a horizontal electric field mode such as a fringe field switching (FFS) mode or an in-plane switching (IPS) mode have been put into practical use. Such an FFS mode or IPS mode liquid crystal display device includes a pixel electrode and a common electrode on one of a pair of substrates. Such a display mode realizes switching by rotating liquid crystal molecules in a plane parallel to the substrate, and has advantages such as a wide viewing angle.

  As an example, in an IPS mode liquid crystal display device, a technique for improving flicker by focusing on the flexo coefficient, which is one of the physical properties of the liquid crystal material, and applying a liquid crystal material with an optimal flexo coefficient range is known. Yes.

JP 2010-282037 A

  An object of the present embodiment is to provide a method for optimizing a liquid crystal display device capable of improving display quality.

According to this embodiment,
A first substrate including a switching element disposed in each pixel, a pixel electrode electrically connected to the switching element and including a strip electrode, and a common electrode having a common potential disposed across a plurality of pixels; A second substrate facing the first substrate; and a positive-type liquid crystal layer held between the first substrate and the second substrate, the liquid crystal applied voltage applied to the liquid crystal layer being the lowest A method of driving a normally black mode liquid crystal display device that displays black in the case of the liquid crystal display device with respect to a liquid crystal applied voltage when a positive voltage higher than a common potential is applied to the pixel electrode. A first VT characteristic representing the transmittance is measured, and a second VT characteristic representing the transmittance of the liquid crystal display device with respect to the liquid crystal applied voltage when a negative voltage lower than a common potential is applied to the pixel electrode. A method for optimizing a liquid crystal display device is provided, in which the maximum liquid crystal applied voltage at which the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic are substantially equal is set as the white display voltage. Is done.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment. FIG. 2 is a schematic plan view of an example of the structure of the pixel PX in the array substrate AR illustrated in FIG. 1 as viewed from the counter substrate CT side. FIG. 3 is a diagram schematically showing an example of a cross-sectional structure of the liquid crystal display panel LPN shown in FIG. FIG. 4 is a diagram illustrating an example of a VT characteristic representing the transmittance (%) of the liquid crystal display device with respect to the liquid crystal applied voltage (V) in the normally black mode liquid crystal display device. FIG. 5 is a diagram showing evaluation results of VT characteristics and burn-in determination levels in liquid crystal display devices to which liquid crystal materials A, B, and C having different flex coefficients are applied, respectively. FIG. 6 is a diagram illustrating evaluation results of burn-in determination levels after optimization of the second liquid crystal display device and the third liquid crystal display device. FIG. 7 is a diagram showing the relationship between the optimum width of the strip electrode PA in the pixel electrode PE and the difference in transmittance between the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment.

  That is, the liquid crystal display device includes an active matrix transmissive liquid crystal display panel LPN. The liquid crystal display panel LPN is held between the array substrate AR, which is the first substrate, the counter substrate CT, which is the second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. Liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers).

  In the active area ACT, the array substrate AR is extended along a second direction Y orthogonal to the first direction X, and a plurality of gate wirings G (G1 to Gn) extending along the first direction X, respectively. The plurality of source lines S (S1 to Sm), the switching element SW electrically connected to the gate line G and the source line S in each pixel PX, and the pixel electrically connected to the switching element SW in each pixel PX An electrode PE, a common electrode CE disposed over the plurality of pixels PX, and the like are provided.

  Each gate line G is drawn outside the active area ACT and connected to the gate driver GD. Each source line S is drawn outside the active area ACT and connected to the source driver SD. The common electrode CE is electrically connected to a power feeding unit VS to which a common voltage (Vcom) is supplied. For example, at least a part of the gate driver GD and the source driver SD is formed on the array substrate AR, and is connected to the driving IC chip 2. In the illustrated example, the drive IC chip 2 functions as a signal source necessary for driving the liquid crystal display panel LPN, controls the gate driver GD and the source driver SD, and supplies a common voltage supplied to the power supply unit VS. Or control. Such a driving IC chip 2 is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN.

  The liquid crystal display panel LPN of the illustrated example has a configuration applicable to the FFS mode or the IPS mode, and the array substrate AR includes a pixel electrode PE and a common electrode CE. In the liquid crystal display panel LPN having such a configuration, a horizontal electric field (for example, an electric field substantially parallel to the main surface of the substrate in the fringe electric field) formed between the pixel electrode PE and the common electrode CE is mainly used. The liquid crystal molecules constituting the liquid crystal layer LQ are switched.

  FIG. 2 is a schematic plan view of an example of the structure of the pixel PX in the array substrate AR illustrated in FIG. 1 as viewed from the counter substrate CT side. Here, only the main parts necessary for the description are shown, and the switching elements and the like are not shown.

  The gate lines G extend along the first direction X, respectively. The source lines S extend along the second direction Y, respectively. The common electrode CE extends along the first direction X. That is, the common electrode CE is disposed in each pixel PX and is formed in common over a plurality of pixels PX adjacent to each other in the first direction X across the source line S. Although not shown, the common electrode CE may be formed in common across a plurality of pixels PX adjacent in the second direction Y.

  The pixel electrode PE arranged in each pixel PX is located above the common electrode CE. Each pixel electrode PE is formed in an island shape corresponding to the pixel shape in each pixel PX. In the illustrated example, the pixel electrode PE is formed in a substantially rectangular shape whose length along the first direction X is shorter than the length along the second direction Y. Each pixel electrode PE has a slit PSL facing the common electrode CE. In other words, the pixel electrode PE includes the strip electrode PA. In the illustrated example, the slit PSL or the strip-shaped electrode PA extends along the second direction Y.

  FIG. 3 is a diagram schematically showing an example of a cross-sectional structure of the liquid crystal display panel LPN shown in FIG.

  That is, the array substrate AR is formed by using a first insulating substrate 10 having light transparency such as a glass substrate. This array substrate AR has a switching element SW, a common electrode CE, a pixel electrode PE, a first insulating film 11, a second insulating film 12, and a first alignment film on the inner surface 10A side of the first insulating substrate 10 facing the counter substrate CT. AL1 etc. are provided.

  The switching element SW is, for example, a thin film transistor (TFT). The switching element SW1 includes a semiconductor layer formed of polysilicon or amorphous silicon. Note that the switching element SW may be either a top gate type or a bottom gate type. Such a switching element SW is covered with the first insulating film 11.

  The common electrode CE is formed on the first insulating film 11. Such a common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode CE is covered with the second insulating film 12. The second insulating film 12 is also disposed on the first insulating film 11.

  The pixel electrode PE is formed on the second insulating film 12 and faces the common electrode CE. The pixel electrode PE is electrically connected to the switching element SW through a contact hole that penetrates the first insulating film 11 and the second insulating film 12. The slit PSL of the pixel electrode PE faces the common electrode CE through the second insulating film 12. Such a pixel electrode PE is formed of a transparent conductive material, for example, ITO or IZO. The first alignment film AL1 covers the pixel electrode PE. The first alignment film AL1 is also disposed on the second insulating film 12. Such a first alignment film AL1 is formed of a material exhibiting horizontal alignment and is disposed on a surface in contact with the liquid crystal layer LQ of the array substrate AR.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass substrate. The counter substrate CT includes a black matrix 31, a color filter 32, an overcoat layer 33, a second alignment film AL2, and the like that partition each pixel PX on the inner surface 30A side of the second insulating substrate 30 facing the array substrate AR. ing.

  In the inner surface 30A of the second insulating substrate 30, the black matrix 31 is opposed to the wiring portions such as the gate wiring G, the source wiring S, and the switching element SW provided on the array substrate AR, and the opening AP facing the pixel electrode PE. Is forming. The color filter 32 is formed on the inner surface 30A of the second insulating substrate 30 and is disposed in the opening AP. The color filter 32 also extends on the black matrix 31. The color filter 32 is formed of, for example, resin materials colored in red, blue, and green, respectively. The boundary between the color filters 32 of different colors is located on the black matrix 31.

  The overcoat layer 33 covers the color filter 32. The overcoat layer 33 flattens the unevenness on the surface of the black matrix 31 and the color filter 32. Such an overcoat layer 33 is formed of, for example, a transparent resin material. The second alignment film AL2 covers the overcoat layer 33. The second alignment film AL2 is formed of a material exhibiting horizontal alignment, and is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the array substrate AR and the counter substrate CT by columnar spacers formed on one substrate. The array substrate AR and the counter substrate CT are bonded together with a cell gap formed. The liquid crystal layer LQ is made of a liquid crystal composition including liquid crystal molecules LM sealed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT. Such a liquid crystal layer LQ is made of, for example, a liquid crystal material having a positive dielectric anisotropy (positive type).

  A backlight BL is arranged on the back side of the liquid crystal display panel LPN having such a configuration. As the backlight BL, various forms are applicable, and any of those using a light emitting diode (LED) or a cold cathode tube (CCFL) as a light source can be applied. The description of the structure is omitted.

  A first polarizing plate PL1 having a first absorption axis is disposed on the outer surface 10B of the first insulating substrate 10. On the outer surface 30B of the second insulating substrate 30, a second polarizing plate PL2 having a second absorption axis that is in a cross-Nicol positional relationship with the first absorption axis is disposed. It should be noted that another optical element such as a retardation plate may be disposed between the first insulating substrate 10 and the first polarizing plate PL1 or between the second insulating substrate 30 and the second polarizing plate PL2.

  As shown in FIG. 2, the first alignment film AL1 and the second alignment film AL2 are subjected to alignment treatment in directions parallel to each other in a plane parallel to the substrate main surface (or XY plane). The first alignment film AL1 is subjected to an alignment process along a direction intersecting an acute angle of 45 ° or less with respect to the major axis of the slit PSL (second direction Y in the example shown in FIG. 2). The alignment processing direction R1 of the first alignment film AL1 is, for example, a direction that intersects the second direction Y with an angle of 5 ° to 15 °. Further, the second alignment film AL2 is subjected to an alignment process along a direction parallel to the alignment processing direction R1 of the first alignment film AL1. The alignment treatment direction R1 of the first alignment film AL1 and the alignment treatment direction R2 of the second alignment film AL2 are opposite to each other.

  The operation of the liquid crystal display device having the above configuration will be described below.

  When the voltage that forms a potential difference is not applied between the pixel electrode PE and the common electrode CE, the voltage is not applied to the liquid crystal layer LQ when the voltage is not applied, and the pixel electrode PE and the common electrode CE No electric field is formed between the two. For this reason, the liquid crystal molecules LM contained in the liquid crystal layer LQ are aligned in the initial alignment direction regulated by the first alignment film AL1 and the second alignment film AL2. For example, as shown by the solid line in FIG. 2, the liquid crystal molecules LM are initially aligned in a direction that intersects the second direction Y at an acute angle in the XY plane, that is, in a direction parallel to the alignment processing direction R1. ing. One of the first absorption axis of the first polarizing plate PL1 and the second absorption axis of the second polarizing plate PL2 is substantially parallel to the initial alignment direction of the liquid crystal molecules LM, and the other is substantially orthogonal to the initial alignment direction. doing.

  When OFF, a part of the backlight light from the backlight BL is transmitted through the first polarizing plate PL1 and enters the liquid crystal display panel LPN. The light incident on the liquid crystal display panel LPN is linearly polarized light orthogonal to the first absorption axis of the first polarizing plate PL1. Such a polarization state of linearly polarized light hardly changes when it passes through the liquid crystal display panel LPN in the OFF state. For this reason, most of the linearly polarized light transmitted through the liquid crystal display panel LPN is absorbed by the second polarizing plate PL2 (black display).

  On the other hand, when a voltage that forms a potential difference is applied between the pixel electrode PE and the common electrode CE, the voltage is applied to the liquid crystal layer LQ, and the pixel electrode PE and the common electrode CE A transverse electric field or fringe electric field substantially parallel to the main surface of the substrate is formed between the two. For this reason, the liquid crystal molecules LM are aligned in an azimuth different from the initial alignment direction in the XY plane, as indicated by a broken line in FIG. In the positive liquid crystal material, the liquid crystal molecules LM are aligned in a direction substantially parallel to the electric field in the XY plane. At this time, the alignment direction of the liquid crystal molecules LM differs depending on the magnitude of the voltage applied to the liquid crystal layer LQ.

  When ON, linearly polarized light orthogonal to the first absorption axis of the first polarizing plate PL1 is incident on the liquid crystal display panel LPN, and the polarization state is the alignment state of the liquid crystal molecules LM or the liquid crystal layer when passing through the liquid crystal layer LQ. It changes according to the retardation of LQ. For this reason, at the time of ON, at least a part of the light that has passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display).

  With such a configuration, a normally black mode is realized.

  Next, a burn-in phenomenon in the FFS mode liquid crystal display device will be briefly described.

  As an example, a voltage that displays a black and white checker pattern (checkered pattern) is applied to the liquid crystal display panel LPN, and the state in which the checker pattern is displayed over the entire active area ACT is held for a predetermined time. For example, in a liquid crystal display device that displays an image with 256 gradations, the liquid crystal applied voltage is set to the lowest (or set to zero V) for the pixels PX in the first region of the active area ACT, and black display (gradation value G0) is performed. )I do. On the other hand, for the pixels PX in the second region adjacent to the first region of the active area ACT, white display is performed by applying a liquid crystal application voltage corresponding to white display (gradation value G255).

  Thereafter, a liquid crystal application voltage for displaying a halftone (for example, a gradation value G127) is applied to the liquid crystal display panel LPN, and a uniform halftone image is displayed on the entire surface of the active area ACT. That is, the liquid crystal application voltage corresponding to the same halftone display is applied to both the pixel PX in the first region and the pixel PX in the second region. At this time, a luminance almost equal to the luminance corresponding to the original halftone is obtained for the first region, but if the luminance of the second region is higher than the luminance of the original halftone, A luminance difference occurs between the area and the second area, and the checker pattern is visually recognized as an afterimage. Such a phenomenon is a “burn-in” phenomenon.

  Such image sticking is alleviated not only by applying a voltage corresponding to the gradation to be displayed to the pixel electrode PE, but also by performing compensation driving that applies a DC bias for each gradation as necessary. .

  On the other hand, according to a study by the inventors, burn-in that cannot be sufficiently mitigated even when the above-described compensation drive is applied occurs, and such burn-in is caused by flexopolarization generated in the liquid crystal layer LQ. It was found. When flexopolarization occurs in the liquid crystal layer LQ, the flexopolarization itself causes an orientation change in response to an electric field, so that a desired transmittance or luminance cannot be obtained. The electric polarization induced by the flexopolarization can be defined using a flexo coefficient that is one of the physical properties unique to the liquid crystal material. The flexo coefficient may differ depending on the compound added to the liquid crystal material depending on the required panel specifications. The inventor has found a method for optimizing a liquid crystal display device that reduces burn-in regardless of the flexural coefficient of the liquid crystal material. The optimization method will be described below.

  FIG. 4 is a diagram illustrating an example of a VT characteristic representing the transmittance (%) of the liquid crystal display device with respect to the liquid crystal applied voltage (V) in the normally black mode liquid crystal display device. The horizontal axis in the figure is the liquid crystal applied voltage (V), and the vertical axis in the figure is the transmittance (%) of the liquid crystal display device. The liquid crystal applied voltage here is an absolute value of a potential difference between the potential of the pixel electrode and the potential of the common electrode. Moreover, the transmittance | permeability here is normalized by making the peak transmittance | permeability into 100%. In the illustrated example, the liquid crystal application voltage at which peak transmittance is obtained is set to a white display voltage, and the white display voltage here is set to 4V. Such VT characteristics are substantially equal regardless of the liquid crystal material when driven under the same conditions in a liquid crystal display device having the same structure.

  Further, here, driving is performed by inverting the polarity of the voltage supplied to the pixel electrode PE every frame. That is, a positive voltage higher than the common potential of the common electrode CE is applied to the pixel electrode PE in the previous frame, and a negative polarity lower than the common potential of the common electrode CE is applied to the pixel electrode PE in the next frame. The AC drive is applied such that a voltage of 1 is applied. At this time, a VT characteristic when a positive voltage is applied (hereinafter referred to as a first VT characteristic) and a VT characteristic when a negative voltage is applied (hereinafter referred to as a second VT characteristic). Then, it becomes a substantially equivalent characteristic. However, there is a difference in the peak transmittance between the first VT characteristic and the second VT characteristic, or there is a difference in the liquid crystal applied voltage that provides the peak transmittance between the first VT characteristic and the second VT characteristic.

  FIG. 5 is a diagram showing evaluation results of VT characteristics and burn-in determination levels in liquid crystal display devices to which liquid crystal materials A, B, and C having different flex coefficients are applied, respectively. The flexo coefficient is smaller in the liquid crystal material A than in the liquid crystal material B and larger in the liquid crystal material C.

  (A1) in the figure is the VT characteristic of the first liquid crystal display device to which the liquid crystal material A is applied, and (B1) in the figure is the VT characteristic of the second liquid crystal display device to which the liquid crystal material B is applied. There, (C1) in the figure is the VT characteristic of the third liquid crystal display device to which the liquid crystal material C is applied. Here, the VT characteristics obtained when the liquid crystal display device having the same structure is configured and driven under the same conditions except that the liquid crystal materials are different are shown. In particular, near the peak transmittance in the VT characteristics. Is shown enlarged. In each liquid crystal display device, the width along the first direction X of the strip electrode PA of the pixel electrode PE was set to 2.2 μm.

  As shown in (A1), in the first liquid crystal display device, in the first VT characteristic of positive polarity, peak transmittance (about 100%) is obtained at a liquid crystal applied voltage of about 4.1 V, whereas negative polarity is obtained. In the second VT characteristic, a peak transmittance (about 98%) is obtained at a liquid crystal applied voltage of about 3.8V. When the white display voltage is set to 4V, the difference in transmittance between the first VT characteristic and the second VT characteristic is about 2%.

  As shown in (B1), in the second liquid crystal display device, in the first VT characteristic, the peak transmittance (about 100%) is obtained at a liquid crystal applied voltage of about 4.15 V, whereas in the second VT characteristic, about A peak transmittance (about 97%) is obtained at a liquid crystal applied voltage of 3.85V. When the white display voltage is set to 4 V, the difference in transmittance between the first VT characteristic and the second VT characteristic is about 3.3%.

  As shown in (C1), in the third liquid crystal display device, in the first VT characteristic, peak transmittance (about 100%) can be obtained with a liquid crystal applied voltage of about 4.2 V, whereas in the second VT characteristic, about A peak transmittance (about 96%) is obtained at a liquid crystal applied voltage of 3.9V. When the white display voltage is set to 4V, the difference in transmittance between the first VT characteristic and the second VT characteristic is about 3.8%.

  (A2) in the figure is a diagram showing the evaluation result of the burn-in determination level of the first liquid crystal display device, (B2) in the figure is a diagram showing the evaluation result of the burn-in determination level of the second liquid crystal display device, (C2) in the figure is a diagram showing the evaluation result of the burn-in determination level of the third liquid crystal display device. The vertical axis is the stress time for which the fixed checker pattern is displayed on the entire screen, and the horizontal axis is the relaxation time for displaying the uniform screen of the evaluation gradation value (G31) on the entire screen after displaying the checker pattern. It is. The values in the table are average values of the judgment levels when the observer subjectively evaluates the burn-in state at each stress time. Level 2 indicates a “poor” state in which burn-in is remarkably visually recognized. Level 3 Indicates a “bad” state where burn-in is visually recognized, level 4 indicates a state where burn-in is hardly visible when observed from the front, and level 5 indicates a “good” state where burn-in is not observed at all.

  As shown in (A2), in the first liquid crystal display device, even if the stress time is 30 minutes (30 m) or more, a determination level substantially equal to or higher than level 4 can be obtained in a relatively short relaxation time. I understand. For this reason, the burn-in of the first liquid crystal display device can be determined to be at the OK level without any particular problem.

  As shown in (B2), in the second liquid crystal display device, when the stress time is 30 minutes (30 m) or longer, it becomes difficult to obtain a determination level of level 4 or higher regardless of the relaxation time, and is determined to be level 4. It can be seen that a relaxation time of 10 minutes or more is required. For this reason, it was determined that the burn-in of the second liquid crystal display device was at the NG level.

  As shown in (C2), in the third liquid crystal display device, an evaluation result similar to that of the second liquid crystal display device is obtained. When the stress time is 30 minutes (30 m) or longer, the determination is level 4 or higher regardless of the relaxation time. It can be seen that the level becomes difficult to obtain, and it takes 10 minutes or more of relaxation time to be determined as level 4. For this reason, it was determined that the burn-in of the third liquid crystal display device was at the NG level.

  In the present embodiment, first, the maximum liquid crystal applied voltage at which the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic are substantially equal is set as the white display voltage. In the above example in which the width of the strip electrode PA is set to 2.2 μm, the first liquid crystal display device in which the difference between the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic is 2% is burned in. Can be determined to be at the OK level, “substantially equivalent” here corresponds to a case where the difference in maximum transmittance is within 2%.

  On the other hand, for the second liquid crystal display device in which the burn-in is determined to be NG level, the white display voltage is set to 3.8 V based on the first VT characteristic and the second VT characteristic shown in FIG. The Thereby, in the first VT characteristic, a transmittance of about 99% is obtained with a liquid crystal applied voltage of 3.8V, whereas in the second VT characteristic, a transmittance of about 97% is obtained with a liquid crystal applied voltage of 3.8V. . That is, in the second liquid crystal display device in which the white display voltage is set to 3.8 V, the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic are substantially equal, and the first VT characteristic and the second VT characteristic are substantially equal. The difference in transmittance is about 2%. In the second liquid crystal display device, 256 gradations are assigned in the voltage range of black display voltage 0V to white display voltage 3.8V.

  For the third liquid crystal display device in which the burn-in is determined to be NG level, the white display voltage is set to 3.7 V based on the first VT characteristic and the second VT characteristic shown in (C1) of FIG. . Thereby, in the first VT characteristic, a transmittance of about 98% is obtained with a liquid crystal applied voltage of 3.7 V, whereas in the second VT characteristic, a transmittance of about 96% is obtained with a liquid crystal applied voltage of 3.7 V. . That is, in the third liquid crystal display device in which the white display voltage is set to 3.7 V, the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic are substantially equal, and the first VT characteristic and the second VT characteristic are substantially equal. The difference in transmittance is about 2%. In the third liquid crystal display device, 256 gradations are assigned in the voltage range from the black display voltage 0V to the white display voltage 3.7V.

  The above is the optimization method using the white display voltage.

  FIG. 6 is a diagram illustrating evaluation results of burn-in determination levels after optimization of the second liquid crystal display device and the third liquid crystal display device.

  (B3) in the figure shows the evaluation result of the burn-in determination level of the second liquid crystal display device after optimization, and (C3) in the drawing shows the burn-in determination level of the third liquid crystal display device after optimization. It is a figure which shows an evaluation result. The vertical axis is the stress time for which the fixed checker pattern is displayed on the entire screen, and the horizontal axis is the relaxation time for displaying the uniform screen of the evaluation gradation value (G31) on the entire screen after displaying the checker pattern. It is.

  As shown in (B3), the second liquid crystal display device has the same evaluation result as that of the first liquid crystal display device. Even if the stress time is 30 minutes (30 m) or more, the level 4 can be achieved with a relatively short relaxation time. It can be seen that a determination level substantially equal to or higher than that is obtained. For this reason, the burn-in of the second liquid crystal display device can be determined to be at the OK level without any particular problem.

  As shown in (C3), in the third liquid crystal display device, the same evaluation results as in the first liquid crystal display device were obtained. Therefore, it was possible to determine that the burn-in of the third liquid crystal display device was at the OK level without any particular problem.

  As described above, according to the present embodiment, the maximum liquid crystal application voltage at which the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic are substantially equal is set to the white display voltage, whereby the liquid crystal Regardless of the flexographic coefficient of the material, it is possible to reduce the seizure. Therefore, display quality can be improved.

  In the above optimization method, the respective peak transmittances of the first VT characteristic and the second VT characteristic are not necessarily obtained at the set white display voltage. For example, in the second liquid crystal display device and the third liquid crystal display device described above, the transmittance of the first VT characteristic at the set white display voltage is about 1 to 2% lower than the peak transmittance. For this reason, when higher transmittance is required, not only the white display voltage is changed, but further optimization is required.

  Therefore, in the present embodiment, attention is paid to the fact that the transmittance can be adjusted by the width of the strip electrode in the pixel electrode PE applied to the FFS mode. That is, when the pixel electrode PE having a strip-like electrode with a minute width is applied, the fringe electric field formed between the pixel electrode PE and the common electrode CE is formed at a narrow pitch, and the fringe electric field Contains many vertical components perpendicular to the surface. In the FFS mode, the retardation of the liquid crystal layer is controlled by rotating the liquid crystal molecules in a plane parallel to the main surface of the substrate mainly by the horizontal component of the fringe electric field. When a fringe electric field containing a large amount of vertical components is formed, the liquid crystal molecules rise perpendicular to the main surface of the substrate and a desired retardation cannot be obtained, so that it is difficult to obtain a high transmittance. On the other hand, when the pixel electrode PE having a wide strip electrode is applied, the fringe electric field spreads in a plane parallel to the main surface of the substrate, so that the fringe electric field contains more horizontal components. For this reason, the liquid crystal molecules are unlikely to rise with respect to the main surface of the substrate, and rotate in a plane parallel to the main surface of the substrate, so that desired retardation is easily obtained. Therefore, higher transmittance can be obtained when the pixel electrode PE having a wide band-like electrode is applied than when the pixel electrode PE having a minute band-like electrode is applied. However, if the width of the strip electrode is excessively enlarged, a region where the horizontal component of the fringe electric field does not act is formed on the strip electrode, resulting in loss of transmittance. For this reason, the width | variety of the strip | belt-shaped electrode which can improve the transmittance | permeability has a restriction | limiting.

  In the present embodiment, optimization is further performed such as setting the width of the strip electrode PA in the pixel electrode PE so as to compensate for the transmittance that decreases when the white display voltage is set by the above optimization.

  FIG. 7 is a diagram showing the relationship between the optimum width of the strip electrode PA in the pixel electrode PE and the difference in transmittance between the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic.

The optimum width (μm) of the strip-shaped electrode PA on the horizontal axis is an electrode width necessary to compensate for the reduced transmittance when the optimization with the white display voltage is performed, and is a value calculated by simulation. The transmittance difference (%) on the vertical axis is the transmittance difference between the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic calculated by this simulation. In this simulation, the entire width of the pixel electrode PE along the first direction X is set to a constant value, and the electrode width per band electrode PA is changed by changing the slit width, and after optimization by the white display voltage ( In other words, in the state where it is determined that the burn-in determination is OK level), the electrode width that can obtain the same transmittance as that before the optimization by the white display voltage is calculated. The illustrated relationship is approximated by a relational expression (y = 0.0366x−0.0599, R ² = 0.9816) in the drawing.

  In other words, according to the relational expression shown in the figure, optimization is performed so that the maximum liquid crystal applied voltage at which the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic are “approximately equal” is set as the white display voltage. In doing so, the transmittance difference that can be regarded as “substantially equivalent” changes in a linear relationship with respect to the optimum width of the strip electrode PA. For example, when the optimum width of the strip electrode PA is 2.2 μm, the transmittance difference that can be regarded as “substantially equivalent” is within about 2%, and when the optimum width of the strip electrode PA is 2.5 μm, The transmittance difference that can be regarded as “substantially equivalent” is within about 3.8% when the optimum width of the strip electrode PA is 2.7 μm.

  Thereby, even after optimization by the white display voltage, by setting the optimum width of the strip electrode PA, the first peak transmittance in the first VT characteristic before the optimization or the second peak transmission in the second VT characteristic. A transmittance equivalent to the transmittance can be obtained. By performing such optimization using the strip electrode PA, the display quality can be further improved.

  As described above, according to the present embodiment, it is possible to provide a method for optimizing a liquid crystal display device that can improve display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the above embodiment, the slit PSL of the pixel electrode PE is formed to have a long axis parallel to the second direction Y, but may be formed to have a long axis parallel to the first direction X. It may be formed so as to have a long axis parallel to a direction intersecting the first direction X and the second direction Y, or may be formed in a shape bent in a dogleg shape.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate PE ... Pixel electrode PA ... Strip electrode PSL ... Slit CE ... Common electrode LQ ... Liquid crystal layer LM ... Liquid crystal molecule

Claims (3)

A first substrate including a switching element disposed in each pixel, a pixel electrode electrically connected to the switching element and including a strip electrode, and a common electrode having a common potential disposed across a plurality of pixels; A second substrate facing the first substrate; and a positive-type liquid crystal layer held between the first substrate and the second substrate, the liquid crystal applied voltage applied to the liquid crystal layer being the lowest A method of driving a normally black mode liquid crystal display device that displays black when
A first VT characteristic representing a transmittance of the liquid crystal display device with respect to a liquid crystal applied voltage when a positive voltage higher than a common potential is applied to the pixel electrode;
Measuring a second VT characteristic representing a transmittance of the liquid crystal display device with respect to a liquid crystal applied voltage when a negative voltage lower than a common potential is applied to the pixel electrode;
A method for optimizing a liquid crystal display device, wherein a maximum liquid crystal applied voltage at which the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic are substantially equal is set as a white display voltage.   The method for optimizing a liquid crystal display device according to claim 1, wherein a difference between the maximum transmittance in the first VT characteristic and the maximum transmittance in the second VT characteristic is 2% or less.   The method for optimizing a liquid crystal display device according to claim 1, wherein the width of the strip electrode is set so as to compensate for the transmittance that decreases when the white display voltage is set.

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