JP2015223019A - Arrangement wiring structure of series connection capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem of an arrangement wiring structure of a series circuit connecting 2K capacitors in series and outputting a positive electrode, an intermediate electrode and a negative electrode, that, in a configuration of simply arranging in series, the wiring inductance increases and the structure is elongated, so that compaction of efficient structure is impossible.SOLUTION: A capacitor on the highest potential side and a capacitor on the lowest potential side are arranged adjacently, a positive terminal of the capacitor on the highest potential side is defined as positive electrode output, a negative terminal of the capacitor on the lowest potential side is defined as negative electrode output, and a first capacitor series arrangement part where K capacitors on the highest potential side are arranged in series and a second capacitor series arrangement part where K capacitors on the lowest potential side are arranged in series are arranged in parallel, a connection point of a negative terminal of the K-th capacitor in the first capacitor series arrangement part and a positive terminal of the K-th capacitor in the second capacitor series arrangement part is defined as an intermediate electrode, outputting from between the capacitors on the highest potential side and the capacitors on the lowest potential side.

Description

  The present invention relates to a capacitor arrangement wiring structure applied to a main circuit of a power conversion circuit, and includes three output lines of a maximum potential, a minimum potential, and an intermediate potential from the capacitor portion, and wiring inductance when connecting to a semiconductor switch circuit. The present invention relates to a reduced placement and wiring structure technology.

FIG. 4 shows a main circuit diagram of a three-level inverter that converts direct current, which is a representative circuit of the power conversion circuit, into three-phase alternating current. 1 is a DC power supply circuit, 2 is a load such as a motor, and 3 is an inverter circuit constituted by a power semiconductor. The inverter circuit 3 has a configuration in which a U-phase arm UA, a V-phase arm VA, and a W-phase arm WA are connected in parallel to the DC power supply circuit 1. Since the circuit configuration of each phase arm (UA, VA, WA) is the same, the U-phase arm will be described. TU1 to TU4 connected in series are IGBTs as semiconductor switch elements, and DU1 to DU4 are freewheeling diodes connected in reverse parallel to each IGBT. The diodes CDU 1 and CDU 2 are neutral point clamping diodes that clamp the AC output potential to the intermediate pole M of the intermediate potential of the DC power supply circuit 1. The AC output, which is the connection point between IGBTTU2 and TU3, can output three potentials: the potential of the positive electrode P of the DC power supply circuit 1, the potential of the intermediate electrode M, and the potential of the negative electrode N. This is called a three-level inverter. . However, in general, the DC power supply circuit 1 is generally composed of a large-capacity capacitor shown in the figure via an AC power supply (not shown) and a diode rectifier. Further, when the DC voltage is higher than the voltage rating of the capacitor to be applied, it is necessary to make a multi-series connection like capacitors Cp1 and Cp2 and Cn1 and Cn2 as shown in the DC power supply circuit 1 of FIG.

  FIG. 5 shows an example of a wiring arrangement structure of a plurality of capacitors connected in series. FIG. 5A shows a configuration when two capacitors are connected in series between the positive electrode P and the intermediate electrode M of the DC power source and between the intermediate electrode M and the negative electrode N when K = 2. FIG. 5B shows a configuration in which three capacitors are connected in series between the positive electrode P and the intermediate electrode M of the DC power source and between the intermediate electrode M and the negative electrode N when K = 3. It is. In FIG. 5A, the potential of the positive terminal of the capacitor Cp1 on the highest potential side is the positive electrode P, and is connected to the P-side potential circuit of the conversion circuit by the conductor 4. The negative terminal of the capacitor Cp1 and the positive terminal of the capacitor Cp2 having the same potential are connected by the conductor 5. Similarly, the conductor 7 is connected between the negative terminal of the capacitor Cp2 and the positive terminal of Cn1, the conductor 8 is connected between the negative terminal of the capacitor Cn1 and the positive terminal of Cn2, and the negative terminal of the capacitor Cn2 on the lowest potential side is the negative electrode N. Thus, the conductor 10 is connected to the N potential circuit of the conversion circuit. The conductor 7 connecting the negative terminal of the capacitor Cp2 and the positive terminal of Cn1 is an intermediate pole M having an intermediate potential, and is connected to the M potential circuit of the conversion circuit.

  In FIG. 5B, the potential of the positive terminal of the capacitor Cp1 on the highest potential side is the positive electrode P, and is connected to the P-side potential circuit of the conversion circuit by the conductor 4. The positive terminal of the capacitor Cp2 having the same potential as the negative terminal of the capacitor Cp1 is connected by the conductor 5, and the positive terminal of the capacitor Cp3 having the same potential as the negative terminal of the capacitor Cp2 is connected by the conductor 6. Similarly, the conductor 7 is between the negative terminal of the capacitor Cp3 and the positive terminal of Cn1, the conductor 8 is between the negative terminal of the capacitor Cn1 and the positive terminal of Cn2, and the conductor 9 is between the negative terminal of Cn2 and the positive terminal of Cn3. The negative terminal of the capacitor Cn3 on the lowest potential side becomes the negative electrode N, and is connected to the N potential circuit of the conversion circuit by the conductor 10. The conductor 7 connecting the negative terminal of the capacitor Cp3 and the positive terminal of Cn1 becomes an intermediate pole M having an intermediate potential, and is connected to the M potential circuit of the conversion circuit.

FIG. 5C shows a conventional technique in which parallel plate wiring is performed with an insulating material (not shown) interposed therebetween in order to reduce wiring inductance in FIG. The conductor 7x that outputs the intermediate pole M of the intermediate potential, the conductor 5 that connects the negative terminal of the capacitor Cp1 and the positive terminal of Cp2, the conductor 10x that outputs the negative terminal of the lowest potential, and the negative terminal of the capacitor Cn1 and the positive terminal of Cn2 are connected. The conductor 8 to be laminated is laminated and wiring inductance is reduced.
The arrangement and connection method of the three-level conversion circuit and the series capacitor as shown in FIG. 4 are described in Patent Documents 1 and 2, and the flat plate connection method of the capacitor and conversion circuit of the three-level inverter is described in Patent Document 3 Has been.

JP-A-11-155286 JP-A-8-214561 JP 2010-288415 A

FIG. 6 shows an operation diagram when the IGBT (TU1) of the U-phase arm UA is turned off in the three-level inverter circuit shown in FIG.
In FIG. 6, when the IGBT (TU1) is in the ON state (mode 1), when the IGBT (TU1) is turned off from the state where the currents I1 and I2 indicated by the dotted lines are flowing, the diode CDU1 becomes conductive and the current path I3, Commutated to I4 (mode 2). At that time, depending on the wiring inductance of the capacitor and the switch element connection line, the wiring inductance L1, L2, L3, L4, and L5 of the connection line between the capacitors, and the current change rate (di / dt) of the IGBT, A voltage is generated in the wiring inductance in the + direction in FIG.

As a result, the maximum voltage expressed by the equation (1) is applied between the collector and emitter of the IGBT (DU1). FIG. 7 shows the collector current (ic) and collector-emitter voltage (V _CE ) waveforms when the IGBT (TU1) is turned off.
V _{CE (peak)} = Edp + (L1 + L2 + L3 + L4 + L5) × di / dt (1) Surge voltage ΔV = (L1 + L2 + L3 + L4 + L5) × di / dt (2)
Edp: DC power source positive side DC voltage (capacitor voltage)
di / dt: IGBT current change rate L1, L2, L3, L4, L5 at IGBT turn-off: inductance value of each wiring

As an example, in the case of an IGBT of several hundreds of A class, the maximum di / dt is about 5000 A / μs. Therefore, assuming that L1 + L2 + L3 + L4 + L5 = 50 nH, the surge amount ((L1 + L2 + L3 + L4 + L5) × di / dt) = 250V It becomes.
Therefore, due to the presence of each wiring inductance, the peak voltage value applied to the IGBT when the IGBT is turned off becomes higher than the DC voltage (Edp) by the surge voltage (ΔV) of the above equation (2).
In particular, when the number of capacitors in series increases, the wiring inductance value between the capacitors increases in proportion to the number of series, so that the problem of an increase in the surge voltage occurs. As a result, an IGBT with a high breakdown voltage is required.

In addition, if the capacitor arrangement as shown in FIG. 5C, the M potential wiring 7x, the N potential wiring 10x, and each wiring have a parallel-plate wiring structure, the capacitor portion of the capacitor portion can be obtained by optimizing the current. Although the wiring inductance can be reduced and the above-mentioned problems can be reduced, the wiring structure is complicated because, for example, the wiring 5 is three-layered, so that the insulating material needs to be two layers.
Further, if the capacitors are arranged in a straight line, the structure becomes extremely long in the longitudinal direction, so that the space factor cannot be effectively used from the viewpoint of the overall device design.
Accordingly, an object of the present invention is to provide a capacitor arrangement and wiring structure in which 2K (K is an integer of 2 or more) capacitors are connected in series and three potentials of a maximum potential, a minimum potential, and an intermediate potential are output. It is to provide an arrangement and a wiring structure that can reduce wiring inductance and reduce arrangement restrictions, make it possible to use a low-breakdown-voltage semiconductor element, and realize downsizing and cost reduction of the device.

  In order to solve the above-mentioned problem, in the first invention, 2K (K is a positive integer of 2 or more) capacitors are connected in series, and three potentials of a maximum potential, a minimum potential, and an intermediate potential are set. In the capacitor arrangement and wiring structure to be output, the capacitor on the highest potential side and the capacitor on the lowest potential side are arranged adjacent to each other, the positive terminal of the capacitor on the highest potential side is set as the highest potential electrode output, First capacitor series arrangement in which the negative terminal of the capacitor on the lowest potential side is the lowest potential electrode output, and K capacitors are arranged in series from the highest potential to the lowest one based on the highest potential capacitor. And a second capacitor series arrangement unit in which K capacitors are arranged in series from the lowest potential to the highest one based on the lowest potential side capacitor in parallel. Terminals having the same potential of adjacent capacitors in the first and second capacitor series arrangement portions are short-circuited with series connection wiring materials, respectively, and the negative terminal of the Kth capacitor in the first capacitor series arrangement portion The connection point of the second capacitor series arrangement portion with the positive terminal of the Kth capacitor is an intermediate potential electrode, and the intermediate potential electrode is connected to the highest potential capacitor and the lowest potential capacitor. Output from between.

  In the second invention, the parallel plate wiring in which the wiring material for output of the intermediate potential electrode in the first invention and the serial connection wiring material in the first and second capacitor series arrangement portions are sandwiched with an insulating material Structure.

  In a third invention, the parallel plate wiring structure sandwiching the insulating material in the second invention uses an L-shaped conductor as a serial connection wiring material in the first and second capacitor series arrangement portions, A U-shaped conductor is used as a wiring material for output of an intermediate potential electrode, and the insulating material is sandwiched in parallel with the capacitor terminal.

  In a fourth invention, the parallel plate wiring structure sandwiching the insulating material in the second invention is a wiring material for output of the intermediate potential electrode and a series connection in the first and second capacitor series arrangement portions. A conductor including a flat plate portion is used as the wiring member, and the insulating material is sandwiched between the flat plate portion in a direction orthogonal to the capacitor terminal.

In the present invention, the capacitor on the highest potential side and the capacitor on the lowest potential side are arranged adjacent to each other, the positive terminal of the capacitor on the high potential side is set as the highest potential electrode output, and the negative terminal of the capacitor on the lowest potential side Is the lowest potential electrode output, and the first capacitor series arrangement portion in which K capacitors are arranged in order from the highest potential to the lowest potential with reference to the high potential side capacitor, and the low potential side capacitor A second capacitor series arrangement section in which K capacitors are arranged in series in order from the lowest potential to the highest one as a reference is arranged in parallel, and the negative terminal of the Kth capacitor of the first capacitor series arrangement section The connection point of the second capacitor series arrangement portion with the positive terminal of the Kth capacitor is an intermediate potential electrode, and the intermediate potential electrode is connected to the highest potential capacitor and the highest potential electrode. It is outputted from between the low potential side of the capacitor.
As a result, it is possible to provide an arrangement and wiring structure of a series capacitor that can reduce the wiring inductance by an arrangement that can reduce structural constraints and a wiring structure, and a low-breakdown-voltage semiconductor element can be used. Pricing is possible.

1 is a structural diagram showing a first embodiment of the present invention. FIG. 3 is a structural diagram showing a second embodiment of the present invention. It is a structural diagram which shows the 3rd Example of this invention. It is an example of a circuit diagram of a three level inverter. It is an example of an arrangement connection diagram of conventional capacitor series connection. It is an example of wiring inductance and an operation mode in a three level inverter. It is an example of an operation waveform at the time of IGBT turn-off.

  The main point of the present invention is that the capacitor on the highest potential side and the capacitor on the lowest potential side are arranged adjacent to each other, the positive terminal of the capacitor on the high potential side is the highest potential electrode output, and the capacitor on the lowest potential side is A first capacitor series arrangement section in which a negative terminal is set to the lowest potential electrode output, and K capacitors are arranged in series from the highest potential to the lowest with reference to the high potential side capacitor; A second capacitor series arrangement section in which K capacitors are arranged in series in order from a low potential to a high potential based on the capacitor is arranged in parallel, and the negative of the Kth capacitor in the first capacitor series arrangement section is arranged. A connection point between the terminal and the positive terminal of the Kth capacitor in the second capacitor series arrangement portion is an intermediate potential electrode, and the intermediate potential electrode is connected to the highest potential side capacitor and the front side. In that the output from between the lowest potential side of the capacitor.

  FIG. 1 shows a first embodiment of the present invention. FIG. 1A shows a configuration when K = 2, and FIG. 1B shows a configuration when K = 3. In FIG. 1A, the capacitor Cp1 on the highest potential side and the capacitor Cn2 on the lowest potential side are arranged adjacent to each other. Capacitors Cp1 and Cp2 are arranged in series to constitute a first capacitor series arrangement part, and capacitors Cn2 and Cn1 are arranged in series to constitute a second capacitor series arrangement part. The first capacitor series arrangement unit and the second capacitor series arrangement unit are arranged in parallel. In the first capacitor series arrangement portion, the negative terminal of the capacitor Cp1 and the positive terminal of CP2 are connected by the conductor 5. In the second capacitor series arrangement portion, the positive terminal of the capacitor Cn2 and the negative terminal of Cn1 are connected by the conductor 8. The positive terminal of the capacitor Cp1 on the highest potential side is output as the highest potential electrode P on the conductor 4, and the negative terminal of the capacitor Cn2 on the lowest potential side is output as the lowest potential electrode N on the conductor 10, respectively. The negative terminal of the 2 (K = 2) th capacitor Cp2 of the first capacitor series arrangement portion and the positive terminal of the 2 (K = 2) th capacitor Cn1 of the second capacitor series arrangement portion are connected by a conductor 7a. The intermediate potential electrode M is output from between the highest potential side capacitor Cp1 and the lowest potential side capacitor Cn2.

  With such a configuration, the conductors 4 and 7a, the conductors 5 and 7a, the conductors 8 and 7a, and the conductors 10 and 7a are magnetically coupled, and the inductance is reduced as compared with the conventional example shown in FIG. Since this configuration does not have a parallel plate configuration, an insulating material is unnecessary and the structure is simplified.

  FIG. 1B shows the configuration when K = 3. In FIG. 1B, the capacitor Cp1 on the highest potential side and the capacitor Cn3 on the lowest potential side are arranged adjacent to each other. The capacitors Cp1 to Cp3 are arranged in series to constitute a first capacitor series arrangement part, and the capacitors Cn3 to Cn1 are arranged in series to constitute a second capacitor series arrangement part. The first capacitor series arrangement unit and the second capacitor series arrangement unit are arranged in parallel. In the first capacitor series arrangement portion, the negative terminal of the capacitor Cp1 and the positive terminal of CP2 are connected by the conductor 5, and the negative terminal of the capacitor Cp2 and the positive terminal of CP3 are connected by the conductor 5, respectively. In the second capacitor series arrangement portion, the positive terminal of the capacitor Cn3 and the negative terminal of Cn2 are connected by the conductor 9, and the positive terminal of the capacitor Cn2 and the negative terminal of Cn1 are connected by the conductor 8, respectively. The positive terminal of the capacitor Cp1 on the highest potential side is output as the highest potential electrode P on the conductor 4, and the negative terminal of the capacitor Cn2 on the lowest potential side is output as the lowest potential electrode N on the conductor 10, respectively. The negative terminal of the 3 (K = 3) th capacitor Cp3 of the first capacitor series arrangement part and the positive terminal of the 3 (K = 3) th capacitor Cn1 of the second capacitor series arrangement part are connected by a conductor 7b. The intermediate potential electrode M is output from between the highest potential side capacitor Cp1 and the lowest potential side capacitor Cn3.

  With such a configuration, the conductors 4 and 7b, the conductors 5 and 7b, the conductors 6 and 7b, the conductors 8 and 7b, the conductors 9 and 7b, and the conductors 10 and 7a are magnetically coupled, and the inductance is the same as in the conventional example shown in FIG. Compared to (b). In this configuration, since each of them does not have a parallel plate configuration using an insulating material, an insulating material is unnecessary and the structure is simplified. In addition, since the dimension in the series arrangement direction is about half that of the conventional example shown in FIG. 5B, restrictions on arrangement can be reduced.

  FIG. 2 shows a second embodiment of the present invention. FIG. 2A shows a configuration when K = 2, and FIG. 2B shows a configuration when K = 3. In FIG. 2A, the capacitor Cp1 on the highest potential side and the capacitor Cn2 on the lowest potential side are arranged adjacent to each other. Capacitors Cp1 and Cp2 are arranged in series to constitute a first capacitor series arrangement part, and capacitors Cn2 and Cn1 are arranged in series to constitute a second capacitor series arrangement part. The first capacitor series arrangement unit and the second capacitor series arrangement unit are arranged in parallel. In the first capacitor series arrangement portion, the negative terminal of the capacitor Cp1 and the positive terminal of CP2 are connected by an L-shaped conductor 5a. In the second capacitor series arrangement portion, the positive terminal of the capacitor Cn2 and the negative terminal of Cn1 are connected by an L-shaped conductor 8a. The positive terminal of the capacitor Cp1 on the highest potential side is the L-shaped conductor 4a as the highest potential electrode P, and the negative terminal of the capacitor Cn2 on the lowest potential side is the output as the lowest potential electrode N with the L-shaped conductor 10a. Is done. The negative terminal of the second (K = 2) -th capacitor Cp2 of the first capacitor series arrangement unit and the positive terminal of the second (K = 2) -th capacitor Cn1 of the second capacitor series arrangement unit are connected by a conductor 7c. The intermediate potential electrode M is output from between the highest potential side capacitor Cp1 and the lowest potential side capacitor Cn2. A portion of the conductor 7c juxtaposed with the conductors 4a, 5a, 8a, and 10a is formed in a U-shape, the conductors 4a and 5a sandwich the insulating material 11, and the conductors 8a and 10a include the insulating material 12. The adjacent wirings are sandwiched between them. As the insulating material, an insulating film, an epoxy resin plate, or the like can be used.

  With such a configuration, the conductors 4a and 7c, the conductors 5a and 7c, the conductors 8a and 7c, and the conductors 10a and 7c are more magnetically coupled than the first embodiment, respectively, and the inductance is the same as that of the conventional example shown in FIG. ) And the embodiment is reduced as compared with FIG. In this configuration, since each conductor is magnetically tightly coupled, the effect of reducing wiring inductance is great.

  FIG. 2B shows the configuration when K = 3. In FIG. 2B, the capacitor Cp1 on the highest potential side and the capacitor Cn3 on the lowest potential side are arranged adjacent to each other. The capacitors Cp1 to Cp3 are arranged in series to constitute a first capacitor series arrangement part, and the capacitors Cn3 to Cn1 are arranged in series to constitute a second capacitor series arrangement part. The first capacitor series arrangement unit and the second capacitor series arrangement unit are arranged in parallel. In the first capacitor series arrangement portion, the negative terminal of the capacitor Cp1 and the positive terminal of CP2 are connected by the conductor 5a, and the negative terminal of the capacitor Cp2 and the positive terminal of CP3 are connected by the conductor 6a. In the second capacitor series arrangement portion, the positive terminal of the capacitor Cn3 and the negative terminal of Cn2 are connected by the conductor 9a, and the positive terminal of the capacitor Cn2 and the negative terminal of Cn1 are connected by the conductor 8a. The positive terminal of the capacitor Cp1 on the highest potential side is output as the highest potential electrode P on the conductor 4a, and the negative terminal of the capacitor Cn3 on the lowest potential side is output as the lowest potential electrode N on the conductor 10a. The negative terminal of the 3 (K = 3) th capacitor Cp3 of the first capacitor series arrangement part and the positive terminal of the 3 (K = 3) th capacitor Cn1 of the second capacitor series arrangement part are connected by a conductor 7d. The intermediate potential electrode M is output from between the highest potential side capacitor Cp1 and the lowest potential side capacitor Cn3. A portion of the conductor 7d juxtaposed with the conductors 4a to 6a and 8a to 10a is formed in a U-shape, the conductors 4a to 6a sandwich the insulating material 11a, and the conductors 8a to 10a are made of the insulating material 12a. The adjacent wirings are sandwiched between them.

  With such a configuration, the conductors 4a and 7d, the conductors 5a and 7d, the conductors 6a and 7d, the conductors 8a and 7d, the conductors 9a and 7d, and the conductors 10a and 7d are each magnetically coupled, and the inductance is the conventional example. This is reduced compared to FIG. 5B or the first embodiment. In this configuration, since the conductors are closely magnetically coupled, the effect of reducing the wiring inductance is great, and the surge voltage ΔV at the time of IGBT turn-off can be suppressed to a small value. In addition, since the dimension in the series arrangement direction is about half that of the conventional example shown in FIG. 5B, restrictions on arrangement can be reduced.

FIG. 3 shows a third embodiment of the present invention. The difference from the second embodiment is the magnetic coupling method, in which the second embodiment uses an L-shaped conductor, whereas the second embodiment uses a flat plate.
FIG. 3A shows an embodiment when K = 2, and FIG. 3B shows an embodiment when K = 3. In FIG. 3A, the capacitor Cp1 on the highest potential side and the capacitor Cn2 on the lowest potential side are arranged adjacent to each other. Capacitors Cp1 and Cp2 are arranged in series to constitute a first capacitor series arrangement part, and capacitors Cn2 and Cn1 are arranged in series to constitute a second capacitor series arrangement part. The first capacitor series arrangement unit and the second capacitor series arrangement unit are arranged in parallel. In the first capacitor series arrangement portion, the negative terminal of the capacitor Cp1 and the positive terminal of CP2 are connected by the conductor 5. In the second capacitor series arrangement portion, the positive terminal of the capacitor Cn2 and the negative terminal of Cn1 are connected by the conductor 8. The positive terminal of the capacitor Cp1 on the highest potential side is output as the highest potential electrode P on the conductor 4, and the negative terminal of the capacitor Cn2 on the lowest potential side is output as the lowest potential electrode N on the conductor 10, respectively. The negative terminal of the 2 (K = 2) th capacitor Cp2 of the first capacitor series arrangement part and the positive terminal of the 2 (K = 2) th capacitor Cn1 of the second capacitor series arrangement part are connected by a conductor 7e. The intermediate potential electrode M is output from between the highest potential side capacitor Cp1 and the lowest potential side capacitor Cn2. The conductor 7e and the conductors 4, 5, 8, and 10 are formed in a laminate structure with the insulating material 13 interposed therebetween.

With this configuration, the conductors 4 and 7e, the conductors 5 and 7e, the conductors 8 and 7e, and the conductors 10 and 7e are magnetically coupled, and the wiring inductance is the same as that shown in FIG. Compared to examples. In this embodiment, the laminate structure shows a configuration in which the insulating material 13 is arranged on the conductor 7e and the conductors 4, 5, 8, and 10 are arranged on the insulating material 13, but the conductor 7e and the conductor 4 are shown. It is also possible to replace 5, 8, 10 with each other. Further, the flat portion of the conductor 7e can be realized only by the portion laminated with the conductors 4, 5, 8, and 10.

  In FIG. 3B, the capacitor Cp1 on the highest potential side and the capacitor Cn2 on the lowest potential side are arranged adjacent to each other. The capacitors Cp1 to Cp3 are arranged in series to constitute a first capacitor series arrangement part, and the capacitors Cn3 to Cn1 are arranged in series to constitute a second capacitor series arrangement part. The first capacitor series arrangement unit and the second capacitor series arrangement unit are arranged in parallel. In the first capacitor series arrangement portion, the negative terminal of the capacitor Cp1 and the positive terminal of CP2 are connected by the conductor 5, and the negative terminal of the capacitor Cp2 and the positive terminal of CP3 are connected by the conductor 6, respectively. In the second capacitor series arrangement portion, the positive terminal of the capacitor Cn3 and the negative terminal of Cn2 are connected by the conductor 9, and the positive terminal of the capacitor Cn2 and the negative terminal of Cn1 are connected by the conductor 8, respectively. The positive terminal of the capacitor Cp1 on the highest potential side is output as the highest potential electrode P on the conductor 4, and the negative terminal of the capacitor Cn3 on the lowest potential side is output as the lowest potential electrode N on the conductor 10, respectively. The negative terminal of the 3 (K = 3) th capacitor Cp3 of the first capacitor series arrangement part and the positive terminal of the 3 (K = 3) th capacitor Cn1 of the second capacitor series arrangement part are connected by a conductor 7f. The intermediate potential electrode M is output from between the highest potential side capacitor Cp1 and the lowest potential side capacitor Cn3. The conductor 7f and the conductors 4-6, 8-10 are formed in a laminate structure with an insulating material 13a interposed therebetween.

  With such a configuration, the conductors 4 and 7f, the conductors 5 and 7f, the conductors 6 and 7f, the conductors 8 and 7f, the conductors 9 and 7f, and the conductors 10 and 7f are magnetically coupled, and the inductance is the same as in the conventional example shown in FIG. It is reduced as compared with (b) or the first embodiment. In this embodiment, the laminate structure shows a configuration in which the insulating material 13a is disposed on the conductor 7f, and the conductors 4-6 and 8-9 are disposed on the insulating material 13a. This can be realized by replacing the conductors 4 to 6 and 8 to 9. Further, the flat portion of the conductor 7f can be realized only by the portion laminated with the conductors 4-6 and 8-9.

In this embodiment, an example is shown in which an IGBT is used as a cylindrical capacitor and a semiconductor device. However, the present invention can also be applied to a case where a cubic capacitor or another power semiconductor device such as a MOSFET is used. The present invention can also be applied when using a printed circuit board mounting type capacitor or a power semiconductor. In the above embodiment, the capacitor is applied to the DC portion of the power conversion circuit. However, all systems (resonance circuit, snubber circuit, filter circuit, etc.) that require a reduction in wiring inductance between capacitors connected in series. ) Is also applicable.

  The present invention is a proposal for reducing wiring inductance when a plurality of capacitors are connected in series, and can be applied to an inverter for driving a motor using a multilevel power conversion circuit, an uninterruptible power supply, a DC power supply, and the like. is there.

DESCRIPTION OF SYMBOLS 1 ... DC power supply circuit 2 ... Load 3 ... Inverter circuits 4-10, 4a-10a, 7a-7f ... Conductor
11-13, 11a-13a ... Insulating materials Cp1-Cp3, Cn1-Cn3 ... Capacitors TU1-TU4, TV1-TV4, TW1-TW4 ... IGBT
DU1 to DU4, DV1 to DV4, DW1 to DW4 ... Diodes CDU1, CDU2, CDV1, CDV2, CDW1, CDW2 ... Diodes

Claims (4)

2K (K is an integer of 2 or more) capacitors connected in series, and in the capacitor arrangement and wiring structure that outputs three potentials of the highest potential, the lowest potential, and the intermediate potential, The capacitor on the lowest potential side is disposed adjacent to the positive terminal of the capacitor on the highest potential side as the highest potential electrode output, and the negative terminal of the capacitor on the lowest potential side is set as the lowest potential electrode output. A first capacitor series arrangement unit in which K capacitors are arranged in order from a higher potential to a lower one with reference to a capacitor on the high potential side, and K capacitors on the basis of the capacitor on the lowest potential side. A second capacitor series arrangement section arranged in series in order from a low potential to a high potential is arranged in parallel, and the adjacent capacitors in the first and second capacitor series arrangement sections are arranged. The terminals having the same potential of the sensor are short-circuited with a serial connection wiring material, and the negative terminal of the Kth capacitor in the first capacitor series arrangement section and the Kth capacitor of the second capacitor series arrangement section are connected. A series-connected capacitor arrangement characterized in that a connection point with a positive terminal is an intermediate potential electrode, and the intermediate potential electrode outputs from between the highest potential side capacitor and the lowest potential side capacitor. Wiring structure.   The series connection capacitor arrangement wiring structure according to claim 1, wherein an insulating material is sandwiched between the wiring material for output of the intermediate potential electrode and the series connection wiring material in the first and second capacitor series arrangement portions. An arrangement wiring structure of series-connected capacitors, characterized by a parallel plate wiring structure.   The parallel connection wiring structure of the serial connection capacitor according to claim 2, wherein the parallel plate wiring structure sandwiching the insulating material is an L-shaped conductor as a serial connection wiring material in the first and second capacitor serial arrangement portions. A series-connected capacitor arrangement wiring structure characterized by using a U-shaped conductor as a wiring material for output of the intermediate potential electrode and sandwiching the insulating material in parallel with the capacitor terminal .   3. The series-connected capacitor arrangement wiring structure according to claim 2, wherein the parallel plate wiring structure sandwiching the insulating material is provided in the wiring material for output of the intermediate potential electrode and the first and second capacitor series arrangement portions. An arrangement wiring structure of series connection capacitors, wherein a conductor including a flat plate portion is used as the serial connection wiring material, and the insulating material is sandwiched between the flat plate portions in a direction orthogonal to the capacitor terminals.