JP2015216779A - Dc/dc converter and power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply having high responsiveness to the change of power consumption in a loading device, while preventing the occurrence of backflow current.SOLUTION: DC/DC converters 1-4 include: a switch SWa connected to the voltage source of an input voltage Vin; a switch SWb connected to a ground terminal; a driver circuit 24 for driving the switches SWa and SWb; and a backflow current detection circuit 42 for detecting backflow current. The driver circuit 24 switches on the switches SWa and SWb when the DC/DC converters 1-4 generate positive output current, whereas the driver circuit 24 switches off the switch SWb when backflow current is detected by the backflow current detection circuit 42 during a preset time period after the activation of a power supply 10.

Description

  The present invention relates to a power supply device including a plurality of DC / DC converters connected in parallel, and a DC / DC converter for such a power supply device.

  A portable device is required to be further downsized with higher performance and higher functionality, and more power is required. For this reason, the power supply device mounted in a portable device is smaller, can handle a large amount of power, and is required to be highly efficient.

  As a candidate for a solution to this problem, a power supply device (multiphase power supply device) using a multiphase power supply technology in which a plurality of DC / DC converters (hereinafter referred to as “converters”) are connected in parallel is already known. In a multi-phase power supply device, a plurality of converters are connected in parallel, and a predetermined phase difference is given to synchronize the switching operations of these converters.

  Since the ripple can be reduced by combining the output currents of the plurality of converters, there is an advantage that it is not necessary to use a large passive element to configure a filter provided in the output unit of the power supply device. In addition, since the current flowing through each converter is smaller than when the power supply unit consists of only a single converter, the heat generated by circuit loss in each converter is also reduced, and the requirements for heat dissipation performance for each converter are relaxed. There is an advantage that. These advantages facilitate the miniaturization of the power supply device.

  Furthermore, when the power consumption of the load device is small, there is an advantage that the power conversion efficiency of the entire power supply device can be improved by suspending some converters. There is an advantage that high efficiency can be maintained over a wide range from the case where the power consumption of the load device is small to the case where it is large.

  As examples of the multi-phase power supply device, for example, the inventions of Patent Documents 1 and 2 are known.

  In recent years, in order to reduce costs, there is a demand for reducing the types of parts even when different products are manufactured. Conventionally, it has been necessary to select an optimal power supply device individually according to the power consumption of the load device. On the other hand, by applying multi-phase power supply technology, various types of converters connected in parallel using only one type of converter for the required specifications (output voltage and output current specifications) of various devices. Promising to provide a power supply with

  In general, it is already known that a function for preventing the generation of excessive reverse current is implemented in a multi-phase power supply apparatus for safety. This is because, when a plurality of converters are connected in parallel, a current reverse flow phenomenon may occur (for a converter on the side where current flows) in which current flows through from one converter to another. When such a backflow current occurs, not only is the energy of the backflow current lost, but the excessive backflow current leads to destruction of the converter. For this reason, the converter of a multiphase power supply device generally has a function of preventing the generation of excessive backflow current.

  The function of preventing the generation of excessive backflow current may be disabled for a backflow current that is small enough not to destroy the power supply device. This is because when the sudden fluctuation from heavy load to light load that can occur on a daily basis occurs, the output voltage of the power supply device rises transiently, but it is output early by instantaneously reversing the current. It is possible to return the voltage to a desired value and return the converter control system to a steady state. For this reason, from the viewpoint of responsiveness, it is rather desirable to allow the backflow current as long as the power supply device is not destroyed. Moreover, since it is a transient phenomenon, the loss due to the backflow current is also limited.

  However, until now, there has been a problem that in a multiphase power supply device, a through current may flow transiently between the converters when the power is turned on. Since all the current flowing through the converters is lost as described above, a loss occurs every time the power is turned on. In particular, in a portable device, it is important to make the power source finely turned on and off to make the battery duration as long as possible. Therefore, every time the power source is turned on and off, a loss occurs in the converter.

  As a countermeasure, a method of operating only one of the converters connected in parallel until the control for equalizing the output current between the converters connected in parallel after the power is turned on can be considered. The intent of this method is to start up the converters in order after correcting device variations that cause through currents between converters. However, when the power consumption of the load device is large, there is a problem that the output voltage of the power supply device decreases and the power supply device does not function normally. If the power consumption of the load device is large immediately after the power is turned on, the desired output power cannot be obtained with only one converter, and the output voltage of the power supply device decreases, so the load device operates normally. It will disappear.

  As another countermeasure, it can be considered that the detection threshold value of the backflow current prevention function is lowered so that even a small backflow current is not allowed. However, according to this control method, although the loss of the backflow current that occurs transiently when the power is turned on can be suppressed, there is a problem that the responsiveness deteriorates. That is, when a sudden change from heavy load to light load occurs, if the reverse current is not allowed, the output voltage of the converter rises transiently, and a high voltage is supplied to the load device to drop it. It takes time. In the worst case, the load device may be destroyed by supplying a high voltage from the power supply device to the load device.

  Even when a converter among the converters connected in parallel shifts from a sleep state to an operation state, a through current may flow due to device variations between the converters when power is turned on, resulting in a loss. was there. For this reason, in order to improve the efficiency, if the converter is stopped according to the fluctuation of the power consumption of the load device and the number of parallel operations is finely changed, the loss may increase and the efficiency may be lowered. was there.

  For example, Patent Document 1 makes the backflow current prevention function effective only at the time of abnormality such as when the power is turned on or at the time of failure, and disables the backflow current prevention function at other times for the purpose of preventing the decrease in efficiency due to the backflow current prevention function. This technology is disclosed. The power supply apparatus of patent document 1 contains the diode as a backflow current prevention element. In synchronous rectification type switching power supplies for small output currents, MOSFETs that are more advantageous in terms of efficiency characteristics than diodes are often used. Since the MOSFET does not have a backflow current prevention function, the technique of Patent Document 1 cannot be applied, and the problem of loss due to through current between converters cannot be solved.

  For this reason, a reverse current prevention function applicable to a converter that is a synchronous rectification type switching power supply is required.

  An object of the present invention is a power supply device including a plurality of DC / DC converters connected in parallel, and a power supply device having high responsiveness to fluctuations in power consumption of a load device while preventing the occurrence of backflow current. It is to provide.

According to the power supply device according to the aspect of the present invention,
In a power supply device including a plurality of DC / DC converters connected in parallel,
Each of the plurality of DC / DC converters is
A first switch and a second switch connected in series between a voltage source of the input voltage and a ground terminal, the first switch connected to the voltage source of the input voltage and a second switch connected to the ground terminal. And the switch
A drive circuit for driving the first and second switches;
An output terminal of the DC / DC converter connected to a node between the first and second switches;
A reverse current detection circuit for detecting a reverse current from the output terminal to a node between the first and second switches;
The drive circuit is
When the DC / DC converter is generating a positive output current, the first or second switch is turned on,
The second switch is turned off when a backflow current is detected by the backflow current detection circuit during a predetermined time period after starting the power supply device.

  According to the power supply device of the present invention, the power supply device includes a plurality of DC / DC converters connected in parallel, and is highly responsive to fluctuations in the power consumption of the load device while preventing the occurrence of backflow current. A power supply device can be provided.

1 is a block diagram illustrating a configuration of a power supply device 10 according to a first embodiment of the present invention. It is a block diagram which shows the detailed structure of the converter 1 of FIG. It is a block diagram which shows the detailed structure of the converter 2 of FIG. FIG. 4 is a circuit diagram showing a detailed configuration of an error detection circuit 21 in FIGS. 2 and 3. FIG. 4 is a circuit diagram showing a detailed configuration of a voltage adjustment circuit 28 in FIG. 3. FIG. 3 is a block diagram illustrating a detailed configuration of an M / S determination circuit 30 in FIG. 2. It is a block diagram which shows the detailed structure of the starting circuit 31 of FIG. It is a flowchart which shows the synchronous starting process performed by the synchronous starting circuit 87 of FIG. It is a timing chart which shows operation | movement of switch SWa, SWb of the power supply device which concerns on the 2nd Embodiment of this invention. It is a timing chart which shows operation of switches SWa and SWb of a comparative example.

  Hereinafter, features of a power supply device according to an embodiment of the present invention will be described in detail with reference to the drawings.

First embodiment.
[Overall Configuration of Power Supply Device 10]
FIG. 1 is a block diagram showing a configuration of a power supply device 10 according to the first embodiment of the present invention. 1 includes a plurality of DC / DC converters (hereinafter referred to as “converters”) 1 to 4 connected in parallel, inductors L1 to L4, and a capacitor C1.

  Converters 1 to 4 have the same configuration, but one of them operates as a master converter and the other operates as a slave converter. In the embodiment to be described, the converter 1 operates as a master converter that always generates an output current during the operation of the power supply device 10. Converters 2 to 4 operate as slave converters having an operation state in which an output current is generated during operation of power supply device 10 and a dormant state in which no output current is generated.

  Converters 1 to 4 have terminals 1a to 1g, 2a to 2g, 3a to 3g, and 4a to 4g, respectively.

  The terminals 1a to 4a are connected to a voltage source of the input voltage Vin, respectively. The terminals 1b to 4b are connected to each other, and send a signal (for example, a voltage signal) Vsense1 indicating the magnitude of the output current of the converter 1 from the master converter 1 to the slave converters 2 to 4. The terminals 1c to 4c are connected to each other and send a clock signal CLK from the master converter 1 to the slave converters 2 to 4.

  Terminals 1d to 4d are connected to an external control device (not shown), and an enable signal EN for starting (powering on) the entire power supply device 10 is input.

  Terminals 1f to 4f are connected to a node of output voltage Vout (one end of capacitor C1) via inductors L1 to L4, respectively. Terminals 1g to 4g are connected to the node of output voltage Vout, respectively.

  The terminal 1h is connected to the voltage source of the input voltage Vin, and the terminal 4e is connected to the ground terminal. Terminals 1e and 2h, terminals 2e and 3h, and terminals 3e and 4h are connected to each other. A current input from the ground terminal to the terminal 4e is referred to as a current I sink4. The current Isrc4 is output from the terminal 4h, and is input as the current I sink3 to the terminal 3e. The current Isrc3 is output from the terminal 3h, and is input as the current I sink2 to the terminal 2e. A current Isrc2 is output from the terminal 2h, and is input to the terminal 1e as a current Isink1. A current Isrc1 is output from the terminal 1h.

  Converters 1 to 4 obtain input voltage Vin from a common DC voltage source, and send output currents Iout1 to Iout4 to capacitor C1 via inductors L1 to L4. The inductors L1 to L4 and the capacitor C1 constitute a filter, and the voltage smoothed by the filter is supplied to the load device 11 as the output voltage Vout of the power supply device.

  Each of converters 1 to 4 internally monitors the magnitudes of output currents Iout1 to Iout4, and further monitors output voltage Vout of power supply device 10. The converter 1 sends a signal (for example, a voltage signal) Vsense1 indicating the magnitude of the output current of the converter 1 to the other converters 2-4. The slave converters 2 to 4 operate so that their output currents Iout2 to Iout4 are equal to the output current Iout1 of the master converter 1, so that the output currents Iout1 to Iout4 of all the converters 1 to 4 become equal.

[Configuration of Converters 1 to 4]
As described above, the master converter 1 and the slave converters 2 to 4 have the same configuration, and each converter autonomously determines whether the converter itself is a master or a slave. Hereinafter, converter 1 that operates as a master converter and converters 2 to 4 that operate as slave converters will be described separately.

  FIG. 2 is a block diagram showing a detailed configuration of converter 1 in FIG. The converter 1 includes a reference voltage source E1, an error detection circuit 21, a triangular wave generation circuit 22, comparators 23 and 25, a driver circuit 24, a timer 26, a current sensor 27, a voltage adjustment circuit 28, an adder 29, a master / slave (M / S) includes a determination circuit 30, a start-up circuit 31, a logical product operation circuit 32, and switches SWa to SWd. FIG. 2 shows a converter 1 which is a step-down DC / DC converter.

  The reference voltage source E1 generates a predetermined reference voltage Vrefa. The adder 29 adds a voltage adjustment value Vadjust (described later) generated by the voltage adjustment circuit 28 to the reference voltage Vrefa, generates a reference voltage Vrefb, and sends it to the error detection circuit 21. The error detection circuit 21 generates an error voltage Verra that represents an error between the output voltage Vout of the power supply device and the reference voltage Vrefb. The triangular wave generation circuit 22 generates a triangular wave having a predetermined frequency and amplitude. The comparator 23 compares the error voltage Verra and the triangular wave and sends a signal indicating the comparison result to the driver circuit 24. The driver circuit 24 generates a PWM (Pulse Width Modulation) signal to control on / off of the switches SWa and SWb. Therefore, the triangular wave generation circuit 22, the comparator 23, and the driver circuit 24 operate as a circuit 41 that drives the switches SWa and SWb based on the error voltage Verra.

  The switches SWa and SWb are connected in series between the voltage source of the input voltage Vin and the ground terminal, the switch SWa is connected to the voltage source of the input voltage Vin, and the switch SWb is connected to the ground terminal. A terminal 1f which is an output terminal of the converter 1 is connected to a node between the switches SWa and SWb. For example, the switch SWa is a p-channel MOSFET, and the switch SWb is an n-channel MOSFET.

  The current sensor 27 detects the magnitude of the output current Iout1 of the converter 1 and converts it into a signal Vsense1 having a voltage proportional to the output current value. The signal Vsense 1 is sent from the master converter 1 to the slave converters 2 to 4.

  The comparator 25 compares the potential of the terminal 1f with the potential of the ground terminal, detects a backflow current from the terminal 1f to the node between the switches SWa and SWb, and notifies the driver circuit 24 of the detection result. The switch SWc is closed only when the switch SWb is closed. The timer 26 operates the comparator 25 only for a predetermined time period after the enable signal EN is input (that is, after the power supply device 10 is activated). The switch SWc, the comparator 25, and the timer 26 operate as a reverse current detection circuit 42.

  M / S determination circuit 30 autonomously determines whether converter 1 is a master or a slave based on the current value obtained through terminal 1e and the voltage value obtained through terminal 1h. .

  When the converter including the voltage adjustment circuit 28 is a slave converter, the voltage adjustment circuit 28 is based on the error voltage Verra of the converter, the output current value of the converter, and the output current value of the master converter 1. An adjustment value Vadjust is generated.

  When the converter including the startup circuit 31 is a slave converter, the startup circuit 31 switches the converter to an operating state or a dormant state based on the error voltage Verra of the converter and the output current value of the master converter 1 A signal ACT is generated.

  The M / S determination circuit 30 of the master converter 1 switches the switch SWd so as to send the signal Vsense1 from the converter 1 to the other converters 2 to 4, and turns off the circuit 43 including the voltage adjustment circuit 28 and the starting circuit 31. . When the activation circuit 31 is off, the activation circuit 31 fixes the activation signal ACT at a high level. Therefore, the voltage adjustment circuit 28 and the activation circuit 31 of the master converter 1 do not generate the voltage adjustment value Vadjust and the activation signal ACT, respectively.

  The AND signal 32 is supplied with an enable signal EN and an activation signal ACT. The circuit 41 of the master converter 1 enters an operating state in accordance with the output signal of the AND operation circuit 32 (that is, in response to the enable signal EN). The circuit 41 of the slave converter enters an operating state or a hibernation state according to the output signal of the AND operation circuit 32.

  FIG. 3 is a block diagram showing a detailed configuration of converter 2 in FIG. The M / S determination circuit 30 of the slave converter 2 switches the switch SWd so as to send the signal Vsense1 received from the master converter 1 to the voltage adjustment circuit 28, and turns on the circuit 43 including the voltage adjustment circuit 28 and the starting circuit 31. To. The M / S determination circuit 30 of the slave converter 2 further includes the number of converters operating in the power supply device 10 and the order of the converters including the M / S determination circuit 30 (relative position with respect to the master converter 1). ) Is sent to the activation circuit 31.

  Converters 3 to 4 are configured similarly to converter 2.

[Configuration of Error Detection Circuit 21]
FIG. 4 is a circuit diagram showing a detailed configuration of the error detection circuit 21 shown in FIGS. The error detection circuit 21 includes a phase compensation circuit and an integration circuit including resistors R1 to R4, capacitors C2 to C4, and an operational amplifier 51. The error detection circuit 21 detects an error between the output voltage Vout of the power supply device 10 and the reference voltage Vrefb, amplifies and integrates this error, and generates an error voltage Verra.

[Configuration of Voltage Adjustment Circuit 28]
FIG. 5 is a circuit diagram showing a detailed configuration of the voltage adjustment circuit 28 of FIG. The voltage adjustment circuit 28 includes a target error voltage generation circuit 61, error detection circuits 65 and 66, an adder 67, and an integrator 68. For example, in the converter 2, the voltage adjustment value Vadjust generates the reference voltage Vrefb by adjusting the reference voltage Vrefa so that the output current Iout2 of the converter 2 becomes equal to the output current Iout1 of the converter 1.

  For example, in the converter 2, the target error voltage generation circuit 61 generates a target error voltage Vaim that is a target value of the first error voltage Verra output from the error detection circuit 21 (ideal value when the converter 2 is in an operating state). Occur. The error detection circuit 65 generates a second error voltage Verrb representing an error between the first error voltage Verra and the target error voltage Vaim. The error detection circuit 66 generates a third error voltage Verrc representing an error between the signal Vsense1 indicating the magnitude of the output current Iout1 of the master converter 1 and the signal Vsense2 indicating the magnitude of the output current Iout2 of the slave converter 2. Occur.

  When the converter 2 is in the operating state, only the target error voltage generation circuit 61 and the error detection circuit 65 may stop functioning, but the other components are operating. Therefore, at this time, the third error voltage Verrc is integrated by the integrator 68 to become the voltage adjustment value Vadjust, and the sum of the reference voltage Vrefa and the voltage adjustment value Vadjust is input to the error detection circuit 21 as the reference voltage Vrefb. . In other words, when the converter 2 is in the operating state, the error detection circuit 21 uses the sum of the reference voltage Vrefa and the integrated third error voltage Verrc as the reference voltage Vrefb of the error detection circuit 21.

  On the other hand, when the converter 2 is in a resting state, the circuit 41 stops functioning. Accordingly, at this time, the second error voltage Verrb is integrated by the integrator 68 to become the voltage adjustment value Vadjust, and the sum of the reference voltage Vrefa and the voltage adjustment value Vadjust is input to the error detection circuit 21 as the reference voltage Vrefb. . In other words, when the converter 2 is in a resting state, the error detection circuit 21 uses the sum of the reference voltage Vrefa and the integrated second error voltage Verrb as the reference voltage of the error detection circuit 21.

  The reference voltage Vrefa of the reference voltage source E1 of the converter 2 should originally match the reference voltage Vrefa of the reference voltage source E1 of the converter 1, but there may be an error due to manufacturing variations. Therefore, when the converter 2 is in the operating state, the reference voltage Vrefa of the reference voltage source E1 is adjusted based on the third error voltage Verrc so that the output current Iout2 of the converter 2 becomes equal to the output current Iout1 of the converter 1. The When converters 1 and 2 operate for a sufficiently long time to reach a steady state, reference voltage Vrefb obtained by adjusting reference voltage Vrefa of reference voltage source E1 of converter 2 is equal to reference voltage Vrefa of reference voltage source E1 of converter 1. It has become. At this time, the magnitudes of the output currents Iout1 and Iout2 detected by the current sensors 27 and 25 of the converters 1 and 2 are equal.

  However, the function of adjusting the error of the reference voltage Vrefa of the reference voltage source E1 in this way is based on the premise that the converter 2 is in an operating state and generates an output current Iout2. Therefore, when the converter 2 is in the resting state, the output current Iout2 becomes zero, so that the error of the reference voltage Vrefa of the reference voltage source E1 cannot be corrected based on the third error voltage Verrc. For this reason, when the converter 2 is in an inactive state, the reference voltage Vrefa of the reference voltage source E1 is adjusted based on the second error voltage Verrb instead of the third error voltage Verrc.

  When the target value of the output voltage Vout of the power supply device 10 is expressed as Vset, the error voltage Verra output from the error detection circuit 21 should be a value proportional to Vset / Vin in a steady state. Therefore, the target error voltage generation circuit 61 is set so as to generate a target error voltage Vaim that is proportional to Vset / Vin.

  The target error voltage generation circuit 61 includes resistors R11 to R14, comparators 62 to 64, transistors SW11 to SW16 that are Nch or Pch field effect transistors, and reference voltage sources E11 and E12.

  The reference voltage source E11 generates a reference voltage Vref11 that is equal to the target value Vset of the output voltage Vout of the power supply device 10. The reference voltage source E12 generates a predetermined reference voltage Vref12.

  The target error voltage generation circuit 61 is supplied with the same input voltage Vin as the input voltage Vin of the power supply device 10 of FIG. By dividing the input voltage Vin by the resistors R11 and R12 and inputting the divided voltage to the error detection circuit 62, a current proportional to the input voltage Vin flows in the resistor R13.

  Since the Pch transistors SW11 and SW12 are biased under the same conditions, the currents flowing through them are equal. For this reason, a current proportional to the input voltage Vin flows through the Nch transistor SW13.

  The Nch transistor SW13 operates in a linear region and can be handled as a variable resistor. The drain voltage of the Nch transistor SW13 is controlled by the comparator 63 so as to be equal to the reference voltage Vref12 of the reference voltage source E12. Therefore, when the Nch transistor SW13 is regarded as a variable resistor, a voltage equal to the reference voltage Vref12 of the reference voltage source E12 is applied, and a current proportional to the input voltage Vin flows. Here, from the relational expression “voltage = resistance × current”, the drain-source resistance value of the Nch transistor SW13 is proportional to 1 / Vin.

  The current flowing through the resistor R14 is controlled by the comparator 64 so as to be proportional to the reference voltage Vref11 of the reference voltage source E11 (that is, the target value Vset of the output voltage Vout of the power supply device 10).

  Since the Pch transistors SW14 and SW15 are biased under the same condition, the current flowing through each is proportional to the transistor size. Therefore, a current proportional to the reference voltage Vref11 (that is, Vset) of the reference voltage source E11 also flows through the Nch transistor SW16.

  The gate voltage of the Nch transistor SW16 is the same as the gate voltage of the Nch transistor SW13, and operates in a linear region. Therefore, the Nch transistor SW16 can be regarded as a variable resistance like the Nch transistor SW13, and has a resistance value almost the same as the resistance value of the Nch transistor SW13. Therefore, the resistance value when the Nch transistor SW16 is regarded as a variable resistor is proportional to 1 / Vin, and a current proportional to the reference voltage Vref11 (that is, Vset) of the reference voltage source E11 flows.

  Therefore, the target error voltage Vaim is proportional to Vset / Vin from the relational expression “voltage = resistance × current”. As a result, the target error voltage Vaim becomes a value close to a desired value of the error voltage Verra output from the error detection circuit 21.

  The converter 2 adjusts an error between the reference voltage Vrefa of the reference voltage source E1 of the converter 2 and the reference voltage Vrefa of the reference voltage source E1 of the converter 1 not only in the operation state but also in the resting state. To do. When the converter 2 is in an inactive state, the reference voltage Vrefb is obtained by using the sum of the reference voltage Vrefa and the integrated second error voltage Verrb as the reference voltage Vrefb of the error detection circuit 21. It becomes equal to the reference voltage Vrefa of E1. The reason is described below.

  Even when the slave converters 2 to 4 are in a dormant state, the master converter 1 is always in an operating state, the output voltage Vout of the power supply device 10 is controlled to be the target value Vset, and error detection is performed. The circuit 21 is operating. Therefore, in a steady state, the error voltage Verra output from the error detection circuit 21 should be a value proportional to Vset / Vin. However, actually, since the reference voltage Vrefa of the reference voltage source E1 of the converters 2 to 4 is different from the reference voltage Vrefa of the reference voltage source E1 of the converter 1, the error voltage Verra It is different from the ideal value at a certain time. The error between the actual error voltage Verra and its ideal value becomes larger with time due to the integration circuit included in the error detection circuit 21.

  Therefore, the target error voltage Vaim, which is the target value of the error voltage Verra, is generated by the target error voltage generation circuit 61, the target error voltage Vaim is compared with the actual error voltage Verra by the error detection circuit 65, and the error becomes zero. Give feedback so that As a result, the reference voltage Vrefb of the slave converter 2 can be expected to be equal to the reference voltage Vrefa of the reference voltage source E1 of the master converter 1. Because the error voltage Verra is equal to the ideal value, the converter 1 and the converters 2 to 4 perform the same operation, and the reference voltages Vrefb input to the error detection circuits 21 of the converters 1 to 4 are equal to each other. Because it means.

  The voltage adjustment circuit 28 of the converters 3 to 4 is configured similarly to the voltage adjustment circuit 28 of the converter 2.

[Configuration of M / S Determination Circuit 30]
FIG. 6 is a block diagram showing a detailed configuration of the M / S determination circuit 30 of FIG. The M / S determination circuit 30 of the converter 1 includes a current / voltage (I / V) converter 71, an analog / digital (A / D) converter 72, a control circuit 73, a variable current source 74, a clock modulation circuit 75, and A clock demodulation circuit 76 is provided. The M / S determination circuits 30 of the other converters 2 to 4 are configured similarly to the M / S determination circuit 30 of the converter 1 and operate in the same manner.

  The I / V converter 71 converts the current values of the currents I sink 1 to I sink 4 acquired from the terminals 1 e to 4 e of the converters 1 to 4 into analog voltage values corresponding to the current values. The A / D converter 72 converts the converted analog voltage value into a digital voltage value and sends it to the control circuit 73.

  Control circuit 73 measures voltages at terminals 1h to 4h of converters 1 to 4 including control circuit 73, respectively. When the voltage source of the input voltage Vin is connected to the terminals 1h to 4h, the control circuit 73 determines that the converter including the control circuit 73 is a master converter. Otherwise, the control circuit 73 is a slave converter. to decide. In the power supply device 10 of FIG. 1, a voltage source of the input voltage Vin is connected to the terminal 1 h of the converter 1. Therefore, the control circuit 73 of the converter 1 determines that the converter 1 is a master converter, and the control circuit 73 of the converters 2 to 4 determines that the converters 2 to 4 are slave converters.

  The control circuit 73 of the slave converters 2 to 4 determines whether the converter including the control circuit 73 is in an operating state or a resting state. When the converter is in the quiescent state, the control circuit 73 sets the same current value as that of the currents I sink 2 to I sink 4 acquired from the terminals 2 e to 4 e of the converters 2 to 4 including the control circuit 73 in the variable current source 74. . On the other hand, when the converter is in an operating state, the control circuit 73 has a current value (for example, 5 μA) determined in advance as the current values of the currents I sink 2 to I sink 4 acquired from the terminals 2 e to 4 e of the converters 2 to 4 including the control circuit 73. ) Is added to the variable current source 74. Currents Isrc2 to Isrc4 having set current values are output from terminals 2h to 4h, respectively.

  All of the converters 1 to 4 are in an operating state for a certain period of time after the power supply device 10 is activated. In this time period, according to the above example of the current value, the current value of the current I sink 4 is 0 μA, the current value of the current I sink 3 is 5 μA, the current value of the current I sink 2 is 10 μA, and the current value of the current I sink 1 Is 15 μA. The control circuit 73 of the converter 1 calculates the total number (four) of the converters 1 to 4 based on the current value of the current I sink 1 and notifies the other converters 2 to 4 using the clock signal CLK as described later. .

  The control circuit 73 of each converter 2 to 4 determines the order of the converters including the control circuit 73 (relative to the master converter 1) based on the current values of the corresponding currents I sink 2 to I sink 4 and the total number of the converters 1 to 4. Target position).

  Thereafter, the converter 1 of the master continues to operate, and the converters 2 to 4 of the slave enter either the operating state or the sleep state. When at least one of the slave converters 2 to 4 is in operation, the slave converters 2 to 4 are connected between the master converter 1 and the slave converter in operation. Operates as if there is no converter. The control circuit 73 of the master converter 1 divides the current I sink 1 by a predetermined current value (for example, 5 μA) to calculate the number of converters in the operating state, and uses the clock signal CLK as described later. Notify other converters 2-4.

  The control circuit 73 of the master converter 1 performs PWM modulation on the clock signal CLK using the clock modulation circuit 75, so that the total number of the converters 1 to 4 and the number of converters in the operating state are determined by the slave converters 2 to 4. Notify the M / S determination circuit 30. The clock demodulation circuit 76 of the slave converters 2 to 4 performs PWM demodulation on the clock signal CLK received from the master converter 1, thereby giving the control circuit 73 the total number of converters 1 to 4 and the number of converters in the operating state. Notice.

  The M / S determination circuits 30 of the slave converters 2 to 4 include the number of converters in the operating state in the power supply device 10 and the order of the converters including the M / S determination circuit 30 (relative positions with respect to the master converter 1). ) Is sent to the activation circuit 31.

[Configuration of Startup Circuit 31]
FIG. 7 is a block diagram showing a detailed configuration of the activation circuit 31 of FIG. The starting circuit 31 includes reference voltage sources E21 to E23, comparators 81 to 83, an asynchronous starting circuit 84, a synchronous starting circuit 87, and an OR operation circuit 88. Asynchronous activation circuit 84 includes an inverter 85 and an AND operation circuit 86.

  The reference voltage source E21 generates a predetermined threshold voltage Vtherr that is higher than the target error voltage Vaim. The reference voltage source E22 generates a threshold voltage Vthu for determining whether to increase the number of converters in the operating state. The reference voltage source E23 generates a threshold voltage Vthd for determining whether or not to reduce the number of converters in the operating state. The threshold voltage Vthu is larger than the threshold voltage Vthd.

  The comparator 81 compares the error voltage Verra and the threshold voltage Vtherr. When the error voltage Verra exceeds the threshold voltage Vtherr, the comparator 81 sets the output signal f_active to a high level. That is, the comparator 81 sets the output signal f_active to a high level when the output voltage Vout is greatly reduced due to a sudden increase in the power consumption of the load device 11. The comparator 82 compares the signal Vsense1 with the threshold value Vthu, and sets the output signal is_up to the high level when the signal Vsense1 exceeds the threshold value Vthu. The comparator 83 compares the signal Vsense1 and the threshold value Vthd, and when the signal Vsense1 becomes less than the threshold value Vthd, sets the output signal is_down to the high level.

[Configuration of Synchronous Activation Circuit 87]
The synchronous activation circuit 87 is composed of a digital logic circuit. Based on the output signals is_up and is_down of the comparators 82 and 83, the synchronous activation circuit 87 generates an activation signal ACTa that switches the converters 2 to 4 to an operation state or a sleep state.

  When the signal Vsense1 becomes less than the threshold value Vthd when the converter including the synchronous activation circuit 87 is in the operating state, the synchronous activation circuit 87 determines that the power consumption of the load device 11 has decreased, and pauses the converter. Switch to state. That is, the synchronous activation circuit 87 sets the activation signal ACTa to the low level when the output signal is_down of the comparator 83 becomes the high level.

  When the converter 2 including the synchronous activation circuit 87 is in a dormant state, the synchronous activation circuit 87 determines that the power consumption of the load device 11 has increased when the signal Vsense1 exceeds the threshold value Vthu. Switch to the operating state. That is, the synchronous activation circuit 87 sets the activation signal ACTa to the high level when the output signal is_up of the comparator 82 becomes the high level. Further, the synchronous activation circuit 87 outputs a high-level hold signal for a predetermined time T1 after changing the activation signal ACTa from the low level to the high level, and then sets the hold signal to the low level. The synchronization activation circuit 87 may subtract a numerical value set in an internal counter (not shown) for each clock in order to measure the time T1.

  FIG. 8 is a flowchart showing the synchronous activation process executed by the synchronous activation circuit 87 of FIG.

  In step S1, the synchronous activation circuit 87 sets the activation signal ACTa to a high level. In step S2, the synchronization activation circuit 87 sets the hold signal to a high level. In step S3, the synchronization activation circuit 87 determines whether or not a predetermined time T1 has elapsed. If YES, the process proceeds to step S4. If NO, step S3 is repeated. In step S4, the synchronization activation circuit 87 sets the hold signal to a low level.

  In step S5, the synchronization activation circuit 87 determines whether or not is_down is at a high level. If YES, the process proceeds to step S6. If NO, step S5 is repeated. In step S6, the synchronous activation circuit 87 determines whether or not the order of the converters including the synchronous activation circuit 87 is equal to the number of converters in the operating state. If YES, the process proceeds to step S7. If NO, Returns to step S5.

  In step S7, the synchronous activation circuit 87 sets the activation signal ACTa to a low level. In step S8, the synchronization activation circuit 87 sets the hold signal to a high level. In step S9, the synchronous activation circuit 87 determines whether or not a predetermined time T1 has elapsed. If YES, the process proceeds to step S10. If NO, step S9 is repeated. In step S10, the synchronization activation circuit 87 sets the hold signal to a low level.

  In step S11, the synchronization activation circuit 87 determines whether or not is_up is at a high level. If YES, the process proceeds to step S12. If NO, step S11 is repeated. In step S12, the synchronous activation circuit 87 determines whether or not the order of the converters including the synchronous activation circuit 87 is the number of converters in the operating state + 1. If YES, the process returns to step S1 and NO. If so, the process returns to step S11.

  The synchronous activation circuit 87 performs a comparatively long time (for example, several tens of times) until the number of converters 2 to 4 corresponding to the amount of power consumption of the load device 11 is driven by performing the synchronous activation process of FIG. Microseconds). However, an appropriate number of converters 2 to 4 corresponding to the amount of power consumption of the load device 11 can be put into operation.

[Configuration of Asynchronous Activation Circuit 84]
The asynchronous activation circuit 84 is configured by a digital logic circuit. The inverter 85 inverts the hold signal sent from the synchronous activation circuit 87. The logical product operation circuit 86 generates a logical product of the output signal of the inverter 85 and the output signal f_active of the comparator 81 as an activation signal ACTb for switching the converters 2 to 4 to an operation state or a sleep state.

  Since the output signal of the inverter 85 becomes high level when the hold signal is at low level, the asynchronous activation circuit 84 sets the activation signal ACTb to high level when the output signal f_active of the comparator 81 becomes high level.

  Since the asynchronous activation circuit 84 does not wait for a predetermined time unlike the synchronous activation process of FIG. 8, when the output signal f_active of the comparator 81 becomes high level, a relatively short time (for example, several nanoseconds). Within 3), the activation signal ACTb is set to the high level. That is, the asynchronous activation circuit 84 sets the activation signal ACTb to the high level almost simultaneously with the output signal f_active of the comparator 81 becoming the high level.

  The activation signals ACTa and ACTb are input to the OR operation circuit 88, and the output signal of the OR operation circuit 88 is sent to the AND operation circuit 32 as the activation signal ACT.

[Configuration of Backflow Current Detection Circuit 42]
The backflow current detection circuit 42 is intended to stably supply power to the load device 11 at an early stage without generating a loss due to a through current between the converters immediately after the start-up (power-on) of the entire power supply device 10. . After the power is turned on, the purpose is to prevent a loss due to a through current between the converters and at the same time realize a high-speed response. That is, an object is to keep the output voltage Vout constant even when the power consumption of the load device 11 fluctuates rapidly. It is another object of the present invention to prevent loss due to a through current between converters even when a certain converter of a slave shifts from a sleep state to an operation state.

  First, the basic voltage conversion operation of the converters 1 to 4 will be described. For example, in the converter 1, when the driver circuit 24 turns on the switch SWa and turns off the switch SWb, the converter 1 supplies power to the load device 11 while accumulating power from the input voltage Vin in the inductor L1. . Further, when the driver circuit 24 turns off the switch SWa and turns on the switch SWb, the converter 1 supplies the power stored in the inductor L1 to the load device 11. These are alternately repeated and smoothed by the capacitor C1, whereby the converter 1 supplies a constant output voltage Vout to the load device 11.

  Next, the reverse current will be described. For the converter 1, when the current Iout1 flows in the direction of the arrow in FIG. That is, when the switch SWb is turned on, the current flowing from the source to the drain of the switch SWb is a forward current. The reverse current that is a problem in this specification is a current that flows from the output terminal 1f of FIG. 2 to a node between the switches SWa and SWb, that is, a current that flows from the drain to the source of the switch SWb when the switch SWb is turned on. means.

  Here, the operation of the reverse current detection circuit 42 will be described.

  A case where the switch SWb is turned on will be described. Ideally, the on-resistance of the switch SWb is preferably zero, but there is actually a slight resistance. When current flows from the source to the drain of the switch SWb, the voltage at the node between the switches SWa and SWb is lower than the potential of the ground terminal due to the voltage drop of the on-resistance of the switch SWb. On the other hand, when a current flows from the drain to the source of the switch SWb, the voltage at the node between the switches SWa and SWb becomes higher than the potential of the ground terminal due to the voltage drop of the on-resistance of the switch SWb. Therefore, the backflow current can be detected by comparing the voltage of the node between the switches SWa and SWb with the potential of the ground terminal using the comparator 25.

  The non-inverting input terminal of the comparator 25 is connected to the node between the switches SWa and SWb via the switch SWc, and the inverting input terminal is connected to the ground terminal. The comparator 25 notifies the driver circuit 24 of the detection result of the backflow current only for a predetermined time period after the power supply device 10 is activated. The driver circuit 24 turns off the switch SWb when the backflow current detection circuit 42 detects a backflow current during a predetermined time period after the power supply device 10 is activated.

  The voltage of the node between the switches SWa and SWb substantially matches the input voltage Vin while the switch SWa is turned on, and a voltage drop due to the on-resistance of the switch SWb cannot be observed. Therefore, the switch SWc inputs the voltage of the node between the switches SWa and SWb to the non-inverting input terminal of the comparator 25 only when the switch SWb is turned on (mask function).

  The driver circuit 24 can turn off the switch SWb when a backflow current is generated to prevent loss due to the backflow current.

  The voltage input to the inverting input terminal of the comparator 25 does not have to be the potential of the ground terminal. By setting the voltage to an arbitrary voltage value, an offset can be given to the value of the backflow current to be detected.

  When the power supply 10 is turned on, all the converters 1 to 4 connected in parallel are started in an operating state, so that even when the power consumption of the load device 11 is large, the power is stabilized immediately after the power is turned on. Can supply. Each of converters 1 to 4 has a means for preventing a reverse current, and validates the means for preventing the reverse current only when the power is turned on. Therefore, no current passes from one converter to another even in an unstable period until the control for equalizing the output currents of the converters 1 to 4 is settled. For this reason, no loss occurs when the power is turned on.

[Prevention of Backflow Current by Voltage Adjustment Circuit 28]
When multiple converters are connected in parallel, the output voltage and output current vary due to variations between the converters (small circuit errors and device characteristics variations that occur during the manufacturing process), and current passes from one converter to another. Such a situation can occur. However, since the output currents of the converters in the operating state are controlled to be equal to each other by the voltage adjustment circuit 28, in the steady state, an unbalanced state in which current passes from one converter to another is not There will be no loss and no loss.

  As described above, the reverse current detection circuit 42 is invalidated except when the power is turned on. However, when the output currents of the converters in the operating state are made equal to each other, the current passes between the converters and loss occurs. There is no. In addition, the power conversion efficiency can be improved as a whole because the power necessary to operate the function of preventing the reverse current is not required.

  In general, when there is a sudden change from a heavy load to a light load, the output voltage Vout increases. However, in the power supply device 10 of FIG. 1, after a predetermined time has elapsed since the start of the power supply device 10, the converter is intentionally allowed to generate a transient backflow current. Thus, the desired voltage can be restored and high-speed response can be realized.

  The voltage adjustment circuit 28 adjusts the reference voltage so as to be equal to the reference voltage of the master converter 1 even in the converter in the idle state. Thereby, even immediately after a certain converter shifts from a sleep state to an operating state, the output voltage and the output current are not significantly different from those of other converters. Therefore, no current passes from the converter to the converter that has been operating from the other time, or no current passes from the converter that has been operating from the other time to the converter, and no loss occurs.

  As described above, according to the power supply device 10 of FIG. 1, it is possible to prevent loss due to through current by controlling the output currents of a plurality of converters connected in parallel to be equal. In addition, by starting all the converters when the power is turned on, power can be stably supplied at an early stage immediately after the power is turned on, and the reverse current detection circuit 42 does not cause a loss due to the through current even when the power is turned on. Further, after the power is turned on, high-speed response can be realized by disabling the backflow current detection circuit 42. Further, by correcting the variation between the converters even in the resting state, loss due to the through current does not occur even when shifting from the resting state to the operating state.

Second embodiment.
Some conventional DC / DC converters use both PWM (Pulse Width Modulation) control and PFM (Pulse Frequency Modulation) control in order to drive two switches for generating an output voltage. In PWM control, the switching frequency is constant, and the ratio between the time when the first switch is turned on and the time when the second switch is turned on is changed. In the PFM control, the time when the first switch is turned on and the time when the second switch is turned on are constant, and the switching frequency is changed.

  At light loads, the PFM control is more efficient than the PWM control, and at heavy loads, the PWM control is more efficient than the PFM control. By switching between PFM control and PWM control according to the power consumption of the load device, the efficiency of the DC / DC converter can be improved.

  The PWM control itself cannot prevent the generation of a reverse current. Therefore, in the first embodiment, when the backflow current detection circuit 42 detects a backflow current when the power supply device 10 is turned on, the backflow current is forcibly cut off by turning off the switches SWa and SWb. On the other hand, in the PFM control, preventing the generation of a backflow current is incorporated in the control itself. In the second embodiment, prevention of backflow current using PFM control will be described.

[Prevention of reverse current by driver circuit 24]
FIG. 9 is a timing chart showing the operation of the switches SWa and SWb in FIGS. FIG. 10 is a timing chart showing the operation of the switches SWa and SWb of the comparative example. A method for preventing reverse current by operating the converter in “discontinuous mode” will be described.

  First, “discontinuous mode” and “continuous mode” will be described. FIG. 9 shows the current Iout1 flowing through the inductor L1 and on / off of the switches SWa and SWb for the converter 1 operating in the discontinuous mode, and FIG. 10 for the converter 1 operating in the continuous mode.

  In the discontinuous mode (FIG. 9), when the switch SWa is turned on, the current Iout1 increases. When the switch SWa is turned off and the switch SWb is turned on, the current Iout1 decreases. When the current Iout1 becomes zero, the switches SWa and SWb Both off. Therefore, the driver circuit 24 turns on the switch SWa or SWb when the converter generates a positive output current, and turns off both the switches SWa and SWb when the converter does not generate a positive output current. .

  On the other hand, in the continuous mode (FIG. 10), the current Iout1 increases when the switch SWa is turned on, and the current Iout1 decreases when the switch SWb is turned on, as in the discontinuous mode. However, in the continuous mode, there is no period in which both the switches SWa and SWb are off, and either one is always on, and the current Iout1 does not become zero (it may become zero instantaneously).

  In order to operate the converter in the discontinuous mode, it is necessary to turn off the switch SWb by detecting that the current Iout1 becomes zero or negative. As a method for detecting that the current Iout1 becomes zero or negative, the backflow current detection circuit 42 is used or a timer is used. That is, since the ratio of the time to turn on the switch SWa and the time to turn on the switch SWb is determined by the input voltage Vin and the output voltage Vout, by controlling the on time of the switch SWa and the on time of the switch SWb, Operation in discontinuous mode can be realized.

  Driving the switches SWa and SWb by PFM control is substantially equivalent to operating the switches SWa and SWb in the discontinuous mode. As long as it operates in the discontinuous mode, no reverse current is generated. Therefore, by forcibly applying the PFM control (discontinuous mode) that is originally used at the time of light load when the power supply device 10 is turned on, generation of a backflow current can be prevented.

[Summary]
At the same time as the power is turned on, the power supply device 10 starts up all the converters 1 to 4 connected in parallel and shifts to an operating state. At this time, the reverse current detection circuit 42 is operated only for a predetermined time period, and then the reverse current detection circuit 42 is turned off. In order to optimize the efficiency according to the power consumption of the load device 11, the number of converters in the operating state is changed according to the output current Iout. When the slave converter transitions between a dormant state and an operating state, the reverse current detection circuit 42 remains turned off.

  According to the power supply device 10, when the power consumption of the load device 11 increases, the stopped converters 2 to 4 can be returned in a short settling time.

  The power supply device 10 may include two, three, five or more converters.

  A power supply device according to an aspect of the present invention includes the following configuration.

According to the power supply device of the first aspect of the present invention,
In a power supply device including a plurality of DC / DC converters connected in parallel,
Each of the plurality of DC / DC converters is
A first switch and a second switch connected in series between a voltage source of the input voltage and a ground terminal, the first switch connected to the voltage source of the input voltage and a second switch connected to the ground terminal. And the switch
A drive circuit for driving the first and second switches;
An output terminal of the DC / DC converter connected to a node between the first and second switches;
A reverse current detection circuit for detecting a reverse current from the output terminal to a node between the first and second switches;
The drive circuit is
When the DC / DC converter is generating a positive output current, the first or second switch is turned on,
The second switch is turned off when a backflow current is detected by the backflow current detection circuit during a predetermined time period after starting the power supply device.

According to the power supply device according to the second aspect of the present invention, in the power supply device according to the first aspect,
Each of the plurality of DC / DC converters is
A first error detection circuit for generating a first error voltage representing an error between the output voltage of the power supply device and a reference voltage;
A current sensor for detecting an output current value of the DC / DC converter,
The drive circuit drives the first and second switches based on the first error voltage,
The plurality of DC / DC converters are:
One master DC / DC converter that generates an output current during operation of the power supply device;
Including at least one slave DC / DC converter having an operation state in which an output current is generated during operation of the power supply device and a sleep state in which no output current is generated;
Each of the slave DC / DC converters
A reference voltage source for generating a predetermined first reference voltage;
A target error voltage generating circuit for generating a target error voltage which is a target value of the first error voltage;
A second error detection circuit for generating a second error voltage representing an error between the first error voltage and the target error voltage;
A third error detection circuit for generating a third error voltage representing an error between the output current value of the master DC / DC converter and the output current value of the slave DC / DC converter;
The first error detection circuit of each of the slave DC / DC converters outputs a voltage based on a sum of the first reference voltage and the second error voltage when the slave DC / DC converter is in an operating state. A voltage based on the sum of the first reference voltage and the third error voltage is used as the reference voltage of the first error detection circuit and when the slave DC / DC converter is in a quiescent state. It is used as a reference voltage for an error detection circuit.

According to the power supply device according to the third aspect of the present invention, in the power supply device according to the second aspect,
The target error voltage is set to be proportional to a ratio of a target value of an output voltage of the power supply device to an input voltage of the power supply device.

According to the DC / DC converter according to the fourth aspect of the present invention,
In a DC / DC converter included in a power supply device including a plurality of DC / DC converters connected in parallel,
The DC / DC converter is
A first switch and a second switch connected in series between a voltage source of the input voltage and a ground terminal, the first switch connected to the voltage source of the input voltage and a second switch connected to the ground terminal. And the switch
A drive circuit for driving the first and second switches;
An output terminal of the DC / DC converter connected to a node between the first and second switches;
A reverse current detection circuit for detecting a reverse current from the output terminal to a node between the first and second switches;
The drive circuit is
When the DC / DC converter is generating a positive output current, the first or second switch is turned on,
The second switch is turned off when a backflow current is detected by the backflow current detection circuit during a predetermined time period after starting the power supply device.

  The embodiments of the present invention are not limited to the described embodiments, and design changes and additions are permitted without departing from the spirit of the invention specified in the scope of claims.

1-4 DC / DC converter,
10 ... power supply,
11 ... load device,
21: Error detection circuit,
22 ... Triangular wave generation circuit,
23 ... comparator,
24 ... Driver circuit,
25 ... comparator,
26: Timer,
27 ... Current sensor,
28 ... Voltage adjustment circuit,
29 ... adder,
30 ... M / S determination circuit,
31 ... Start-up circuit,
32 ... AND operation circuit,
61 ... Target error voltage generation circuit,
62-64 ... comparator,
65-66 ... error detection circuit,
67 ... adder,
68 ... integrator,
51. Operational amplifier,
71 ... I / V converter,
72 ... A / D converter,
73. Control circuit,
74: Variable current source,
75: Clock modulation circuit,
76: Clock demodulation circuit,
81-83 ... comparator,
84: asynchronous start circuit,
85: Inverter,
86: AND operation circuit,
87 ... Synchronous start-up circuit,
88. OR operation circuit,
C1 to C4 capacitors,
E1, E11, E12, E21 to E23 ... reference voltage source,
L1 to L4 ... inductors,
R1 to R4, R11 to R14 ... resistors,
SWa to SWd: switches.
SW11, SW12, SW14, SW15... Pch transistor,
SW13, SW16... Nch transistor.

Japanese Patent Laid-Open No. 10-248261 JP 2012-090423 A

Claims (4)

In a power supply device including a plurality of DC / DC converters connected in parallel,
Each of the plurality of DC / DC converters is
A first switch and a second switch connected in series between a voltage source of the input voltage and a ground terminal, the first switch connected to the voltage source of the input voltage and a second switch connected to the ground terminal. And the switch
A drive circuit for driving the first and second switches;
An output terminal of the DC / DC converter connected to a node between the first and second switches;
A reverse current detection circuit for detecting a reverse current from the output terminal to a node between the first and second switches;
The drive circuit is
When the DC / DC converter is generating a positive output current, the first or second switch is turned on,
The power supply device, wherein the second switch is turned off when a reverse current is detected by the reverse current detection circuit during a predetermined time period after the power supply device is activated. Each of the plurality of DC / DC converters is
A first error detection circuit for generating a first error voltage representing an error between the output voltage of the power supply device and a reference voltage;
A current sensor for detecting an output current value of the DC / DC converter,
The drive circuit drives the first and second switches based on the first error voltage,
The plurality of DC / DC converters are:
One master DC / DC converter that generates an output current during operation of the power supply device;
Including at least one slave DC / DC converter having an operation state in which an output current is generated during operation of the power supply device and a sleep state in which no output current is generated;
Each of the slave DC / DC converters
A reference voltage source for generating a predetermined first reference voltage;
A target error voltage generating circuit for generating a target error voltage which is a target value of the first error voltage;
A second error detection circuit for generating a second error voltage representing an error between the first error voltage and the target error voltage;
A third error detection circuit for generating a third error voltage representing an error between the output current value of the master DC / DC converter and the output current value of the slave DC / DC converter;
The first error detection circuit of each of the slave DC / DC converters outputs a voltage based on a sum of the first reference voltage and the second error voltage when the slave DC / DC converter is in an operating state. A voltage based on the sum of the first reference voltage and the third error voltage is used as the reference voltage of the first error detection circuit and when the slave DC / DC converter is in a quiescent state. 2. The power supply apparatus according to claim 1, wherein the power supply apparatus is used as a reference voltage for an error detection circuit.   3. The power supply apparatus according to claim 2, wherein the target error voltage is set to be proportional to a ratio of a target value of an output voltage of the power supply apparatus to an input voltage of the power supply apparatus. In a DC / DC converter included in a power supply device including a plurality of DC / DC converters connected in parallel,
The DC / DC converter is
A first switch and a second switch connected in series between a voltage source of the input voltage and a ground terminal, the first switch connected to the voltage source of the input voltage and a second switch connected to the ground terminal. And the switch
A drive circuit for driving the first and second switches;
An output terminal of the DC / DC converter connected to a node between the first and second switches;
A reverse current detection circuit for detecting a reverse current from the output terminal to a node between the first and second switches;
The drive circuit is
When the DC / DC converter is generating a positive output current, the first or second switch is turned on,
A DC / DC converter characterized in that the second switch is turned off when a backflow current is detected by the backflow current detection circuit during a predetermined time period after starting the power supply device.

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