JP2015215365A - Thermal resistance measurement method - Google Patents
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本発明は、半導体素子の順方向ゲートソース間電圧の温度依存を利用した半導体素子の熱抵抗測定方法に関する。 The present invention relates to a method for measuring the thermal resistance of a semiconductor device using the temperature dependence of the forward gate-source voltage of the semiconductor device.
特許文献１には、半導体素子の順方向ゲートソース間電圧（以後、Ｖｇｓという）が半導体素子の温度に依存することを利用して半導体素子の熱抵抗を測定する方法が開示されている。この熱抵抗測定方法は、Ｖｇｓが温度のみによって変化することを前提としている。 Patent Document 1 discloses a method for measuring the thermal resistance of a semiconductor element by utilizing the fact that the forward gate-source voltage (hereinafter referred to as Vgs) of the semiconductor element depends on the temperature of the semiconductor element. This thermal resistance measurement method is based on the premise that Vgs changes only with temperature.
しかしながら、半導体素子のＶｇｓは、温度以外の要因で変動することがある。具体的には、Ｖｇｓは半導体素子へのバイアス印加や高周波電力の入力等で変動することがある。この場合、Ｖｇｓが温度のみによって変化することを前提とした熱抵抗測定方法では、正確に熱抵抗を測定できないことがあった。 However, the Vgs of the semiconductor element may vary due to factors other than temperature. Specifically, Vgs may fluctuate due to bias application to the semiconductor element, input of high frequency power, or the like. In this case, the thermal resistance measurement method based on the premise that Vgs changes only with temperature sometimes fails to accurately measure the thermal resistance.
本発明は、上述のような課題を解決するためになされたもので、半導体素子の熱抵抗を正確に測定できる熱抵抗測定方法を提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a thermal resistance measurement method capable of accurately measuring the thermal resistance of a semiconductor element.
本願の発明にかかる熱抵抗測定方法は、半導体素子の順方向ゲートソース間電圧の温度係数を測定する工程と、該半導体素子へのドレイン電圧印加前に該順方向ゲートソース間電圧を測定し、該半導体素子へのドレイン電圧印加によるチャネル温度上昇後に該順方向ゲートソース間電圧を測定し、該ドレイン電圧印加前の該順方向ゲートソース間電圧と該ドレイン電圧印加後の該順方向ゲートソース間電圧との差分を求める工程と、該差分を求める工程における該半導体素子への印加電力、該温度係数、及び該差分から、該半導体素子の熱抵抗値を算出する工程と、を有し、該温度係数を測定する工程の前に、該温度係数を測定する工程と同一条件でダミー温度係数測定を行うことを特徴とする。
本願の発明にかかる他の熱抵抗測定方法は、半導体素子の順方向ゲートソース間電圧の温度係数を測定する工程と、該半導体素子へのドレイン電圧印加前に該順方向ゲートソース間電圧を測定し、該半導体素子へのドレイン電圧印加によるチャネル温度上昇後に該順方向ゲートソース間電圧を測定し、該ドレイン電圧印加前の該順方向ゲートソース間電圧と該ドレイン電圧印加後の該順方向ゲートソース間電圧との差分を求める工程と、該差分を求める工程における該半導体素子への印加電力、該温度係数、及び該差分から、該半導体素子の熱抵抗値を算出する工程と、を有し、該差分を求める工程の前に、該差分を求める工程と同一条件でダミー差分測定を行うことを特徴とする。
The thermal resistance measurement method according to the present invention includes a step of measuring a temperature coefficient of a forward gate-source voltage of a semiconductor element, and measuring the forward gate-source voltage before applying a drain voltage to the semiconductor element, The forward gate-source voltage is measured after the channel temperature rises due to the drain voltage application to the semiconductor element, and the forward gate-source voltage before the drain voltage application and the forward gate-source voltage after the drain voltage application. A step of obtaining a difference from the voltage, and a step of calculating a thermal resistance value of the semiconductor element from the applied power to the semiconductor element, the temperature coefficient, and the difference in the step of obtaining the difference, Before the step of measuring the temperature coefficient, dummy temperature coefficient measurement is performed under the same conditions as the step of measuring the temperature coefficient.
Another thermal resistance measurement method according to the present invention includes a step of measuring a temperature coefficient of a forward gate-source voltage of a semiconductor element, and measuring the forward gate-source voltage before applying a drain voltage to the semiconductor element. The forward gate-source voltage is measured after the channel temperature rises due to the drain voltage application to the semiconductor element, and the forward gate-source voltage before the drain voltage is applied and the forward gate after the drain voltage is applied. A step of obtaining a difference from a source voltage, and a step of calculating a thermal resistance value of the semiconductor element from the applied power to the semiconductor element, the temperature coefficient, and the difference in the step of obtaining the difference. The dummy difference measurement is performed under the same conditions as the step of obtaining the difference before the step of obtaining the difference.
本発明によれば、半導体素子の電気特性を安定化させた後に熱抵抗測定のための測定を実施するので、半導体素子の熱抵抗を正確に測定できる。 According to the present invention, since the measurement for measuring the thermal resistance is performed after stabilizing the electrical characteristics of the semiconductor element, the thermal resistance of the semiconductor element can be accurately measured.
実施の形態１．
図１は、本発明の実施の形態１に係る熱抵抗測定方法を示すフローチャートである。本発明の実施の形態１に係る熱抵抗測定方法はＧａＮで形成されたＨＥＭＴ（以後、半導体素子という）の熱抵抗を測定するものである。以後、図１に沿って説明を進める。まず、半導体素子のエージングを実施する（ステップ１０）。エージングは、半導体素子に対し３ｄＢ利得圧縮点にて高周波電力入力を３０秒程度実施するものである。
Embodiment 1 FIG.
FIG. 1 is a flowchart showing a thermal resistance measurement method according to Embodiment 1 of the present invention. The thermal resistance measurement method according to the first embodiment of the present invention measures the thermal resistance of a HEMT (hereinafter referred to as a semiconductor element) formed of GaN. Hereinafter, the description will be made with reference to FIG. First, aging of the semiconductor element is performed (step 10). In aging, high frequency power is input to a semiconductor element at a 3 dB gain compression point for about 30 seconds.
次いで、Ｖｇｓの温度係数を測定する（ステップ１２）。Ｖｇｓの温度係数は、各温度においてＶｇｓとＩｇｓの相関を測定して得る。次いで、Ｖｄ・Ｉｄ印加条件を決定する（ステップ１４）。ここでいうＶｄ・Ｉｄ印加条件とは、半導体素子が発熱する程度のＶｄ・Ｉｄである。次いで、半導体素子のエージングを実施する（ステップ１６）。このエージングは、前述のステップ１０のエージングと同条件で実施するものである。
Next, the temperature coefficient of Vgs is measured (step 12). The temperature coefficient of Vgs is obtained by measuring the correlation between Vgs and Igs at each temperature. Next, Vd · Id application conditions are determined (step 14). The Vd · Id application condition referred to here is Vd · Id enough to generate heat in the semiconductor element. Next, aging of the semiconductor element is performed (step 16). This aging is performed under the same conditions as the aging in
次いで、ドレイン電圧印加（Ｖｄ・Ｉｄ印加）によるチャネル温度上昇前後のＶｇｓの差分（以後、ΔＶｆという）を求める（ステップ１８）。この工程では、半導体素子へのドレイン電圧印加前にＶｇｓを測定し、半導体素子へのドレイン電圧印加によるチャネル温度上昇後にＶｇｓを測定し、ドレイン電圧印加前のＶｇｓとドレイン電圧印加後のＶｇｓとの差分を求める。そして、ステップ１８では、ステップ１４で決定したＶｄ・Ｉｄが印加される。よってこのＶｄ・Ｉｄを印加すると半導体素子の温度、即ち半導体素子のチャネル温度が上昇する。
Next, a difference in Vgs before and after the channel temperature rise due to drain voltage application (Vd · Id application) (hereinafter referred to as ΔVf) is obtained (step 18). In this step, Vgs is measured before the drain voltage is applied to the semiconductor element, Vgs is measured after the channel temperature is increased by applying the drain voltage to the semiconductor element, and Vgs before the drain voltage is applied and Vgs after the drain voltage is applied. Find the difference. In
次いで、熱抵抗値を算出する（ステップ２０）。半導体素子の熱抵抗値は、差分を求める工程における半導体素子への印加電力、温度係数、前述の差分（ΔＶｆ）から求める。本発明の実施の形態１に係る熱抵抗測定方法は上述の工程を備える。 Next, a thermal resistance value is calculated (step 20). The thermal resistance value of the semiconductor element is obtained from the applied power to the semiconductor element, the temperature coefficient, and the difference (ΔVf) described above in the step of obtaining the difference. The thermal resistance measurement method according to Embodiment 1 of the present invention includes the above-described steps.
本発明の実施の形態１に係る熱抵抗測定方法によれば、Ｖｇｓの温度係数を測定する前にエージング工程を実施する。エージング工程により半導体素子の電気特性が安定化し、Ｖｇｓはほぼ温度のみによって変化するようになる。これにより正確なＶｇｓが測定できるので、正確な温度係数を測定できる。また、Ｖｇｓの差分を求める工程の前にもエージング工程を実施する。このエージング工程により半導体素子の電気特性を安定化させることができる。これにより正確なＶｇｓが測定できるので、正確なΔＶｆを求めることができる。このように、Ｖｇｓの温度係数測定前、及びΔＶｆを求める前にエージング工程を実施することで、各工程におけるＶｇｓが温度以外の要因で変動することを抑制できる。ゆえに、半導体素子の熱抵抗を正確に測定できる。 According to the thermal resistance measurement method according to the first embodiment of the present invention, the aging process is performed before the temperature coefficient of Vgs is measured. The electrical characteristics of the semiconductor element are stabilized by the aging process, and Vgs is changed only by temperature. As a result, accurate Vgs can be measured, so that an accurate temperature coefficient can be measured. The aging process is also performed before the process of obtaining the difference in Vgs. The electrical characteristics of the semiconductor element can be stabilized by this aging process. Thereby, since accurate Vgs can be measured, accurate ΔVf can be obtained. In this way, by performing the aging process before measuring the temperature coefficient of Vgs and before obtaining ΔVf, it is possible to suppress fluctuations in Vgs in each process due to factors other than temperature. Therefore, the thermal resistance of the semiconductor element can be accurately measured.
本発明の実施の形態ではＶｇｓの温度係数測定前、及びΔＶｆを求める前にエージング工程を実施した。しかしながらＶｇｓの温度係数を測定する前のエージングにより半導体素子の電気特性が安定化し、ΔＶｆ測定前のエージング工程が必要ない場合にはそれを省略してもよい。また、不要であればＶｇｓの温度係数を測定する前のエージングを省略してもよい。 In the embodiment of the present invention, the aging process was performed before measuring the temperature coefficient of Vgs and before obtaining ΔVf. However, if the electrical characteristics of the semiconductor element are stabilized by aging before measuring the temperature coefficient of Vgs, and the aging process before measuring ΔVf is not necessary, it may be omitted. Further, if unnecessary, aging before measuring the temperature coefficient of Vgs may be omitted.
本発明の実施の形態１に係る熱抵抗測定方法では、ステップ１４にて半導体素子が発熱する程度のＶｄ・Ｉｄ印加条件を決定した。しかしながら、半導体素子は通常動作時のＶｄ・Ｉｄで発熱するものなので、ステップ１４を省略して、ステップ１８にて通常動作時のＶｄ・Ｉｄを印加することとしてもよい。
In the thermal resistance measurement method according to the first embodiment of the present invention, the Vd · Id application condition is determined in
本発明の実施の形態に係る半導体素子はＧａＮで形成されたＨＥＭＴであるとしたがこれに限定されない。半導体素子は、Ｖｇｓがバイアス印加や高周波電力の入力等で変化し得るものであれば特に限定されない。 Although the semiconductor element according to the embodiment of the present invention is a HEMT formed of GaN, the present invention is not limited to this. The semiconductor element is not particularly limited as long as Vgs can be changed by bias application, high-frequency power input, or the like.
実施の形態２．
図２は、本発明の実施の形態２に係る熱抵抗測定方法を示すフローチャートである。以後、図２に沿って説明を進める。まず、ダミー温度係数測定（以後、ダミー測定１という）を実施する（ステップ２０）。ダミー測定１は、前述の「Ｖｇｓの温度係数を測定する工程」と同一条件で行う。次いで、１２、１４、１８及び２０を実施する。これらの工程は実施の形態１にて説明したとおりである。
Embodiment 2. FIG.
FIG. 2 is a flowchart showing a thermal resistance measurement method according to Embodiment 2 of the present invention. Hereinafter, the description will be made with reference to FIG. First, dummy temperature coefficient measurement (hereinafter referred to as dummy measurement 1) is performed (step 20). The dummy measurement 1 is performed under the same conditions as the above-described “step of measuring the temperature coefficient of Vgs”. Then 12, 14, 18 and 20 are performed. These steps are as described in the first embodiment.
Ｖｇｓの温度係数を測定する工程の前にダミー測定１を行うことにより、半導体素子の電気特性を安定化させることができる。つまり、Ｖｇｓが温度以外の要因で変動することを抑制して、正確な温度係数を測定できる。 By performing the dummy measurement 1 before the step of measuring the temperature coefficient of Vgs, the electrical characteristics of the semiconductor element can be stabilized. That is, an accurate temperature coefficient can be measured by suppressing Vgs from fluctuating due to factors other than temperature.
図３は本発明の実施の形態２に係る熱抵抗測定方法の変形例を示すフローチャートである。変形例の熱抵抗測定方法はΔＶｆを求める工程の前に、ダミー差分（ΔＶｆ）測定工程（以後、ダミー測定２という）を実施する。ダミー測定２は、前述の「ΔＶｆを求める工程」と同一条件で行う。 FIG. 3 is a flowchart showing a modification of the thermal resistance measurement method according to Embodiment 2 of the present invention. In the thermal resistance measurement method of the modification, a dummy difference (ΔVf) measurement step (hereinafter referred to as dummy measurement 2) is performed before the step of obtaining ΔVf. The dummy measurement 2 is performed under the same conditions as the above-mentioned “step for obtaining ΔVf”.
ΔＶｆを求める工程の前にダミー測定２を行うことにより、半導体素子の電気特性を安定化させることができる。つまり、Ｖｇｓが温度以外の要因で変動することを抑制して、正確なΔＶｆを測定できる。 By performing the dummy measurement 2 before the step of obtaining ΔVf, the electrical characteristics of the semiconductor element can be stabilized. That is, accurate ΔVf can be measured by suppressing Vgs from fluctuating due to factors other than temperature.
本発明の実施の形態１及び２により、温度係数を測定する工程の前にエージング又はダミー測定１を行うことを説明した。ここで本発明は、温度係数を測定する工程の前に「昇温工程」を実施し、半導体素子の電気特性を安定化させてから温度係数を測定することを特徴の1つとする。つまり、温度係数を測定する工程の前に行う工程はエージング工程やダミー測定工程に限定されず、昇温工程であればよい。同様に、ΔＶｆを求める工程の前のエージング又はダミー測定２についても、これらに限定されず、昇温工程であればよい。 According to the first and second embodiments of the present invention, the aging or dummy measurement 1 is performed before the step of measuring the temperature coefficient. One feature of the present invention is that the temperature coefficient is measured after performing the “temperature raising step” before the step of measuring the temperature coefficient to stabilize the electrical characteristics of the semiconductor element. That is, the process performed before the process of measuring the temperature coefficient is not limited to the aging process or the dummy measurement process, and may be a temperature raising process. Similarly, the aging or dummy measurement 2 before the step of obtaining ΔVf is not limited to these and may be a temperature raising step.
ダミー測定１及びダミー測定２は複数回実施して半導体素子の電気特性をさらに安定化させてもよい。なお、本発明の実施の形態２に係る熱抵抗測定方法は、少なくとも実施の形態１と同程度の変形は可能である。 The dummy measurement 1 and the dummy measurement 2 may be performed a plurality of times to further stabilize the electrical characteristics of the semiconductor element. Note that the thermal resistance measurement method according to the second embodiment of the present invention can be modified at least as much as the first embodiment.
１０ エージング工程、 １２ Ｖｇｓの温度係数測定工程、 １６ エージング工程、 １８ ΔＶｆを求める工程、 ２０ 熱抵抗を算出する工程 10 aging process, 12 Vgs temperature coefficient measuring process, 16 aging process, 18 calculating ΔVf, 20 calculating thermal resistance
Claims (3)
前記半導体素子へのドレイン電圧印加前に前記順方向ゲートソース間電圧を測定し、前記半導体素子へのドレイン電圧印加によるチャネル温度上昇後に前記順方向ゲートソース間電圧を測定し、前記ドレイン電圧印加前の前記順方向ゲートソース間電圧と前記ドレイン電圧印加後の前記順方向ゲートソース間電圧との差分を求める工程と、
前記差分を求める工程における前記半導体素子への印加電力、前記温度係数、及び前記差分から、前記半導体素子の熱抵抗値を算出する工程と、を有し、
前記温度係数を測定する工程の前に、前記温度係数を測定する工程と同一条件でダミー温度係数測定を行うことを特徴とする熱抵抗測定方法。 Measuring a temperature coefficient of a forward gate-source voltage of a semiconductor element;
The forward gate-source voltage is measured before applying the drain voltage to the semiconductor element, the forward gate-source voltage is measured after the channel temperature rises due to the drain voltage application to the semiconductor element, and before the drain voltage is applied. Obtaining a difference between the forward gate-source voltage and the forward gate-source voltage after applying the drain voltage;
Calculating the thermal resistance value of the semiconductor element from the applied power to the semiconductor element in the step of obtaining the difference, the temperature coefficient, and the difference, and
Before the step of measuring the temperature coefficient, a dummy temperature coefficient measurement is performed under the same conditions as the step of measuring the temperature coefficient.
前記半導体素子へのドレイン電圧印加前に前記順方向ゲートソース間電圧を測定し、前記半導体素子へのドレイン電圧印加によるチャネル温度上昇後に前記順方向ゲートソース間電圧を測定し、前記ドレイン電圧印加前の前記順方向ゲートソース間電圧と前記ドレイン電圧印加後の前記順方向ゲートソース間電圧との差分を求める工程と、
前記差分を求める工程における前記半導体素子への印加電力、前記温度係数、及び前記差分から、前記半導体素子の熱抵抗値を算出する工程と、を有し、
前記差分を求める工程の前に、前記差分を求める工程と同一条件でダミー差分測定を行うことを特徴とする熱抵抗測定方法。 Measuring a temperature coefficient of a forward gate-source voltage of a semiconductor element;
The forward gate-source voltage is measured before applying the drain voltage to the semiconductor element, the forward gate-source voltage is measured after the channel temperature rises due to the drain voltage application to the semiconductor element, and before the drain voltage is applied. Obtaining a difference between the forward gate-source voltage and the forward gate-source voltage after applying the drain voltage;
Calculating the thermal resistance value of the semiconductor element from the applied power to the semiconductor element in the step of obtaining the difference, the temperature coefficient, and the difference, and
Prior to the step of obtaining the difference, a dummy difference measurement is performed under the same conditions as the step of obtaining the difference.
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