JP2015213197A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device having a highly-reliable capacitor structure with a thin capacitor film, by ensuring a large polarization inversion amount while suppressing an increase of a leakage current even when the capacitor film is thinned.SOLUTION: When an FeRAM ferroelectric capacitor structure is formed, a lower electrode film is formed (a step S1), a first ferroelectric film is formed (a step S2), the first ferroelectric film is crystallized by a first heat treatment (a step S3), a second ferroelectric film in an amorphous state is formed on the first ferroelectric film (a step S4), an SRO film in an amorphous state is formed on the second ferroelectric film (a step S5), a first upper electrode film is formed on the SRO film (a step S6), and the second ferroelectric film and the SRO film are crystallized by a second heat treatment (a step S7).

Description

  The present invention relates to a semiconductor device having a capacitor structure in which a capacitor film made of a dielectric material is sandwiched between a lower electrode and an upper electrode, and more particularly to a ferroelectric capacitor structure in which the capacitor film is made of a ferroelectric material. It is preferable.

  In recent years, development of a ferroelectric memory (FeRAM: Ferro-electric Random Access Memory) that holds information in a ferroelectric capacitor structure by utilizing polarization inversion of the ferroelectric has been advanced. A ferroelectric memory is a non-volatile memory in which retained information is not lost even when the power is turned off, and is attracting particular attention because it can be expected to realize high integration, high speed driving, high durability, and low power consumption.

JP 2000-260954 A JP 2000-252444 A

  Recently, there is an increasing demand for low-voltage operation of ferroelectric memories. In order to achieve this low voltage operation, it is necessary to reduce the thickness of the ferroelectric film that is the capacitor film of the ferroelectric capacitor.

However, when the ferroelectric film is thinned, there is a problem that the amount of polarization inversion decreases and the leakage current increases.
As a cause of the decrease in the amount of polarization inversion, it is conceivable that lattice matching at the interface between the ferroelectric film and the upper electrode affects the electrical characteristics as the ferroelectric film becomes thinner. If the lattice matching is not good, a high amount of polarization inversion cannot be obtained.
Similarly, the cause of the increase in leakage current is considered to depend on the state of the interface between the ferroelectric film and the upper electrode. When the ferroelectric film is crystallized by heat treatment, a grain boundary is formed at the interface, and a void is generated in the grain boundary. When the material of the upper electrode is buried in the gap, the effective thickness of the ferroelectric film becomes thin, and the leakage current increases.

Patent Documents 1 and 2 disclose a configuration in which an SrRuO ₃ (SRO) film is used for part or all of the upper electrode, and the composition of Pb, Zr, and Ti of the capacitor film made of PZT is adjusted. However, in this case, the leakage current increases compared to the case where no SRO film is used.

  The present invention has been made in view of the above-described problems. Although the capacitor film is reduced in thickness, a large amount of polarization inversion is ensured while suppressing an increase in leakage current, and a highly reliable capacitor film is provided. An object of the present invention is to provide a method of manufacturing a semiconductor device that realizes a semiconductor device having a capacitor structure.

One aspect of a method for manufacturing a semiconductor device includes a step of forming a first electrode film serving as a lower electrode above a semiconductor substrate, and a step of forming a first dielectric film on the first electrode film. Applying a first heat treatment to the semiconductor substrate; forming an amorphous second dielectric film on the first dielectric film; and an amorphous state on the second dielectric film. Forming a SrRuO ₃ film having a thickness of 1 nm or more and 4 nm or less, forming a second electrode film on the SrRuO ₃ film as at least a part of an upper electrode, and the amorphous state of the first film As a heat treatment subsequent to the first heat treatment in a state where the amorphous SrRuO ₃ film and the second electrode film are sequentially formed on the second dielectric film, a second heat treatment is performed on the semiconductor substrate. And a step of applying the first Collector layer, said second dielectric layer, the SrRuO ₃ film, and the first etching step of etching the second electrode layer, so as to cover the entire surface, forming a first protective insulating film And applying a third heat treatment to the semiconductor substrate; and a second etching step of etching only a portion of the first electrode film and the first protective insulating film on the first electrode film; , Including a step of forming a second protective insulating film so as to cover the entire surface, and a step of performing a fourth heat treatment on the semiconductor substrate.

  According to the semiconductor device manufacturing method described above, the capacitor film is made thin, but a large amount of polarization inversion is secured while suppressing an increase in leakage current, and a highly reliable capacitor structure having a thin capacitor film is provided. A semiconductor device is realized.

It is a schematic sectional drawing which shows the manufacturing method of FeRAM by 1st Embodiment. 2 is a schematic cross-sectional view illustrating the method of manufacturing the FeRAM according to the first embodiment, following FIG. FIG. 3 is a schematic cross-sectional view showing the FeRAM manufacturing method according to the first embodiment, following FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the manufacturing method of the FeRAM according to the first embodiment following FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating the manufacturing method of the FeRAM according to the first embodiment following FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating the manufacturing method of the FeRAM according to the first embodiment following FIG. 5. FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 illustrating the method for manufacturing the FeRAM according to the first embodiment. FIG. 8 is a schematic cross-sectional view showing the manufacturing method of the FeRAM according to the first embodiment, following FIG. 7. It is a flowchart which shows the main processes in the manufacturing method of FeRAM by 1st Embodiment. 10 is a flowchart showing main steps in a method for manufacturing FeRAM according to Comparative Example 1. FIG. 10 is a flowchart showing main steps in a method for manufacturing FeRAM according to Comparative Example 2. FIG. 10 is a flowchart showing main steps in a method for manufacturing FeRAM according to Comparative Example 3. FIG. 10 is a flowchart showing main steps in a method for manufacturing FeRAM according to Comparative Example 4. FIG. It is a characteristic view which shows the measurement result of polarization inversion amount. It is a characteristic view which shows the measurement result of leakage current. It is a schematic sectional drawing which shows the manufacturing method of FeRAM by 2nd Embodiment. FIG. 17 is a schematic cross-sectional view subsequent to FIG. 16 illustrating the method for manufacturing the FeRAM according to the second embodiment. FIG. 18 is a schematic cross-sectional view subsequent to FIG. 17 showing the method for manufacturing FeRAM according to the second embodiment. FIG. 19 is a schematic cross-sectional view illustrating the manufacturing method of the FeRAM according to the second embodiment following FIG. 18. FIG. 20 is a schematic cross-sectional view subsequent to FIG. 19 illustrating the method for manufacturing the FeRAM according to the second embodiment. FIG. 21 is a schematic cross-sectional view showing a method for manufacturing the FeRAM according to the second embodiment, following FIG. 20. FIG. 22 is a schematic cross-sectional view showing a method for manufacturing the FeRAM according to the second embodiment, following FIG. 21.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the following embodiments, the case where the present invention is applied to FeRAM will be exemplified, but the present invention can also be applied to a semiconductor memory using a normal dielectric film as a capacitor structure.

(First embodiment)
Hereinafter, a first embodiment will be described in detail with reference to the drawings.

-Manufacturing method of FeRAM-
In the present embodiment, a so-called planar type FeRAM that secures conduction between the lower electrode and the upper electrode of the ferroelectric capacitor structure above the ferroelectric capacitor structure is illustrated. For convenience of explanation, the structure of the FeRAM will be described together with its manufacturing method.
1 to 8 are schematic sectional views showing the structure of the FeRAM according to the first embodiment in the order of steps together with the manufacturing method thereof.

As shown in FIG. 1A, a MOS transistor 20 that functions as a selection transistor is formed on a silicon semiconductor substrate 10.
Specifically, the element isolation structure 11 is formed on the surface layer of the silicon semiconductor substrate 10 by, for example, an STI (Shallow Trench Isolation) method. Thereby, an active region is defined on the semiconductor substrate 10.

Impurities, for example, boron (B) which is a P-type impurity, for example, is ion-implanted into the element active region under the conditions of a dose amount of 3.0 × 10 ¹³ / cm ² and an acceleration energy of 300 keV. Thereby, the well 12 is formed.

  A thin gate insulating film 13 having a thickness of about 3.0 nm is formed in the active region by thermal oxidation or the like. A polycrystalline silicon film with a film thickness of about 180 nm and, for example, a silicon nitride film with a film thickness of about 29 nm are sequentially deposited on the gate insulating film 13 by CVD or the like. The silicon nitride film, the polycrystalline silicon film, and the gate insulating film 13 are processed into electrode shapes by lithography and subsequent dry etching. Thereby, the gate electrode 14 is formed on the gate insulating film 13. At the same time, a cap film 15 made of a silicon nitride film is formed on the gate electrode 14.

Using the cap film 15 as a mask, an impurity, for example, arsenic (As), which is an N-type impurity in this case, is ion-implanted under the conditions of a dose amount of 5.0 × 10 ¹⁴ / cm ² and an acceleration energy of 10 keV. Thereby, a so-called LDD region 16 is formed.

  For example, a silicon oxide film is deposited on the entire surface by a CVD method or the like, and the entire surface of the silicon oxide film is subjected to anisotropic dry etching (etch back). As a result, the silicon oxide film remains only on the side surfaces of the gate electrode 14 and the cap film 15, and the sidewall insulating film 17 is formed.

  Using the cap film 15 and the sidewall insulating film 17 as a mask, an impurity, for example, phosphorus (P), which is an N-type impurity in this case, is ion-implanted under a condition that the impurity concentration is higher than that of the LDD region 16. As a result, the source / drain region 18 overlapping the LDD region 16 is formed, and the MOS transistor 20 is formed.

Subsequently, as shown in FIG. 1B, a protective film 21 and an interlayer insulating film 22a of the MOS transistor 20 are sequentially formed.
Specifically, a protective film 21 and an interlayer insulating film 22 a are sequentially deposited so as to cover the MOS transistor 20. Here, as the protective film 21, a silicon oxide film is used as a material, and is deposited to a thickness of about 20 nm by a CVD method or the like. As the interlayer insulating film 22a, first, for example, a stacked structure in which a plasma SiO film (film thickness of about 20 nm), a plasma SiN film (film thickness of about 80 nm), and a plasma TEOS film (film thickness of about 1000 nm) are sequentially formed is formed. . After the lamination, polishing is performed by CMP until the film thickness becomes about 700 nm. Thereby, the interlayer insulating film 22a is formed.

Subsequently, as shown in FIG. 1C, an interlayer insulating film 22b and a protective film 23 are sequentially formed.
1C and the following drawings, for convenience of illustration, only the structure above the interlayer insulating film 22a is shown, and illustration of the silicon semiconductor substrate 10, the MOS transistor 20, and the like is omitted.
Specifically, a silicon oxide film is deposited on the interlayer insulating film 22a to a thickness of about 100 nm by, for example, a plasma CVD method using TEOS. Thereby, the interlayer insulating film 22b is formed. Thereafter, the interlayer insulating film 22b is annealed. As conditions for the annealing treatment, for example, the annealing is performed at 650 ° C. for 20 minutes to 45 minutes while supplying N ₂ gas at a flow rate of 20 liters / minute.

A protective film 23 is formed on the interlayer insulating film 22b to prevent hydrogen / water from entering a ferroelectric film having a ferroelectric capacitor structure, which will be described later.
As the protective film 23, alumina (Al ₂ O ₃ ) is used as a material and is deposited to a film thickness of about 20 nm to 50 nm by a sputtering method or the like. As specific film forming conditions, an Al ₂ O ₃ target is used, an input power of 2 kW, Ar as a sputtering gas is supplied at a flow rate of 22 sccm, and a film is formed for 44 seconds. Thus, the protective film 23 made of alumina having a thickness of about 20 nm is formed. Thereafter, the protective film 23 is annealed. As conditions for the annealing treatment, for example, the annealing is performed at 650 ° C. for 30 seconds to 120 seconds while supplying O ₂ gas at a flow rate of 2 liters / minute.

Subsequently, as shown in FIG. 1D, a lower electrode film 24 to be a lower electrode is formed.
Specifically, Pt is deposited by sputtering or the like, and the lower electrode film 24 is formed. As specific film formation conditions, a Pt target is used, an input power of 0.44 kW, Ar as a sputtering gas is supplied at a flow rate of 119 sccm, and film formation is performed at a film formation temperature of 350 ° C. for 180 seconds. Thus, the lower electrode film 24 made of Pt with a film thickness of about 153 nm is formed.

Subsequently, as shown in FIG. 2A, a first ferroelectric film 25a which is a lower layer of the capacitor film is formed.
In particular, Pb, for example, a thickness of about 50nm~120nm by sputtering or the like _{(Zr x, Ti 1-x} ) O 3 (0 <x <1) is deposited (PZT), a first ferroelectric film 25a Form. As specific film formation conditions, a PZT target is used, an input power of 1 kW, Ar as a sputtering gas is supplied at a flow rate of 18 sccm, and film formation is performed at a film formation temperature of 50 ° C. for 112 seconds. As a result, the first ferroelectric film 25a made of PZT having a Pb amount of 1.13 and a thickness of about 70 nm is formed on the lower electrode film 24. The first ferroelectric film 25a is formed in an amorphous state.
As the material of the first ferroelectric film 25a, PZT to which elements such as Ca, Sr, La, Nb, Ta, Ir, W, and Ru are added can be used.

Subsequently, as shown in FIG. 2B, the semiconductor substrate 10 is heat-treated (first heat treatment).
Specifically, as the first heat treatment, the semiconductor substrate 10 is subjected to a rapid heating (RTA) process using a predetermined rapid thermal processing apparatus to crystallize the first ferroelectric film 25a. As specific heat treatment conditions, Ar is supplied as an atmosphere gas at a flow rate of 1.975 slm, O ₂ is supplied at 25 sccm, a processing temperature is about 450 ° C. to 700 ° C., here 582 ° C., a processing time is 20 seconds to 300 seconds, Here, it is 90 seconds. Thereby, the first ferroelectric film 25a, which was in an amorphous state at the beginning of the film formation, is crystallized.

  In the above RTA processing, if the processing temperature is lower than 450 ° C. or the processing time is shorter than 20 seconds, there is a concern that the first ferroelectric film 25a is not sufficiently crystallized and an increase in leakage current is caused. There are concerns. Further, if the processing temperature is higher than 700 ° C. or the processing time is longer than 300 seconds, there is a concern that leakage current increases. Therefore, by setting the processing temperature and processing time to values within the above ranges, the first ferroelectric film 25a can be sufficiently crystallized without increasing the leakage current.

Subsequently, as shown in FIG. 2C, a second ferroelectric film 25b which is an upper layer of the capacitor film is formed.
Specifically, PZT is deposited to a thickness of, for example, about 5 nm to 40 nm by sputtering or the like to form the second ferroelectric film 25b. As specific film formation conditions, a PZT target is used, an input power of 1 kW, Ar as a sputtering gas is supplied at a flow rate of 18 sccm, and film formation is performed at a film formation temperature of 50 ° C. for 19 seconds. As a result, the second ferroelectric film 25b made of PZT having a Pb amount of 1.13 and a thickness of about 10 nm is formed on the first ferroelectric film 25a. The second ferroelectric film 25b is formed in an amorphous state.
As the material of the second ferroelectric film 25b, PZT or the like to which elements such as Ca, Sr, La, Nb, Ta, Ir, W, and Ru are added can also be used.

Subsequently, as shown in FIG. 3A, an SrRuO ₃ (SRO) film 19 is formed.
Specifically, the SRO film 19 is formed by depositing SRO to a thickness of, for example, about 1 nm to 5 nm by sputtering or the like. As specific film formation conditions, an SRO target is used, an input power of 0.31 kW, Ar as a sputtering gas is supplied at a flow rate of 100 sccm, and film formation is performed at a film formation temperature of 60 ° C. for 2 seconds. Thus, the SRO film 19 having a thickness of about 1 nm is formed on the second ferroelectric film 25b. The SRO film 19 is formed in an amorphous state. By forming the SRO film on the ferroelectric capacitor film, a high polarization inversion amount in the capacitor structure can be obtained even if the capacitor film is formed thin. From the consideration to be described later, it is possible to obtain a large amount of polarization inversion by forming the SRO film 19 with a film thickness of about 1 nm to 5 nm.

Subsequently, as shown in FIG. 3B, a first upper electrode film 26a which is a lower layer of the upper electrode is formed.
Specifically, IrO ₂ is deposited to a thickness of, for example, about 10 nm to 200 nm by a sputtering method or the like to form the first upper electrode film 26a. As specific film formation conditions, an Ir target is used, an input power is 1.91 kW, Ar is supplied as a sputtering gas at a flow rate of 100 sccm, O ₂ is supplied at 52 sccm, and film formation is performed at a film formation temperature of 20 ° C. for 9 seconds. Thus, the first upper electrode film 26a made of IrO ₂ having a thickness of about 49 nm is formed on the SRO film 19.
As a material of the first upper electrode film 26a, Ir, Ru, RuO ₂ , other conductive oxides, or the like can be used instead of IrO ₂ .

Subsequently, as shown in FIG. 3C, the semiconductor substrate 10 is heat-treated (second heat treatment).
Specifically, as the second heat treatment, the semiconductor substrate 10 is subjected to RTA treatment using a predetermined rapid heat treatment apparatus, and the second ferroelectric film 25b and the SRO film 19 are crystallized. As specific heat treatment conditions, Ar is supplied as an atmosphere gas at a flow rate of 1.98 slm, O ₂ is supplied at 20 sccm, a processing temperature is about 550 ° C. to 800 ° C., here 732 ° C., a processing time is 30 seconds to 300 seconds, Here, it is set to 118 seconds. As a result, the second ferroelectric film 25b and the SRO film 19 that were in an amorphous state at the beginning of the film formation are crystallized.

  In the above RTA processing, if the processing temperature is lower than 550 ° C. or the processing time is shorter than 30 seconds, the second ferroelectric film 25b (and the SRO film 19, particularly the second ferroelectric film) There is a concern that 25b) is not sufficiently crystallized, and that leakage current is increased. Further, if the processing temperature is higher than 800 ° C. or the processing time is longer than 300 seconds, there is a fear of unexpected influence on the first ferroelectric film 25a and an increase in leakage current. Therefore, by setting the processing temperature and the processing time to values within the above ranges, the second ferroelectric film can be prevented without adversely affecting the first ferroelectric film 25a and causing an increase in leakage current. 25b can be sufficiently crystallized.

Subsequently, as shown in FIG. 4A, a second upper electrode film 26b which is an upper layer of the upper electrode is formed.
Specifically, IrO ₂ is deposited to a thickness of, for example, about 25 nm to 250 nm by sputtering or the like to form the second upper electrode film 26b. As specific film forming conditions, an Ir target is used, an input power of 1.03 kW, Ar as a sputtering gas is supplied at a flow rate of 100 sccm, O ₂ is supplied at 90 sccm, and a film is formed at a film forming temperature of 20 ° C. for 28 seconds. Subsequently, Ar is supplied at a flow rate of 100 sccm and O ₂ at 90 sccm as an input power of 2.03 kW, and a film is formed at a film formation temperature of 20 ° C. for 4.4 seconds. As a result, the second upper electrode film 26b made of IrO ₂ having a thickness of about 100 nm is formed on the first upper electrode film 26a.
As a material of the second upper electrode film 26b, Ir, Ru, RuO ₂ , other conductive oxides, or the like can be used instead of IrO ₂ .

Subsequently, as shown in FIG. 4B, the upper electrode 33 is formed.
Specifically, the first and second upper electrode films 26a and 26b are processed into a plurality of electrode shapes by lithography and subsequent dry etching. As a result, the upper electrode 33 composed of the first and second upper electrode films 26a and 26b is formed.

Subsequently, as shown in FIG. 4C, a capacitor film 32 is formed.
More specifically, the SRO film 19 and the first and second ferroelectric films 25a and 25b are aligned with the upper electrode 33 and processed by lithography and subsequent dry etching. Thereby, the SRO film 19 is processed, and the capacitor film 32 composed of the first and second ferroelectric films 25a and 25b is formed.
After the capacitor film 32 is formed, the capacitor film 32 is heat treated to restore the function of the capacitor film 32.

Subsequently, as shown in FIG. 5A, a protective film 27 for preventing hydrogen / water from entering the capacitor film 32 is formed.
More specifically, an alumina (Al ₂ O ₃ ) material is deposited on the lower electrode film 24 so as to cover the capacitor film 32, the SRO film 19, and the upper electrode 33 to a thickness of about 50 nm by sputtering or the like. Thereby, the protective film 27 is formed. Thereafter, the protective film 27 is annealed.

Subsequently, as shown in FIG. 5B, the lower electrode film 24 is processed together with the protective film 27 to form a ferroelectric capacitor structure 30.
Specifically, the protective film 27 and the lower electrode film 24 are processed by lithography and subsequent dry etching so that the lower electrode film 24 remains in a larger size than the capacitor film 25 so as to match the processed capacitor film 25. Then, the lower electrode 31 is formed. As a result, the ferroelectric capacitor structure 30 in which the capacitor film 32, the SRO film 19, and the upper electrode 33 are sequentially stacked on the lower electrode 31 is formed. At the same time, the protective film 27 remains so as to cover from the upper surface of the upper electrode 33 to the side surfaces of the upper electrode 33, the SRO film 19 and the capacitor film 32, and the upper surface of the lower electrode 31. Thereafter, the protective film 27 is heat-treated.

Subsequently, as shown in FIG. 5C, a protective film 28 is formed.
Specifically, the film is deposited to a thickness of about 20 nm to 50 nm by sputtering or the like using alumina (Al ₂ O ₃ ) as a material so as to cover the ferroelectric capacitor structure 30 and the protective film 27. Thereby, the protective film 28 is formed. Thereafter, the protective film 28 is heat-treated.

Subsequently, as shown in FIG. 6A, an interlayer insulating film 29 is formed.
Specifically, the interlayer insulating film 29 is formed so as to cover the ferroelectric capacitor structure 30 with the protective films 27 and 28 interposed therebetween. Here, as the interlayer insulating film 29, a silicon oxide film is deposited to a film thickness of about 1500 nm to 2500 nm by, for example, a plasma CVD method using TEOS, and then polished by CMP until the film thickness becomes, for example, about 1000 nm. Form. After CMP, for example, N ₂ O plasma annealing is performed for the purpose of dehydrating the interlayer insulating film 29.

Subsequently, as shown in FIG. 6B, a conductive plug 36 connected to the source / drain region 18 of the MOS transistor 20 is formed.
Specifically, the interlayer insulating film 29, the protective films 28 and 27, the interlayer insulating films 22b and 22a, and the protective film 21 are processed by lithography and subsequent dry etching. This dry etching is performed using the source / drain region 18 as an etching stopper until a part of the surface of the source / drain region 18 is exposed. Thereby, for example, a via hole 36a having a diameter of about 0.3 μm is formed.

For example, a Ti film and a TiN film are sequentially deposited to a film thickness of about 20 nm and a film thickness of about 50 nm so as to cover the wall surface of the via hole 36a. As a result, a base film (glue film) 36b is formed. For example, a W film is formed so as to fill the via hole 36a through the glue film 36b by a CVD method or the like. The W film and the glue film 36b are polished by CMP using the interlayer insulating film 29 as a stopper. As a result, the conductive plug 36 filling the via hole 36a with W through the glue film 36b is formed. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

Subsequently, as shown in FIG. 6C, after forming a hard mask 37 and a resist mask 38, via holes 34a and 35a to the ferroelectric capacitor structure 30 are formed.
Specifically, a silicon nitride film is deposited to a thickness of about 100 nm on the interlayer insulating film 29 by a CVD method or the like. Thereby, the hard mask 37 is formed. A resist is applied on the hard mask 37, and the resist is processed by lithography. Thereby, a resist mask 38 having openings 38a and 38b is formed.

The hard mask 37 is dry-etched using the resist mask 38, and openings 37a and 37b are formed at portions matching the openings 38a and 38b of the hard mask 37.
The hard mask 37 is mainly used, and the interlayer insulating film 29 and the protective films 28 and 27 are dry-etched using the upper electrode 33 and the lower electrode 31 as etching stoppers, respectively. In this dry etching, processing performed on the interlayer insulating film 29 and the protective films 28 and 27 until a part of the surface of the upper electrode 33 is exposed, and the interlayer insulating film 29 and the protection until a part of the surface of the lower electrode 31 is exposed. The processing applied to the films 28 and 27 is performed simultaneously. As a result, via holes 34a and 35a having a diameter of, for example, about 0.5 μm are simultaneously formed in the respective portions.

Subsequently, as shown in FIG. 7A, the resist mask 38 and the hard mask 37 are removed.
Specifically, first, the remaining resist mask 38 is removed by ashing or the like. Thereafter, an annealing process is performed to recover the damage received by the ferroelectric capacitor structure 30 through various steps after the formation of the ferroelectric capacitor structure 30. Then, the hard mask 37 is removed by whole surface anisotropic etching, so-called etch back.

Subsequently, as shown in FIG. 7B, conductive plugs 34 and 35 connected to the ferroelectric capacitor structure 30 are formed.
Specifically, first, base films (glue films) 34b and 35b are formed so as to cover the wall surfaces of the via holes 34a and 35a, and then the via holes 34a and 35a are embedded via the glue films 34b and 35b by a CVD method or the like. Thus, a W film is formed. Then, for example, the W film and the glue films 34b and 35b are polished by CMP using the interlayer insulating film 29 as a stopper. As a result, conductive plugs 34 and 35 are formed which fill the via holes 34a and 35a with W via the glue films 34b and 35b. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

Subsequently, as shown in FIG. 8A, first wirings 45 connected to the conductive plugs 34, 35, and 36 are formed.
Specifically, the barrier metal film 42, the wiring film 43, and the barrier metal film 44 are deposited on the entire surface of the interlayer insulating film 29 by sputtering or the like. As the barrier metal film 42, for example, a Ti film is laminated to a thickness of about 5 nm and a TiN film is laminated to a thickness of about 150 nm by sputtering or the like. As the wiring film 43, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 44, for example, a Ti film is deposited to a thickness of about 5 nm and a TiN film is deposited to a thickness of about 150 nm by sputtering or the like. Here, since the structure of the wiring film 43 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing of the wiring and reliability.

  For example, after forming a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 44, the wiring film 43, and the barrier metal film 42 are processed into a wiring shape by lithography and subsequent dry etching. To do. As a result, the first wirings 45 connected to the conductive plugs 34, 35, and 36 are formed. Instead of forming an Al alloy film as the wiring film 43, a Cu film (or Cu alloy film) may be formed using a so-called damascene method or the like, and a Cu wiring may be formed as the first wiring 45.

Subsequently, as shown in FIG. 8B, a second wiring 54 connected to the first wiring 45 is formed.
Specifically, an interlayer insulating film 46 is formed so as to cover the first wiring 45. As the interlayer insulating film 46, a silicon oxide film is formed to a thickness of about 700 nm, a plasma TEOS film is formed to a total thickness of about 1100 nm, and then the surface is polished by CMP to a thickness of 750 nm. Form to the extent.

A conductive plug 47 connected to the first wiring 45 is formed.
The interlayer insulating film 46 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 45 is exposed. Thereby, for example, a via hole 47a having a diameter of about 0.25 μm is formed.
After a base film (glue film) 48 is formed so as to cover the wall surface of the via hole 47a, a W film is formed so as to fill the via hole 47a via the glue film 48 by a CVD method or the like. Then, for example, the W film and the glue film 48 are polished using the interlayer insulating film 46 as a stopper. As a result, a conductive plug 47 that fills the via hole 47a with W via the glue film 48 is formed.

A second wiring 54 connected to each of the conductive plugs 47 is formed.
First, a barrier metal film 51, a wiring film 52, and a barrier metal film 53 are deposited on the entire surface by sputtering or the like. As the barrier metal film 51, for example, a Ti film is laminated to a thickness of about 5 nm and a TiN film is laminated to a thickness of about 150 nm by sputtering or the like. As the wiring film 52, for example, an Al alloy film (here, Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 53, for example, a Ti film is deposited to a thickness of about 5 nm and a TiN film is deposited to a thickness of about 150 nm by sputtering or the like. Here, since the structure of the wiring film 52 is the same as that of the logic part other than the FeRAM of the same rule, there is no problem in processing of the wiring and reliability.

  For example, after forming a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 53, the wiring film 52, and the barrier metal film 51 are processed into a wiring shape by lithography and subsequent dry etching. To do. Thereby, the second wiring 54 is formed. Instead of forming an Al alloy film as the wiring film 52, a Cu film (or Cu alloy film) may be formed by using a so-called damascene method or the like, and a Cu wiring may be formed as the second wiring 54.

  Thereafter, the planar type FeRAM according to the present embodiment is formed through various processes such as formation of an interlayer insulating film and a further upper layer wiring.

-Superiority of FeRAM according to this embodiment-
Hereinafter, the superiority of the FeRAM manufactured according to this embodiment will be described based on a comparison with a comparative example.

In the FeRAM manufacturing method according to the present embodiment, the main steps shown in FIG. 9 are performed when the ferroelectric capacitor structure 30 as a component is formed.
In the present embodiment, the lower electrode film is formed as shown in FIG. 1D (step S1). As shown in FIG. 2A, a first ferroelectric film is formed (step S2). As shown in FIG. 2B, the first ferroelectric film is crystallized by the first heat treatment (step S3). As shown in FIG. 2C, a second ferroelectric film is formed (step S4). As shown in FIG. 3A, an SRO film is formed (step S5). As shown in FIG. 3B, a first upper electrode film is formed (step S6). As shown in FIG. 3C, the second ferroelectric film and the SRO film are crystallized by the second heat treatment (step S7).

  In this embodiment, for comparison with the comparative example, two types of SRO films having a thickness of 1 nm and 5 nm are formed in step S5. In the former case, the film forming conditions are the same as the conditions exemplified with reference to FIG. In the latter case, the SRO target is used, the deposition power is 0.31 kW, Ar is supplied as a sputtering gas at a flow rate of 100 sccm, and the film is formed at a film formation temperature of 60 ° C. for 11 seconds. As a result, an SRO film having a thickness of about 5 nm is formed.

In the first comparative example, the main process shown in FIG. 10 is performed when the ferroelectric capacitor structure 30 as a constituent element is formed.
In Comparative Example 1, no SRO film is formed. That is, step S1, step S2, step S3, step S4, step S6, and step S7 are sequentially performed. The film forming conditions in each step are the same as in this embodiment.

In Comparative Example 2, the main process shown in FIG. 11 is performed when the ferroelectric capacitor structure 30 as a constituent element is formed.
In Comparative Example 2, the second ferroelectric film is not formed. That is, step S1, step S2, step S3, step S5, step S6, and step S7 are sequentially performed. Among the steps, the film formation conditions of the first ferroelectric film in step S1 are slightly different from those illustrated in the present embodiment. The film forming conditions in Step S1 in Comparative Example 2 are as follows: a PZT target is used, an input power of 1 kW, Ar as a sputtering gas is supplied at a flow rate of 18 sccm, and a film is formed for 131 seconds at a film forming temperature of 50 ° C. As a result, the first ferroelectric film made of PZT having a Pb amount of 1.13 and a thickness of about 80 nm is formed. The SRO film formed in step S5 has a thickness of about 1 nm.

In Comparative Example 3, the main process shown in FIG. 12 is performed when the ferroelectric capacitor structure 30 as a constituent element is formed.
In Comparative Example 3, the first heat treatment is not performed, and the second ferroelectric film is not formed. That is, step S1, step S2, step S5, step S6, and step S7 are sequentially performed. Among the steps, the film formation conditions of the first ferroelectric film in step S1 are slightly different from those in the present embodiment, and are the same as the film formation conditions in step S1 in comparative example 2. The SRO film formed in step S5 has a thickness of about 1 nm.

In Comparative Example 4, the main process shown in FIG. 13 is performed when the ferroelectric capacitor structure 30 as a constituent element is formed.
In Comparative Example 4, after the first ferroelectric film is formed, the second ferroelectric film is formed, and then the SRO film is formed, and then heat treatment is performed. That is, step S1, step S2, step S3, step S4, the second ferroelectric film is crystallized by heat treatment (step S11), step S5, the SRO film is crystallized by heat treatment (step S12), step S6. Step S7 is sequentially performed. Among steps S1 to S7, the conditions for the first heat treatment in step S3 are slightly different from those in the present embodiment. The heat treatment conditions in Step S4 in Comparative Example 4 are as follows: Ar is supplied as an atmospheric gas at a flow rate of 1.975 slm, O ₂ is supplied at 25 sccm, the processing temperature is 620 ° C., and the processing time is 90 seconds. The heat treatment conditions in step S11 are the same as in step S4. The heat treatment conditions in step S12 are as follows: O ₂ is supplied as an atmospheric gas at 2.0 slm, the treatment temperature is 642 ° C., and the treatment time is 90 seconds. The SRO film formed in step S5 has a film thickness of about 5 nm.

Table 1 below shows values of the polarization inversion amount (μC / cm ² ) and the leakage current (A) measured for this embodiment in which the SRO film is formed to a thickness of 1 nm and Comparative Examples 1, 2, and 3.

Table 2 below shows values of the polarization inversion amount (μC / cm ² ) and the leakage current (A) measured for this embodiment and Comparative Example 4 in which the SRO film is formed to a thickness of 5 nm.

In Comparative Example 1 in which no SRO film is formed, as shown in Table 1, the leakage current is small, but the amount of polarization inversion is also small.
In Comparative Example 2 in which the SRO film is formed but the second ferroelectric film is not formed, as shown in Table 1, the leakage current is large and the polarization inversion amount is small.
In Comparative Example 3 in which the first heat treatment is not performed and the second ferroelectric film is not formed, as shown in Table 1, the leakage current is large and the polarization inversion amount is small.
In Comparative Example 4 in which heat treatment is performed after forming the first ferroelectric film, the second ferroelectric film, and the SRO film, the amount of polarization inversion is large as shown in Table 2, but the leakage current is compared. Compared to Example 1, it has increased by an order of magnitude.

  On the other hand, in this embodiment, as shown in Tables 1 and 2, a polarization inversion amount larger than that of Comparative Example 4 is obtained, and the leakage current is as small as that of Comparative Example 1.

  In the present embodiment, the second ferroelectric film in an amorphous state is formed on the first ferroelectric film crystallized by the first heat treatment, and then the second ferroelectric film, the SRO film, A second heat treatment is performed on the first upper electrode film in a lump. This second heat treatment is performed with the second ferroelectric film in an amorphous state. As a result, the grain boundary at the interface between the second ferroelectric film and the SRO film and at the interface between the SRO film and the first upper electrode film is expanded, and the Sr of the SRO film is formed in the second ferroelectric film. , Ru and Ir of the first upper electrode film are easily doped. Sr, Ru, Ir doped in the second ferroelectric film improves the lattice spacing consistency with the first upper electrode film of the second ferroelectric film, and the second ferroelectric film The lattice distortion of the film is improved. Thereby, a large amount of polarization inversion can be obtained.

  Here, even if the grain boundary expands in the present embodiment as described above, the first ferroelectric film that has been crystallized already exists under the second ferroelectric film. The capacitor film has a two-layer structure of the first and second ferroelectric films, the effective film thickness of the capacitor film is ensured, and excessive diffusion of Sr, Ru, Ir is suppressed. As a result, an increase in leakage current is suppressed.

-Suitable thickness of SRO film in this embodiment-
With respect to the ferroelectric capacitor structure manufactured according to the present embodiment, the polarization inversion amount and the leakage current were measured based on comparison with the ferroelectric capacitor structure without the SRO film manufactured according to Comparative Example 1 described above. The ferroelectric capacitor structure according to the present embodiment is a ferroelectric capacitor structure formed by forming SRO films with thicknesses of 1 nm, 2 nm, 3 nm, 4 nm, and 5 nm, respectively.

  FIG. 14 shows the measurement result of the polarization inversion amount, and FIG. 15 shows the measurement result of the leakage current. 14 and 15, the results obtained by measuring nine times for each of Comparative Example 1 and the above-described five examples of the present embodiment are displayed.

As shown in FIG. 14, the polarization reversal amount is larger as the SRO film thickness is smaller. It can be seen that even in a ferroelectric capacitor structure in which an SRO film is formed to a thickness of 5 nm, a higher polarization inversion amount can be obtained than in Comparative Example 1 in which no SRO film is formed.
As shown in FIG. 15, the leakage current has a small value almost equal to that of each ferroelectric capacitor structure according to Comparative Example 1 in each ferroelectric capacitor structure according to the present embodiment.

  The amount of Sr, Ru, Ir doped in the second ferroelectric film differs depending on the film thickness of the SRO film, and a difference appears in the amount of polarization inversion. If the SRO film is too thick, the amount of Sr, Ru, Ir doped in the second ferroelectric film becomes excessive, and the amount of polarization inversion becomes small. If the SRO film is too thin, the amount of Sr, Ru, Ir doped in the second ferroelectric film is insufficient, and the amount of polarization inversion is not improved. Therefore, in the present embodiment, it is preferable to form the SRO film within the range of 1 nm to 5 nm.

  As described above, according to the present embodiment, the capacitor film 32 is thinned, but a large amount of polarization inversion is ensured while suppressing an increase in leakage current, and the highly reliable and strong capacitor film 32 is provided. A planar-type FeRAM including the dielectric capacitor structure 30 is realized.

(Second Embodiment)
In the present embodiment, a so-called stack type FeRAM that secures conduction of the lower electrode of the ferroelectric capacitor structure below the ferroelectric capacitor structure and secures conduction of the upper electrode above the ferroelectric capacitor structure is exemplified. . For convenience of explanation, the structure of the FeRAM will be described together with its manufacturing method.
16 to 22 are schematic sectional views showing the structure of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof.

First, as shown in FIG. 16A, a MOS transistor 120 that functions as a selection transistor is formed on a silicon semiconductor substrate 110.
Specifically, the element isolation structure 111 is formed on the surface layer of the silicon semiconductor substrate 110 by, for example, STI (Shallow Trench Isolation). Thereby, an active region is defined on the semiconductor substrate 110.

Impurities, for example, boron (B) which is a P-type impurity, for example, is ion-implanted into the element active region under the conditions of a dose amount of 3.0 × 10 ¹³ / cm ² and an acceleration energy of 300 keV. Thereby, the well 112 is formed.

  A thin gate insulating film 113 having a thickness of about 3.0 nm is formed in the active region by thermal oxidation or the like. A polycrystalline silicon film with a film thickness of about 180 nm and, for example, a silicon nitride film with a film thickness of about 29 nm are sequentially deposited on the gate insulating film 113 by CVD or the like. The silicon nitride film, the polycrystalline silicon film, and the gate insulating film 113 are processed into electrode shapes by lithography and subsequent dry etching. Thereby, the gate electrode 114 is formed on the gate insulating film 113. At the same time, a cap film 115 made of a silicon nitride film is formed on the gate electrode 114.

Using the cap film 115 as a mask, an impurity, for example, arsenic (As), which is an N-type impurity in this case, is ion-implanted under the conditions of a dose amount of 5.0 × 10 ¹⁴ / cm ² and an acceleration energy of 10 keV. Thereby, a so-called LDD region 116 is formed.

  For example, a silicon oxide film is deposited on the entire surface by CVD or the like, and the entire surface of the silicon oxide film is etched back. As a result, the silicon oxide film remains only on the side surfaces of the gate electrode 114 and the cap film 115, and the sidewall insulating film 117 is formed.

  Using the cap film 115 and the sidewall insulating film 117 as a mask, an impurity, for example, phosphorus (P), which is an N-type impurity in this case, is ion-implanted under a condition that the impurity concentration is higher than that of the LDD region 116. As a result, a source / drain region 118 overlapping the LDD region 116 is formed, and the MOS transistor 120 is formed.

Subsequently, as shown in FIG. 16B, a protective film 121, an interlayer insulating film 122, and an upper insulating film 123a of the MOS transistor 120 are sequentially formed.
Specifically, a protective film 121, an interlayer insulating film 122, and an upper insulating film 123a are sequentially formed so as to cover the MOS transistor 120. Here, as the protective film 121, a silicon oxide film is used as a material, and is deposited to a thickness of about 20 nm by a CVD method or the like. As the interlayer insulating film 122, first, for example, a stacked structure in which a plasma SiO film (film thickness of about 20 nm), a plasma SiN film (film thickness of about 80 nm), and a plasma TEOS film (film thickness of about 1000 nm) are sequentially formed is formed. After the lamination, polishing is performed by CMP until the film thickness becomes about 700 nm. Thereby, an interlayer insulating film 122a is formed. As the upper insulating film 123a, a silicon nitride film is used as a material, and is deposited to a thickness of about 100 nm by a CVD method or the like.

Subsequently, as shown in FIG. 16C, a conductive plug 136 connected to the source / drain region 118 of the MOS transistor 120 is formed. In FIG. 15C and subsequent figures, for convenience of illustration, only the structure above the interlayer insulating film 122 is shown, and illustration of the silicon semiconductor substrate 110, the MOS transistor 120, and the like is omitted.
Specifically, using the source / drain region 118 as an etching stopper, the upper insulating film 123a, the interlayer insulating film 122, and the protective film 121 are lithography and subsequent dry etching until a part of the surface of the source / drain region 118 is exposed. To process. Thereby, for example, a via hole 136a having a diameter of about 0.3 μm is formed.

For example, a Ti film and a TiN film are sequentially deposited to a film thickness of about 20 nm and a film thickness of about 50 nm so as to cover the wall surface of the via hole 136a. As a result, a base film (glue film) 136b is formed. For example, a W film is formed by a CVD method or the like so as to fill the via hole 136a through the glue film 136b. Thereafter, the W film and the glue film 136b are polished by CMP using the upper insulating film 123a as a stopper. As a result, a conductive plug 136 that fills the via hole 136a with W via the glue film 136b is formed. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

Subsequently, as shown in FIG. 16D, an orientation improving film 123b and an oxygen barrier film 123c are sequentially formed.
Specifically, in order to improve the orientation of the ferroelectric capacitor structure, for example, after depositing Ti to a thickness of about 20 nm, Ti is nitrided by rapid annealing (RTA) treatment at 650 ° C. in an N ₂ atmosphere to form TiN To do. Thereby, the conductive orientation improving film 123b is formed.
For example, TiAlN is deposited to a thickness of about 100 nm. Thereby, the conductive oxygen barrier film 123c is formed.

Subsequently, as shown in FIG. 17A, a lower electrode film 124 to be a lower electrode is formed.
Specifically, Pt is deposited by sputtering or the like, and the lower electrode film 124 is formed. As specific film formation conditions, a Pt target is used, an input power of 0.44 kW, Ar as a sputtering gas is supplied at a flow rate of 119 sccm, and film formation is performed at a film formation temperature of 350 ° C. for 180 seconds. Thus, the lower electrode film 124 made of Pt with a film thickness of about 153 nm is formed.

Subsequently, as shown in FIG. 17B, a first ferroelectric film 125a is formed as a lower layer of the capacitor film.
In particular, Pb, for example, a thickness of about 50nm~120nm by sputtering, etc. _{(Zr x, Ti 1-x} ) O 3 (0 <x <1) deposited (PZT), a first ferroelectric film 125a Form. As specific film formation conditions, a PZT target is used, an input power of 1 kW, Ar as a sputtering gas is supplied at a flow rate of 18 sccm, and film formation is performed at a film formation temperature of 50 ° C. for 112 seconds. As a result, the first ferroelectric film 125a made of PZT having a Pb amount of 1.13 and a thickness of about 70 nm is formed on the lower electrode film. The first ferroelectric film 125a is formed in an amorphous state.
As the material of the first ferroelectric film 125a, PZT to which elements such as Ca, Sr, La, Nb, Ta, Ir, W, and Ru are added can also be used.

Subsequently, as shown in FIG. 17C, the semiconductor substrate 110 is subjected to heat treatment (first heat treatment).
Specifically, as the first heat treatment, the semiconductor substrate 110 is subjected to rapid heating (RTA) using a predetermined rapid thermal processing apparatus to crystallize the first ferroelectric film 125a. As specific heat treatment conditions, Ar is supplied as an atmosphere gas at a flow rate of 1.975 slm, O ₂ is supplied at 25 sccm, a processing temperature is about 450 ° C. to 700 ° C., here 582 ° C., a processing time is 20 seconds to 300 seconds, Here, it is 90 seconds. As a result, the first ferroelectric film 125a that was in an amorphous state at the beginning of film formation is crystallized.

Subsequently, as shown in FIG. 17D, a second ferroelectric film 125b which is an upper layer of the capacitor film is formed.
More specifically, PZT is deposited to a thickness of, for example, about 5 nm to 40 nm by sputtering or the like to form the second ferroelectric film 125b. As specific film formation conditions, a PZT target is used, an input power of 1 kW, Ar as a sputtering gas is supplied at a flow rate of 18 sccm, and film formation is performed at a film formation temperature of 50 ° C. for 19 seconds. As a result, the second ferroelectric film 125b made of PZT having a Pb amount of 1.13 and a thickness of about 10 nm is formed on the first ferroelectric film 125a. The second ferroelectric film 125b is formed in an amorphous state.
As the material of the second ferroelectric film 125b, PZT to which an element such as Ca, Sr, La, Nb, Ta, Ir, W, or Ru is added can be used.

Subsequently, as shown in FIG. 18A, an SrRuO ₃ (SRO) film 119 is formed.
Specifically, the SRO film 119 is formed by depositing SRO to a film thickness of, for example, about 1 nm to 5 nm by sputtering or the like. As specific film formation conditions, an SRO target is used, an input power of 0.31 kW, Ar as a sputtering gas is supplied at a flow rate of 100 sccm, and film formation is performed at a film formation temperature of 60 ° C. for 2 seconds. Thus, the SRO film 119 having a thickness of about 1 nm is formed on the second ferroelectric film 125b. The SRO film 119 is formed in an amorphous state. By forming the SRO film on the ferroelectric capacitor film, a high polarization inversion amount in the capacitor structure can be obtained even if the capacitor film is formed thin. From the above consideration, a large amount of polarization inversion can be obtained by forming the SRO film 119 with a film thickness of about 1 nm to 5 nm.

Subsequently, as shown in FIG. 18B, a first upper electrode film 126a which is a lower layer of the upper electrode is formed.
Specifically, IrO ₂ is deposited to a film thickness of, for example, about 10 nm to 200 nm by sputtering or the like to form the first upper electrode film 126a. As specific film formation conditions, an Ir target is used, an input power is 1.91 kW, Ar is supplied as a sputtering gas at a flow rate of 100 sccm, O ₂ is supplied at 52 sccm, and film formation is performed at a film formation temperature of 20 ° C. for 9 seconds. Thus, the first upper electrode film 126a made of IrO ₂ having a thickness of about 49 nm is formed on the SRO film 119.
As a material of the first upper electrode film 126a, Ir, Ru, RuO ₂ , other conductive oxides, or the like can be used instead of IrO ₂ .

Subsequently, as shown in FIG. 18C, the semiconductor substrate 110 is subjected to heat treatment (second heat treatment).
Specifically, as the second heat treatment, the semiconductor substrate 110 is subjected to RTA treatment using a predetermined rapid heat treatment apparatus, and the second ferroelectric film 125b and the SRO film 119 are crystallized. As specific heat treatment conditions, Ar is supplied as an atmosphere gas at a flow rate of 1.98 slm, O ₂ is supplied at 20 sccm, a processing temperature is about 550 ° C. to 800 ° C., here 732 ° C., a processing time is 30 seconds to 300 seconds, Here, it is set to 118 seconds. As a result, the second ferroelectric film 125b and the SRO film 119, which were in an amorphous state at the time of film formation, are crystallized.

Subsequently, as shown in FIG. 18D, a second upper electrode film 126b which is an upper layer of the upper electrode is formed.
Specifically, IrO ₂ is deposited to a film thickness of, for example, about 25 nm to 250 nm by sputtering or the like to form the second upper electrode film 126b. As specific film forming conditions, an Ir target is used, an input power of 1.03 kW, Ar as a sputtering gas is supplied at a flow rate of 100 sccm, O ₂ is supplied at 90 sccm, and a film is formed at a film forming temperature of 20 ° C. for 28 seconds. Subsequently, Ar is supplied at a flow rate of 100 sccm and O ₂ at 90 sccm as an input power of 2.03 kW, and a film is formed at a film formation temperature of 20 ° C. for 4.4 seconds. As a result, the second upper electrode film 126b made of IrO ₂ having a thickness of about 100 nm is formed on the first upper electrode film 126a.
As a material of the second upper electrode film 126b, Ir, Ru, RuO ₂ , other conductive oxides, or the like can be used instead of IrO ₂ .

Subsequently, as shown in FIG. 19A, a TiN film 128 and a silicon oxide film 129 are formed.
Specifically, the TiN film 128 is deposited on the second upper electrode film 126b to a thickness of about 200 nm by sputtering or the like. The silicon oxide film 129 is deposited on the TiN film 128 to a thickness of about 1000 nm by, for example, a CVD method using TEOS. Here, an HDP film may be formed instead of the TEOS film. A silicon nitride film may be further formed on the silicon oxide film 129.

Subsequently, as shown in FIG. 19B, a resist mask 101 is formed.
Specifically, a resist is applied on the silicon oxide film 129, and this resist is processed into an electrode shape by lithography to form a resist mask 101.

Subsequently, as shown in FIG. 19C, the silicon oxide film 129 is processed.
Specifically, the silicon oxide film 129 is dry etched using the resist mask 101 as a mask. At this time, the silicon oxide film 129 is patterned following the electrode shape of the resist mask 101 to form a hard mask 129a. Further, the resist mask 101 is etched to reduce its thickness.

Subsequently, as shown in FIG. 19D, the TiN film 128 is processed.
Specifically, the TiN film 128 is dry etched using the resist mask 101 and the hard mask 129a as a mask. At this time, the TiN film 128 is patterned according to the electrode shape of the hard mask 129a to form the hard mask 128a. Further, the resist mask 101 is thinned by being etched during the etching. Thereafter, the resist mask 101 is removed by ashing or the like.

Subsequently, as shown in FIG. 20A, the second upper electrode film 126b, the first upper electrode film 126a, the SRO film 119, the second ferroelectric film 125b, and the first ferroelectric film 125a. The lower electrode film 124, the oxygen barrier film 123c, and the orientation improving film 123b are processed.
Specifically, the hard masks 128a and 129a are used as masks, and the upper insulating film 123a is used as an etching stopper. Then, the second upper electrode film 126b, the first upper electrode film 126a, the SRO film 119, the second ferroelectric film 125b, the first ferroelectric film 125a, the lower electrode film 124, the oxygen barrier film 123c, The orientation improving film 123b is dry-etched. Following the hard mask 128a, the second upper electrode film 126b, the first upper electrode film 126a, the SRO film 119, the second ferroelectric film 125b, the first ferroelectric film 125a, the lower electrode film 124, The oxygen barrier film 123c and the orientation improving film 123b are patterned. The hard mask 129a is etched and thinned during the etching. Thereafter, the hard mask 129a is removed by dry etching (etchback) on the entire surface.

Subsequently, as shown in FIG. 20B, a ferroelectric capacitor structure 130 is formed.
Specifically, the hard mask 128a used as a mask is removed by wet etching. At this time, the ferroelectric capacitor structure 130 in which the capacitor film 132, the SRO film 119, and the upper electrode 133 are sequentially stacked on the lower electrode 131 is formed. The lower electrode 131 is made of a lower electrode film 124. The capacitor film 132 is composed of crystallized first and second ferroelectric films 125a and 125b. The upper electrode 133 is composed of first and second upper electrode films 126a and 126b. In the ferroelectric capacitor structure 130, the lower electrode 131 is connected to the conductive plug 136 through the conductive orientation improving film 123b and the oxygen barrier film 123c. The source / drain 118 and the lower electrode 131 are electrically connected through the conductive plug 136, the orientation improving film 123b, and the oxygen barrier film 123c.

Subsequently, as shown in FIG. 20C, a protective film 102 and an interlayer insulating film 134 are formed.
Specifically, the film is deposited to a thickness of about 20 nm to 50 nm by sputtering or the like using alumina (Al ₂ O ₃ ) as a material so as to cover the entire surface of the ferroelectric capacitor structure 130. Thereby, the protective film 102 is formed. Thereafter, the protective film 102 is annealed.

An interlayer insulating film 134 is formed so as to cover the ferroelectric capacitor structure 130 via the protective film 102. Here, as the interlayer insulating film 134, a silicon oxide film is deposited to a thickness of about 1500 nm to 2500 nm by, for example, a plasma CVD method using TEOS, and then polished by CMP until the thickness becomes, for example, about 1000 nm. Form. For example, N ₂ O plasma annealing is performed after CMP for the purpose of dehydrating the interlayer insulating film 134.

Subsequently, as shown in FIG. 21A, a via hole 135a to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.
Specifically, the interlayer insulating film 134 and the protective film 102 are patterned by lithography and subsequent dry etching. As a result, a via hole 135a exposing a part of the surface of the upper electrode 133 is formed.

Subsequently, as shown in FIG. 21B, a conductive plug 135 connected to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.
More specifically, a base film (glue film) 135b is formed so as to cover the wall surface of the via hole 135a, and then a W film is formed by the CVD method or the like so as to fill the via hole 135a via the glue film 135b. Then, for example, the W film and the glue film 135b are polished by CMP using the interlayer insulating film 134 as a stopper. As a result, the conductive plug 135 filling the via hole 135a with W via the glue film 135b is formed. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

Subsequently, as shown in FIG. 22A, first wirings 145 respectively connected to the conductive plugs 135 are formed.
Specifically, the barrier metal film 142, the wiring film 143, and the barrier metal film 144 are deposited on the entire surface of the interlayer insulating film 134 by sputtering or the like. As the barrier metal film 142, for example, a Ti film and a TiN film are stacked to form a film having a thickness of about 5 nm and a thickness of about 150 nm by sputtering or the like. As the wiring film 143, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 144, for example, a Ti film is deposited to a thickness of about 5 nm and a TiN film is deposited to a thickness of about 150 nm by sputtering or the like. Here, since the structure of the wiring film 143 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing or reliability of the wiring.

  For example, after forming an SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 144, the wiring film 143, and the barrier metal film 142 are processed into a wiring shape by lithography and subsequent dry etching. To do. As a result, a first wiring 145 connected to the conductive plug 135 is formed. Instead of forming an Al alloy film as the wiring film 143, a Cu film (or Cu alloy film) may be formed by using a so-called damascene method or the like, and a Cu wiring may be formed as the first wiring 145.

Subsequently, as shown in FIG. 22B, a second wiring 154 connected to the first wiring 145 is formed.
Specifically, an interlayer insulating film 146 is formed so as to cover the first wiring 145. As the interlayer insulating film 146, a silicon oxide film is formed to a thickness of about 700 nm, a plasma TEOS film is formed to a total thickness of about 1100 nm, and then the surface is polished by CMP to a thickness of 750 nm. Form to the extent.

Next, a conductive plug 147 connected to the first wiring 145 is formed.
The interlayer insulating film 146 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 145 is exposed. Thereby, for example, a via hole 147a having a diameter of about 0.25 μm is formed. After a base film (glue film) 148 is formed so as to cover the wall surface of the via hole 147a, a W film is formed so as to fill the via hole 147a via the glue film 148 by a CVD method or the like. Then, for example, the W film and the glue film 148 are polished using the interlayer insulating film 146 as a stopper. As a result, the conductive plug 147 filling the via hole 147a with W via the glue film 148 is formed.

A second wiring 154 connected to each of the conductive plugs 147 is formed.
A barrier metal film 151, a wiring film 152, and a barrier metal film 153 are deposited on the entire surface by sputtering or the like. As the barrier metal film 151, for example, a Ti film is deposited to a thickness of about 5 nm and a TiN film is deposited to a thickness of about 150 nm by sputtering or the like. As the wiring film 152, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 153, for example, a Ti film is laminated to a thickness of about 5 nm and a TiN film is laminated to a thickness of about 150 nm by sputtering or the like. Here, since the structure of the wiring film 152 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing or reliability of the wiring.

  For example, after forming an SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 153, the wiring film 152, and the barrier metal film 151 are processed into a wiring shape by lithography and subsequent dry etching. To do. Thereby, the second wiring 154 is formed. Instead of forming an Al alloy film as the wiring film 152, a Cu film (or Cu alloy film) may be formed using a so-called damascene method or the like, and a Cu wiring may be formed as the second wiring 154.

  After that, the stack type FeRAM according to the present embodiment is formed through various processes such as formation of an interlayer insulating film and further upper layer wiring.

  As described above, according to the present embodiment, the capacitor film 132 is made thin, but a large amount of polarization inversion is secured while suppressing an increase in leakage current, and a highly reliable and strong capacitor film 132 is provided. A stacked FeRAM including the dielectric capacitor structure 130 is realized.

10, 110 Semiconductor substrate 11, 111 Element isolation structure 12, 112 Well 13, 113 Gate insulating film 14, 114 Gate electrode 15, 115 Cap film 16, 116 LDD region 17, 117 Side wall insulating film 18, 118 Source / drain region 19, 119 SRO film 20, 120 MOS transistors 21, 23, 27, 28, 102, 121 Protective films 22a, 22b, 29, 46, 122, 134, 146 Interlayer insulating films 24, 124 Lower electrode films 25a, 125a First Ferroelectric films 25b, 125b Second ferroelectric films 26a, 126a First upper electrode films 26b, 126b Second upper electrode films 30, 130 Ferroelectric capacitor structures 31, 131 Lower electrodes 32, 132 Capacitors Films 33 and 133 Upper electrodes 34, 35, 36, 47, 135, 136, 147 Conductive plugs 34a, 35a, 36a, 47a, 135a, 136a, 147a Via holes 34b, 35b, 36b, 48, 135b, 136b, 148 Glue film 37 Resist masks 37a, 37b, 38a, 38b Opening 38 Hard mask 42 , 44, 51, 53, 142, 144, 151, 153 Barrier metal film 43, 52, 143, 152 Wiring film 45, 145 First wiring 54, 154 Second wiring 101 Resist mask 123a Upper insulating film 123b Orientation Improvement film 123c Oxygen barrier film 128 TiN film 128a, 129a Hard mask 129 Silicon oxide film

Claims (6)

Forming a first electrode film serving as a lower electrode above the semiconductor substrate;
Forming a first dielectric film on the first electrode film;
Applying a first heat treatment to the semiconductor substrate;
Forming an amorphous second dielectric film on the first dielectric film;
Forming an amorphous SrRuO ₃ film on the second dielectric film to a thickness of 1 nm to 4 nm;
Forming a second electrode film on at least a part of the upper electrode on the SrRuO ₃ film;
As the heat treatment subsequent to the first heat treatment in a state in which the SrRuO ₃ film in the amorphous state and the second electrode film are sequentially formed on the second dielectric film in the amorphous state, the semiconductor Applying a second heat treatment to the substrate;
A first etching step of etching the first dielectric film, the second dielectric film, the SrRuO ₃ film, and the second electrode film;
Forming a first protective insulating film so as to cover the entire surface;
Applying a third heat treatment to the semiconductor substrate;
A second etching step of etching only a portion of the first electrode film and the first protective insulating film on the first electrode film;
Forming a second protective insulating film so as to cover the entire surface;
Performing a fourth heat treatment on the semiconductor substrate. A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first dielectric film and the second dielectric film are formed of a ferroelectric material. The first dielectric film and the second dielectric film are made of Pb (Zr _x , Ti _1-x ) O ₃ (0 <x <1), or Pb (Zr _x , Ti _{1− 3. The} method of manufacturing a semiconductor device according to claim 2, wherein _x ) is formed of O3.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the second dielectric film has a thickness smaller than that of the first dielectric film. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the SrRuO ₃ film is formed by a sputtering method.   The method for manufacturing a semiconductor device according to claim 1, wherein the second electrode film contains Ir.

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