JP2015213152A - Interposer frame with polymer matrix and method of fabrication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interposer frame with a polymer matrix, achieving reduced size in a package, shortening a connection length to the outside, and having reduced cost and increased reliability, and a method of fabrication.SOLUTION: An array of chip sockets 12 is defined by an organic matrix framework 16 surrounding sockets 12 passing through the organic matrix framework 16 and further comprising a grid of metal vias 14 passing through the organic matrix framework 16. A panel includes an array of chip sockets 12, and each chip socket 12 is surrounded and defined by an organic matrix framework 38 including a grid of copper vias 14 passing through the organic matrix framework 16. The panel includes at least a first region with sockets 12 having a set of dimensions for receiving one type of chip 35 and a second region with sockets 12 having another set of dimensions for receiving another type of chip 35.

Description

This application is a continuation-in-part of US patent application Ser. No. 14 / 249,282 (Title: “Method for Fabricating Embedded Chips”) filed on April 9, 2014. The aforementioned U.S. Patent Application No. 14 / 249,282 is incorporated herein by reference in its entirety.

  The present invention relates to chip packaging, and particularly to embedded chips.

  Increasing demands for downsizing of electronic components, which are becoming more complex, are increasingly integrating consumer electrical devices such as computing devices and communication devices. Therefore, a need has arisen for a support structure such as an IC substrate and an IC interposer having a plurality of high-density conductive layers and vias that are electrically insulated from each other by a dielectric.

  Common requirements for such a support structure are reliability, adequate electrical performance, thinness, stiffness, flatness, good heat dissipation, and competitive price.

  Among the various ways to achieve such requirements, one widely practiced manufacturing technique for creating interconnect vias between layers is to use a laser and pass through the next laid dielectric substrate, A hole is drilled through to the last metal layer, and then a metal, usually copper, is deposited and filled into the hole by a plating technique. This via creation method may be referred to as “drill & fill”, and the via created thereby may also be referred to as “drill & fill via”.

  The drill and via method has a number of disadvantages. Since each via needs to be drilled separately, the processing speed is limited and the cost of producing sophisticated multi-via IC substrates and interposers is very high. For large arrays, it is difficult to produce high quality vias of various sizes and shapes in close proximity to each other in a high density with a drill and fill method. Also, the laser drilled via has a sidewall that is rough across the thickness of the dielectric and tapers inwardly. This taper reduces the effective diameter of the via. In particular, ultra-small vias can adversely affect electrical contact with the previous conductive metal layer, resulting in reliability problems. Furthermore, the sidewalls are particularly rough when the perforated dielectric is a composite material comprising glass or ceramic fibers in a polymer matrix, and this roughness can lead to stray inductance.

  The filling process of the drilled via hole is usually performed by electrolytic copper plating. Electroplating in the perforations can lead to dimple formation, in which case a small crater appears at the end of the via. Alternatively, if the via channel is filled with more copper than the via channel can hold, overfill can occur, resulting in a hemispherical top surface that protrudes over the surrounding material. Both dimple formation and overfill tend to cause problems when stacking vias as needed when manufacturing high density substrates and interposers. Also, it will be appreciated that large via channels are difficult to fill uniformly, especially when close to small vias within the same interconnect layer of an interposer or IC substrate design.

  The acceptable size range and reliability have improved over time. Nevertheless, the disadvantages described above are inherent in the drill and fill technique and are expected to limit the range of possible via sizes. It will also be noted that laser drilling is optimal for creating circular via channels. Although slot-shaped via channels can theoretically be made by laser milling, in practice the range of geometries that can be made is somewhat limited, and vias in a given support structure are In general, it is cylindrical and substantially identical.

  Making vias by drill and fill is expensive and it is difficult to fill via channels created by drill and fill evenly and consistently with copper using a relatively cost-effective electroplating process It is.

Vias drilled in composite dielectrics are practically limited to a minimum diameter of 60 × 10 ⁻⁶ m, but even so, due to the associated laser ablation process, the nature of the composite material to be drilled As a result, not only a significant taper shape but also a rough side wall is damaged.

  In addition to the other drawbacks associated with laser drilling described above, for drill and fill technology, different speeds of via channels are created when drilling different sized via channels and then filling with metal to create different sized vias. Has a further disadvantage that it is difficult to make vias of different diameters in the same layer. As a result, the technique of depositing different sized vias cannot be optimized simultaneously, exacerbating the typical problem of dimple formation or overfill that is characteristic of drill and fill techniques.

  Another solution to overcome many of the shortcomings associated with drill and fill is to create a via by depositing copper or other metal on a pattern made with photoresist, a technique known as “pattern plating”. There are methods to make vias using them.

  In pattern plating, a seed layer is first deposited. A photoresist layer is then deposited thereon and then exposed to create a pattern and selectively removed to create a trench that exposes the seed layer. Via posts are created by depositing copper in the photoresist trench. Thereafter, the remaining photoresist is removed, the seed layer is etched away, and a dielectric, typically a polymer-impregnated glass fiber mat, is laminated over and around the via post. Various techniques and processes are then used to planarize the dielectric, remove a portion of the dielectric, and expose the end of the via post to build up the next metal layer on the dielectric. Can be electrically connected to ground. Subsequent layers of metal conductors and via posts may be deposited thereon by repeating this process to build up the desired multilayer structure.

  In another but closely related technique, hereinafter known as “panel plating”, a continuous layer of metal or alloy is deposited on the substrate. A photoresist layer is deposited on the edge of the substrate and the pattern is developed therein. The developed photoresist pattern is stripped to selectively expose the underlying metal, which can then be etched away. Undeveloped photoresist prevents the underlying metal from being etched away, leaving an upstanding feature and via pattern.

  After stripping the undeveloped photoresist, a dielectric, such as a polymer-impregnated glass fiber mat, can be laminated around and on the upstanding copper features and / or via posts. Subsequent to planarization, subsequent layers of metal conductors and via posts may be deposited thereon by repeating this process to build up the desired multilayer structure.

  Via layers created by the pattern plating or panel plating methods described above are commonly known as copper “via posts” and feature layers.

  Of course, the general direction of driving the development of microelectronics is aimed at producing increasingly smaller, thinner, lighter, stronger and more reliable products. Due to the use of thick, cored interconnects, ultra-thin products cannot be made. In order to create increasingly dense structures in an interconnect IC substrate or “interposer”, more and more layers of increasingly smaller connections are required.

  If the plated and laminated structure is deposited on copper or other suitable sacrificial substrate, the substrate can be etched away leaving a free-standing, coreless laminated structure. Additional layers may be deposited on the side previously bonded to the sacrificial substrate, thereby allowing double-sided build-up, thereby reducing warpage and helping to obtain planarity.

  One flexible technique for creating high density interconnects is a pattern-plated or panel-plated multilayer structure consisting of metal vias or via post features having various geometries and shapes within a dielectric matrix. There is a technology to build up. The metal may be copper and the dielectric may be a film polymer or a fiber reinforced polymer. Generally, a polymer having a high glass transition temperature (Tg), such as polyimide or epoxy, is used. These interconnects may be cored or coreless and may include cavities for stacking components. The interconnect may have odd or even layers and the via may be non-circular. The enabling technology is described in a previous patent granted to Amitec-Advanced Multilayer Interconnect Technologies.

  For example, US Pat. No. 7,682,972, entitled “Advanced Multilayer Coreless Support Structures and Method for the Fabrication” granted to Hurwitz et al., Entitled “Advanced Multilayer Coreless Support Structure and Method for Fabrication of the Structure”. Describes a method of making a free-standing film including a via array in a dielectric for use as a precursor in constructing an upper electronic support structure. The method includes creating a film of conductive vias within a dielectric perimeter on a sacrificial carrier and separating the film from the sacrificial carrier to form a free standing stacked array. Electronic substrates based on such free-standing films can be formed by thinning and planarizing the stacked array and then terminating the vias. This publication is incorporated herein by reference in its entirety.

  In US Pat. No. 7,669,320, entitled “Coreless cavity substrates for chip packaging and their fabrication,” granted to Hurwitz et al. A method of making an IC support that supports a first IC die connected in series; the IC support includes a stack of alternating layers of copper features and vias within an insulating perimeter, the first IC die being attached to the IC support The second IC die can be bonded into the cavity within the IC support, and the cavity is formed by etching away the copper base and selectively etching away the build-up copper. This publication is incorporated herein by reference in its entirety.

  U.S. Pat. No. 7,635,641, entitled “Integrated Circuit Support Structures and Ther Fabrication” granted to Hurwitz et al. Describes a method for fabricating electronic substrates. The method includes the following steps: (A) selecting a first base layer; (B) depositing a first etchant barrier layer on the first base layer; (C) alternating conductivity. Building up a first half stack of layers and insulating layers, wherein the conductive layers are interconnected through the insulating layer by vias; (D) applying a second base layer to the first half stack (E) applying a protective coating of photoresist to the second base (F) removing the first base layer by etching; (G) removing the protective coating of the photoresist; (H) removing the first etchant barrier layer; (I) alternating. Building up a second half stack of conductive layers and insulating layers, wherein the conductive layers are interconnected through the insulating layer by vias, the second half stack being substantially symmetrical with respect to the first half stack. (J) applying an insulating layer over the second half stack of alternating conductive layers and insulating layers; (K) removing the second base layer; and (L) the stack. Terminating the substrate by exposing the end of the via on the outer surface of the substrate and adding the termination to the substrate. This publication is incorporated herein by reference in its entirety.

  The via post technology described in US Pat. No. 7,682,972, US Pat. No. 7,669,320 and US Pat. No. 7,635,641 is a large quantity because a large number of vias are electroplated simultaneously. Suitable for production. As described above, the effective minimum diameter of current drill and fill vias is approximately 60 microns. In contrast, via post technology using photoresist and electroplating provides much higher density vias. Via diameters can be as small as 30 microns, and vias of various geometric shapes and shapes can be made simultaneously in the same layer.

  Over time, it is anticipated that both drill and fill techniques and via post deposition will allow the creation of substrates with smaller and denser vias and features. Nevertheless, it seems that competitiveness can be maintained by developing via-post technology.

  The substrate allows the chip to be interlocked with other components. In order to allow electronic communication between the chip and the substrate, the chip needs to be bonded to the substrate by an assembly process that provides a reliable electronic connection.

  By embedding the chip in the external interposer, the chip package can be reduced and the connection to the outside can be shortened, and the cost can be reduced by simpler manufacturing without the assembly process of the die to the substrate Reliability may be improved.

  In essence, the concept of embedding active components such as analog, digital and MEMS chips involves the construction of a chip support structure or substrate with vias around the chip.

  One method for obtaining an embedded chip is to produce a chip support structure on a chip array on a wafer where the circuit of the support structure is larger than the die unit size. This is known as FOWLP (Fan Out Wafer Layer Packing). Although the size of silicon wafers is increasing, due to the expensive material set and manufacturing process, the diameter size is still limited to 12 inches, thereby limiting the number of FOWLP units on the wafer. In fact, although 18 inch wafers are being considered, the required investment, material set and equipment are still unknown. By limiting the number of chip support structures that can be processed at a time, the unit price of FOWLP becomes high, and it becomes too expensive for markets with extremely intense price competition such as wireless communication, home appliances, and automobile markets.

  FOWLP also has performance limitations because the thickness of metal features provided on a silicon wafer as a fan-out or fan-in circuit is limited to a few microns. Thereby, the problem regarding an electrical resistance comes out.

  Another fabrication means involves partitioning the wafer, separating the chips, and embedding the chips in a panel of dielectric layers having copper interconnects. One advantage of this alternative is that the panel can be made into a much larger panel with a much larger number of chips embedded in a single step. As an example, for example, a 12-inch wafer can process 2,500 FOWLP chips measuring 5 mm x 5 mm in one step, whereas the current panel used by the applicant, Zhuhai Access, Inc. Is 25 inches × 21 inches, and 10,000 chips can be processed at one time. The price for processing such a panel is considerably cheaper than that for wafer processing, and the processing amount per panel is four times higher than the processing amount for wafers, so the unit price can be greatly reduced, resulting in the opening of a new market.

  In both technologies, the line spacing and track widths used in the industry are shrinking over time, the standard for panels is 15 microns to 10 microns and the standard for wafers is 5 microns to 2 microns. is decreasing.

  There are many advantages of embedding. First-level assembly costs such as wire bonding, flip chip or SMD (Surface Mount Device) soldering are eliminated. Electrical performance is improved because the die and substrate are joined together seamlessly in a single product. Packaged dies become thinner and improve form factor, and the top surface of the embedded die package becomes free for other uses, including stacked die technology and PoP (Package on Package) technology. .

  In both FOWLP and panel-based embedded die technologies, chips are packaged as an array (on a wafer or panel) and, once fabricated, separated by dicing.

  Embodiments of the present invention address the fabrication of embedded chip packages.

  Embodiments of the present invention address a polymer frame having chip sockets for packaging chips.

  A first aspect provides an array of chip sockets defined by a framework, wherein the framework includes a polymer matrix and includes an array of metal vias through the framework of the polymer matrix. About doing.

  In general, each chip socket is surrounded by a polymer matrix frame containing copper vias through the framework.

  Generally, the framework further includes a glass fiber reinforcement in the polymer matrix.

  In some embodiments, the metal via is a via post.

  In some embodiments, each via has a width in the range of 25 microns to 500 microns.

  In some embodiments, the grid of metal vias through the organic matrix framework includes a plurality of via layers.

  In some embodiments, the frame around the at least one socket includes a continuous coil of elongated via posts.

  In some embodiments, the elongated via post continuous coil spans multiple layers.

  In some embodiments, each via is cylindrical and has a diameter range of 25 microns to 500 microns.

  In some embodiments, adjacent chip sockets have different dimensions.

  In some embodiments, adjacent chip sockets have different sizes.

  In some embodiments, adjacent chip sockets have different shapes.

  A second aspect is a panel that includes an array of chip sockets, each of which relates to a panel that is surrounded and defined by a polymer matrix framework that includes a grid of copper vias through the polymer matrix framework. Includes at least one region having a socket having a first dimension set for receiving one type of chip and another region having a socket having a second dimension set for receiving another type of chip. .

  Optionally, the at least one via is non-cylindrical.

  Optionally, at least one via is elongated.

  In some embodiments, the frame includes two or more via layers.

  In some embodiments, the elongated via is a coil.

  Optionally, the at least one via is a coaxial via.

  Optionally, the frame further comprises a glass fiber reinforcement in the polymer matrix.

  Preferably, the frame further comprises a fabric of glass fiber bundles in a polymer matrix.

  In some embodiments, the frame includes an array of two different sockets for two different dies in adjacent sockets.

  Optionally, the different sockets have different shapes.

  Optionally, the different sockets have different sizes.

A fourth aspect relates to providing a method of making an array of chip sockets surrounded by an organic matrix framework, the method comprising:
Obtain a sacrificial carrier;
Laying a layer of photoresist and patterning with a grid of copper vias;
Plating copper on the grid;
Laminated with a polymer dielectric;
Thin and flatten to expose the end of the copper via;
Removing the carrier; and machining the chip socket in a polymer dielectric.

  Generally, the carrier is a copper carrier that is removed by dissolving copper.

  Preferably, the method further includes applying an etch resistant layer on the carrier prior to depositing the copper via.

  In one embodiment, the etch resistant layer includes nickel.

  Optionally, the planarized polymer dielectric with the copper via ends exposed is protected with an etch resistant material while the copper carrier is etched away.

  Optionally, the etch resistant material is a dry film photoresist.

  In some embodiments, the copper seed layer is electroplated on nickel.

  In some embodiments, the copper seed layer is electroplated prior to depositing the nickel barrier layer.

  In some embodiments, the grid is made by punching out the socket leaving the framework.

  In some embodiments, the grid is made by machining the socket with a CNC leaving the framework.

A variation of a method of making an array of chip sockets surrounded by an organic matrix framework, the method comprising:
Obtain a sacrificial carrier;
Laying a layer of photoresist and patterning with a grid of copper vias and a chip socket array;
Plating copper on grids and arrays;
Laminated with a polymer dielectric;
Thin and planarize to expose copper via ends and array;
Shielding the end of the copper via;
Lysing the array;
Removing the carrier.

  In some embodiments, the via post is an elongated via post and the chip socket includes a plurality of via posts separated by a feature layer.

  Optionally, the plurality of elongated via posts provide at least one continuous coil around at least one chip socket of the frame.

  Preferably, the at least one socket is formed by the organic frame and by a multi-layer metal structure that is embedded in the organic frame and includes a plurality of extending via post layers, each pair of adjacent via post layers by the feature layer. Separated and enclosed so that the multilayer metal structure includes a continuous coil.

  In order to make the present invention more understandable and to show how the present invention can be implemented, reference will now be made, by way of example only, to the accompanying drawings.

  Referring now in particular to the drawings in detail, the illustrated details are only examples and are for the purpose of providing only a useful description of the preferred embodiments of the present invention, and are most useful for the principles and conceptual aspects of the present invention. Emphasize the points that have been presented to provide what seems to be an easily understandable explanation. In this regard, the details of the present invention are not shown in more detail than is required for a basic understanding of the present invention; Will be made clear to those skilled in the art. The attached figure is as follows.

FIG. 6 is a schematic illustration of a portion of a polymer or composite grid having sockets therein for chips and also having through vias around the sockets. FIG. 6 is a schematic diagram of a panel used to fabricate an embedded chip surrounded by through vias and shows how some panels, such as one frame, may have sockets for different types of chips. ing. 2 is a schematic illustration of a portion of the polymer or composite framework of FIG. 1 with the chip in each socket held by a polymer or composite such as a molding compound, for example. FIG. 4 is a schematic illustration of a cross section of a portion of the framework, showing embedded chips held in each socket with a polymer material, and also showing through vias and pads on both sides of the panel. 1 is a schematic illustration of a cross section of a die including an embedded chip. 1 is a schematic illustration of a cross section of a package containing different die pairs in adjacent sockets. FIG. 6 is a schematic bottom view of a package as shown in FIG. 2 is a flowchart showing manufacturing steps for making a polymer or composite panel including an array of through vias. 6 is a schematic diagram relating to an intermediate substrate obtained after step 8 (a) of the flowchart 8; 6 is a schematic diagram relating to an intermediate substrate obtained after step 8 (b) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (c) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (d) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (e) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (f) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (g) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (h) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (i) of the flowchart 8; 6 is a schematic diagram relating to an intermediate substrate obtained after step 8 (j) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (k) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (l) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (m) of the flowchart 8; 10 is a schematic diagram relating to an intermediate substrate obtained after step 8 (n) of the flowchart 8; FIG. 5 is a flow chart showing what drill-fill technique is required to punch a socket and create a plated through hole. 10 is a schematic diagram relating to an intermediate substrate obtained after step 9 (a) of the flowchart 9; 6 is a schematic diagram relating to an intermediate substrate obtained after step 9 (b) of the flowchart 9; 6 is a schematic diagram relating to an intermediate substrate obtained after step 9 (c) of the flowchart 9; 6 is a schematic diagram relating to an intermediate substrate obtained after step 9 (d) of the flowchart 9; 6 is a schematic diagram relating to an intermediate substrate obtained after step 9 (e) of the flowchart 9; It is a schematic diagram of a frame with a three-layer coil of elongated vias embedded in it, showing the flexibility of the manufacturing technique and how it can be used to make embedded transformers, etc. ing.

In the following description, a support structure consisting of metal vias in a dielectric matrix, in particular copper via posts in a polymer matrix such as polyimide, epoxy or BT (bismaleimide / triazine) or mixtures thereof reinforced with glass fibres. To be considered.

  U.S. Patent No. 7,682,972, U.S. Patent No. 7,669,320 and U.S. Patent No. 7,635,641 to Hurwitz et al., Which are incorporated herein by reference, A feature of the Access photoresist and pattern or panel plating and lamination techniques is that large panels can be made that contain a very large array of substrates with a very large number of via posts. Such a panel is substantially smooth.

  A further feature regarding the Access technology is that vias made by electroplating using photoresist can be narrower than vias made by drill and fill. Currently, the narrowest drill and fill via is about 60 microns. By electroplating using photoresist, resolutions of less than 50 microns or a minimum of 30 microns can be achieved. It is difficult to couple an IC to such a substrate. One method for flip chip bonding is to provide a copper pad that is flush with the dielectric surface. Such a method is described in the inventor's US patent application Ser. No. 13 / 912,652.

  All methods of attaching the chip to the interposer are expensive. Wire bonding and flip-chip technology are expensive and can fail if the connection is broken.

  Referring to FIG. 1, a portion of an array 10 of chip sockets 12 defined by a framework 16 containing a polymer matrix 14 and an array of metal vias 14 through the polymer matrix framework 16 is shown.

  The array 10 may be part of a panel that includes an array of chip sockets, each chip socket being surrounded and defined by a polymer matrix framework that includes a grid of copper vias through the polymer matrix framework.

  Each chip socket 12 is therefore surrounded by a polymer frame 18 and a number of through copper vias through the frame 18 are disposed around the socket 12 '.

  The frame 18 may be a polymer that is applied as a polymer sheet, or may be a glass fiber reinforced polymer that is applied as a prepreg. More details will be described later with reference to FIGS. 8 and 9 where the manufacturing method is described.

  Referring to FIG. 2, the panel 20 of the applicant, Zhuhai Access, is generally divided into 2 × 2 arrays of blocks 21, 22, 23, 24, which are divided into horizontal bars 25, vertical bars 26. They are separated from each other by a main frame comprising an outer frame 27. Each block includes an array of chip sockets 12 (FIG. 1). Given a 5mm x 5mm chip socket and an Access 21 "x 25" panel, this manufacturing technology allows 10,000 chips to be packaged on each panel. In contrast, if a chip package is fabricated on a 12-inch wafer, the largest wafer currently used in the industry, only 2500 chips can be processed at one time, so the scale advantage of fabricating a large panel But you will understand.

  However, a panel suitable for this technology may be somewhat wider in size. Generally, the panels are about 12 inches x 12 inches to about 24 inches x 30 inches. Among the standard sizes currently in use are 20 "x 16", 20.3 "x 16.5" and 24.7 "x 20.5".

  It is not necessary to arrange chip sockets 12 of the same size in all blocks of the panel 20. For example, in the schematic diagram of FIG. 2, the chip socket 28 of the upper right block 22 is larger than the chip sockets 29 of the other blocks 21, 23, 24. Also, not only can one or more blocks 22 be used for different sized sockets that accept different sized chips, but any sub-array of any size creates any particular die package. Can be used to make a small series of short die packages even at high throughput, and different die packages can be processed simultaneously for a particular customer, Or different packages can be made for different customers. Accordingly, the panel 20 has at least one region 22 having a socket 28 having a first dimension set for receiving one type of chip, and another having a socket 29 having a second dimension set for receiving another type of chip. One region 21 can be included.

  As described above with reference to FIG. 1, each chip socket 12 (28, 29 in FIG. 2) is surrounded by a polymer frame 18 and each block (21, 22, 23, 24-FIG. 2) includes An array of sockets 28 (29) is arranged.

  Referring to FIG. 3, a chip 35 can be placed in each socket 12 and the space around the chip 35 can be filled with a polymer 36 that can be used to make the frame 16. It may or may not be the same polymer used. The polymer 36 may be, for example, a molding compound. In some embodiments, the matrix of filler polymer 36 and the matrix of frame 16 may use similar polymers, but may also be used with different reinforcing fibers. For example, the frame may include reinforcing fibers while the polymer 36 used to fill the socket may not include fibers.

  Typical die sizes can be anywhere from about 1.5 mm x 1.5 mm to about 31 mm x 31 mm, and the socket is slightly larger to accommodate the desired die with clearance. The interposer frame thickness should be at least as deep as the die, preferably 10 to 100 microns thick. Generally, the depth of the frame is a die thickness of 20 microns.

  As a result of embedding the chips 35 in the socket 12, each individual chip is surrounded by a frame 38 having vias 14 through the frame disposed around the edge of each die.

  Via 14 is made as a via post by using selective etching after either pattern plating or panel plating using the Access via post technology, and then using a polymer film, or To add stability, a prepreg consisting of woven glass fiber bundles may be used in the polymer matrix and laminated with a dielectric. In one embodiment, this dielectric is Hitachi 705G. In another embodiment, MGC832NXA NSFLCA is used. In the third embodiment, Sumitomo GT-K may be used. In another embodiment, Sumitomo LAZ-4785 series films are used. In another embodiment, the Sumitomo LAZ-6785 series is used. Another material is HBI and Zaristo-125 from Taiyo Ink Manufacturing Co., Ltd.

  Alternatively, the vias may be made using what is commonly known as drill-fill technology. First, a polymer or fiber reinforced polymer matrix is made and then, after curing, drilled mechanically or by laser drilling. Thereafter, the drilled holes may be filled with copper by electroplating.

  There are many advantages to making vias using via posts rather than drill-fill techniques. In via post technology, all vias can be made simultaneously, so holes are drilled individually, whereas via post technology is faster. Also, the drilled via is cylindrical, whereas the via post can have any shape. In practice, all drill-fill vias are the same diameter (within tolerance), whereas via posts can have different shapes and sizes. Also, to enhance rigidity, preferably the polymer matrix is generally fiber reinforced with a woven bundle of glass fibers. The polymer prepreg fibers, when placed on an upstanding via post and cured, are characterized by the sides being smooth and vertical. However, drill-fill vias are generally somewhat tapered and when the composite is drilled; generally the surface becomes rough and introduces stray inductance that causes noise.

  Generally, vias 14 range from 25 microns to 500 microns wide. If cylindrical, as required for drill-fill and as is typical for via posts, the diameter of each via can range from 25 microns to 500 microns.

  Still referring to FIG. 3, after making the polymer matrix framework 16 by embedding vias, the socket 12 may be made by CNC or stamping. Alternatively, the sacrificial copper block may be deposited using either panel plating or pattern plating. If the copper via post 14 is selectively shielded using, for example, a photoresist, such copper block can be etched away to create the socket 12.

  The polymer framework 38 of the socket array having vias 14 in the frame 38 around each chip socket 12 includes a plurality of chip packages and a built up multilayer chip package such as a “PoP (Package-on-Package)” array. Can be used to create individual multiple chip packages.

  Once the chip 35 is placed in the socket 12, the chip 35 can be secured in place using a polymer 36 such as a molding compound, dry film or prepreg.

  Referring to FIG. 4, the copper routing layers 42 and 43 can be formed on one side or both sides of the framework 40 in which the chip 35 is embedded. Generally, the chip 35 is a flip chip and is coupled to a pad 43 that extends outward from the edge of the chip 35. Through vias 14, the top pad 42 can bond additional layers of the chip for a PoP package or the like. Of course, in essence, the upper and lower pads 42, 43 allow for further via posts and routing layers to be built up to create more complex structures.

  A dicing tool 45 is shown. Of course, the array of chips 35 packaged in the panel 40 is easily diced into individual chips 48, as shown in FIG.

  Referring to FIG. 6, in some embodiments, adjacent chip sockets may have different dimensions, including different sizes and / or different shapes. For example, the processor chip 35 can be disposed in one socket and coupled to a memory chip 55 disposed in an adjacent socket. Thus, the package may include two or more chips or different chips.

  The pads 42 and 43 can be coupled to a chip via BGA (Ball Grid Array) or LGA (Land Grid Array). With current state of the art, via posts can be about 130 microns long. If the chips 35, 55 are thicker than about 130 microns, it may be necessary to stack one via on top of another. Via stacking techniques are known and described, among others, in co-pending Hurwitz et al. US patent application 13 / 482,099 and US patent application 13 / 483,185.

  Referring to FIG. 7, a die package 48 including a die 55 in a polymer frame 16 is shown from below, the die 55 is surrounded by the frame 16, and a through via 14 penetrates the frame 16 and dies. 55 is provided around the outer periphery. The die is placed in the socket and held in place by the second polymer 36. The frame 16 is typically made from a fiber reinforced prepreg for stabilization. The second polymer 36 may be a prepreg, but may be a polymer film or a molding compound. Generally, as shown, the through via 14 is simply a cylindrical via, but may have different shapes or sizes. Some ball grid arrays of solder balls 57 on chip 55 are connected to through vias 14 in a fan-out configuration by pads 43. As shown, there may be additional solder balls that are directly bonded to the substrate under the chip. In some embodiments, at least one of the through vias is a coaxial via for communication and data processing. In other embodiments, the at least one via is a transmission line. Techniques for manufacturing coaxial vias are described, for example, in co-pending US patent application Ser. No. 13 / 483,185. Techniques for making transmission lines are presented, for example, in US patent application Ser. No. 13 / 483,234.

  In addition to providing contacts for stacking chips, the through vias 14 around the chip can be used to isolate the chip from its periphery and to provide a Faraday shield. Such shielding vias are coupled to pads that allow the shielding vias to be interconnected on the chip to provide a shield for the chip.

  One or more through vias may be present surrounding the chip, with the inner row being used for signal transmission and the outer row being used for shielding. The outer row can be bonded to a solid copper block made on the chip, so that the block can function as a heat sink to dissipate the heat generated by the chip. Different dies can also be packaged in this way.

  The embedded chip technology with frames with through vias described herein is particularly suitable for analog processing because of the short contacts and the relatively small number of contacts per chip.

  Of course, this technique is not limited to IC chip packages. In some embodiments, the die includes a component selected from the group consisting of a fuse, a capacitor, an inductor, and a filter. Techniques for manufacturing inductors and filters are described in co-pending U.S. Patent Application No. 13 / 962,316 to Hurwitz et al.

  Referring to FIG. 8 and FIGS. 8 (a) to 8 (l), the method of making an array of chip sockets surrounded by an organic matrix frame includes the following steps: Obtaining a sacrificial carrier 80-8 (A).

  Optionally, a copper seed layer 82 is applied over the copper barrier-8 (b). An etch resistant layer 84 is applied on the carrier −8 (c), and the etch resistant layer is typically made of nickel and is usually deposited by a physical vapor phase method such as sputtering. Alternatively, the etch resistant layer may be deposited, for example, by electroplating or electroless plating. Other candidate materials include tantalum, tungsten, titanium, titanium-tungsten alloy, tin, lead, tin-lead alloy, all of which may be sputtered and tin and lead may be electroplated or non-plated. The barrier metal layer can be electroplated and is typically 0.1 to 1 micron thick. (The material of each candidate barrier layer is later removed with a suitable solvent or plasma etching conditions.) After applying the barrier layer, an additional copper seed layer 86 is applied-8 (d). The copper seed layer is typically about 0.2-5 microns thick.

  Steps 8 (b) -8 (d) ensure that the barrier layer adheres well to the substrate, adheres and grows the vias well, and then removes the substrate by etching without damaging the vias. Preferred to enable. The best results include these steps, but these steps are optional and one or more steps may not be used.

  A photoresist layer 88 is then applied—step (e), FIG. 8 (e), patterned with a copper via pattern— 8 (f). Thereafter, copper 90 is plated in a pattern −8 (g), and the photoresist 88 is peeled −8 (h). Upright copper vias 90 may be laminated with a polymer dielectric 92 -8 (i), which may be a prepreg of a fiber reinforced polymer matrix. The stacked via array is thinned and planarized to expose the end of the copper via-8 (j). Thereafter, the carrier is removed.

  Optionally, but preferably, the planarized polymer dielectric with exposed copper via ends is protected by applying an etch-resistant material 94 such as a photoresist or dielectric film −8 (k), after which Copper carrier 80 is etched away -8 (l). Generally, the carrier is a copper carrier 80 that is removed by dissolving copper. Ammonium hydroxide or copper chloride can be used to dissolve the copper.

  Thereafter, the barrier layer may be etched away -8 (m) and the etch inhibitor layer 94 may be removed -8 (n).

  Although not described herein, of course, upright copper vias are made by panel plating, and excess copper can be selectively etched away to leave the vias. Alternatively, in practice, the socket can be made by selectively etching away a portion of the copper panel while shielding the via.

  Via post technology is preferred, but drill and fill technology can also be used. Referring to FIG. 9, in another alternative method, a carrier consisting of a copper clad laminate (CCL) 100 is obtained-9 (a). The thickness of the CCL is several tens of microns to several hundreds of microns. A typical thickness is 150 microns. Hole 102 is drilled through the CCL-9 (b). The diameter of the hole 102 can be several tens of microns to several hundreds of microns. Generally, the hole diameter is 150 microns.

  Next, the through hole is plated to create a plated through hole 104-9 (c).

  The copper clad laminate 100 is then polished or etched to remove the surface copper layers 106, 108 and leave the laminate 110 with the plated through-hole (Pth) copper vias 104 (d).

  Thereafter, using CNC or stamping, a socket 112 is made through the laminate that receives the chip-9 (e).

  As mentioned above, electroplated vias deposited in photoresist using a suitable via post technique can have any shape or size. Further, the frame can include two or more via layers separated by pads. Referring to FIG. 10, this flexibility allows a copper 200 coil to be embedded, which typically includes via posts and is embedded around a cavity 204 within a dielectric frame 202. By way of example only, the illustrated coil 200 has three layers of extending via posts 206, 207, 208, and in some cases, via posts are deposited on the feature layer. Layers 206, 207, 208 are coupled together by vertical elements 209, 210. The vertical elements 209, 210 may be via posts or feature layers, or via posts on feature layers. The coil 200 can provide a Faraday shield for an embedded chip, for example. If the iron core is deposited in a socket 204 having a frame 202 containing a coil 200, a transformer can be made. Thus, the polymer frame with copper vias of the present invention makes it possible to make any type of frame with copper vias in it to embed various components.

  In practice, the copper via post coil 200 will typically include elongated via posts coupled together by feature layers or elongated feature layers coupled by via posts. In general, via post layers alternate with feature layers, and coils need to be built up layer by layer.

  Accordingly, those skilled in the art will appreciate that the invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention is defined by the appended claims and, in addition to both the various feature combinations and subcombinations described above, those of ordinary skill in the art will recognize upon reading the foregoing description. Modifications and modifications are also included.

  In the claims, the word “comprise” and variations thereof, “comprises”, “comprising”, etc., not only include the listed components, but also generally It means that the component is not excluded.

10 Array 12 Chip socket 14, 210 Via 16, 18, 38, 202 Frame 20 Panel
21, 22, 23, 24 Block 25 Horizontal bar 26 Vertical bar 27 External frame 28, 29 Chip socket 35, 55 Chip 36 Polymer 40 Framework 42, 43 Routing layer 45 Dicing tool 48 Die package 57 Solder ball 80 Copper carrier 82 seed layer 84 etch resistant layer 86 further copper seed layer 88 photoresist layer 90 copper via 92 polymer dielectric 94 etch inhibitor layer 100 copper clad laminate 102 hole 104 through hole 106, 108 surface copper layer 110 laminate 112, 204 Socket 200 Coil 206, 207, 208 Via post 209, 210 Vertical element

Claims (28)

  An array of chip sockets defined by the organic matrix framework that surrounds the sockets through the organic matrix framework and further includes a grid of metal vias through the organic matrix framework.   The array of chip sockets of claim 1, wherein each chip socket is surrounded by an organic matrix frame that includes copper vias through the frame.   The array of chip sockets of claim 1, wherein the organic matrix framework further comprises a glass fiber bundle.   The array of chip sockets of claim 1, wherein the copper via is a via post.   The array of chip sockets of claim 1, wherein each via has a width in the range of 25 microns to 500 microns.   The array of chip sockets of claim 1, wherein each via is cylindrical and has a diameter range of 25 microns to 500 microns.   8. The array of chip sockets of claim 7, wherein the frame around at least one socket includes alternating via posts and feature layers, including at least one via post layer and at least one feature layer.   The array of chip sockets of claim 1, wherein the grid of metal vias through the organic matrix framework includes a plurality of via layers.   The array of chip sockets of claim 7, wherein the frame around the at least one socket includes alternating via posts and at least one feature layer continuous coil across at least one via post layer and at least one feature layer.   The array of claim 7, wherein the via post comprises an elongated via post.   The array of chip sockets of claim 9, wherein the continuous coil of elongated via posts spans multiple via post layers.   The array of chip sockets of claim 1 including adjacent chip sockets of different dimensions.   The array of chip sockets of claim 12, comprising adjacent chip sockets of different sizes.   13. An array of chip sockets according to claim 12, comprising different shapes of adjacent chip sockets.   A panel comprising an array of chip sockets, each chip socket being surrounded and defined by the organic matrix framework comprising a grid of copper vias through the organic matrix framework, the panel comprising: A panel comprising at least one region having a socket having a first dimension set for receiving one type of chip and another region having a socket having a second dimension set for receiving another type of chip . A method of making an array of chip sockets surrounded by an organic matrix framework, the method comprising:
Obtain a sacrificial carrier;
Laying a layer of photoresist and patterning with a grid of copper via posts;
Plating copper on the grid;
Laminated with a polymer dielectric;
Thin and flatten to expose the end of the copper via;
Removing the carrier;
Machining a chip socket in the polymer dielectric.   The method of claim 16, wherein the carrier is a copper carrier that is removed by dissolving the copper.   The method of claim 16, further comprising applying an etch resistant layer on the carrier prior to depositing the copper via post.   The method of claim 16, wherein the etch resistant layer comprises nickel.   The method of claim 16, wherein the planarized polymer dielectric with an exposed end of a copper via post is protected with an etch resistant material while the copper carrier is etched away.   21. The method of claim 20, wherein the etch resistant material is a photoresist.   The method of claim 18, wherein the copper seed layer is electroplated on nickel.   The method of claim 18, wherein a copper seed layer is electroplated prior to depositing the nickel barrier layer.   The method of claim 16, wherein the grid is machined by either punching a socket leaving a framework or by CNC. A method of making an array of chip sockets surrounded by an organic matrix framework, the method comprising:
Obtain a sacrificial carrier;
Laying a layer of photoresist and patterning with a grid of copper via posts and a chip socket array;
Plating copper on the grid and the array;
Laminated with a polymer dielectric;
Thin and planarize to expose the ends of the copper vias and the array;
Shielding the end of the copper via post;
Lysing the array;
Removing the carrier.   26. The via post is an elongated via post, and the at least one chip socket surrounded by an organic matrix frame having an embedded metal structure includes at least one elongated via post and at least one feature layer. The method described in 1.   26. The method of claim 25, wherein the elongated via post and feature layer comprise a continuous coil.   At least one socket is separated by a feature layer, each pair of adjacent via post layers being separated by a feature layer by an organic frame and by a multilayer metal structure including a plurality of extending via post layers embedded in the organic frame; 26. The method of claim 25, wherein the multilayer metal structure is enclosed to include a continuous coil.