JP2015203950A - Arithmetic processing unit and control method for arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently execute an SIMD (Single Instruction Multiple Data) indirect access instruction.SOLUTION: An arithmetic processing unit includes: an instruction decoder; a memory access entry part RSA; a memory access pipeline EAGA; a multi-data instruction entry part RSF; a plurality of arithmetic units 330; and a plurality of registers for multi-data instructions. The plurality of arithmetic units 330 process the processing of the entry of multi-data instructions output from the RSF in parallel, and an arithmetic pipeline FLA generates a plurality of memory access requests corresponding to multi-data indirect memory access instructions in the EAGA in response to the output of the entry of the multi-data indirect memory access instructions, and the plurality of arithmetic units 330 supply a plurality of memory addresses acquired from the plurality of registers for multi-data instructions to the FLA.

Description

  The present invention relates to an arithmetic processing unit and a control method for the arithmetic processing unit.

  Techniques such as superscalar, out-of-order, SIMD (Single Instruction Multiple Data) are known as methods for speeding up a CPU that is an arithmetic processing unit or a CPU core that is an arithmetic processing unit. For example, in the superscalar, a plurality of instructions are processed simultaneously, and in the out-of-order, those that can be processed for the resources in the CPU core are processed in random order and are completed in the order of the program.

  On the other hand, SIMD processes a plurality of data in parallel with one instruction. In the SIMD process, a register called a SIMD register is used. In the SIMD register, a plurality of pieces of data equal to or greater than the number that can be processed in parallel by the SIMD instruction are stored as one unit. The SIMD register for storing the plurality of data as one unit is selected by the operand specified by the SIMD instruction, and the instruction processing is executed for each of the plurality of data in the SIMD register. Each of the plurality of pieces of data is called an element, and the number of elements of data to be processed in parallel is called a SIMD width. In the SIMD instruction, for example, the first source operand, the second source operand, and the third source operand specified by the instruction are read from the SIMD register, the SIMD operation is performed, and the data is written to the destination operand. In this SIMD processing, processing of the same instruction is executed in parallel for a plurality of data.

  Further, in processing of instructions other than SIMD instructions, a register called a general purpose register is used. For example, data that is not processed in parallel by memory access or SIMD is stored in the general-purpose register.

  Conventionally, data transfer between a memory and a SIMD register is performed using an address stored in a general-purpose register. In the memory access instruction, the operand address generator reads the first source operand and the second source operand specified by the instruction from the general-purpose register, and generates an address for memory access. Using this read address as the head address, the SIMD width data existing in the continuous address area of the memory is read, the read data is loaded into the SIMD register for the destination operand, or the SIMD is stored in the continuous address area of the memory. Stores SIMD width data read from the register.

JP 2009-163442 A Japanese Patent Publication No. 4-79026 JP 2004-38750 A JP 2011-34450 A

  However, when there is no data that can be processed in parallel in the continuous address area of the memory, the above SIMD load instruction and SIMD store instruction cannot be applied.

  Further, the conventional CPU core is not provided with a configuration for executing an indirect memory access instruction for performing memory access by designating a SIMD register storing a plurality of independent addresses as a source operand using the SIMD instruction. Therefore, the conventional CPU core performs data transfer by a plurality of memory access instructions for the SIMD width using, for example, a configuration capable of individually accessing each element of the SMID register.

  Alternatively, it is conceivable that the indirect access instruction is decomposed into a plurality of instructions such as a block load instruction, and instructions corresponding to the SIMD width are sequentially executed. However, in the method of executing a plurality of instructions as described above, the instruction decoder must be used as many times as the SIMD width, and the reservation station and commit stack entries for executing instructions must be used as many times as the SIMD width. It must use many internal resources of the CPU core. Furthermore, since the instruction decoder occupies a plurality of cycles, subsequent instructions having no dependency cannot be executed out-of-order, and the CPU core configuration that can be processed out-of-order cannot be utilized.

  Accordingly, one object of the present embodiment is to provide an arithmetic processing device and an arithmetic unit that use a plurality of independent data stored in a register as addresses and execute an instruction to access a plurality of locations in a memory area with a single instruction. It is providing the control method of a processing apparatus.

The first aspect of the present embodiment is
An instruction decoder for decoding instructions;
A memory access entry part (RSA) for generating an entry of a memory access instruction by the instruction decoder;
A memory access pipeline (EAGA) for executing an entry of the memory access instruction output from the memory access entry unit with respect to a memory;
A multi-data instruction entry part (RSF) for generating an entry of a multi-data instruction for processing a plurality of data with one instruction by the instruction decoder;
A plurality of arithmetic units and a plurality of multi-data instruction registers; processing of the multi-data instruction entry output from the multi-data instruction entry unit is processed in parallel by the plurality of arithmetic units; An operation pipeline (FLA) for storing operation results in a multi-data instruction register;
The operation pipeline is responsive to an output of an entry of a multi-data indirect memory access instruction that performs memory access to the memory for a plurality of memory addresses stored in the plurality of multi-data instruction registers. A plurality of memory access requests corresponding to the multi-data indirect memory access instruction on a line, and the plurality of computing units obtain the plurality of memory addresses acquired from the plurality of multi-data instruction registers in the memory access pipeline. It is the arithmetic processing unit which supplies to.

  According to the first aspect, the multi-data indirect memory access instruction is efficiently executed with few resources.

It is a figure explaining the indirect memory access system which can implement | achieve the arithmetic processing unit in this Embodiment. It is a figure which shows the example of the pipeline process by a block load instruction. It is a figure which shows the pipeline process by the SIMD indirect memory access instruction in this Embodiment. It is a figure which shows the information processing apparatus carrying the arithmetic processing apparatus in this Embodiment. 2 is a diagram illustrating an overall configuration of a CPU core 30. FIG. It is a figure which shows the structure of CPU core which performs the SIMD indirect memory access (load or store) instruction | indication of this Embodiment. It is a figure which shows the flag structure stored as an entry in the floating point arithmetic reservation station RSF. It is a flowchart which shows the process of a SIMD indirect load command and a normal load command. It is a flowchart which shows the process of a SIMD indirect load command and a normal load command. It is a figure which shows the pipeline and time chart of a SIMD indirect load instruction which is one of the SIMD indirect memory accesses. It is a figure which shows the structure of CPU core which performs the SIMD indirect memory access (load or store) instruction | indication of this Embodiment. FIG. 3 is a diagram showing the configuration of a calculation interface 331 and an address interface 310. FIG. 10 is a diagram showing changes in input / output signals of a pipeline and an address interface 310 in the case of a SIMD indirect memory access instruction with a SIMD width of 2; FIG. 11 is a diagram showing changes in input / output signals of the pipeline and address interface circuit 310 in the case of a SIMD indirect memory access instruction with a SIMD width of 4; FIG. 7 is a diagram illustrating a configuration of an arithmetic interface 331 and an address interface 310 when the single memory access pipeline EAGA of FIG. 6 is provided. It is a figure which shows the collision with the memory access thrown in from subsequent RSA in the case of SIMD width 2. It is a figure which shows the collision with the memory access thrown in from the subsequent RSA in the case of SIMD width 4. It is a figure which shows the collision with the memory access request produced | generated by throwing in the entry of the subsequent SIMD indirect memory access instruction in the case of SIMD width 4. It is a figure which shows the structure of the interface for operation 333 which produces | generates the suppression signal which avoids the collision of an indirect memory access request. It is a figure which shows the output suppression circuit of the entry of RSF and its SIMD indirect memory access instruction. It is a figure which shows the output suppression circuit of RSA and its normal memory access instruction entry. It is a figure which shows the completion waiting circuit in CSE.

  In this embodiment, an instruction for processing a plurality of data with one instruction is referred to as a SIMD instruction (or a multi-data instruction). In the SIMD instruction, for example, SIMD-width arithmetic units perform parallel processing on SIMD-width data, and the processing results are stored in SIMD registers each having a SIMD-width register as one register unit.

  FIG. 1 is a diagram for explaining an indirect memory access method that can be realized by the arithmetic processing unit according to the present embodiment. FIG. 1 shows an indirect memory access method in which a plurality of independent data stored in the SIMD register 332_1 are used as addresses and a plurality of locations in the memory area 14 are accessed by one instruction. In the example of FIG. 1, the SIMD width is an example of 4, and such an indirect memory access instruction is referred to as a SIMD indirect memory access instruction.

FIG. 1A shows an example of a SIMD indirect load instruction (or SIMD indirect load instruction). The four independent data stored in the SIMD register 332_1 are used as addresses, and four addresses ADD_0− The data DATA_0 to DATA_3 of ADD_3 is read and written to another SIMD register 332_2. This SIMD indirect load instruction is described as follows, for example.
load% f100% f200
Here,% f100 is the register number of the SIMD register 332_1 in which the address is stored, and% f200 is the register number of the SIMD register 332_2 to which data is written.

FIG. 1B is an example of a SIMD indirect store instruction (or SIMD indirect store instruction), using four independent data stored in the SIMD register 332_1 as addresses, and data in another SIMD register 332_3. DATA_0-DATA_3 is written in the areas of the four addresses ADD_0-ADD_3 in the memory 14. This SIMD indirect store instruction is described as follows, for example.
store% f100% f300
Here,% f100 is the register number of the SIMD register 332_1 in which the address is stored, and% f300 is the register number of the SIMD register 332_3 in which the write data is stored.

  In the above case, the process of writing four independent addresses to the SIMD register 332_1 is performed by executing, for example, four load instructions. Alternatively, it is performed by writing four independent addresses at successive addresses in the memory and executing a SIMD load instruction with the head address of the memory as the source address.

  FIG. 2 is a diagram illustrating an example of pipeline processing by a block load instruction. The block load instruction here is an instruction for writing data in a continuous area of a memory into a plurality of general purpose registers, for example. When the block load instruction is decoded by the instruction decoder, the instruction decoder generates a plurality of memory access instructions, and the plurality of memory access instructions are sequentially decoded by the instruction decoder and entered in the memory access reservation station, Accessed. In other words, it is a multiflow method.

  Therefore, when loading four data from the memory, the block load instruction is divided into four memory access instructions, and instruction decoding, entry to the reservation station, and memory access are repeated four times, respectively. Therefore, the subsequent operation instruction is in a decoding wait state for four cycles.

  When trying to implement the SIMD indirect load instruction using the block load instruction method, it is necessary to repeat the instruction decoding, the entry to the reservation station, and the indirect load process four times. The resources in the CPU core are occupied for 4 cycles, and the subsequent operation instruction can be decoded after the decoding of the last instruction of the multiflow is completed. This makes it impossible to take advantage of the out-of-order available when the subsequent instruction has no dependency.

[This embodiment]
FIG. 3 is a diagram showing pipeline processing by the SIMD indirect memory access instruction in the present embodiment. In the SIMD indirect memory access instruction according to the present embodiment, the instruction decoder decodes one SIMD indirect memory access instruction, the instruction decoder enters one instruction in the SIMD reservation station, and repeatedly executes four memory accesses. To do. Therefore, since the instruction decoder is released in one cycle, a subsequent operation instruction that does not depend on the SIMD indirect memory access instruction can be decoded in the next cycle. Therefore, the advantage of out-of-order can be utilized. Further, although not shown in FIG. 3, since one SIMD indirect memory access instruction is entered in the SIMD reservation station, it is not necessary to use a plurality of entries in the reservation station, and there is one entry in the commit stack entry. Therefore, the resources in the CPU core are used efficiently.

  FIG. 4 is a diagram showing an information processing apparatus equipped with the arithmetic processing apparatus in the present embodiment. An information processing apparatus 10 such as a computer has a CPU / memory board 12 and a hard disk 11 which is a large-capacity storage device. The CPU / memory board 12 includes an arithmetic processing unit 20 that is a CPU chip, an interconnect 13 that connects the arithmetic processing unit 20 and an external hard disk 11, and a memory 14 such as a DRAM.

  The arithmetic processing unit 20 controls access to, for example, four CPU cores (arithmetic processing units) 30A-30D, a secondary cache 24 shared by the four CPU cores, an input / output interface 26, and the main memory 14. And a memory access controller 28.

  FIG. 5 is a diagram illustrating the overall configuration of the CPU core 30. The CPU core 30 includes a branch prediction unit 302 that performs branch instruction prediction, an instruction fetch address generator 301 that generates an instruction fetch address based on the prediction of the program counter PC and the branch prediction unit 302, a primary instruction cache 303, An instruction decoder 305 for decoding the fetched instruction, a register renaming unit 306, a memory access reservation station RSA (Reservation Station for Address generate), an integer operation reservation station RSE (Reservation Station for Execute), and a floating point It has a SIMD reservation station RSF (Reservation Station for Floating), a branch reservation station RSBR (Reservation Station for Branch), and a commit stack entry CSE (Commit Stack Entry).

  The memory access pipeline EAGA of the memory access reservation station RSA includes an address interface 310, an operand address generator 311, an address selection circuit 313, and a primary data cache 312. The integer arithmetic pipeline EXA of the integer arithmetic reservation station RSE includes an arithmetic interface 333, a fixed point arithmetic unit 320, a fixed point renaming register 321, and a fixed point register 322.

  The floating-point SIMD reservation station RSF has a floating-point SIMD operation pipeline FLA that includes an operation interface 333, a SIMD calculator 330 having the maximum SIMD width, a floating-point SIMD renaming register 331, and a floating-point SIMD register 332. And have. Further, the CPU core 30 has two program counters PC and NEXTPC. The CPU core 30 has a store buffer STB that temporarily stores data generated by the arithmetic units 320 and 330.

  For the SIMD width of the SIMD calculator 330, for example, 2 or 4 can be specified by an instruction. The floating point SIMD register is composed of four elements having a maximum SIMD width. These register elements are referred to as element 0, element 1, element 2, and element 3, respectively. When a floating point SIMD width 2 operation is performed, elements 0 and 1 of the SIMD register are used. When performing a floating point SIMD width 4 operation, all elements of the SIMD register are used.

  The memory access pipeline EAGA, the integer arithmetic pipeline EXA, and the floating-point SIMD arithmetic pipeline FLA may each have one pipeline or two or more pipelines, and can execute instructions independently. In addition, when the number of pipelines of the memory access pipeline EAGA is 2, the primary data cache 312 may be provided with two ports according to the number of pipelines so that it can be accessed simultaneously with a maximum of two addresses. Further, the number of pipelines of the memory access pipeline EAGA may be set to the same four groups as the maximum SIMD width. In that case, it is desirable that the primary data cache 312 also has four ports and can be accessed by a maximum of four addresses simultaneously.

  The instruction fetch address generator 301 selects an instruction address from the branch prediction unit 302 or the program counter PC and issues an instruction fetch request to the primary instruction cache 303. The primary instruction cache 303 stores an instruction corresponding to the instruction fetch request in the instruction buffer 304. Instructions are supplied from the instruction buffer 304 to the instruction decoder 305 in the order specified by the program, that is, in order, and the instruction decoder 305 decodes the instruction supplied from the instruction buffer in order.

  The instruction decoder 305 creates a necessary entry corresponding to the instruction in each of the reservation stations RSA, RSE, RSF, and RSBR according to the type of the decoded instruction. At the same time, the instruction decoder 305 creates entries in the CSE corresponding to all decoded instructions.

  The register renaming unit 306 assigns the addresses of the renaming registers 321 and 331 to the register addresses used in the processing according to the instruction when an entry is created in any of the reservation stations RSA, RSE, and RSF. .

  The reservation stations RSA, RSE, and RSF sequentially output to the pipeline the resources (data, arithmetic units, registers, etc.) required for processing from the held entries, and the subsequent pipelines EAGA, EXA , The process corresponding to the entry output to FLA is executed. As a result, the instruction is executed out of order.

  For example, an entry corresponding to a SIMD operation instruction is stored in the reservation station RSF for floating point operation. One pipeline FLA has SIMD arithmetic units 330 having a number of SIMD widths. The SIMD calculator 330 selects data to be calculated based on the entry from the RSF, and executes the calculations in parallel by SIMD calculators having the number of SIMD widths. The calculation result is temporarily stored in the floating point / SIMD renaming register 331.

  In the reservation station RSA for memory access, an entry corresponding to a memory access instruction other than the SIMD indirect memory access instruction is generated and stored by the instruction decoder 305. Then, the RSA selects any one of the stored entries and outputs it to the pipeline. When an entry of a memory access instruction is output to the pipeline, a memory access request corresponding to the entry transfers each stage of the pipeline in turn. The operand address generation circuit 311 selects data to be calculated based on the memory access request of the RSA entry, generates an address, and inputs the memory access request to the primary data cache 312 using the generated address. The primary data cache 312 performs memory access in response to a memory access request.

  The commit stack entry CSE holds entries corresponding to all instructions decoded by the instruction decoder 305, manages the execution status of processing corresponding to each entry, and completes these instructions in order. For example, when the CSE determines that the result of the process corresponding to the next entry to be completed is stored in the fixed-point renaming register 321 and the floating-point SIMD renaming register 331, the stored data is stored in the fixed-point register 322 or The data is output to the floating point SIMD register 332. As a result, instructions executed out-of-order at each reservation station are completed in-order.

  In the CPU core 30 of FIG. 5, the fixed-point arithmetic pipeline EXA does not have a SIMD configuration. On the other hand, the floating point arithmetic pipeline FLA has a SIMD configuration and includes SIMD arithmetic units 330 having the maximum SIMD width. However, the fixed-point arithmetic pipeline EXA may also have a SIMD configuration.

  The CPU core 30 of this embodiment supplies a bus 334 for supplying an output signal of the arithmetic interface 333 of the floating-point SIMD arithmetic pipeline FLA to the address interface 310 of the memory access pipeline EAGA to generate a memory access instruction. And a bus 335 for supplying the address acquired by the SIMD arithmetic unit 330 to the address selection circuit 313. The address interface 310 outputs memory access instructions having the number of SIMD widths generated based on the output signal of the arithmetic interface 333 to the memory access pipeline EAGA. The address selection circuit 313 selects the bus 335 from the floating-point SIMD calculator 330 instead of the bus from the operand address generator 331, and the SIMD calculator 330 selects the floating-point SIMD register 332 or the floating-point SIMD renaming register. The address obtained from 331 is supplied to the primary data cache 312 together with the above-mentioned SIMD width memory access instruction.

[Outline of Configuration and Processing for Processing SIMD Indirect Memory Access Instruction of Embodiment]
FIG. 6 is a diagram illustrating a configuration of a CPU core that executes a SIMD indirect memory access (load or store) instruction according to the present embodiment. In FIG. 6, each cycle of the pipeline to be described later is shown in parentheses.

  The CPU core 30 in FIG. 6 has one memory access pipeline EAGA from which a memory access reservation station RSA (or memory access entry unit) outputs an entry of a memory access instruction. The floating-point SIMD reservation station RSF (or multi-data instruction entry unit) also has one SIMD operation pipeline FLA that outputs SIMD instruction entries. The SIMD arithmetic pipeline FLA has the same number of floating point SIMD arithmetic units 330 as the maximum SIMD width 4.

  The outline of processing of the SIMD indirect memory access instruction of the present embodiment is as follows. The instruction decoder 305 decodes the SIMD indirect memory access instruction and generates the entry in the floating point SIMD reservation station RSF. When the RSF outputs an entry for the SIMD indirect memory access instruction to the SIMD operation pipeline FLA, the SIMD operation pipeline FLA responds to the number of memory access requests corresponding to the SIMD width via the bus 334 in response to the entry. Generate on line EAGA. Specifically, the flag signal group of the entry in which the arithmetic interface 333 is input is supplied to the address interface 310 via the bus 334, and the address interface 310 uses the memory access pipeline EAGA based on the flag signal group. To sequentially generate access requests for a plurality of memory access instructions. Alternatively, the operation interface 333 may sequentially generate access requests for a plurality of memory access instructions based on the flag signal, and supply the request to the address interface 310 via the bus 334 to generate the pipeline EAGA.

  In response to the input or output of the entry of the SIMD indirect memory access instruction, the SIMD arithmetic unit 330 having the number of SIMD widths acquires the address of the SIMD width number from the floating-point SIMD register 332 in parallel, and the bus 335 To the memory access pipeline EAGA. Specifically, the SIMD calculator 330 sequentially supplies the acquired plurality of addresses to the address selection circuit 313 via the bus 335. The address selection circuit 313 selects a plurality of addresses supplied from the bus 335 according to the access request timings of the plurality of previously generated memory access instructions, and outputs the selected addresses to the primary data cache 312.

  Specifically, as shown in the upper right of FIG. 6, the address selection circuit 313 includes a selector L5 that selects either the address flag A_EAGA_ADD of the operand address generator 311 or the bus 335. As will be described later, the selector L5 causes the bus 335 by the flag signal B1_EAGA_INDDIRECT “1” generated by the address interface 310 in response to the entry of the SIMD indirect memory instruction being output to the SIMD operation pipeline FLA. And the address supplied via the bus 335 is selected and transferred to the primary data cache 312 as an address flag A_EAGA_ADD. As a result, the address is supplied via the bus 335 at the A cycle stage after the B1 cycle stage in alignment with the transfer timing of the memory access request generated by the address interface 310 at the B1 cycle stage. A memory access request including the address of the direct memory access instruction is transferred to the primary data cache 312.

  In the case of a load instruction, the primary data cache 312 stores a plurality of data read from the primary cache 312 or the memory 14 in the floating point SIMD renaming register 331. Then, in response to a command from the commit stack entry, a plurality of read data is transferred from the floating point SIMD renaming register 331 to the floating point SIMD register 332. In these registers 331 and 332, the registers having the number of SIMD widths are collectively specified by register numbers. In the case of a store instruction, a plurality of data stored in the floating point SIMD register 332 are sequentially written to the primary cache 312 or the memory 14.

  The outline of processing of the SIMD indirect memory access instruction will be described more specifically as follows.

  First, the instruction decoder 305 decodes the SIMD indirect memory access instruction and creates entries in the RSF and CSE. The CSE entry number (entry instruction identification information) is called IID. By notifying the CSE of this IID and completion signal upon completion of computation or memory access, the CSE determines completion of the instruction. Simultaneously with the creation of the entry, the instruction decoder 305 secures a continuous number of fetch ports FP that are resources managed by the primary data cache 312 as many as the SIMD width. The fetch port FP is a resource for storing a memory address necessary when the primary data cache performs memory access, and one FP is secured for a normal memory access instruction. In the SIMD indirect memory access instruction, a plurality of prefetch ports FP are used in order to access with the same number of addresses as the SIMD width.

  FIG. 7 is a diagram showing a flag configuration stored as an entry in the floating-point arithmetic reservation station RSF. In order to execute the SIMD indirect memory access instruction, an indirect flag DIRECT and a fetch port flag FP are added. The DIRECT flag becomes “1” when the decoded instruction is a SIMD indirect memory access instruction. The FP flag indicates the first FP number secured at the time of decoding. In addition to these, the RSF includes an OPCODE that instructs the SIMD computing unit 330 to specify the type of operation, a 4 SIMD flag that identifies the SIMD width of the instruction (“0” if the width is 2, and “1” if the width is 4). R1_ADRS indicating the operand to be used, IID indicating the CSE entry number, and the like are stored.

  When the resources necessary for the entry of the SIMD indirect memory access instruction are prepared and can be executed, the RSF outputs or inputs the instruction entry to the arithmetic interface 333 of the floating-point SIMD pipeline FLA.

  When the instruction output from the RSF is an entry of a SIMD indirect memory access instruction, the arithmetic interface 333 indicates whether the indirect instruction, SIMD width, IID, FP, or FLA instruction of the entry is valid. Are transferred to the address interface 310 via the bus 334. The address interface 310 serially generates memory access requests for a plurality of memory access instructions in the memory access pipeline EAGA based on the flag signal group.

  Simultaneously with the generation of the plurality of memory access instructions, the SIMD calculator 330 reads SIMD-width number addresses in parallel from the SIMD register 332 based on the flag signal from the calculation interface 333. The register number of the SIMD register 332 is indicated in the source operand of the SIMD indirect memory access instruction. When the reading of the address from the SIMD register 332 is completed, the SIMD arithmetic unit 330 transfers the plurality of addresses to the address selection circuit 313 via the bus 335. Then, the address interface 310 selects the addresses by matching the timings of the plurality of memory access requests sequentially generated by the address interface 310 to the pipeline EAGA and the plurality of addresses transferred via the bus 335. Transfer to circuit 313. That is, the address selection circuit 313 selects the address supplied from the SIMD calculator 330 instead of the address from the operand address generator 331, and serially transfers a plurality of addresses to the primary data cache 312. The primary data cache 312 reads data or writes data in the SIMD register for each of a plurality of addresses.

  When the primary data cache 312 completes the reading of data, the primary data cache 312 stores the read data in the floating-point SIMD renaming register, and sends entry identification information IID and completion notification to the CSE. In the case of data writing, the primary data cache 312 simply sends entry identification information IID and completion notification of writing completion to the CSE. The CSE waits for reading or writing of all the elements of the SIMD width by the entry identification information IID and the completion notification, and completes the SIMD indirect memory access instruction.

  Next, in order to prevent the memory access request generated based on the entry of the SIMD indirect instruction from colliding with the access request of the subsequent memory access instruction, the arithmetic interface 333 transmits the instruction to the RSA and RSF. Generates a suppression signal that suppresses entry output. That is, first, the arithmetic interface 333 outputs a suppression signal 336 to the RSA in response to the entry of the SIMD indirect memory access instruction, and the RSA receives the address interface based on the SIMD indirect memory access instruction. The output of the entry of the subsequent memory access instruction colliding with the memory access request generated at 310 is suppressed. Second, the operation interface 333 outputs a suppression signal 337 to the RSF in response to the entry of the SIMD indirect memory access instruction, and causes the RSF to suppress the output of the subsequent SIMD indirect memory access instruction entry. . As a result, a memory access request over a plurality of cycles generated in the address interface 310 by the preceding SIMD indirect memory access instruction collides with a memory access request generated based on the subsequent SIMD indirect memory access instruction. To prevent.

  8 and 9 are flowcharts showing the processing of the SIMD indirect load instruction and the normal load instruction. First, instruction fetch (S1), instruction buffer storage (S2), and instruction decode (S3) are performed. If the result of the instruction decoder is a normal load instruction (NO in S4), the process from step S5 is performed. In the case of a SIMD indirect memory access instruction (YES in S4), the processes in and after step S21 are performed.

  In the case of a normal load instruction (NO in S4), the instruction decoder 305 secures one fetch port FP and creates an entry for the load instruction in the RSA (S5). The RSA confirms that the load instruction entry is ready (YES in S6), and does not collide with a memory access instruction generated based on the preceding SIMD indirect memory access instruction (in S7). NO), the entry of the load instruction is output or input to the memory access pipeline EAGA.

  In the memory access pipeline EAGA, the operand address generator 311 reads data from the fixed-point register 322 or the like (S8), the operand address generator 311 generates an address (S9), and the address selection circuit 313 receives from the operand address generator. Address is selected (S10). Then, the primary data cache 312 executes a process of reading data using the address (S11). When the data read by the primary data cache 312 is stored in the floating-point SIMD renaming register and the processing is completed (S12), in the case of a normal load instruction, the CSE releases one fetch port FP and SIMD renaming. Read data is transferred from the register 331 to the SIMD register 332 (S19).

  As described above, in the normal load instruction, an entry of the load instruction is generated in RSA, the operand address generator 331 of the memory access pipeline EAGA acquires and generates an address, and a load request is sent to the primary data cache 312. Do.

  If SIMD load instruction entries for consecutive memory addresses are generated in the RSA, the operand address generator 311 reads the head address from the fixed-point register 322 or the like, and the primary data cache 312 continues for example two Address data is stored in two SIMD renaming registers. However, the SIMD load instruction for the continuous memory addresses is different from the SIMD indirect memory access instruction for a plurality of independent addresses in the plurality of SIMD registers in the present embodiment.

  Next, in the case of a SIMD indirect memory access instruction (YES in S4), the instruction decoder secures the number of fetch ports FP with the SIMD width, and generates an entry for the SIMD instruction in the RSF (S21). The RSF confirms that the entry is ready to be entered (YES in S22), and does not collide with a memory access instruction generated based on the preceding SIMD indirect memory access instruction (NO in S23). An entry of the SIMD indirect memory access instruction is output or input to the SIMD operation pipeline FLA.

  Then, the SIMD arithmetic unit 330 of the SIMD arithmetic pipeline FLA reads addresses in the number of SIMD widths in parallel from the SIMD register 332 (S23). This reading requires two cycles as will be described later. Simultaneously with this reading, the calculation interface 333 of the SIMD calculation pipeline FLA transfers the flag signal group to the address interface 310 via the bus 334, and causes the memory access pipeline EAGA to generate a memory access request 0 (S24). ). The generated request transfers the memory access pipeline EAGA. Further, the SIMD arithmetic unit 330 supplies the address of the number of SIMD widths acquired from the SIMD register 332 to the address selection circuit 313 via the bus 335 (S35), and the address selection circuit 313 receives the SIMD arithmetic unit based on the request 0. (S26), and the fetch port FP is assigned to the request 0 (S27).

  The above steps S23-S27 are repeated twice. A memory access request 1 is generated the second time. Further, when the SIMD width is 4 (YES in S28), the same processing steps S29-S32 as steps S23-S27 are repeated twice. As a result, memory access requests 2 and 3 are generated.

  Then, the primary data cache 312 starts executing a process of reading data using the address of the fetch port FP (S11). When the SIMD width is 2, the CSE responds to the primary data cache processing completion notification (S12, S14) twice, and when the SIMD width is 4, the primary data cache processing completion notification (S12, S14). In response to S14, S16, S17), the completion of SIMD processing is detected, the number of fetch ports FP is released by the SIMD width, and read data is transferred from the SIMD renaming register 331 to the SIMD register 332 (S20).

  As described above, in the case of the SIMD indirect load instruction, the instruction decoder decodes the SIMD indirect load instruction once, the instruction decoder generates one entry of the SIMD indirect load instruction in the RSF, and the SIMD operation pipeline. The FLA generates a memory access request for the number of SIMD widths in the memory access pipeline EAGA, causes a plurality of SIMD computing units to obtain a plurality of addresses in parallel from the SIMD register, and stores the plurality of addresses obtained by the SIMD computing unit in the memory The data is transferred to the access pipeline EAGA and merged into a plurality of memory access requests, and the memory access pipeline EAGA makes a load request to the primary data cache. The SIMD indirect store instruction is the same operation as the above load instruction except that the primary data cache stores in the memory.

Next, the pipeline processing of the SIMD indirect memory access instruction of this embodiment will be described. First, the pipeline stage of the SIMD indirect load instruction is shown below. By referring to the stages shown in parentheses in FIG. 6, the following pipeline stages become clear.
D (Decode): The instruction decoder decodes the instruction.
DT (Decode Transfer): Transfers D-cycle instructions and stores them in the RSF.
P (Priority): Determines and outputs (inputs) an entry of an instruction that the RSF inputs to the SIMD computing unit.
PT (Priority Transfer): The flag signal group of the entry in the P cycle is transferred through the calculation interface and is input to the SIMD calculator 330.
B1, B2 (Buffer): SIMD calculator inputs data necessary for calculation from a register. For example, the data is acquired from the floating point SIMD register 332 or the renaming register 331. In this example, two cycles are required for acquisition.
X (eExection): The SIMD calculator reads data necessary for memory access.
A (Address): The address at which the SIMD computing unit accesses the memory is transferred to the address selection circuit 313.
T (Tag): The primary data cache accesses the tag based on the address.
M (Match): The cache tag read by the primary data cache is compared.
B (Buffer): Buffers data read from the primary data cache.
R (Result): The primary data cache access is completed.
RT (Result): Transfers R cycle data, writes to the renaming register, and notifies the CSE of completion.
C (Commit): It is determined whether or not the instruction has been completed.
W (Write): Various registers are updated and resources are released by a completed instruction. At this time, the read data is transferred from the floating point SIMD renaming register 331 to the SIMD register 332.

The pipeline stages of normal load instructions other than SIMD indirect load instructions are shown below.
D (Decode): Decodes an instruction.
DT (Decode Transfer): Transfers an instruction of D cycle and stores an instruction entry in RSA.
P (Priority): An entry of an instruction to be input from the reservation station RSA to the execution unit is determined and output (input).
B1, B2 (Buffer): Operand address generator determines data necessary for load address generation and inputs from a register.
A (Address): The address at which the operand address generator accesses the memory is calculated.
T (Tag): The tag is accessed based on the address calculated by the primary data cache.
M (Match): The cache tag read by the primary data cache is compared.
B (Buffer): Buffers data read from the primary data cache.
R (Result): The primary data cache access is completed.
RT (Result): Transfers R cycle data, writes to the renaming register, and notifies the CSE of completion.
C (Commit): The completion of the instruction is determined.
W (Write): Various registers are updated and resources are released by a completed instruction. At this time, the data is transferred from the renaming register to the register.

  FIG. 10 is a diagram showing a pipeline and a time chart of a SIMD indirect load instruction which is one of SIMD indirect memory accesses.

  The RSF inputs the SIMD indirect load instruction entry to the SIMD operation pipeline FLA in the P cycle of timing 3. Then, in the B1 cycle at timing 5, the arithmetic interface 333 outputs a flag signal of the SIMD indirect load instruction.

  In the case of a SIMD indirect load instruction with a SIMD width of 2, the SIMD operation pipeline FLA generates a memory access request 0 in the pipeline EAGA in the address interface 310 at timing 6, and at the next timing 7, Request 1 is generated. The generated memory access request is the B1 cycle in the load instruction other than the SIMD indirect load instruction in the memory access pipeline EAGA. The generated memory access entry identification information IID is sent from the SIMD operation pipeline FLA, and the fetch port FP uses the FP value of the SIMD operation pipeline FLA and a value obtained by adding 1 to it. The SIMD operator 330 of the SIMD operation pipeline FLA reads element 0 out of the plurality of data read from the SIMD register (or SIMD renaming register) in the X1 cycle at timing 7 and the SIMD register (or SIMD in the X2 cycle at timing 8). Each element 1 read from the renaming register is serially transferred to the address selection circuit 313 of the memory access pipeline EAGA. At timings 8 and 9 (A cycle), the address selection circuit 313 selects the addresses of the elements 0 and 1 transferred from the SIMD operation pipeline FLA and transfers them to the primary data cache 312. When all the data accessed to the primary data cache exists, the primary data cache 312 transfers the data read at timings 13 and 14 to the SIMD renaming register 331 and reports completion of all memory accesses at timing 14. As a result, the CSE determines completion of the instruction and transfers the data in the SIMD renaming register 331 to the SIMD register 332.

  In the case of a SIMD indirect load instruction with a SIMD width of 4, the SIMD operation pipeline FLA sends requests 0, 1, and 0 for memory access to the pipeline EAGA in the address interface at timings 6, 7, 8, and 9. 2 and 3 are generated serially. The generated four memory access requests are B1 cycles in a load instruction other than the SIMD indirect load instruction in the memory access pipeline EAGA. The entry identification information IID of the generated memory access request uses the information sent from the SIMD operation pipeline FLA, and the fetch port FP uses the FP value of the SIMD operation pipeline FLA and a value obtained by adding 1, 2, and 3 to it. use. The SIMD arithmetic unit 330 of the SIMD operation pipeline FLA has element 0 of SIMD data read from the SIMD register (or SIMD renaming register) in the X1, X2, X3, and X4 cycles at timings 7, 8, 9, and 10. Element 1, element 2 and element 3 are serially transferred to the address selection circuit 313 of the memory access pipeline EAGA. At timings 8, 9, 10, and 11 (A cycle), the address selection circuit 313 selects the addresses transferred from the SIMD operation pipeline FLA and transfers them to the primary data cache 312. When all data accessed to the primary data cache exists, the primary data cache 312 transfers the data read at timings 13, 14, 15, and 16 to the SIMD renaming register 331, and all memory accesses are completed at timing 16. Make a report. As a result, the CSE determines completion of the instruction and transfers the data in the SIMD renaming register 331 to the SIMD register 332.

  Although the SIMD indirect load instruction has been described above, even in the SIMD indirect store instruction, the SIMD arithmetic pipeline FLA generates a memory access request of the number of SIMD widths in the memory access pipeline EAGA, and the SIMD arithmetic unit Obtaining SIMD-width-number addresses in parallel from the SIMD registers and serially transferring them to the memory access pipeline EAGA is equivalent to submitting a SIMD-width-number memory store request to the primary data cache. In the case of the SIMD indirect store instruction, the primary data cache writes data of the number of SIMD widths stored in the SIMD register into the primary cache memory or the memory.

[Detailed description of SIMD indirect memory access in this embodiment]
FIG. 11 is a diagram illustrating a configuration of a CPU core that executes a SIMD indirect memory access (load or store) instruction according to the present embodiment. A detailed description of SIMD direct memory access in the CPU core configuration of FIG. 11 will be given.

  The CPU core 30 of FIG. 11 differs from FIG. 6 in that the memory access reservation station RSA (or the memory access entry unit) uses two pipelines EAGA and EAGB as memory access pipelines for outputting memory access instruction entries. Have. Correspondingly, the primary data cache 312 has a configuration for processing two memory access requests in parallel. The floating-point SIMD reservation station RSF (or multi-data instruction entry unit) has two pipelines FLA and FLB as SIMD operation pipelines that output SIMD instruction entries. The SIMD operation pipelines FLA and FLB have the same number of floating-point SIMD calculators 330 as the maximum SIMD width 4. As for the floating-point SIMD register 332 and the floating-point SIMD renaming register 331, the same number of registers as the maximum SIMD width 4 can be collectively designated by register numbers. Other configurations are the same as those in FIG.

  Therefore, the SIMD operation pipeline FLA can simultaneously generate two memory access requests to the two memory access pipelines EAGA and EAGB in response to the entry of the SIMD indirect access memory instruction. , Two addresses acquired from the SIMD register 332 can be transferred in parallel to the address selection circuits 313 of the two memory access pipelines EAGA and EAGB. This is as shown in FIG.

  When the SIMD width is 2, the SIMD operation pipeline FLA generates two memory access requests to the two pipelines EAGA and EAGB in one cycle via the bus 334. That is, the arithmetic interface 333 transfers the flag signal group to the address interface 310 via the bus 334, and the address interface 310 makes two memory access requests in one cycle based on the transferred flag signal group. The two pipelines EAGA and EAGB are generated. Then, the SIMD computing unit 330 transfers two addresses to the address selection circuits 313 of the two pipelines EAGA and EAGB in one cycle via the bus 335. As described above, the selector L5 (see FIG. 6) in the address selection circuit 313 selects the bus 335 side by “1” of the indirect flag signals B1_EAGA_INDDIRECT, B1_WAGB_INDDIRECT, and two addresses supplied from the SIMD calculator 330 Are output to the two pipelines EAGA and EAGB. As a result, the two addresses supplied from the bus 335 are added to the two memory access requests generated by the address interface 310 at the stage of the cycle A of the address selection circuit 313.

  When the SIMD width is 4, the SIMD operation pipeline FLA generates four memory access requests in two cycles in two pipelines EAGA and EAGB, and transfers four addresses in two cycles. As shown in FIG.

  The flowcharts of FIGS. 8 and 9 can also be applied to the configuration of the CPU core of FIG. However, since the CPU core in FIG. 1 has two memory access pipelines EAGA and EAGB, each of steps S24 to S27 and steps S29 to S32 in FIG. 8 may be performed once.

[Generation of Indirect Memory Access Requests by the Operation Interface 331 and the Address Interface 310]
FIG. 12 is a diagram showing the configuration of the calculation interface 331 and the address interface 310. The calculation interface 331 outputs a control signal at an appropriate timing from the entry of the calculation instruction input from the RSF to the subsequent SIMD calculator 330 or the like. Similarly, the address interface 310 outputs a control signal at an appropriate timing from the entry of the memory access instruction input from the RSA to the operand address generator 311 in the subsequent stage.

  The address interface 310 latches the flag signal of the entry of the normal memory access instruction other than the SIMD indirect memory access instruction, which is input from the RSA into the two pipelines EAGA and EAGB, by the latch circuit groups F1_A and F1_B. To the operand address generator 311. On the other hand, the arithmetic interface 331 transfers the flag signal of the entry of the SIMD indirect memory access instruction input from the RSF to the SIMD arithmetic pipeline FLA to the address interface 310 via the bus 334. Then, the AND gates A1, A2, the latch circuit groups F2, F3, the selectors L1, L2, L3, L4, the OR gates R1, R2, and the adders ADD1, ADD2 in the address interface 310 have been transferred. Based on the flag signal, a memory access request is generated in each of the two memory access pipelines EAGA and EAGB.

  In FIG. 12, the address interface 310 is shown as having a circuit surrounded by a broken line. However, the arithmetic interface 333 may have a part of the circuit surrounded by the broken line. Therefore, the SIMD operation pipeline FLA generates a memory access request to each of the two memory access pipelines EAGA and EAGB by the configuration of the operation interface 333, the address interface 310, and the bus 334.

  Each signal in FIG. 12 will be described.

  The flag signal of the entry on the pipeline FLA side is as follows. The input signal (valid signal) B1_FLA_VALID_EAITF becomes 1 when a calculation request is issued to the SIMD calculator 330 of the pipeline FLA in the B1 cycle of the floating point / SIMD pipeline.

  The input signal (indirect signal) B1_FLA_INDDIRECT_EAITF becomes 1 when the operation request is a SIMD indirect memory access instruction in the B1 cycle of the floating point / SIMD pipeline.

  The input signal (4 SIMD signal) B1_FLA_4SIMD_EAITF becomes 1 when the SIMD width is 4 in the B1 cycle of the floating point / SIMD pipeline.

  The identification information IID of the entry of the instruction executed in the pipeline FLA is transferred to the input signal (IID signal) B1_FLA_IID_EAITF.

  The input signal (FP signal) B1_FLA_FP_EAITF transfers the leading number of the fetch port FP secured by the instruction decoder 305 in the SIMD indirect memory access instruction.

  The flag signals of the entries on the pipelines EAGA and EAGB are as follows. Input signals (valid signals) P_EAGA_VALID and P_EAGB_VALID become 1 when a memory access request is output from the RSA to the operand address generator 331 and the primary data cache 312.

  When a memory access request is issued from the RSA to the operand address generator 331, the fetch port number FP number used in the primary cache memory 312 is transferred to the input signals (FP signals) P_EAGA_FP and P_EAGB_FP.

  When a memory access request is issued from the RSA to the operand address generator 331, entry identification information IID corresponding to each request is transferred to the input signals (IID signals) P_EAGA_IID and P_EAGB_IID.

  When the SIMD indirect memory access instruction entry is input to the SIMD operation pipeline FLA, the address interface circuit 310 uses the flag signal output from the operation interface 333 to generate two addresses in the memory access pipelines EAGA and EAGB. Alternatively, four memory access requests are generated. This memory access request corresponds to four output signals B1_EAGA _ *** and four output signals B1_EAGB _ *** described below. Further, when an entry of a normal memory access instruction is input to the memory access pipelines EAGA and EAGB, the address interface circuit 310 transfers the flag signal of the entry to the operand address generator 311 as it is.

  The output signal (valid signal) B1_EAGA_VALID_OR is output by the OR gate R1, and is a logical sum of the memory access request generated by the SIMD indirect memory access instruction input by the RSF and the memory access request for the normal memory access instruction from the RSA. is there. When this valid signal is 1, a memory access request to the operand address generator 311 and the primary data cache 312 of the memory access pipeline EAGA is valid.

  The output signal (valid signal) B1_EAGB_VALID_OR is a valid signal on the memory access pipeline EAGB side and is the same as described above.

  The output signal (indirect signal) B1_EAGA_INDDIRECT and the output signal B1_EAGB_INDDIRECT are valid when the corresponding valid signal B1_EAGA_VALID_OR and B1_EAGB_VALID_OR signals are 1, and the memory access request is generated by the SIMD indirect memory access instruction. Indicates. OR gate R2 outputs. This signal is transferred to the address selection circuit 313 via the subsequent operand address generator 311 and is used to select an address transferred from the SIMD calculator 330 via the bus 335 in the address selection circuit 313. .

  The output signal (IID signal) B1_EAGA_IID and the output signal (IID signal) B1_EAGB_IID are signals that are valid when the corresponding valid signals B1_EAGA_VALID_OR and B1_EAGB_VALID_OR signals are 1. In the case of the SIMD indirect memory access instruction, the selector L4 selects the entry identification information IID of the input signal B1_FLA_IID_EAITF transferred from the calculation interface 333. Otherwise, the selector L4 selects the IID signals P_EAGA_IID and P_EAGB_IID from the RSA.

  The output signal (FP signal) B1_EAGA_FP and the output signal (FP signal) B1_EAGB_FP are signals that are valid when the corresponding valid signals B1_EAGA_VALID_OR and B1_EAGB_VALID_OR signals are 1. In the case of the SIMD indirect memory access instruction, when the SIMD width is 2, the selector FP selects the FP value transferred by the input FP signal B1_FLA_FP_EAITF and the FP value added by +1 by the adder ADD2. And output. On the other hand, when the SIMD width is 4, the FP value transferred by the adder ADD1 to the FP value transferred by the input FP signal B1_FLA_FP_EAITF in the next clock cycle, and the FP value obtained by adding +1 by the adder ADD2 Are selected and output by the selector L3. For example, when the SIMD width is 4, the SIMD indirect memory access instruction and the value transferred by the FP signal B1_FLA_FP_EAITF is 5, the FP signal B1_EAGA_FP of the request generated in the pipeline EAGA at the timing 6 in FIG. 5, the FP signal B1_EAGB_FP of the request generated in the pipeline EAGB is 6, the FP signal B1_EAGA_FP of the request generated in the pipeline EAGA at timing 7 is 7, and the FP signal B1_EAGB_FP of the request generated in the pipeline EAGB is 8 become. If it is not the SIMD indirect memory access instruction, the FP signals P_EAGA_FP and P_EAGB_FP from the RSA are selected by the selector L3.

  FIG. 13 is a diagram showing input / output signal changes in the pipeline and address interface 310 in the case of a SIMD indirect memory access instruction with a SIMD width of 2. The operation interface 333 of the SIMD operation pipeline FLA outputs the input signal (B1_FLA _ ***) of FIG. 12 in the cycle B1 of timing 5, and the address interface 310 outputs the signal at timing 6 based on these input signals. A memory access request is generated by 12 output signals (B1_EAGA _ ***, B1_EAGB _ ***).

  The input IID signal B1_FLA_IDD_EAITF (= 2) at the timing 5 is latched by the latch F2 via the selector L1, and the output IID signals B1_EAGA_IID and B1_EAGB_IID at the timing 6 are both 2.

  The logical product of the input valid signal B1_FLA_VALID_EAITF (= 1) at the timing 5 and the input indirect signal B1_FLA_DIRECT_EAITF (= 1) is latched by the latch F2 through the AND gate A1, and the output valid at the timing 6 through the OR gates R1 and R2. The signals B1_EAGA_VALID_OR and B1_EAGB_VALID_OR are both 1, and the output indirect signals B1_EAGA_INDDIRECT and B1_EAGB_INDDIRECT are both 1.

  Then, the input FP signal B1_FLA_EAITF (= 4) at timing 5 is latched by the latch F2_FP via the selector L2, and becomes the output FP signals B1_EAGA_FP (= 4) and B1_EAGB_FP (= 5) via the selector L3. .

  By the above operation, the SIMD operation pipeline FLA makes two memory access requests to the two memory access pipelines EAGA and EAGB in the address interface 310 at timing 6 based on the flag signal output from the operation interface 333. Is generated.

  FIG. 14 is a diagram showing input / output signal changes in the pipeline and address interface circuit 310 in the case of a SIMD indirect memory access instruction having a SIMD width of 4. The operation interface 333 of the SIMD operation pipeline FLA outputs the input signal (B1_FLA _ ***) of FIG. 12 in the cycle B1 of the timing 5, and the address interface 310 receives the timing 6, 7 generates a memory access request by the output signals (B1_EAGA _ ***, B1_EAGB _ ***) in FIG.

  The input signal output from the operation interface 333 at timing 5 and the output signal generated in the memory access pipelines EAGA and EAGB in the address interface 310 at timing 6 are the same as in the case of the SIMD width 2 in FIG. .

  However, in the case of the SIMD width 4, the input IID signal of the latch F2 at timing 6 is latched again via the selector L1, and the logical product of the output of the AND gate A1 at timing 6 and the latch signal of the input 4 SIMD signal B1_FLA_4SIMD_EAITF Is latched by the latch F3 via the AND gate A2. Further, the value obtained by adding +2 by the adder ADD1 to the value of the input FP signal B1_FLA_FP_EAITF at timing 6 is latched by the latch F2_FP via the selector L2. Correspondingly, at timing 7, as in timing 6, the output valid signal and output indirect signal of the memory access pipelines EAGA and EAGB maintain 1, the output IID signal maintains 2, and the output FP signal Becomes 6,7.

  With the above operation, the SIMD operation pipeline FLA issues two memory access requests to the two memory access pipelines EAGA and EAGB in the address interface 310 at timing 6 according to the signal output from the operation interface 333. In addition, two more memory access requests are generated in the memory access pipelines EAGA and EAGB at timing 7.

  FIG. 15 is a diagram showing the configuration of the arithmetic interface 331 and the address interface 310 when the single memory access pipeline EAGA of FIG. 6 is provided. In the case of the SIMD indirect memory access instruction, the following operation is performed unlike FIG. This will be described with reference to FIG.

  First, the logical product of the input valid signal B1_FLA_VALID_EAITF at timing 5 and the input indirect signal B1_FLA_INDDIRECT_EAITF is latched by the two latches F2_1 via the AND gate A1, and the output of the latch F2_1 is further latched by the latch F2_2 at the next timing. At timings 6 and 7, the output valid signal B1_EAGA_VALID_OR and the output indirect signal B1_EAGA_INDDIRECT output 1 over 2 cycles.

  When the SIMD width is 4, the logical product of the output of the latch F2_2 at timing 7 and the output of the latch F2_2 of the input 4 SIMD signal is latched by the latch F3_1 via the AND gate A2, and the output of the latch F3_1 is further increased. Latched at the next timing, and at timings 8 and 9, the output valid signal B1_EAGA_VALID_OR and the output indirect signal B1_EAGA_INDDIRECT output 1 over two cycles.

  The input IID signal B1_FLA_IID_EAITF at timing 5 is latched four times by the latch F2 through the selector L1, and is output as the output IID signal B1_EAGA_IID through the selector L4 at timings 6, 7, 8, and 9.

  An input FP signal B1_FLA_FP_EAITF at timing 5 is latched by the latch F2_FP via the selector L2, and then the value of the fetch port FP incremented by the adder ADD1 in three cycles is latched by the latch F2_FP. At timings 6, 7, 8, and 9, the output FP signal B1_EAGA_FP becomes the input FP value and the FP value that is +1, +2, or +3.

[Inhibition of new entry by RSA and RAF to avoid collision]
FIGS. 16 and 17 are diagrams showing a collision between a memory access input from a subsequent RSA in the case of SIMD width 2 and 4. Both are shown in the example of FIG.

  In the present embodiment, when the RAF inputs an entry for the SIMD indirect memory access instruction to the SIMD operation pipeline FLA, the SIMD operation pipeline FLA uses the signal output from the operation interface 333 to generate an address interface 310. A plurality of memory access requests are generated in the memory access pipelines EAGA and EAGB. Therefore, the generated memory access request may collide with a memory access request input from the subsequent RSA. In the example of FIG. 11, when the SIMD width is 2, the memory access request is generated once, so there is a case of collision once, and when the SIMD width is 4, the memory access request is generated twice. There may be a collision. In one example of the memory access pipeline EAGA of FIG. 6, there may be two collisions with SIMD width 2 and four collisions with SIMD width 4.

  The description of the example of FIG. 11 is as follows. 16 and 17, the collision is indicated by a strike-through line to B1.

  (1) In the case of SIMD width 2 in FIG. 16, at timing 3, RSF outputs an SIMD indirect memory access instruction entry of SIMD width 2 to pipeline FLA, and at timing 5, RSA stores memory in pipeline EAGA or EAGB. When an access instruction entry is output, at timing 6, the memory access request cycle B1 signal generated by the SIMD indirect memory access instruction and the memory access request cycle B1 signal transferred from the RSA collide.

  (2) In the case of SIMD width 4 in FIG. 17, RSF outputs an indirect instruction entry of SIMD width 4 to pipeline FLA at timing 3, and RSA makes memory access to pipeline EAGA or EAGB at timing 5 or 6 When an instruction entry is output, the following collision occurs.

  That is, when RSA outputs a memory access instruction entry to pipeline EAGA or EAGB at timing 5, it is transferred from memory access request cycle B1 generated by the SIMD indirect memory access instruction at timing 6 and from RSA. The memory access request cycle B1 signals collide with each other.

  Also, when RSA outputs a memory access instruction entry to pipeline EAGA or EAGB at timing 6, the memory access request cycle B 1 signal generated by the SIMD indirect memory access instruction at timing 7 is transferred from RSA. Conflicts with the signal of the memory access request cycle B1.

  FIG. 18 is a diagram showing a collision with a memory access request generated by inputting an entry of a subsequent SIMD indirect memory access instruction in the case of SIMD width 4. Both are shown in an example having two memory access pipelines EAGA and EGAB in FIG.

  In this embodiment, in response to the entry of the entry of the SIMD indirect memory access instruction, the SIMD operation pipeline FLA uses the signal output from the operation interface 333 to store memory in the memory access pipelines EAGA and EAGB. Generate an access request. For this reason, the generated memory access request may collide with the memory access request generated in the memory access pipelines EAGA and EAGB in response to the entry of the entry of the subsequent SIMD indirect memory access instruction. In the example of FIG. 11, since the memory access request is generated twice when the SIMD width is 4, there may be a collision with the memory access request corresponding to the subsequent SIMD indirect memory access instruction. In the example of FIG. 6, there is a case where the collision occurs once for the SIMD width 2 and the collision occurs three times for the SIMD width 4.

  The description of the example of FIG. 11 is as follows as shown in FIG. In FIG. 18, the collision is indicated by a strikethrough to B1.

  (3) When the RSF outputs an entry for a SIMD indirect memory access instruction with a SIMD width of 4 at timing 3, and when the RSF outputs an entry for a SIMD indirect memory access instruction with a SIMD width of 2 or 4 at timing 4, A collision occurs. That is, the memory access request cycle B1 signal generated by the 4 SIMD indirect memory access instruction output from the RSF at timing 3 and the 2 or 4 SIMD indirect memory access instruction output from the RSF at the next timing 4 The signal in cycle B1 of the memory access request made collides at timing 7.

  FIG. 19 is a diagram illustrating a configuration of the calculation interface 333 that generates a suppression signal that avoids collision of indirect memory access requests. The calculation interface 333 receives the P cycle flag signal of the entry of the SIMD indirect memory access instruction input by the RSF, latches it in the latch group F10, and further latches it in the latch group F11. Thereby, the operation interface 333 transfers the output signal of the B1 cycle two cycles after the P cycle to the SIMD operation unit 330 of the SIMD operation pipeline FLA and the address interface 310 of the memory access pipelines EAGA and EAGB. . The reason why the calculation interface 333 includes the two latch groups F10 and F11 is, for example, to adjust timing.

  Then, the arithmetic interface 333 receives the B1 together with the inhibition signal INH_FLA_INDDIRECT_OP for inhibiting the entry of the subsequent SIMD indirect memory access instruction entry from the three flag signals in the P cycle to the RSF, and the two flag signals in the PT cycle. Also from the three flag signals of the cycle, an inhibition signal INH_RSA_PRIORITY that inhibits the subsequent memory access instruction from being input to the RSA is generated.

  The operation of the calculation interface 333 is as follows.

  The input signal (valid signal) P_FLA_VALID becomes 1 when a calculation request is output to the SIMD calculator to the pipeline FLA in the P cycle of the floating point / SIMD pipeline.

  The input signal (indirect signal) P_FLA_INDDIRECT is a signal that is valid when the input valid signal P_FLA_VALID is 1, and is 1 in the P cycle of the floating point / SIMD pipeline when the operation request is a SIMD indirect memory access instruction. It becomes.

  The input signal (4SIMD signal) P_FLA_4SIMD is a signal that becomes valid when the input valid signal P_FLA_VALID is 1, and becomes 1 in the P cycle of the floating-point / SIMD pipeline when the operation width of the SIMD arithmetic unit is 4. .

  The input signal (IDD signal) P_FLA_IID is a signal that is valid when the input valid signal P_FLA_VALID is 1, and indicates the CSE entry number of the operation executed in the pipeline FLA.

  The input signal (FP signal) P_FLA_FP is a signal that is valid when the input valid signal P_FLA_VALID is 1 and the input indirect signal P_FLA_DIRECT is 1, and is in the primary data cache secured by the instruction decoder in the SIMD indirect memory access instruction. Of the first fetch port FP.

  The arithmetic interface 333 latches and relays the five input signals by the latches F10 and F11, and transfers the five output signals B1_FLA_VALID_EAITF, B1_FLA_DIRECT_EAITF, B1_FLA_4SIMD_EAITF, B1_FLA_IID_EAITF, and B1_FLA_P address access to the B1_FLA_P address. Generate.

  Similarly, the calculation interface 333 latches and relays four input signals by the latches F10 and F11, and transfers the four output signals B1_FLA_VALID, B1_FLA_DIRECT, B1_FLA_4SIMD, and B1_FLA_IID to the SIMD calculator.

  In the arithmetic interface 333, the AND gate A4 generates a logical product of the two input signals P_FLA_VALID and P_FLA_INDDIRECT of the P cycle as the inhibition signal INH_RSA_PRIORITY of the subsequent normal memory access instruction and transfers it to the RSA. As a result, the RSA suppresses the entry of the subsequent memory access instruction entry into the memory access pipelines EAGA and EAGB.

  As shown in FIG. 16, when the two signals in the P cycle at timing 3 are all 1, the inhibition signal INH_RSA_PRIORITY becomes 1 at timing 4, and at timing 5, RSA is the pipelines EAGA and EAGB of the entry of the memory access instruction. Suppressing input to. As a result, the B1 cycle signal is not generated at timing 6, and collision is avoided.

  Further, in the arithmetic interface 333, the AND gate A5 generates a logical product of the three input signals P_FLA_VALID, P_FLA_INDDIRECT, and P_FLA_4SIMD in the P cycle as an inhibition signal INH_RSA_PRIORITY of the subsequent normal memory access instruction and transfers it to the RSA. As a result, the RSA inhibits subsequent memory access instructions from being input to the memory access pipelines EAGA and EAGB.

  As shown in FIG. 17, when all three signals in the P cycle at timing 3 are 1, the inhibition signal INH_RSA_PRIORITY becomes 1 at timing 5, and RSA is sent to the pipelines EAGA and EAGB of memory access instructions at timing 6. Suppress input. As a result, the B1 cycle signal is not generated at timing 7, and collision is avoided. In FIG. 17, as in FIG. 16, the inhibition signal INH_RSA_PRIORITY becomes 1 at timing 4, and the input of the memory access instruction at RSA at timing 5 is inhibited.

  In the arithmetic interface 333, the AND gate A3 generates a logical product of the three input signals P_FLA_VALID, P_FLA_INDDIRECT, and P_FLA_4SIMD in the P cycle as a subsequent SIMD indirect memory access instruction suppression signal INH_FLA_INDDIRECT_OP and transfers it to the RSF. As a result, the RSF suppresses the entry of the subsequent SIMD indirect memory access instruction entry into the SIMD operation pipeline FLA.

  As shown in FIG. 18, when all three signals of the P cycle at timing 3 are 1, the inhibition signal INH_FLA_INDDIRECT_OP becomes 1, and at the next timing 4, the RSF becomes the pipeline FLA of the entry of the SIMD indirect memory access instruction. Suppressing input to. Thereby, the signal of the B1 cycle generated at the timing 7 is not generated, and the collision is avoided.

  FIG. 20 is a diagram illustrating an output suppression circuit for an entry of an RSF and its SIMD indirect memory access instruction. The RSF has, for example, 20 entry holding units 337, and stores flags corresponding to the entries of instructions generated in the reservation station RSF. An example of the flag is shown in FIG.

  The RSF entry output condition detection circuit 338 corresponding to each entry holding unit 337 uses these flags to detect that an output enabling condition to the pipeline is established for each entry in the RSF. The RSF entry output condition detection circuit 338 outputs 1 when an entry of an instruction stored in each RSF can be processed, and outputs 0 when output is not possible.

  The inhibition circuit 339 forces the output of the output condition detection circuit 338 to 0 when both the inhibition signal INH_FLA_INDDIRECT_OP generated by the arithmetic interface 333 and the INDIRECT flag stored in the RSF entry holding unit 337 are 1. To. As a result, the READY signal indicating whether or not the corresponding RSF entry can be output is latched in the latch RSFxx_READY. xx is 00-19.

  The FLA output selection circuit 340 selects the RSF entry to be output next from the RSF entry whose READY signal is 1, and outputs it to the operation interface 333. However, in the case of a SIMD indirect memory access instruction, the INDIRECT flag is set to 1. Therefore, when the inhibition signal INH_FLA_INDDIRECT_OP is set to 1, the READY signal of the entry is set to 0, so that the FLA output selection circuit 340 has its SIMD input. The direct memory access instruction entry is not selected. In the case of an instruction other than the SIMD indirect memory access instruction, the DIRECT flag is set to 0, so that the output of the entry output condition detection circuit 338 is used as the READY signal. Therefore, for an instruction other than the SIMD indirect memory access instruction, if there is an entry in which necessary resources are prepared, the entry of that instruction is output. As a result, the RSF suppresses the output of the SIMD indirect memory access instruction entry in response to the suppression signal INH_FLA_INDDIRECT_OP.

  FIG. 21 is a diagram showing an output suppression circuit for an entry of RSA and its normal memory access instruction. The RSA has, for example, 20 entry holding units 314. The RSA entry output condition detection circuit 315 corresponding to each entry holding unit 314 detects that an output enabling condition to the pipeline is established for each RSA entry. The RSA entry output condition detection circuit 315 outputs 1 when an instruction stored in each RSA can be processed, and outputs 0 when the instruction cannot be output.

  The inhibition circuit 316 forcibly sets the output of the RSA entry output condition detection circuit 315 to 0 when the inhibition signal INH_RSA_PRIORITY generated by the arithmetic interface 333 is 1. As a result, a READY signal indicating whether or not the corresponding RSA entry can be output is latched in the latch RSAxx_READY.

  The EAGA / EAGB output selection circuit 317 selects the RSA entry output from the RSA entry whose READY signal is 1, outputs it to the memory access pipeline EAGA or EAGB, and transfers it to the address interface. When the inhibition signal INH_RSA_PRIORITY is 1, the READY signals of all RSAs become 0 regardless of the value output from the RSA entry output condition detection circuit 315. As a result, the EAGA / EAGB output selection circuit 315 does not output an entry to the memory access pipelines EAGA and EAGB because there is no entry that can be output. As a result, the RSA inhibits output of the memory access instruction entry in response to the inhibit signal INH_RSA_PRIORITY.

  FIG. 22 is a diagram showing a completion waiting circuit in the CSE. FIG. 22 shows a completion waiting circuit for one entry of the CSE.

  First, the indirect flag CSE_INDDIRECT is included in the CSE entry. When the CSE entry is a SIMD indirect memory access instruction, the indirect flag CSE_INDDIRECT of the entry becomes 1. Further, when the instruction is 4 SIMD, 4 SIMD signal CSE_4SIMD becomes 1. If the instruction entered in the CSE is a SIMD indirect memory access instruction, the primary data cache 312 sends a completion report to the CSE twice for 2 SIMD and 4 completions for 4 SIMD for the same CSE entry number IID.

  An input signal (indirect signal) CSE_INDDIRECT and an input signal (4SIMD signal) CSE_4SIMD are flags of entries registered in the CSE by the instruction decoder 305. When the input signal CSE_INDDIRECT is 1, it indicates that the entry of CSE is a SIMD indirect memory access instruction. When the input signal CSE_4SIMD is 1, it indicates that the SIMD width of the CSE entry is 4, and when it is 0, it indicates that the SIMD width is 2.

  The primary data cache 312 of the present embodiment processes two independent memory accesses simultaneously. Therefore, the primary data cache 312 notifies two memory access completion signals independently.

  Input signals RT_STV_0 and RT_STV_1 are memory access completion signals transferred from the primary data cache.

  The input signals RT_STV_0_CSE_SEL and RT_STV_1_CSE_SEL are set to 1 when the entry number IID being processed in the primary data cache matches the entry number of the CSE.

  When RT_STV_0 and RT_STV_0_CSE_SEL become 1, or when RT_STV_1 and RT_STV_1_CSE_SEL become 1, the output of the AND gate A8 or A9 makes the memory access completion report to the CSE valid. When the memory access completion report becomes valid, the adder 351 adds +1 to the 3-bit input signal and outputs it to the memory access completion count storage element 353.

  When the instruction decode creates an entry in the CSE, the memory access completion count storage element 353 is reset to zero. Thereafter, when both RT_STV_0 and RT_STV_0_CSE_SEL are set to 1 or both RT_STV_1 and RT_STV_1_CSE_SEL are set to 1 by the completion report from the primary data cache 312, the adder 351 adds +1 to the memory access completion count.

  Depending on the type of memory access instruction, the output signal (completion signal) CSE_MEM_COMP becomes 1 when the memory access completion count reaches a specified value (1, 2, 4). When the ANDD A6 notifies the SIMD indirect memory access instruction and the SIMD width is 4, when the completion of four memory accesses is notified, the output of bit 2 of the adder 351 becomes 1, and the completion signal CSE_MEM_COMP is set to 1. Become. When the SIMD indirect memory access instruction and the SIMD width are 2, when the completion of two memory accesses is notified, the output of bit 1 of the adder 351 becomes 1, and the completion signal becomes 1. In the case of a memory access instruction that is not a SIMD indirect instruction, the output of bit 0 of the adder 351 becomes 1 when the completion of memory access is notified once, and the completion signal CSE_MEM_COMP becomes 1.

  The completion determination circuit 354 receives the completion signal CSE_MEM_COMP and generates a signal indicating that the instruction can be completed. The completion determination circuit 354 determines that the instructions that have been processed are completed in the order of the program, for example, transfers the processing result from the renaming register to the register, and releases the entry.

  As described above, according to the present embodiment, when an entry of a SIMD indirect memory access instruction is generated in the RSF and the entry is output to the SIMD operation pipeline FLA, the SIMD is transferred to the memory access pipelines EAGA and EGAB. The number of memory accesses corresponding to the width is generated, and the SIMD computing unit 330 acquires a plurality of independent addresses stored in the plurality of SIMD registers 332 and transfers them to the memory access pipelines EAGA and EGAB, and the primary data cache 312 Performs memory access to a plurality of data stored in the plurality of SIMD registers 332 using the plurality of addresses. Therefore, SIMD indirect memory access instructions are executed by efficiently using resources such as instruction decoders and CSE, RSA, and RSF entries.

  The above embodiment is summarized as follows.

(Appendix 1)
An instruction decoder for decoding instructions;
A memory access entry part for generating an entry of a memory access instruction by the instruction decoder;
A memory access pipeline for executing an entry of the memory access instruction output from the memory access entry unit with respect to a memory;
A multi-data instruction entry unit for generating an entry of a multi-data instruction for processing a plurality of data with one instruction by the instruction decoder;
A plurality of arithmetic units and a plurality of multi-data instruction registers; processing of the multi-data instruction entry output from the multi-data instruction entry unit is processed in parallel by the plurality of arithmetic units; An operation pipeline for storing operation results in a register for multi-data instructions,
The operation pipeline is responsive to an output of an entry of a multi-data indirect memory access instruction that performs memory access to the memory for a plurality of memory addresses stored in the plurality of multi-data instruction registers. A plurality of memory access requests corresponding to the multi-data indirect memory access instruction on a line, and the plurality of computing units obtain the plurality of memory addresses acquired from the plurality of multi-data instruction registers in the memory access pipeline. Arithmetic processing device to supply to.

(Appendix 2)
The arithmetic pipeline generates the plurality of memory access requests at a stage of the first cycle of the memory access pipeline, and the plurality of stages at a stage of a second cycle after the first cycle of the memory access pipeline. The arithmetic processing unit according to attachment 1, which supplies a memory address.

(Appendix 3)
The arithmetic processing device according to appendix 2, wherein the arithmetic pipeline supplies the plurality of memory addresses in accordance with pipeline transfer timings of a plurality of memory access requests generated in the memory access pipeline.

(Appendix 4)
A cache unit connected to the memory access pipeline;
The arithmetic pipeline includes the identification information of a plurality of fetch ports that store access destination memory addresses in the cache unit in the plurality of memory access requests generated in the memory access pipeline. apparatus.

(Appendix 5)
The arithmetic processing pipeline according to any one of appendices 1, 2, and 3 that serially generates the plurality of memory access requests and supplies the plurality of memory addresses serially to the memory access pipeline. apparatus.

(Appendix 6)
A plurality of the memory access pipelines;
The arithmetic pipeline generates at least a part of the plurality of memory access requests in parallel to the plurality of memory access pipelines, and supplies at least a part of the plurality of memory addresses in parallel. The arithmetic processing device described in any one of Supplementary Notes 1, 2, and 3.

(Appendix 7)
A cache unit connected to the memory access pipeline;
The arithmetic processing unit according to attachment 1, wherein the cache unit performs data transfer with the plurality of multi-data instruction registers in response to the plurality of memory access requests.

(Appendix 8)
The operation pipeline outputs a suppression signal to the memory access entry unit, and outputs to the memory access entry unit an entry of a memory access instruction that collides with the plurality of memory access requests generated in the memory access pipeline. The arithmetic processing unit described in the supplementary note 1.

(Appendix 9)
The operation pipeline outputs a suppression signal to the multi-data instruction entry unit, and the multi-data indirect memory that collides with the memory access request generated serially in the memory access pipeline to the multi-data instruction entry unit The arithmetic processing unit according to attachment 5, wherein output of an access command entry is suppressed.

(Appendix 10)
The entry of the multi-data indirect memory access instruction output to the arithmetic pipeline includes an indirect memory access signal indicating multi-data indirect memory access and a multi-data width information signal indicating the number of the plurality of data. Have
The operation pipeline generates the number of memory access requests indicated by the multi-data width information signal and supplies the plurality of memory addresses indicated by the multi-data width information signal to the memory access pipeline. 1. The arithmetic processing apparatus according to 1.

(Appendix 11)
An instruction decoder for decoding instructions;
A memory access entry part for generating an entry of a memory access instruction by the instruction decoder;
A memory access pipeline for executing an entry of the memory access instruction output from the memory access entry unit with respect to a memory;
A multi-data instruction entry unit for generating an entry of a multi-data instruction for processing a plurality of data with one instruction by the instruction decoder;
A plurality of arithmetic units and a plurality of multi-data instruction registers; processing of the multi-data instruction entry output from the multi-data instruction entry unit is processed in parallel by the plurality of arithmetic units; In a control method of an arithmetic processing unit having an arithmetic pipeline for storing an arithmetic result in a multi-data instruction register,
In response to input of an entry of a multi-data indirect memory access instruction for performing memory access to the memory with respect to a plurality of memory addresses stored in the plurality of multi-data instruction registers, the operation pipeline Generating a plurality of memory access requests corresponding to the multi-data indirect memory access instruction in a line;
A method for controlling an arithmetic processing unit, wherein the arithmetic pipeline supplies the plurality of memory addresses acquired by the plurality of arithmetic units from the plurality of multi-data instruction registers to the memory access pipeline.

(Appendix 12)
The arithmetic pipeline generates the plurality of memory access requests at a stage of the first cycle of the memory access pipeline, and the plurality of stages at a stage of a second cycle after the first cycle of the memory access pipeline. The method for controlling an arithmetic processing unit according to attachment 11, which supplies a memory address.

301: Instruction fetch address generator 302: Branch prediction mechanism 303: Primary instruction cache 304: Instruction buffer 305: Instruction decoder 306: Register renaming unit RSA: Memory access reservation station (address generation reservation station), Memory access entry unit 310 : Address interface 311: Operand address generator 312: Primary data cache 313: Address selection circuit EAGA, EAGB: Operand address generator, memory access pipeline STB: Store buffer RSE: Reservation station 320 for fixed point arithmetic: Fixed point arithmetic 322: Fixed point register 321: Fixed point renaming register RSF: Reservation station for floating point arithmetic Multi-data instruction entry unit 330: floating-point SIMD arithmetic unit, multi-data instruction arithmetic unit 332: floating-point SIMD register, multi-data instruction register 331: floating-point SIMD renaming register 333: arithmetic interface FLA, FLB: floating-point SIMD operation pipeline, SIMD operation pipeline CSE: commit stack entry RSBR: branch reservation station PC: program counter

Claims (10)

An instruction decoder for decoding instructions;
A memory access entry part for generating an entry of a memory access instruction by the instruction decoder;
A memory access pipeline for executing an entry of the memory access instruction output from the memory access entry unit with respect to a memory;
A multi-data instruction entry unit for generating an entry of a multi-data instruction for processing a plurality of data with one instruction by the instruction decoder;
A plurality of arithmetic units and a plurality of multi-data instruction registers; processing of the multi-data instruction entry output from the multi-data instruction entry unit is processed in parallel by the plurality of arithmetic units; An operation pipeline for storing operation results in a register for multi-data instructions,
The operation pipeline is responsive to an output of an entry of a multi-data indirect memory access instruction that performs memory access to the memory for a plurality of memory addresses stored in the plurality of multi-data instruction registers. A plurality of memory access requests corresponding to the multi-data indirect memory access instruction on a line, and the plurality of computing units obtain the plurality of memory addresses acquired from the plurality of multi-data instruction registers in the memory access pipeline. Arithmetic processing device to supply to. The arithmetic pipeline generates the plurality of memory access requests at a stage of the first cycle of the memory access pipeline, and the plurality of stages at a stage of a second cycle after the first cycle of the memory access pipeline. The arithmetic processing unit according to claim 1, wherein a memory address is supplied. The arithmetic processing device according to claim 2, wherein the arithmetic pipeline supplies the plurality of memory addresses in accordance with pipeline transfer timings of a plurality of memory access requests generated in the memory access pipeline. A cache unit connected to the memory access pipeline;
2. The operation according to claim 1, wherein the operation pipeline includes identification information of a plurality of fetch ports storing access destination memory addresses in the cache unit in the plurality of memory access requests generated in the memory access pipeline. Processing equipment. 4. The operation according to claim 1, wherein the operation pipeline serially generates the plurality of memory access requests and supplies the plurality of memory addresses serially to the memory access pipeline. Processing equipment. A plurality of the memory access pipelines;
The arithmetic pipeline generates at least a part of the plurality of memory access requests in parallel to the plurality of memory access pipelines, and supplies at least a part of the plurality of memory addresses in parallel. The arithmetic processing device according to claim 1, 2, or 3. A cache unit connected to the memory access pipeline;
The arithmetic processing unit according to claim 1, wherein the cache unit performs data transfer with the plurality of multi-data instruction registers in response to the plurality of memory access requests. The operation pipeline outputs a suppression signal to the memory access entry unit, and outputs to the memory access entry unit an entry of a memory access instruction that collides with the plurality of memory access requests generated in the memory access pipeline. The arithmetic processing unit according to claim 1, wherein The operation pipeline outputs a suppression signal to the multi-data instruction entry unit, and the multi-data indirect memory that collides with the memory access request generated serially in the memory access pipeline to the multi-data instruction entry unit The arithmetic processing unit according to claim 5, wherein output of an access command entry is suppressed. An instruction decoder for decoding instructions;
A memory access entry part (RSA) for generating an entry of a memory access instruction by the instruction decoder;
A memory access pipeline for executing an entry of the memory access instruction output from the memory access entry unit with respect to a memory;
A multi-data instruction entry unit for generating an entry of a multi-data instruction for processing a plurality of data with one instruction by the instruction decoder;
A plurality of arithmetic units and a plurality of multi-data instruction registers; processing of the multi-data instruction entry output from the multi-data instruction entry unit is processed in parallel by the plurality of arithmetic units; In a control method of an arithmetic processing unit having an arithmetic pipeline for storing an arithmetic result in a multi-data instruction register,
In response to input of an entry of a multi-data indirect memory access instruction for performing memory access to the memory with respect to a plurality of memory addresses stored in the plurality of multi-data instruction registers, the operation pipeline Generating a plurality of memory access requests corresponding to the multi-data indirect memory access instruction in a line;
A method for controlling an arithmetic processing unit, wherein the arithmetic pipeline supplies the plurality of memory addresses acquired by the plurality of arithmetic units from the plurality of multi-data instruction registers to the memory access pipeline.

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