JP2015198192A - Substrate with through electrode and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress occurrence of problems due to opening of a void left in a through electrode, while leaving the void in the through electrode.SOLUTION: A first electrode layer 15 covering the inner wall surface of a through hole 12 is shaped so as to leave a void 15a penetrating the front and rear surfaces of a substrate. With such an arrangement, plating liquid, or the like, can be prevented from being left in the void 15a, when forming the first electrode layer 15. Thereafter, both ends of the void 15a are closed by a second electrode layer 16, through a vapor process different from a liquid phase process. Consequently, liquid can be prevented from being left in the void 15a, and opening of the void 15a in the subsequent step can be suppressed.

Description

  The present invention relates to a substrate including a through electrode formed by forming a through electrode on a silicon substrate, a glass substrate, or the like, and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, there is a substrate provided with a through electrode formed by forming a through electrode on a silicon substrate or a glass substrate. This substrate is manufactured by the following process, for example.

  First, a silicon substrate is prepared, and a mask material is disposed on the surface of the silicon substrate. Next, the mask material is patterned, and a mask is formed by opening a region where the through electrode is to be formed in the silicon substrate. Then, by performing anisotropic etching in a state where the silicon substrate other than the region where the through electrode is to be formed is covered with a mask, via holes are formed up to a predetermined depth of the silicon substrate, and then the silicon substrate is removed from the back side. Grind and polish until the via hole is reached. Thereby, the via hole becomes a through hole and is formed in the silicon substrate.

  Subsequently, for example, by performing thermal oxidation, an insulating film is formed on the surface of the silicon substrate including the inside of the through hole. Then, after forming a seed layer composed of a base metal for plating on the insulating film, Cu (copper) plating or the like is performed to form an electrode layer including the inside of the through hole. Thereafter, the electrode layer and the seed layer on the front and back surfaces of the silicon substrate are removed by CMP (Chemical Mechanical Polishing) or the like so that the electrode layer and the seed layer in each through hole are electrically separated from each other. To form a through electrode.

  And the board | substrate provided with the penetration electrode is completed by performing the formation process of an interlayer insulation film, a surface wiring formation process, and a back surface wiring formation process with respect to the silicon substrate after forming the penetration electrode. An interposer in which an IC chip in which an integrated circuit or the like is formed is mounted on the front and back surfaces of the substrate and an electrical connection is made between the IC chips through the through electrode. Used as

  On the other hand, in the method of manufacturing a substrate having a through electrode as described above, since a void (hole) remains in the through electrode, an electrode material is embedded in Patent Document 1 so as to embed all the through holes. A method of forming has been proposed. Specifically, after placing a substrate with an electrode material on the surface so as to block one end of the through hole on one side of the substrate on which the through hole (through hole) is formed, the electrode material from the opening end side of the through hole Embed. Thus, a through electrode in which an electrode material is arranged so as to embed all the inside of the through hole is obtained.

JP 2006-161124 A

  However, when the through electrode is completely embedded in the through hole as in Patent Document 1, there is a possibility that a crack may be generated around the through electrode on the substrate. That is, as shown in FIG. 5, when the through electrode J3 is completely embedded in the through hole J2 formed in the substrate J1, the constituent material of the substrate J1 (eg, silicon) and the constituent material of the through electrode J3 (eg, Cu) Due to the difference in thermal expansion coefficient, when a high temperature process is performed after the through electrode is formed, stress due to expansion of the through electrode J3 is applied to the substrate J1. As a result, as shown in the figure, a crack J4 occurs in the substrate J1. For this reason, from the viewpoint of improving the durability of the substrate J1, a structure in which a void remains in the through electrode as in the prior art is preferable instead of the method described in Patent Document 1.

  However, it has been confirmed that problems also occur in the manufacturing method of the structure in which voids remain in the through electrodes. This problem will be described with reference to FIG.

  As shown in FIG. 6A, in order to form the through electrode J10, after forming the through hole J12 in the substrate J11, the insulating film J13 is formed on the surface of the substrate J11 including the inside of the through hole J12. After forming the seed layer J14 and the like, Cu plating or the like is performed. Thereby, the electrode layer J15 can be formed in the through hole J12, and the void J16 remains in the central portion of the electrode layer J15 formed with a predetermined film thickness in the through hole J12.

  At this time, as shown in FIG. 6A, when the electrode layers J15 are in close contact with each other at both ends in the through hole J12, the void J16 becomes a sealed space, and a plating solution or the like remains inside. Therefore, as a subsequent step, as shown in FIG. 6B, when the electrode layer J15 and the seed layer J14 are removed on the front and back surfaces of the substrate J11 by CMP or the like, the end of the void J16 becomes very thin. Or open. In such a state, as shown in FIG. 6C, it is included when the interlayer insulating film forming step is performed on the substrate J11, and when the subsequent front surface wiring forming step and back surface wiring forming step are further performed. When the high temperature process is performed, the plating solution remaining inside the void J16 is ejected. For example, when the interlayer insulating film J17 is formed of a polyimide layer, a curing process is performed at about 300 ° C. for 1 hour.

  As a result, the sprayed plating solution or the like covers the surface of the through electrode J10, which causes a problem of causing poor conduction. There is also a problem that the material of the film disposed thereon enters the void J16 that is opened, and the photolithography process cannot be performed satisfactorily.

  In view of the above points, the present invention provides a substrate including a through electrode having a structure capable of suppressing the occurrence of defects due to opening of the void left in the through electrode while leaving the void inside the through electrode. And it aims at providing the manufacturing method.

  In order to achieve the above object, in the inventions according to claims 1 to 4, the base substrate (11) having a through hole (12) penetrating from the front surface to the back surface, and the inner wall surface of the through hole are covered. A first electrode layer (15) formed with a void (15a) penetrating the front and back surfaces of the base substrate, and a first metal layer that closes the opening of the void at both ends of the void formed in the first metal layer. And a through-hole electrode (10) penetrating the front and back surfaces of the base substrate is formed by at least the first metal layer.

  As described above, the first metal layer covering the inner wall surface of the through-hole has a shape in which a void penetrating the front and back surfaces of the substrate remains, so that a plating solution or the like when forming the first metal layer does not remain in the void. Can be. And since the both ends of a void are obstruct | occluded with the obstruction | occlusion member, it can prevent that a liquid remains in a void and can suppress that a void opens in a post process. Therefore, it is possible to provide a substrate having a through electrode having a structure capable of suppressing the occurrence of defects due to the opening of the void left in the through electrode while leaving the void inside the through electrode. .

  In the inventions according to claims 5 to 7, the step of preparing the base substrate (11), the step of forming the through hole (12) with respect to the base substrate, and the base inside while covering the inner wall surface of the through hole. The step of forming the first electrode layer (15) so as to form a void (15a) penetrating the front and back surfaces of the substrate, and closing the opening of the void at both ends of the void formed in the first metal layer Forming a closing member (16).

  As described above, the first metal layer covering the inner wall surface of the through-hole has a shape in which a void penetrating the front and back surfaces of the substrate remains, so that a plating solution or the like when forming the first metal layer does not remain in the void. Can be. Then, since both ends of the void are closed with the closing member after this, liquid can be prevented from remaining in the void, and the void can be prevented from opening in a subsequent process. Therefore, even if a high temperature process is performed after forming the closing member, it is possible to prevent the plating solution or the like from being ejected from the void. In addition, since the void is blocked by the blocking member, when the interlayer insulating film or the like is formed after the through electrode is formed, the film disposed in the upper layer does not enter the void, and the photolithography process is performed well. It becomes possible.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is a figure which shows the cross-sectional structure of the board | substrate provided with the penetration electrode concerning 1st Embodiment of this invention. It is sectional drawing which showed the manufacturing process of the board | substrate provided with the penetration electrode shown in FIG. FIG. 3 is a cross-sectional view illustrating a manufacturing process of a substrate including a through electrode continued from FIG. 2. It is sectional drawing which showed the manufacturing process of the board | substrate provided with the penetration electrode concerning 2nd Embodiment of this invention. It is sectional drawing which showed a mode that the crack generate | occur | produced when the inside of a trench was embedded with the penetration electrode. It is sectional drawing which showed a mode that plating solution remained, when leaving a void in a trench.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

  (1st Embodiment) The board | substrate provided with the penetration electrode concerning 1st Embodiment of this invention is demonstrated. First, with reference to FIG. 1, the structure of the board | substrate provided with the penetration electrode concerning this embodiment is demonstrated.

  As shown in FIG. 1, in this embodiment, a silicon substrate 11 is used as a base substrate of a substrate 1 provided with a through electrode 10.

  A plurality of through holes 12 are formed in the silicon substrate 11. The through hole 12 has a cylindrical shape with a diameter of about 20 to 100 μm, for example, and the through electrode 10 is disposed in the through hole 12. Specifically, the inner wall surface of the through hole 12 is covered with an insulating film 13, and a first electrode layer 15 is formed inside the insulating film 13 via a seed layer 14, and the first electrode layer 15 is formed. The through electrode 10 is formed by forming the second electrode layer 16 so as to close both ends of the void 15a formed therein.

  The insulating film 13 is composed of, for example, a silicon oxide film formed by thermal oxidation, and is uniformly formed on the inner wall surface of the through hole 12 with a predetermined film thickness, for example, 0.5 to 1.0 μm. Thus, the silicon substrate 11 and the through electrode 10 are insulated.

  The seed layer 14 serves as a base metal when the first electrode layer 15 is formed by plating. For example, in addition to Cu, any one of Ti (titanium), Ni (nickel), Au (gold), etc. Consists of metals including metallic materials. Here, the seed layer 14 is formed on the surface of the insulating film 13, but the seed layer 14 is not formed directly on the insulating film 13, but, for example, a Poly-Si layer and a dielectric film are sequentially formed. Then, the seed layer 14 may be further formed. With such a configuration, a noise removing capacitor can be configured to surround the through electrode 10.

  The first electrode layer 15 constitutes a conductor portion of the through electrode 10 together with the seed layer 14 and is made of Cu or a metal material containing Cu, for example, formed by Cu plating or the like. The first electrode layer 15 is formed to have a predetermined thickness on the surface of the seed layer 14, and the film thickness is adjusted so that a void 15 a passing through the front and back of the silicon substrate 11 remains in the center of the first electrode layer 15. The opening diameter of the void 15a is about 1 to 5 μm, for example, 2 μm, and the both ends of the void 15a are surely opened on both the front and back surfaces of the silicon substrate 11.

  The second electrode layer 16 corresponds to a closing member, and is embedded on the front and back surfaces of the silicon substrate 11 so as to close the openings in the first electrode layer 15, that is, both ends of the void 15 a. In the present embodiment, the surface of the second electrode layer 16 and the surface of the first electrode layer 15 are coplanar, and the surface of the insulating film 13 left on the front and back surfaces of the silicon substrate 11 is coplanar. Yes. Thus, since the opening of the first electrode layer 15 is blocked by the second electrode layer 16, the void 15 a is left inside the area surrounded by the first electrode layer 15 and the second electrode layer 16. It is in a state.

  As described above, the seed layer 14 and the first and second electrode layers 15 and 16 are formed in the through hole 12 via the insulating film 13 so that the through electrode 10 is formed on the silicon substrate 11. Yes.

  Furthermore, an interlayer insulating film 17 is formed on the front and back surfaces of the silicon substrate 11 on which the through electrodes 10 are formed in this way. The interlayer insulating film 17 is made of, for example, polyimide. A contact hole 17a is formed at a position corresponding to the through electrode 10 in the interlayer insulating film 17, and the through electrode 10 is exposed through the contact hole 17a.

  Then, on the surface side of the silicon substrate 11, the surface wiring 18 is patterned on the interlayer insulating film 17, and on the back surface side of the silicon substrate 11, the back surface wiring 19 is patterned on the interlayer insulating film 17. Yes. The front surface wiring 18 and the back surface wiring 19 are electrically connected to the through electrode 10 through a contact hole 17 a formed in the interlayer insulating film 17.

  With such a configuration, the substrate 1 including the through electrode 10 according to the present embodiment is configured. Although not shown, the substrate 1 having the through-electrode 10 configured in this manner is mounted with an IC chip on which an integrated circuit or the like is formed on the front and back surfaces of the substrate 1, and between the IC chips through the through-electrode 10. Used as an interposer for electrical connection.

  Then, the manufacturing method of the board | substrate 1 provided with the penetration electrode 10 concerning this embodiment is demonstrated with reference to FIGS.

  First, as shown in FIG. 2A, a silicon substrate 11 is prepared. Next, after a mask material is arranged on the surface of the silicon substrate 11, the mask material is patterned to open a region where the through electrode 10 is to be formed in the silicon substrate 11 to form the mask 20. Then, anisotropic etching is performed in a state where the region other than the region where the through electrode 10 is to be formed is covered with the mask 20 in the silicon substrate 11, so that the silicon substrate 11 has a predetermined depth as shown in FIG. A cylindrical via hole 21 having a diameter of about 20 to 100 μm is formed up to the position. Furthermore, as shown in FIG. 2C, the silicon substrate 11 is ground and polished until it reaches the via hole 21 from the back surface side. Thereby, the via hole 21 becomes the through hole 12 and is formed in the silicon substrate 11.

  Subsequently, as shown in FIG. 2D, the insulating film 13 having a thickness of about 0.5 to 1.0 μm is formed on the surface of the silicon substrate 11 including the inside of the through hole 12 by performing, for example, thermal oxidation. . Then, as shown in FIG. 2 (e), a seed layer 14 made of a metal containing any one of metal materials such as Cu, Ti, Ni, and Au is provided on the insulating film 13 as a base metal for plating. Form. Then, the 1st electrode layer 15 is formed into a film including the inside of the through-hole 12 by giving Cu (copper) plating. At this time, the first electrode layer 15 is formed to have a predetermined thickness on the surface of the seed layer 14, but the film thickness is adjusted so that a void 15 a passing through the front and back of the silicon substrate 11 remains in the center of the first electrode layer 15. Thus, since the first electrode layer 15 may be formed to such an extent that the voids 15a remain, the time for forming the first electrode layer 15 can be shortened, and the throughput can be improved.

  In the plating process for forming the first electrode layer 15, there is a possibility that the plating solution may remain in the void 15a. However, if the diameter of the void 15a is secured to about 1 to 5 μm, it takes time. As a result, the plating solution dries out. Alternatively, the plating solution in the void 15a can be removed by performing a cleaning process as necessary.

  Then, as shown in FIG. 3A, a step of closing the openings at both ends of the first electrode layer 15, that is, both ends of the void 15a, with the second electrode layer 16 is performed. For example, both ends of the void 15a can be blocked by the second electrode layer 16 by performing a vapor phase process such as vapor deposition, sputtering, or CVD. That is, by forming the second electrode layer 16 with a film thickness of ½ or more of the diameter of the void 15a, for example, when the diameter of the void 15a is 2 μm, both ends of the void 15a can be closed. .

  Thereafter, as shown in FIG. 3B, the seed layer 14, the first electrode layer 15 and the second electrode layer 16 on the front and back surfaces of the silicon substrate 11 are planarized and removed by CMP or the like. Accordingly, the through electrode 10 is formed so that the first electrode layer 15 and the seed layer 14 in each through hole 12 are electrically separated from each other. At this time, since the first electrode layer 15 is not thick enough to eliminate the voids 15a, it is possible to shorten the time of the planarization process such as CMP and further improve the throughput.

  Further, as shown in FIG. 3C, after performing a step of forming an interlayer insulating film 17 made of polyimide or the like on the surface side of the silicon substrate 11 after the through electrode 10 is formed, this is patterned. The contact hole 17a is formed. Then, a process of forming the surface wiring 18 is performed on the interlayer insulating film 17, and Cu plating or the like is formed on the surface of the surface wiring 18 as necessary. Similarly, as shown in FIG. 3D, after performing a step of forming an interlayer insulating film 17 made of polyimide or the like on the back side of the silicon substrate 11 after the through electrode 10 is formed, this is patterned. Thus, a contact hole 17a is formed. Then, a process of forming the back surface wiring 19 is performed on the interlayer insulating film 17, and Cu plating or the like is formed on the surface of the back surface wiring 19 as necessary. Thus, the board | substrate 1 provided with the penetration electrode 10 concerning this embodiment is completed.

  As described above, in the present embodiment, the first electrode layer 15 covering the inner wall surface of the through-hole 12 has a shape in which the voids 15a penetrating the front and back surfaces of the substrate remain, so that the first electrode layer 15 is formed. The plating solution or the like can be prevented from remaining in the void 15a. Then, since both ends of the void 15a are closed by the second electrode layer 16 by a gas phase process different from the liquid phase process, no liquid remains in the void 15a. It can suppress opening in a process.

  Therefore, even if a high temperature process is performed in the formation process of the interlayer insulating film 17 after the second electrode layer 16 is formed, the plating solution or the like can be prevented from being ejected from the void 15a. In addition, since the void 15a is blocked by the second electrode layer 16, when the interlayer insulating film 17 and the like are formed after the through electrode 10 is formed, the film disposed in the upper layer does not enter the void 15a. The photolithography process can be performed satisfactorily.

  Further, since the void 15 a is left inside the through electrode 10, stress due to expansion of the through electrode 10 is applied to the silicon substrate 11 due to a difference in thermal expansion coefficient between the silicon substrate 11 and the through electrode 10. Even so, the stress is relieved by the void 15a. For this reason, it becomes possible to suppress the generation of cracks in the silicon substrate 11.

  As described above, according to the present embodiment, the void 15a inside the through electrode 10 is left, and the occurrence of problems due to the opening of the void 15a left in the through electrode 10 can be suppressed. It becomes possible to set it as the board | substrate 1 provided with the penetration electrode 10. FIG. In addition, even if the void 15a is opened, since no liquid is ejected from the inside, the occurrence of poor conduction can be suppressed.

(Second Embodiment)
A second embodiment of the present invention will be described. This embodiment is different from the first embodiment in that the formation process of the second electrode layer 16 serving as a closing member is changed with respect to the first embodiment, and the others are the same as the first embodiment. Only the part will be described.

  In this embodiment, the 2nd electrode layer 16 used as a closure member is formed by affixing. FIG. 4 shows details of the formation process of the second electrode layer 16.

  As shown in FIG. 4A, an object prepared up to the step shown in FIG. 2E described in the first embodiment is prepared. Subsequently, as shown in FIG. 4B, a metal (for example, Cu or Al (for example, Cu or Al)) is formed on the surface of the second and third substrates 30 and 40 via the release materials 31 and 41 on the surface of the second and third substrates 30 and 40. A metal layer 32, 42 composed of aluminum)) is prepared. For example, as the second and third substrates 30 and 40, silicon substrates or glass substrates are used, and as the release materials 31 and 41, for example, those using a thermoplastic resin are used. Then, on each of the front and back surfaces of the silicon substrate 11 on which the first electrode layer 15 is formed, the second substrate 30 on which the metal layer 32 is formed and the third substrate 40 on which the metal layer 42 is formed are connected to the respective metal layers 32, The 42 side is arranged toward the silicon substrate 11 side. Then, the metal layers 32 and 42 are bonded to the first electrode layer 15 by performing a heat treatment or the like.

  Thereafter, as shown in FIG. 4C, the second and third substrates 30 and 40 are peeled off from the silicon substrate 11 in the release materials 31 and 41, leaving only the metal layers 32 and 42. For example, by performing heat treatment, bubbles can be generated in the release materials 31 and 41, and the second and third substrates 30 and 40 can be released in the release materials 31 and 41.

  And as shown in FIG.4 (d), by patterning the part formed in the front and back of the silicon substrate 11 among the metal layers 32 and 42 and the 1st electrode layer 15, these correspond to the through-hole 12. FIG. Leave in position. Thus, the second electrode layer 16 is configured by the metal layers 32 and 42, and the through electrode 10 including the seed layer 14 and the first and second electrode layers 15 and 16 is configured.

  Subsequent steps are the same as those in the first embodiment, and the substrate 1 including the through electrode 10 having the same structure as that in the first embodiment is manufactured by performing various steps shown in FIG. can do. In the case of such a manufacturing method, the surface of the second electrode layer 16 is not flush with the surface of the first electrode layer 15, but the film thickness of the second electrode layer 16 is as thin as about 1 to 2 μm, Since the step is hardly formed, it does not affect the subsequent photolithography process.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in the first embodiment, the closing member for closing both ends of the void 15a is configured by the second electrode layer 16 made of a metal material. However, this is merely an example, and the closing member may be made of other materials such as Poly-Si or resin. For example, the closing member made of a material different from metal can be formed by CVD or vacuum filling. Even in such a case, when the through electrode 10 is planarized by CMP or the like, the surface of the first electrode layer 15 and the surface of the closing member can be flush with each other, and the first electrode layer 15 is exposed. Therefore, electrical connection between the first electrode layer 15 and the front surface wiring 18 and the back surface wiring 19 can be achieved.

  Moreover, the formation process of the obstruction | occlusion member should just be a process different from a liquid phase process, and may be performed by a solid-phase process other than a gaseous-phase process. For example, when a granular metal pellet is spread on the surface of the silicon substrate 11 after the first electrode layer 15 is formed in a reduced-pressure atmosphere, and the reduced-pressure atmosphere is returned to the air atmosphere while heating, the opening of the reduced-pressure void 15a The pellets are attracted to each other and both ends of the void 15a can be closed with the molten metal material. If it does in this way, the 2nd electrode layer 16 can also be formed by a solid phase process.

  Further, although the silicon substrate 11 is used as the base substrate, another semiconductor substrate may be used, or a glass substrate or a ceramic substrate may be used. If an insulating substrate is used as the base substrate, it is not necessary to form the insulating film 13.

  Further, in each of the above embodiments, the first electrode layer 15 and the closing member are made of different materials, but may be made of the same material as the first electrode layer 15.

DESCRIPTION OF SYMBOLS 1 Substrate 10 Through electrode 11 Silicon substrate 12 Through hole 15 1st electrode layer 15a Void 16 2nd electrode layer 17 Interlayer insulation film 18 Surface wiring 19 Back surface wiring

Claims (7)

A base substrate (11) having a through hole (12) penetrating from the front surface to the back surface;
A first electrode layer (15) in which a void (15a) penetrating the front and back surfaces of the base substrate is formed inside while covering an inner wall surface of the through hole;
A closing member (16) made of a material different from the first metal layer that closes the opening of the void at both ends of the void formed in the first metal layer;
A substrate provided with a through electrode, wherein a through electrode (10) penetrating the front and back surfaces of the base substrate is constituted by at least the first metal layer.   The substrate having a through electrode according to claim 1, wherein the first metal layer is made of Cu or a metal material containing Cu.   The substrate having a through electrode according to claim 1 or 2, wherein the closing member is a second electrode layer (16) made of a metal material different from that of the first metal layer.   The board | substrate provided with the penetration electrode of Claim 1 or 2 with which the said closure member is comprised by Poly-Si or resin. Preparing a base substrate (11);
Forming a through hole (12) in the base substrate;
Forming a first electrode layer (15) so as to form a void (15a) penetrating the front and back surfaces of the base substrate while covering an inner wall surface of the through hole;
Forming a closing member (16) for closing the opening of the void at both ends of the void formed in the first metal layer, and manufacturing a substrate having a through electrode Method. The step of forming the first metal layer includes
Forming a seed layer (15) serving as a base metal of the first metal layer so as to cover an inner wall surface of the through hole;
The method for manufacturing a substrate having a through electrode according to claim 5, further comprising: forming the first metal layer on a surface of the seed layer by plating.   7. The method for manufacturing a substrate having a through electrode according to claim 5, wherein the step of forming the closing member is performed by a gas phase process using any one of vapor deposition, sputtering, and CVD.

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