JP2015194412A - Sensor signal processing circuit, infrared sensor module and sensor signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sensor signal processing circuit, infrared sensor module and sensor signal processing method that are less in influence of disturbance noise, and less in current consumption, when signal processing is performed on a plurality of sensors.SOLUTION: A sensor signal processing circuit according to an embodiment 1 comprises: a selection circuit 35 that selects an output signal from a plurality of infrared sensors 31a and 31b; a signal processing circuit 32 that has a ΔΣ AD conversion circuit 42 performing an AD conversion of the output signal selected in the selection circuit 35; and a control circuit 37 that controls the selection circuit 35 in time division. The ΔΣ AD conversion circuit 42 includes: a plurality of integral capacities corresponding to the infrared sensors 31a and 31b; and first switch units SW1C and SW2C that select any of the integral capacities for switching.

Description

  The present invention relates to a sensor signal processing circuit, an infrared sensor module, and a sensor signal processing method, and more particularly to a sensor signal processing circuit, an infrared sensor module, and a sensor signal processing method including a plurality of infrared sensors.

  Conventionally, for example, a technique described in Patent Document 1 is known as a technique related to a circuit that processes signals from a plurality of sensors. The thing of this patent document 1 is related with the pointing device of the electronic device using the infrared sensor which can detect a human body (user's hand), and its control method, and measures the output from two infrared sensors. A sensor output measurement unit, a sensor output comparison / difference calculation unit, a sensor output comparison unit, a sensor output difference calculation unit, and a pointer movement direction / movement amount control unit are provided.

JP 2009-129023 A

FIG. 1 is a block diagram illustrating an example of a signal processing circuit when a measurement target is observed simultaneously by a plurality of sensors. In this signal processing circuit, signal processing of a plurality of systems is simultaneously performed according to the number of first and second sensors 1a and 1b, so that a plurality of amplifier circuits 21a and 21b, a plurality of AD converters 22a and 22b, A plurality of registers 3a and 3b and a digital interface 4 are provided. In each channel, the weak signals output from the sensors 1a and 1b are amplified in the signal levels by the amplifier circuits 21a and 21b, and the digital data converted by the AD converters 22a and 22b are stored in the respective registers 3a and 3b. To do.
In such a signal processing circuit that processes each sensor signal, when there is disturbance noise such as environmental temperature, the output in each channel is as follows.
First sensor: (S1 + N) × α
Second sensor: (S2 + N) × α
Here, S1 and S2 indicate output signals of the sensors, N indicates disturbance noise, and α indicates the gain of the amplifier circuit.

At this time, by taking the difference between the outputs of the first and second sensors 1a and 1b, the disturbance noise is canceled and only the difference between the signal components can be extracted.
An example of an application that uses such a signal difference detection is human detection. One sensor detects the presence / absence of a person, and the other sensor monitors the local environment as a reference (for example, a ceiling, a wall, etc. in a room). Thus, it is assumed that the plurality of sensors have different observation directions, and the target signal is a low-speed signal in the vicinity of DC (˜50 Hz). The disturbance noise is assumed to have the same influence on a plurality of sensors regardless of the sensor observation direction.
However, a configuration having a signal processing channel for each of a plurality of sensors has a problem that a circuit area is large and current consumption is also large.

FIG. 2 is a block diagram illustrating another example of a signal processing circuit when a measurement target is observed simultaneously by a plurality of sensors. In order to reduce the circuit area and current consumption, a signal processing circuit that performs signal processing in a time division manner using a selection circuit as shown in FIG. 2 can be considered.
In the signal processing circuit of FIG. 2, signal processing is performed in a time-sharing manner in accordance with the plurality of sensors 1a and 1b. Therefore, the amplifier circuit 21, the AD converter 22, the plurality of registers 3a and 3b, the selection circuit 5, and the control circuit 7 are used. And. Reference numeral 6 denotes an output circuit.
When the signal processing of the first sensor 1a is performed, the selection circuit 5 is switched, and the output signal of the first sensor 1a is amplified by the amplifier circuit 21, is AD-converted by the AD converter 22, and is transferred to the first register 3a. Stored. Next, when the signal processing of the second sensor 1b is performed, the selection circuit 5 is switched, and the output signal of the second sensor 1b is amplified by the amplifier circuit 21, AD-converted by the AD converter 22, Stored in the register 3b.
In this way, the selection circuit 5 switches the signal processing of the first sensor and the signal processing of the second sensor in a time-sharing manner based on the control signal of the control circuit 7, so that the measurement target can be selected by a plurality of sensors. Observe.

FIG. 3 is a timing chart of the signal processing circuit of FIG.
In the T1 section, the output signal of the first sensor 1a is selected by SW1 which is the selection circuit 5, and the output signal of the first sensor 1a is input to the input of the amplifier circuit 21 (1ch sensor signal). The amplified output signal of the first sensor 1a is accumulated by the AD converter 22 for a predetermined time and AD converted. Then, at the end of the T1 period, the output signal of the AD converter 22 at that timing is set as the first measurement data of the first sensor 1a by the enable signal (Enable1) input to the first register 3a. Are stored in the register 3a, and then held (n-th data).

Next, in the period T2, the output signal of the second sensor 1b is selected by SW2 which is the selection circuit 5, and the output signal of the second sensor 1b is input to the input of the amplifier circuit 21 (2ch sensor). signal). The amplified output signal of the second sensor 1b is integrated by the AD converter 22 for a predetermined time and AD converted. Then, at the end of the T2 period, the nth measurement data of the second sensor 1b is stored in the second register 3b by the enable signal (Enable2) input to the second register 3b, and then held. (Nth data).
By repeating this, a plurality of sensors can be signal-processed in a time division manner.
However, in the signal processing circuit of FIG. 2, when there is disturbance noise such as environmental temperature, the output in each channel is as follows, and the disturbance cannot be canceled.
First sensor: (S1 + N (t)) × α
Second sensor: (S1 + N (t ′)) × α
Here, S1 and S2 indicate output signals of the sensors, N (t) indicates disturbance noise at time t, and α indicates the gain of the amplifier circuit.

Since the disturbance noise changes due to environmental changes such as ambient temperature, it is difficult to remove the noise component even if the difference between the output data from the first sensor 1a and the second sensor 1b is taken. In particular, when t = T5 and t ′ = T6, the disturbance noises N (t) and N (t ′) are significantly different in magnitude, and it is difficult to remove noise components.
For example, in FIG. 3, assuming that the disturbance noise increases due to temperature or the like, the influence of the disturbance noise on the output data from the first sensor 1a in the T5 section and the output data from the second sensor 1b in the T6 section. Is significantly different. Therefore, it is difficult to remove the noise component even if the difference between the output data from the first sensor 1a and the output data from the second sensor 1b is taken.

In addition, the switching timing of the selection circuit 5 depends on the response time of the amplifier circuit and the AD conversion circuit of the signal processing circuit. When the response time is long with respect to the change of the disturbance noise, that is, when the signal processing is slow, the disturbance There is also a problem that the influence of noise becomes very large. Furthermore, if the response time is to be shortened, there is a problem that the current consumption becomes very large.
The present invention has been made in view of such a problem. The object of the present invention is to provide a sensor signal processing circuit that is less affected by disturbance noise and consumes less current when signal processing is performed on a plurality of sensors. An infrared sensor module and a sensor signal processing method are provided.

The present invention has been made to achieve such an object. The invention according to claim 1 is directed to a selection circuit for selecting output signals from a plurality of infrared sensors, and an output selected by the selection circuit. A signal processing circuit having a ΔΣ AD conversion circuit that AD converts a signal, and a control circuit that controls the selection circuit in a time-sharing manner, wherein the ΔΣ AD conversion circuit includes a plurality of integration capacitors corresponding to the infrared sensor; A sensor signal processing circuit comprising: a first switching unit that selects and switches any one of the plurality of integration capacitors.
According to a second aspect of the present invention, in the first aspect of the invention, the ΔΣ AD converter circuit includes a plurality of delay elements according to the integration capacitor, and one of the plurality of delay elements. And a second switching unit for selecting and switching.

According to a third aspect of the present invention, in the second aspect of the present invention, the first switching unit and the second switching unit are configured such that the selection circuit changes the first infrared sensor from a plurality of infrared sensors. When selecting, when selecting and switching the first integration capacitor and the first delay element from the plurality of integration capacitors and delay elements, the selection circuit selects the second infrared sensor from the plurality of infrared sensors. The second integration capacitor and the second delay element are selected and switched from a plurality of integration capacitors and delay elements.
According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the ΔΣ AD converter circuit switches the integration capacitor in a time-division manner and outputs a signal from the infrared sensor. It is characterized by accumulating and AD converting.

The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein the control circuit switches the first switching unit in a time-sharing manner in accordance with the selection circuit. It is characterized by controlling as follows.
According to a sixth aspect of the present invention, in the invention according to any one of the first to fifth aspects, the ΔΣ AD converter circuit has at least the number of integral capacitors equal to or greater than the number of the infrared sensors. It is a feature.
The invention according to claim 7 is the invention according to any one of claims 1 to 6, wherein the signal processing circuit further includes a filter circuit, and the filter circuit is connected to the ΔΣ AD converter circuit. In addition, the apparatus includes a plurality of filter capacitors that accumulate signals from the infrared sensors, and a third switching unit that selects and switches any one of the filter capacitors from the filter capacitors.

The invention according to claim 8 is the invention according to claim 7, wherein when the selection circuit selects the first infrared sensor from the plurality of infrared sensors, the third switching unit has a plurality of When the selection circuit selects the second infrared sensor from the plurality of infrared sensors, the second filter capacitor is selected from the plurality of filter capacitors and switched. It is characterized by.
The invention according to claim 9 is the invention according to any one of claims 1 to 8, wherein a plurality of output signals of the ΔΣ conversion circuit are stored corresponding to the plurality of infrared sensors. A register is further provided, and the control circuit controls timing for updating data stored in the plurality of registers.

  According to a tenth aspect of the present invention, in the invention according to any one of the first to ninth aspects, a selection circuit that selects output signals from a plurality of infrared sensors, and an output selected by the selection circuit. A signal processing circuit having a ΔΣ AD conversion circuit for AD converting a signal; a control circuit for controlling the selection circuit in a time-sharing manner; and a chopper modulation unit for switching polarities of output signals from the plurality of infrared sensors. The type AD conversion circuit includes a plurality of normal integration capacitors corresponding to normal output signals of the plurality of infrared sensors, a plurality of inversion integration capacitors corresponding to inverted output signals of the plurality of infrared sensors, And a fourth switching unit that selects and switches one of the integration capacitors for normal rotation and the plurality of inversion integration capacitors.

According to an eleventh aspect of the present invention, in the invention according to the tenth aspect, the ΔΣ AD converter circuit includes a plurality of forward rotation delay elements and the plurality of inversion integrations in accordance with the plurality of normal rotation integration capacitors. A plurality of inversion delay elements, and a fifth switching unit that selects and switches any one of the plurality of normal rotation delay elements and the plurality of inversion delay elements in accordance with a capacity; It is a feature.
According to a twelfth aspect of the invention, in the invention of the tenth or eleventh aspect, the signal processing circuit further includes a filter circuit, and each of the infrared sensors is arranged in accordance with the ΔΣ AD conversion circuit. A plurality of forward filter capacitors for storing the normal rotation signals from and a plurality of inversion filter capacitors for storing the inverted signals from the respective infrared sensors, and one of the filter capacitors is selected and switched. And a sixth switching unit.

  The invention according to claim 13 is the invention according to claim 12, wherein the fourth switching unit, the fifth switching unit, and the sixth switching unit are configured such that the selection circuit includes a plurality of infrared sensors. When the signal of the first infrared sensor is selected from the above and the chopper modulation unit makes a normal rotation signal, the first integration capacitor for normal rotation and the first delay element for normal rotation from a plurality of integration capacitors, delay elements and filter capacitors The first filter capacitor for forward rotation is selected and switched, and when the selection circuit selects a signal of the first infrared sensor from a plurality of infrared sensors and the chopper modulation unit uses the inverted signal as a reverse signal, The first inversion capacitor for inversion, the first delay element for inversion, and the first filter capacitor for inversion are selected and switched from the delay element and the filter capacitor, and the selection circuit switches from the plurality of infrared sensors to the second infrared sensor. Select the signal When the chopper modulation section uses a normal signal, the second normal capacitor for normal rotation, the second delay element for normal rotation, and the second filter capacitor for normal rotation are selected from a plurality of integral capacitors, delay elements, and filter capacitors. When the selection circuit selects the signal of the second infrared sensor from the plurality of infrared sensors and the chopper modulator uses the inverted signal, the second integration for inversion is performed from the plurality of integration capacitors, delay elements, and filter capacitors. The capacitor, the inversion second delay element, and the inversion second filter capacitor are selected and switched.

The invention according to claim 14 is the chopper demodulation according to any one of claims 10 to 13, wherein the difference between the normal signal and the inverted signal is calculated after the ΔΣ AD converter circuit. It is characterized by having a part.
The invention according to claim 15 is the invention according to claim 14, further comprising a plurality of registers for storing the outputs of the chopper demodulator corresponding to the plurality of infrared sensors. It is a feature.
The invention according to claim 16 is an infrared sensor module comprising the sensor signal processing circuit according to any one of claims 1 to 15 and a plurality of infrared sensors.

The invention described in claim 17 is the invention described in claim 16, characterized in that the number of the infrared sensors is four.
In the invention according to claim 18, the first output signal of the first infrared sensor is selected from a plurality of infrared sensors, the first output signal is signal-processed, and the first detection signal is used as the first detection signal. And a second output signal of the second infrared sensor is selected from a plurality of infrared sensors, and the second output signal is subjected to signal processing to obtain a second detection signal as a second detection signal. A second step of accumulating in the two capacitive elements, and at least the first step and the second step are repeated a plurality of times, and then the first detection signal and the second detection signal accumulated Sampling and storing as first data and second data, and outputting a difference between the stored first data and the second data. With sensor signal processing method That.

  According to a nineteenth aspect of the present invention, in the eighteenth aspect, the third output signal of the third infrared sensor is selected from a plurality of infrared sensors, and the third output signal is subjected to signal processing. A third step of accumulating in the third capacitive element as a third detection signal, and selecting a fourth output signal of the fourth infrared sensor from a plurality of infrared sensors, and subjecting the fourth output signal to signal processing The fourth step of accumulating the fourth detection element in the fourth capacitor element and repeating at least the first step, the second step, the third step, and the fourth step a plurality of times After that, the accumulated first detection signal, second detection signal, third detection signal, and fourth detection signal are sampled to obtain first data, second data, third data, fourth Storing the data as Is characterized in that it further comprises the step of said the third data and outputs the difference between the fourth data.

  According to a twentieth aspect of the present invention, in the invention of the eighteenth aspect, the first infrared sensor and the second infrared sensor are arranged to face each other, and the third infrared sensor and the first infrared sensor are arranged. 4 is arranged opposite to the infrared sensor and outputs the difference between the stored first data and the second data, or the difference between the stored third data and the fourth data. Is further included.

  According to the present invention, when signal processing is performed on a plurality of sensors, it is possible to realize a sensor signal processing circuit, an infrared sensor module, and a sensor signal processing method that are less affected by disturbance noise and consume less current.

It is a block diagram which shows an example of the signal processing circuit in the case of observing a measuring object simultaneously with a some sensor. It is a block diagram which shows the other example of the signal processing circuit in the case of observing a measuring object simultaneously with a some sensor. FIG. 3 is a timing chart of the signal processing circuit in FIG. 2. It is a block diagram for demonstrating the sensor signal processing circuit of this Embodiment 1. FIG. FIG. 5 is a diagram illustrating a timing chart of the sensor signal processing circuit of FIG. 4. It is a block diagram for demonstrating the sensor signal processing circuit of this Embodiment 2. FIG. It is a figure which shows the timing chart of the sensor signal processing circuit of FIG. It is a block diagram for demonstrating the sensor signal processing circuit of this Embodiment 3. It is a figure which shows the timing chart of the sensor signal processing circuit of FIG. It is a block diagram for demonstrating the sensor signal processing circuit of this Embodiment 4. It is a figure which shows the timing chart of the sensor signal processing circuit of FIG. It is a figure for demonstrating the calculation of the digital filter in FIG.

Embodiments of the present invention will be described below with reference to the drawings.
[Embodiment]
The sensor signal processing circuit according to the present embodiment includes a selection circuit that selects output signals from a plurality of infrared sensors, a signal processing circuit that includes a ΔΣ AD conversion circuit that AD converts the selected output signals, and a selection circuit. A control circuit that controls by division, and the ΔΣ AD converter circuit includes a plurality of integration capacitors corresponding to the infrared sensor, and a first switching unit that selects and switches any one of the plurality of integration capacitors And having.
In this embodiment, since the time division processing is possible by the selection circuit, low current consumption can be realized. Further, the current consumption can be suppressed by adopting a configuration in which the integration capacity corresponding to the infrared sensor is switched to perform AD conversion instead of increasing the response speed of the AD conversion circuit.

The ΔΣ AD conversion circuit includes a plurality of integration capacitors that accumulate the output signals from the infrared sensors, and a first switching unit that selects and switches any one of the integration capacitors. Thereby, the signal processing circuit can perform signal processing while accumulating the signal with the corresponding integration capacitor in accordance with the selected infrared sensor. Thereby, parallel signal processing of a plurality of infrared sensors becomes possible, and the influence of disturbance noise can be reduced.
For example, even if the amount of disturbance noise fluctuates during a predetermined data update interval, the data can be determined after performing a time division operation while accumulating the integration capacity in that interval, reducing the influence of disturbance noise be able to.

Further, the ΔΣ conversion circuit includes a plurality of delay elements according to the integration capacitance, and a second switching unit that selects and switches one of the delay elements from each delay element.
When the selection circuit selects the first infrared sensor from the plurality of infrared sensors, the first switching unit and the second switching unit include the first integration capacitor and the first delay element from the plurality of integration capacitors and delay elements. When the selection circuit selects the second infrared sensor from the plurality of infrared sensors, the second integration capacitor and the second delay element are selected and switched from the plurality of integration capacitors and delay elements. Examples include the configuration.

In addition, the amplifier circuit includes a plurality of integration capacitors for accumulating signals from the infrared sensors, and a third switching unit that selects and switches one of the integration capacitors according to the AD conversion circuit. . Thereby, the amplifier circuit can perform signal processing according to the selected infrared sensor while accumulating particularly a low-band signal with a corresponding integration capacitor. Thereby, also in the amplifier circuit, signal processing can be performed in accordance with the high-speed operation of the time division operation, and the influence of disturbance noise can be reduced.
The configuration may be an infrared sensor module including the above-described sensor signal processing circuit and a plurality of infrared sensors.
In addition, the control circuit controls the selection circuit to select output signals from a plurality of infrared sensors at a timing earlier than the environmental temperature fluctuation around the infrared sensor, thereby reducing the influence of disturbance noise. Can do.

  The sensor signal processing method of the present embodiment selects a first output signal of a first infrared sensor from a plurality of infrared sensors, performs signal processing on the first output signal, and outputs a first detection signal as a first detection signal. A first step of accumulating in the capacitive element; a second output signal of the second infrared sensor is selected from the plurality of infrared sensors; and the second output signal is signal-processed to obtain a second detection signal as a second detection signal. The second step of accumulating in the capacitor element, and at least the first step and the second step are repeated a plurality of times, and then the accumulated first detection signal and second detection signal are used. Sampling and storing as first data and second data.

  Since each detection signal is processed while being accumulated in each capacitor element and then sampled, the influence of disturbance noise can be reduced. For example, by performing the above steps, disturbance noise of approximately the same level affects the first data and the second data, and the difference between the stored first data and second data is calculated. The disturbance noise component can be canceled after the output step. In addition, processing can be performed in a time-sharing manner, current consumption is small, and sensor signal processing can be performed.

Hereinafter, the present embodiment will be specifically described with reference to the drawings.
<Embodiment 1>
FIG. 4 is a block diagram for explaining the sensor signal processing circuit according to the first embodiment. In the figure, reference numerals 31a and 31b are first and second infrared sensors, 32 is a signal processing circuit, 33a and 33b are first and second registers, 34 is a digital interface unit, 35 is a selection circuit, 36 is an output circuit, Reference numeral 37 is a control circuit, 41 is an amplifier circuit, 42 is a ΔΣ ADC (delta sigma AD converter circuit), 421 is an integrator, 422 is a quantizer, 423 is a DAC, 424a and 424b are delay elements.

The sensor signal processing circuit according to the first embodiment includes a selection circuit 35 that selects output signals from the plurality of infrared sensors 31a and 31b, and a ΔΣ AD conversion circuit 42 that AD converts the output signal selected by the selection circuit 35. The signal processing circuit 32 and a control circuit 37 that controls the selection circuit 35 in a time-sharing manner are provided. The ΔΣ AD conversion circuit 42 includes a plurality of integration capacitors corresponding to the infrared sensors 31a and 31b, and the plurality of integration capacitors. Are provided with first switching units SW1C and SW2C that select and switch any of the integration capacitors.
That is, the sensor signal processing circuit of the first embodiment includes a selection circuit 35, a signal processing circuit 32, a control circuit 37, first and second registers 33a and 33b, and a digital interface unit 34.

The selection circuit (SW1A, SW2A) 35 selects the output signal S1 or S2 from the first and second infrared sensors 31a, 31b.
The signal processing circuit 32 processes the selected output signal S1 or S2. The ΔΣ AD conversion circuit 42 is a first-order ΔΣ conversion circuit, includes an integrator 421, a quantizer 422, and a DAC 423, and includes first and second integration capacitors corresponding to the infrared sensors 31a and 31b, 1st and 2nd delay elements 424a and 424b, 1st switching part SW1C and SW2C which selectively switch integration capacity, and 2nd switching part which selectively switches 1st and 2nd delay elements 424a and 424b SW1D and SW2D.
The control circuit 37 generates a control signal for controlling the selection circuit 35 in a time division manner. Also, enable signals (Enable1, Enable2) are output to the first and second registers 33a, 33b.

The first switching units SW1C and SW2C select and switch one of the integration capacitors.
The second switching units SW1D and SW2D select and switch one of the delay elements from the delay elements 424a and 424b.
The first and second registers 33a and 33b store and hold output signals of signal processing circuits corresponding to the infrared sensors 31a and 31b, respectively.
The digital interface unit 34 receives the output data of the first and second registers 33a and 33b and outputs the digital data.
In the first embodiment, when signal processing is performed in a time-division manner, signals processed by the first and second integration capacitors are accumulated according to the selected first and second infrared sensors 31a and 31b. . Since signal processing can be performed while accumulating, the influence of disturbance noise can be reduced.

FIG. 5 is a timing chart of the sensor signal processing circuit of FIG.
SW1A, 1C, and 1D repeat ON / OFF at the same timing, and SW2A, 2C, and 2D repeat ON / OFF at the same timing. In addition, SW1A, 1C, and 1D and SW2A, 2C, and 2D operate in reverse. Thereby, the output signals (S1, S2) of the first and second infrared sensors 31a, 31b are alternately inputted to the input of the amplifier circuit (amplifier).

  In each register 33a, 33b, in a section (T1 + T2) in which data is updated from the (n-1) th data to the nth data, the signal processing circuit 32 outputs the output signals of the first and second infrared sensors 31a, 31b. For example, signal processing is performed while accumulating signals by time division at a frequency eight times the data update frequency. At the data update timing (timing at which the enable signals 1 and 2 become High), signals corresponding to the first and second infrared sensors 31a and 31b, which are outputs of the signal processing circuit 32, are respectively sent to the registers 33a and 33b. Stored and retained.

  That is, compared with the timing chart of FIG. 3, the time division operation for selecting the infrared sensor is faster in FIG. In FIG. 3, the timing of storing in the first and second registers 33a and 33b is such that the output data from the first infrared sensor 31a is updated at the end of the data update section T1, and at the end of the data update section T2. While the output data from the second infrared sensor 31b is updated, in FIG. 5, the output data from the first and second infrared sensors 31a and 31b are both updated at the end of the data update section T1 + T2. .

Here, assuming that there is a disturbance noise N (t), the output corresponding to the first infrared sensor 31a and the output corresponding to the second infrared sensor 31b are as follows.
First sensor: (S1 + N (t)) × α
Second sensor: (S2 + N (t ′)) × α
Here, S1 and S2 indicate output signals of the sensors, N (t) indicates disturbance noise at time t, and α indicates the gain of the amplifier circuit. In the first embodiment, since the time-sharing operation is quickly performed with respect to the fluctuation of the disturbance noise, the first infrared sensor 31a and the second infrared sensor 31b are almost equally affected by the disturbance noise, and N (t) ≈ N (t ′).

Therefore, it can be seen that the influence of the disturbance noise can be greatly reduced compared to the case of the conventional sensor signal processing circuit in the T5 + T6 section where the fluctuation amount of the disturbance noise is large compared to the case of FIG. That is, it is possible to realize human detection that is robust to the environment (for example, room temperature) (an internal mechanism or property that prevents a certain system from being changed by the influence of a disturbance such as stress or environmental change).
If the cycle of the switching timing of SW1A and 2A is simply shortened in the circuit of FIG. 2, the switching cycle of the internal signal processing circuit is shortened at the same time, and the signal processing time is sufficient for the response time. In the first embodiment, in order to avoid lack of response time, the signal processing is performed while accumulating the signal being processed by each integration capacitor of the ΔΣ conversion circuit 42, thereby enabling switching in a short cycle. In addition, the current consumption is extremely small as compared with the case where the response speed of the amplifier circuit 41 or the ADC 42 itself is greatly improved.

Specifically, when the operating frequency of the internal circuit is increased by the conventional method, it is possible to obtain a result of N (t) ≈N (t ′). However, the operating frequency of the clock and the response of the internal circuit are reduced. Since it is necessary to increase the speed, there is a demerit that the current consumption of the oscillation circuit and the internal circuit is much larger than that of the present embodiment.
As described above, according to the first embodiment, the disturbance noise resistance can be improved and the current consumption can be reduced by performing the time division operation of the infrared sensor at high speed.

<Embodiment 2>
FIG. 6 is a block diagram for explaining a sensor signal processing circuit according to the second embodiment. In the figure, reference numeral 411 denotes a gain amplifier, 412 denotes an anti-aliasing filter, and 413 denotes an amplifier. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.
In the sensor signal processing circuit according to the second embodiment, in addition to the first embodiment, the amplifier circuit 41 includes an anti-aliasing filter 412, a gain amplifier 411, and third switching units SW1E and SW2E.

For example, when a filter circuit or the like is used as the amplifier circuit 41, the filter circuit has a capacity corresponding to each infrared sensor and is switched by time division by the third switching units SW1E and SW2E. Even when a lower-band signal is input, since the amplifier 413 amplifies and outputs the signal while accumulating each signal with the capacity of the filter circuit, the lower-band signal is more parallel than the time-division switching. Analog filter processing is possible.
In the second embodiment, in addition to the integration capacitor and delay elements 424a and 424b of the ΔΣ AD converter circuit 42, the capacitor of the anti-aliasing filter 412 is also provided corresponding to the infrared sensor, and the third switching units SW1E and SW2E It is the structure which can be switched by time division. The third switching units SW1E and SW2E are switched in a time division manner by a control signal from the control circuit 37.

FIG. 7 is a timing chart of the sensor signal processing circuit of FIG.
SW1A, 1C, 1D, and 1E repeat ON / OFF at the same timing, SW2A, 2C, 2D, and 2E repeat ON / OFF at the same timing, SW1A, 1C, 1D, and 1E, and SW2A, 2C, 2D, and SWE The operation reverse to 2E is performed.
Thus, the output signals of the first and second infrared sensors 31a and 31b are alternately input to the input of the amplifier circuit (amplifier) 41.
In the anti-alias filter 412, when the first infrared sensor 31a is selected by the selection circuit 35 (SW1A is ON), the third switching unit is switched to select the first capacitor (SW1E is ON), When the second infrared sensor 31b is selected by the selection circuit 35 (SW2A is ON), the third switching unit is switched to select the second capacity (SW2E is ON),

When the third infrared sensor (not shown) is selected by the selection circuit 35 (SW3A is ON), the third switching unit is switched (SW3E is ON) so as to select the third capacitor.
When the fourth infrared sensor (not shown) is selected by the selection circuit 35 (SW4A is ON), the third switching unit is switched to select the fourth capacity (SW4E is ON). . At this time, the output from each infrared sensor is stored in each capacitor, and the stored output is output to the ΔΣ AD conversion circuit 42 in the next stage.
As a result, even when a low-band signal is input from the infrared sensor to the anti-aliasing filter 412 in a time-sharing manner, a signal having a band lower than the switching frequency can be processed because of the capacity corresponding to each infrared sensor. it can.

<Third Embodiment>
FIG. 8 is a block diagram for explaining the sensor signal processing circuit of the third embodiment. In the figure, reference numerals 31a to 31d are first to fourth infrared sensors, 33a to 33d are first to fourth registers, 38 is a digital filter circuit, 38a to 38d are first to fourth digital filters, and 424a to 424d. Indicates first to fourth delay elements. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.
The third embodiment is a case where there are four output signals from the infrared sensor.
The amplifier circuit 41 includes a GAIN circuit (amplifier) 411 and an anti-alias filter 412.
The ΔΣ AD conversion circuit 42 is a primary ΔΣ conversion circuit. The ΔΣ conversion circuit includes an integrator 421, a quantizer 422, and a DAC 423, corresponding to the infrared sensor, first to fourth integration capacitors that are storage elements, and similarly, first to first integration elements that are storage elements. 4 delay elements 424a to 424d. In addition, the first switching units SW1C to SW4C that selectively switch the integration capacitance and the second switching units SW1D to SW4D that selectively switch the first to fourth delay elements 424a to 424d are provided.

In the third embodiment, the signal processing circuit 32 further includes first to fourth digital filters 38a to 38d corresponding to a plurality of infrared sensors. The digital filters 38 a to 38 d are connected between the registers 33 a to 33 d and the ΔΣ AD conversion circuit 42.
Further, first to fourth registers 33a to 33d for storing output data of the digital filters 38a to 38d are provided. A control signal is input from the control circuit 37 to each of the digital filters 38a to 38d, and the signals input corresponding to the respective infrared sensors are averaged. In the third embodiment, a digital filter is provided corresponding to each infrared sensor. However, averaging may be performed in a time division manner using one digital filter corresponding to each infrared sensor. In that case, the digital filter holds the output obtained by averaging the signals of the respective infrared sensors, and averages the held result and the digital signal from the ΔΣ conversion circuit next. And the form etc. which are stored in each register | resistor 33a-33d at predetermined timing according to the enable signal of a control circuit are mentioned.

Corresponding to the first infrared sensor 31a, the control circuit 37 selects the first capacitor, which is the capacitor of the antialiasing filter 412, and selects the first integration capacitor and the first delay element 424a of the ΔΣ AD conversion circuit 42. To do. In addition, the control circuit 37 generates a control signal that averages and holds the output of the ΔΣ conversion circuit in the first digital filter 38a.
Corresponding to the second infrared sensor 31b, the control circuit 37 selects the second capacitor, which is the capacitor of the anti-aliasing filter 412, and selects the second integration capacitor and the second delay element 424b of the ΔΣ AD conversion circuit 42. To do. Further, the control circuit 37 generates a control signal that averages and holds the output of the ΔΣ conversion circuit in the second digital filter 38b.

Corresponding to the third infrared sensor 31c, the control circuit 37 selects the third capacitor, which is the capacitor of the antialiasing filter 412, and selects the third integration capacitor and the third delay element 424c of the ΔΣ AD conversion circuit 42. To do. In addition, the control circuit 37 generates a control signal that averages and holds the output of the ΔΣ conversion circuit in the third digital filter 38c.
Corresponding to the fourth infrared sensor 31d, the control circuit 37 selects the fourth capacitor, which is the capacitor of the antialiasing filter 412, and selects the fourth integration capacitor and the fourth delay element 424d of the ΔΣ AD conversion circuit 42. To do. In addition, the control circuit 37 generates a control signal that averages and holds the output of the ΔΣ conversion circuit in the fourth digital filter 38d.
Further, by adopting a configuration including the four infrared sensors 31a to 31d, it is possible to realize more accurate or various human sensors.

FIG. 9 is a timing chart of the sensor signal processing circuit of FIG.
The output signals (S1 to S4) of the infrared sensor selected by SW1A to 4A are input to the amplifier. At this time, for 1C to 4C, 1D to 4D, and 1E to 4E, those corresponding to the same channel (selection of the output signal of the infrared sensor) as SW1A to 4A are turned ON.
In the timing chart of FIG. 9, the time division operation is performed four times in the section in which the output data from the four infrared sensors is updated. In the section where each register is updated from the (n-1) th data to the nth data, the signal processing circuit 32 outputs the output signals of the first to fourth infrared sensors 31a to 31d, for example, 4 of the data update frequency. Signal processing is performed while accumulating signals by time division at double frequency.

First, SW1A is turned ON, and the output of the first infrared sensor 31a is input to the GAIN circuit (amplifier in FIG. 8) 411. At this time, SW1C, SW1D, and SW1E are selected and AD-converted by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the first digital filter 38a, and an averaging process is performed. After a predetermined period, the switch is turned off, and the averaged result is held in the first digital filter 38a.
Next, SW2A is turned ON, and the output of the second infrared sensor 31b is input to the GAIN circuit (amplifier in FIG. 8) 411. At this time, SW2C, SW2D, and SW2E are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the AD conversion result is input to the second digital filter 38b, and an averaging process is performed. After a predetermined period, the switch is turned off, and the averaged result is held in the second digital filter 38b.

Next, SW3A is turned ON, and the output of the third infrared sensor 31c is input to the GAIN circuit (amplifier in FIG. 8) 411. At this time, SW3C, SW3D, and SW3E are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the third digital filter 38c, and an averaging process is performed. After a predetermined period, the switch is turned off, and the averaged result is held in the third digital filter 38c.
Next, SW4A is turned ON, and the output of the fourth infrared sensor 31d is input to the GAIN circuit (amplifier in FIG. 8) 411. At this time, SW4C, SW4D, and SW4E are selected and AD-converted by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the AD conversion result is input to the fourth digital filter 38d, and an averaging process is performed. After a predetermined period, the switch is turned off, and the averaged result is held in the fourth digital filter 38d.

Next, SW1A is turned ON again, and the output of the first infrared sensor 31a is input to the GAIN circuit (amplifier in FIG. 8) 411. At this time, SW1C, SW1D, and SW1E are selected and AD-converted by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the AD converted result is input to the first digital filter 38a, and the averaging process is performed together with the result held last time. After a predetermined period, the switch is turned off, and the averaged result is held in the first digital filter 38a.
This operation is repeated a plurality of times. In the timing chart of FIG. 9, the process is repeated four times, and the fourth time is the data update timing.
At the data update timing, the first to fourth enable signals become High, and the signals corresponding to the first to fourth infrared sensors 31a to 31d are stored and held in the respective registers.

In the fourth time, SW1A is turned ON, and the output of the first infrared sensor 31a is input to the GAIN circuit (amplifier in FIG. 8) 411. At this time, SW1C, SW1D, and SW1E are selected and AD-converted by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the AD converted result is input to the first digital filter 38a, and the averaging process is performed together with the result held last time. After a predetermined period, the switch is turned off, and the result averaged by the first digital filter 38a by the first enable signal is stored in the first register 33a.
Similarly, the second to fourth infrared sensors 31b to 31d are also stored in the second to fourth registers 33b to 33d, respectively. Thereby, at the data update timing, the (n-1) th data is sequentially updated to the nth data.

<Embodiment 4>
FIG. 10 is a block diagram for explaining a sensor signal processing circuit according to the fourth embodiment. In the figure, reference numerals 38a1_P, 38a1_N to 38d1_P, 38d1_N denote digital filters, and 39a to 39d, 43 denote chopper demodulation units. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.
This is a specific example of the sensor signal processing circuit according to the fourth embodiment, in which a chopper modulation / demodulation operation is added to the third embodiment.
By applying chopper modulation to the signal processing, the offset of the internal circuit itself (that is, in the signal processing circuit) can be canceled.

  The sensor signal processing circuit of FIG. 10 includes a selection circuit 35, a signal processing circuit 32 having a gain amplifier 411, an Henrialia filter 412 and a ΔΣ AD conversion circuit 42, digital filters 38a1_P, 38a1_N to 38d4_P, 38d4_N, The first to fourth registers 33a to 33d and the digital interface unit 34 are provided. A chopper modulation unit 43 is provided between the selection circuit 35 and the gain amplifier 411. Also, between the digital filters 38a1_P and 38a1_N and the first register 33a, between the digital filters 38b2_P and 38b2_N and the second register 33b, between the digital filters 38c3_P and 38c3_N and the first register 33c, and the digital filter 38d4_P , 38d4_N and the fourth register 33d include chopper demodulation units 39a to 39d.

The polarity of the output signal of each infrared sensor is switched by the chopper modulation unit 43, and the signal input to the ΔΣ AD conversion circuit 42 is a signal in which the polarity repeats normal rotation and inversion. On the other hand, since the signal offset from the signal processing circuit to the digital filter is a DC component, the signal from the infrared sensor and the offset can be separated as a frequency band.
Further, when the modulation is performed at a frequency faster than the response speed of the circuit as the chopper frequency to be chopper-modulated as in the fourth embodiment, the integration capacity of the ΔΣ AD converter circuit corresponds to each infrared sensor. Prepare two for chopper forward rotation and reverse rotation. In addition, in addition to corresponding to each infrared sensor, two delay elements for a chopper forward rotation and an inversion are prepared for the ΔΣ AD conversion circuit.

In addition, for the capacity of the anti-aliasing filter 412, in addition to corresponding to each infrared sensor, two for normal rotation and one for inversion are prepared.
That is, the number of infrared sensors × 2 (for forward rotation and for inversion) integration capacitors, delay elements, and capacitors.
Similarly, the digital filter has the number of infrared sensors × 2 (for forward rotation and for inversion).
The chopper demodulating unit takes a difference between the chopper normal rotation signal and the chopper inversion signal. Thereby, the offset component of the internal circuit is canceled, and the infrared sensor signal can be detected with high accuracy.

FIG. 12 is a diagram for explaining the calculation of the digital filter in FIG.
Specifically, as shown in FIG. 12, the difference between the results held in the digital filter 38a1_P and the digital filter 38a1_N is calculated by a logic circuit or the like. The same applies to the digital filter 38b1_P and the digital filter 38b1_N, the digital filter 38c1_P and the digital filter 38c1_N, the digital filter 38d1_P, and the digital filter 38d1_N.
In addition, as long as the difference between the normal signal and the inverted signal can be calculated, any mode may be used, and an operation of multiplying the inverted signal by -1 and adding it to the normal signal is performed. But you can. In the fourth embodiment, the chopper demodulation is designated for the AD converted digital signal. However, the chopper demodulation is realized by an analog circuit before AD conversion (for example, after output of the anti-aliasing filter circuit). It may be a form to do.

FIG. 11 is a timing chart of the sensor signal processing circuit of FIG.
In the timing chart of FIG. 11, the time division operation is performed four times in the section in which the output data from the four infrared sensors is updated. Further, in addition to the time division operation, chopper modulation for switching the polarity of the output signal is also performed.
The output signals (S1 to S4) of the infrared sensors selected by SW1A to 4A are input to the gain amplifier 411 with the output polarity switched by the chopper modulation unit 43, respectively. In FIG. 11, the forward rotation signal S1P, the reverse signal S1N of the infrared sensor 1, the forward rotation signal S2P of the infrared sensor 2, the reverse signal S2N, the forward rotation signal S3P of the infrared sensor 3, the reverse rotation signal S3N, and the forward rotation signal of the infrared sensor 4 S4P and inverted signal S4N are input to the amplifier in this order.

When the chopper modulation unit 43 outputs a signal in the normal rotation, SW1C to 4C_P, SW1D to 4D_P, and SW1E to 4E_P that correspond to the same channel as SW1A to 4A (selection of the output signal of the infrared sensor) Turn on.
On the other hand, when the signal is inverted and output by the chopper modulation unit 43, SW1C to 4C_N, SW1D to 4D_N, and SW1E to 4E_N corresponding to the same channel as SW1A to 4A (selection of the output signal of the infrared sensor) Turns on.

Therefore, AD conversion is performed while accumulating signals in each polarity of each infrared sensor. Specifically, it is as follows.
1) The first outside line sensor is selected SW1A is turned ON, and the output of the first infrared sensor is input to the GAIN circuit (amplifier in FIG. 10) 411. First, SW1C_P, SW1D_P, and SW1E_P are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the digital filter 1_P, and an averaging process is performed. After a predetermined period, SW1C_P, SW1D_P, and SW1E_P are turned off, and the averaged result is held in the digital filter 1_P. Next, SW1C_N, SW1D_N, and SW1E_N are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the digital filter 1_N, and an averaging process is performed. After a predetermined period, SW1C_N, SW1D_N, and SW1E_N are turned off, and the averaged result is held in the digital filter 1_N. Accordingly, the normal rotation signal of the first infrared sensor 31a is held in the digital filter 1_P, and the inverted signal of the first infrared sensor 31a is held in the digital filter 1_N. Then, the difference between them is calculated by the circuit shown in FIG.

2) The second infrared sensor is selected SW2A is turned ON, and the output of the second infrared sensor 31b is input to the GAIN circuit (amplifier in FIG. 10) 411. First, SW2C_P, SW2D_P, and SW2E_P are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the digital filter 2_P, and an averaging process is performed. After a predetermined period, SW2C_P, SW2D_P, and SW2E_P are turned off, and the averaged result is held in the digital filter 2_P. Next, SW2C_N, SW2D_N, and SW2E_N are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the digital filter 2_N, and an averaging process is performed. After a predetermined period, SW2C_N, SW2D_N, and SW2E_N are turned off, and the averaged result is held in the digital filter 2_N. Accordingly, the normal rotation signal of the second infrared sensor 31b is held in the digital filter 2_P, and the inverted signal of the second infrared sensor 31b is held in the digital filter 2_N. Then, the difference between them is calculated by the circuit shown in FIG.

3) The third infrared sensor is selected SW3A is turned ON, and the output of the third infrared sensor 31c is input to the GAIN circuit (amplifier in FIG. 10) 411. First, SW3C_P, SW3D_P, and SW3E_P are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the digital filter 2_P, and an averaging process is performed. After a predetermined period, SW3C_P, SW3D_P, and SW3E_P are turned off, and the averaged result is held in the digital filter 3_P. Next, SW3C_N, SW3D_N, and SW3E_N are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the digital filter 3_N, and an averaging process is performed. After a predetermined period, SW3C_N, SW3D_N, and SW3E_N are turned off, and the averaged result is held in the digital filter 3_N. Accordingly, the normal rotation signal of the third infrared sensor 31c is held in the digital filter 3_P, and the inverted signal of the third infrared sensor 31c is held in the digital filter 3_N. Then, the difference between the two is calculated based on the held result by the circuit shown in FIG.

4) The fourth infrared sensor is selected SW4A is turned ON, and the output of the infrared sensor 4 is input to the GAIN circuit (amplifier in FIG. 10) 411. First, SW4C_P, SW4D_P, and SW4E_P are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the result of AD conversion is input to the digital filter 4_P, and an averaging process is performed. After a predetermined period, SW4C_P, SW4D_P, and SW4E_P are turned off, and the averaged result is held in the digital filter 4_P. Next, SW4C_N, SW4D_N, and SW4E_N are selected and subjected to AD conversion by the ΔΣ conversion circuit via the anti-aliasing filter 412. Then, the AD converted result is input to the digital filter 4_N, and an averaging process is performed. After a predetermined period, SW4C_N, SW4D_N, and SW4E_N are turned off, and the averaged result is held in the digital filter 4_N. Accordingly, the normal rotation signal of the fourth infrared sensor 31d is held in the digital filter 4_P, and the inverted signal of the fourth infrared sensor 31d is held in the digital filter 4_N. Then, the difference between them is calculated by the circuit shown in FIG.

Next, SW1A is turned ON again, the AD converted result is input to the digital filter 1_P, and the averaging process is performed together with the result held last time. After the predetermined period, the averaged result is held in the digital filter 1_P. Similarly, the result of AD conversion is input to the digital filter 1_N, and an averaging process is performed together with the result held last time. After the predetermined period, the averaged result is held in the digital filter 1_N. Based on the stored result, the difference between the two is calculated.
This operation is repeated a plurality of times. In the timing chart of FIG. 11, the process is repeated four times, and the fourth time is the data update timing.
At the data update timing, the first to fourth enable signals become High, and the difference between the normal signal and the inverted signal of the first to fourth infrared sensors 31a to 31d of the chopper demodulator is stored in each register. And retained. Specifically, it is as follows.

In the fourth time, as described in 1) above, first, the normal rotation signal is AD-converted by the ΔΣ conversion circuit. Then, the AD converted result is input to the digital filter 1_P, the averaging process is performed together with the result held last time, and the digital filter 1_P holds it. Similarly, the digital filter 1_N is also input with the AD converted result, and is averaged together with the previously held result and held. Then, the difference between the held results is calculated by the chopper demodulator. The result calculated by the first enable signal is stored in the first register 33a. In FIG. 11, it is stored in the first register 33a at the fall of the first enable signal, and the (n-1) th data is updated to the nth data.
Similarly, the second to fourth infrared sensors 31b to 31d are also stored in the second to fourth registers 33b to 33d, respectively. Thereby, at the data update timing, the (n-1) th data is sequentially updated to the nth data.

As described above, in the time division signal processing of a plurality of sensors, it is possible to make the appearance of disturbance noise between the sensor signals equal. Even if the circuit itself has a slow response, the time-dependent difference in disturbance noise between sensor signals is reduced.
Further, the present invention can be applied in the field of motion detection in which the signal from the sensor is faster than the human detection described as an example.
Further, an infrared sensor module including the above-described sensor signal processing circuit and a plurality of infrared sensors can be realized. Also, an infrared sensor module having four infrared sensors can be realized.

Next, a sensor signal processing method will be described.
A first step of selecting a first output signal of the first infrared sensor from a plurality of infrared sensors, signal-processing the first output signal, and storing the first output signal as a first detection signal in the first capacitive element; A second step of selecting a second output signal of the second infrared sensor from the plurality of infrared sensors, processing the second output signal, and storing the second output signal as a second detection signal in the second capacitive element; Sampling at least the first step and the second step a plurality of times and then sampling the stored first detection signal and second detection signal and storing them as first data and second data And a step of outputting a difference between the stored first data and second data.

A third step of selecting a third output signal of the third infrared sensor from the plurality of infrared sensors, processing the third output signal, and storing the third output signal as a third detection signal in the third capacitive element; And a fourth step of selecting a fourth output signal of the fourth infrared sensor from the plurality of infrared sensors, subjecting the fourth output signal to signal processing, and storing the fourth output signal as a fourth detection signal in the fourth capacitive element. And at least the first step, the second step, the third step, and the fourth step are repeated a plurality of times, and then the accumulated first detection signal, second detection signal, third detection signal, Sampling the fourth detection signal and storing it as first data, second data, third data, and fourth data, and outputting a difference between the stored third data and fourth data Further comprising the steps of:
In addition, the first infrared sensor and the second infrared sensor are arranged to face each other, the third infrared sensor and the fourth infrared sensor are arranged to face each other, and the stored first data and second data are stored. The method further includes a step of outputting a difference with the data or outputting a difference between the stored third data and the fourth data.

DESCRIPTION OF SYMBOLS 1a, 1b 1st and 2nd sensor 2 Signal processing circuit 3a, 3b Register 4 Digital interface 7 Control circuit 21a, 21b Amplifier circuit 22a, 22b AD converter 31a-31d 1st-4th infrared sensor 32 Signal processing circuit 33a to 33d First to fourth registers 34 Digital interface unit 35 Selection circuit 36 Output circuit 37 Control circuit 38 Digital filter circuits 38a to 38d First to fourth digital filters 38a1_P, 38a1_N to 38d1_P, 38d1_N Digital filters 39a to 39d , 43 Chopper demodulator 41 Amplifier circuit 42 ΔΣ ADC (Delta Sigma AD converter circuit)
411 Gain amplifier 412 Antialias filter 413 Amplifier 421 Integrator 422 Quantizer 423 DAC
424a to 424d 1st to 4th delay elements

Claims (20)

A selection circuit for selecting output signals from a plurality of infrared sensors;
A signal processing circuit having a ΔΣ AD conversion circuit for AD converting the output signal selected by the selection circuit;
A control circuit for controlling the selection circuit in a time-sharing manner,
The ΔΣ AD conversion circuit includes a plurality of integration capacitors corresponding to the infrared sensor,
A sensor signal processing circuit comprising: a first switching unit that selects and switches any one of the plurality of integration capacitors.   2. The ΔΣ AD conversion circuit includes a plurality of delay elements according to the integration capacitor, and a second switching unit that selects and switches any one of the plurality of delay elements. Sensor signal processing circuit. The first switching unit and the second switching unit are:
When the selection circuit selects the first infrared sensor from the plurality of infrared sensors, the first integration capacitor and the first delay element are selected and switched from the plurality of integration capacitors and delay elements,
3. When the selection circuit selects a second infrared sensor from a plurality of infrared sensors, the second integration capacitor and the second delay element are selected and switched from a plurality of integration capacitors and delay elements. Sensor signal processing circuit.   The sensor signal processing circuit according to claim 1, wherein the ΔΣ AD conversion circuit switches the integration capacitor in a time division manner, accumulates a signal from the infrared sensor, and performs AD conversion.   The sensor signal processing circuit according to any one of claims 1 to 4, wherein the control circuit controls the first switching unit to switch in a time division manner in accordance with the selection circuit.   The sensor signal processing circuit according to claim 1, wherein the ΔΣ AD conversion circuit includes at least the number of the integration capacitors equal to or more than the number of the infrared sensors. The signal processing circuit further includes a filter circuit,
The filter circuit includes a plurality of filter capacitors for accumulating signals from the infrared sensors and a third switching unit for selecting and switching one of the filter capacitors in accordance with the ΔΣ AD conversion circuit. The sensor signal processing circuit according to any one of claims 1 to 6. The third switching unit includes:
When the selection circuit selects a first infrared sensor from a plurality of infrared sensors, the first filter capacitance is selected from a plurality of filter capacitors and switched,
8. The sensor signal processing circuit according to claim 7, wherein when the selection circuit selects a second infrared sensor from a plurality of infrared sensors, the second filter capacitance is selected and switched from a plurality of filter capacitors. Corresponding to the plurality of infrared sensors, further comprising a plurality of registers for storing output signals of the ΔΣ conversion circuit,
The sensor signal processing circuit according to claim 1, wherein the control circuit controls timing for updating data stored in the plurality of registers. A selection circuit for selecting output signals from a plurality of infrared sensors;
A signal processing circuit having a ΔΣ AD conversion circuit for AD converting the output signal selected by the selection circuit;
A control circuit for controlling the selection circuit in a time-sharing manner;
A chopper modulation unit that switches the polarity of output signals from the plurality of infrared sensors,
The ΔΣ AD converter circuit is
A plurality of normal integration capacitors corresponding to normal output signals of the plurality of infrared sensors;
A plurality of inversion integrating capacitors corresponding to the inversion output signals of the plurality of infrared sensors;
10. A sensor according to claim 1, further comprising: a fourth switching unit that selects and switches any one of the plurality of forward integration capacitors and the plurality of inversion integration capacitors. Signal processing circuit.   The ΔΣ AD conversion circuit includes a plurality of forward delay elements according to the plurality of forward integration capacitors, a plurality of inversion delay elements according to the plurality of inversion integration capacitors, the plurality of forward rotation delay elements, and The sensor signal processing circuit according to claim 10, further comprising: a fifth switching unit that selects and switches any one of the plurality of inversion delay elements. The signal processing circuit further includes a filter circuit,
The filter circuit includes a plurality of forward filter capacitors that accumulate forward signals from the infrared sensors and a plurality of inversion filter capacitors that accumulate inverted signals from the infrared sensors in accordance with the ΔΣ AD converter circuit. The sensor signal processing circuit according to claim 10, further comprising: a sixth switching unit that selects and switches one of the filter capacitors from each filter capacitor. The fourth switching unit, the fifth switching unit, and the sixth switching unit are:
When the selection circuit selects the signal of the first infrared sensor from the plurality of infrared sensors and the chopper modulation unit uses the normal rotation signal, the first integration capacitor for forward rotation is selected from the plurality of integration capacitors, delay elements, and filter capacitors. And switching between the first delay element for normal rotation and the first filter capacitor for normal rotation,
When the selection circuit selects the signal of the first infrared sensor from the plurality of infrared sensors and the chopper modulation unit uses the inverted signal as the inverted signal, the first integration capacitor for inversion from the plurality of integration capacitors, the delay element, and the filter capacitor Select and switch the first delay element for inverting and the first filter capacitor for inverting,
When the selection circuit selects the signal of the second infrared sensor from the plurality of infrared sensors and the chopper modulation unit sets the normal rotation signal, the second integration capacitor for normal rotation is selected from the plurality of integration capacitors, delay elements, and filter capacitors. And switching between the second delay element for normal rotation and the second filter capacitor for normal rotation,
When the selection circuit selects the signal of the second infrared sensor from the plurality of infrared sensors and the chopper modulation unit uses the inverted signal as the inverted signal, the second integration capacitor for inversion from the plurality of integration capacitors, the delay element, and the filter capacitor The sensor signal processing circuit according to claim 12, wherein the inversion second delay element and the inversion second filter capacitor are selected and switched.   The sensor signal processing circuit according to any one of claims 10 to 13, further comprising a chopper demodulating unit that calculates a difference between the normal signal and the inverted signal at a subsequent stage of the ΔΣ AD conversion circuit.   The sensor signal processing circuit according to claim 14, further comprising a plurality of registers in which outputs of the chopper demodulating unit are stored corresponding to the plurality of infrared sensors.   An infrared sensor module comprising the sensor signal processing circuit according to claim 1 and a plurality of infrared sensors.   The infrared sensor module according to claim 16, wherein the number of the infrared sensors is four. A first step of selecting a first output signal of a first infrared sensor from a plurality of infrared sensors, processing the first output signal, and storing the first output signal in a first capacitive element as a first detection signal; ,
A second step of selecting a second output signal of the second infrared sensor from a plurality of infrared sensors, subjecting the second output signal to signal processing, and storing the second detection signal as a second detection signal in the second capacitive element; ,
At least the first step and the second step are repeated a plurality of times, and then the accumulated first detection signal and second detection signal are sampled to obtain first data and second data. As a step to store as
A sensor signal processing method comprising: outputting a difference between the stored first data and the second data. A third step of selecting a third output signal of a third infrared sensor from a plurality of infrared sensors, subjecting the third output signal to signal processing, and storing the third detection signal as a third detection signal in a third capacitive element; ,
A fourth step of selecting a fourth output signal of a fourth infrared sensor from a plurality of infrared sensors, subjecting the fourth output signal to signal processing, and accumulating the fourth detection signal as a fourth detection signal in a fourth capacitive element; ,
After at least the first step, the second step, the third step, and the fourth step are repeated a plurality of times, the accumulated first detection signal, second detection signal, and third detection Sampling the signal and the fourth detection signal and storing them as first data, second data, third data, and fourth data;
Outputting a difference between the stored third data and the fourth data;
The sensor signal processing method according to claim 18, further comprising: The first infrared sensor and the second infrared sensor are arranged to face each other, the third infrared sensor and the fourth infrared sensor are arranged to face each other,
The method further comprises a step of outputting a difference between the stored first data and the second data, or outputting a difference between the stored third data and the fourth data. The sensor signal processing method according to claim 18.

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