CN106130561B - ADC integrator with DAC function and measuring method - Google Patents
ADC integrator with DAC function and measuring method Download PDFInfo
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- CN106130561B CN106130561B CN201610454417.4A CN201610454417A CN106130561B CN 106130561 B CN106130561 B CN 106130561B CN 201610454417 A CN201610454417 A CN 201610454417A CN 106130561 B CN106130561 B CN 106130561B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
Abstract
The invention discloses an ADC integrator with a DAC function and a measuring method, wherein the integrator circuit comprises a sampling capacitor, 2 integrating capacitors, 1 operational amplifier and a switch group; the sampling capacitor is provided with two groups, one group is connected with the positive input end of the operational amplifier, and the other group is connected with the negative input end of the operational amplifier; 2 integrating capacitors respectively connected to the positive input end and the negative input end of the operational amplifier; the switch group is arranged between the operational amplifier and the sampling circuit and between the sampling capacitor and the input signal. The integrator and the measuring method can help the measured signal to have a larger direct current component signal, and then the measured signal is converted through the ADC, so that the accurate measurement of a signal with smaller variation on a large signal is realized.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to an integrator realized by a switched capacitor circuit.
Background
The integrator circuit is a component applied to a sigma delta analog to digital converter (sigma-delta adc). A sigma delta analog to digital converter is a proportional measurement, i.e. an analog to digital conversion process in which the ratio of an analog input signal multiplied by a gain a and an analog reference voltage is converted into an n-bit digital signal. In the past, when analog signal measurement finds that the signal of the measured signal is large but the signal variation of the measured signal is often small, the ADC needs to cost a lot in order to realize accurate measurement of the small variation of the measured signal.
For example, patent application 201110047941.7 discloses a differential input integrator, which includes a differential signal source Vin, operational amplifiers a1, a2 and an instrumentation amplifier A3, wherein two ends of the differential signal source Vin are connected in series with a resistor R through a wire and then are respectively connected to the reverse input ends of the operational amplifiers a1 and a2, the output ends of the operational amplifiers a1 and a2 are connected in series with the resistor R1 through a wire and then are respectively connected to the reverse input end and the forward input end of the instrumentation amplifier A3, and the output end of the instrumentation amplifier A3 is used as the output end of a total signal; capacitors C are connected in parallel between the positive input terminal and the output terminal of the operational amplifier a1 and between the positive input terminal and the output terminal of the operational amplifier a2, respectively.
Although the application can suppress integral drift caused by common-mode voltage, the integral drift is realized by a plurality of operational amplifiers, and integral measurement has certain accuracy, but sometimes is unreliable and has higher hardware cost.
Disclosure of Invention
In order to solve the above problems, an objective of the present invention is to provide an ADC integrator with a DAC function and a measurement method thereof, which can help a measured signal to have a larger dc component signal, and then perform conversion by the ADC, thereby realizing accurate measurement of a signal with a smaller variation on a large signal.
In order to achieve the above object, the technical solution of the present invention is as follows.
An ADC integrator with a DAC function is characterized in that the integrator circuit comprises a sampling capacitor, 2 integrating capacitors, 1 operational amplifier and a switch group; the sampling capacitor is provided with two groups, one group is connected with the positive input end of the operational amplifier, and the other group is connected with the negative input end of the operational amplifier; 2 integrating capacitors respectively connected to the positive input end and the negative input end of the operational amplifier; the switch group is arranged between the operational amplifier and the sampling circuit and between the sampling capacitor and the input signal.
The sampling capacitors comprise 2x n sampling capacitors, namely each group of sampling capacitors comprises n sampling capacitors which are connected in series and are connected to the operational amplifier.
The switch group comprises a plurality of sampling switches and a plurality of control switches.
Two sampling switches are connected in series with one sampling capacitor and connected to the positive end of a VIP input signal and the negative end of a VIN input signal; the two sampling switches are connected in parallel to a sampling capacitor and are connected to the positive terminal REFP of the reference voltage and the negative terminal REFN of the reference voltage.
The sampling capacitors are divided into n positive-end signal sampling capacitors such as Cs 11-Cs 1n and n negative-end signal sampling capacitors such as Cs 21-Cs 2n, wherein the upper plate of the Cs1x (x-1, 2, …, n) positive-end signal sampling capacitor is respectively and correspondingly connected with three switches 1x (x-1, 2, …, n), 3x1 (x-1, 2, …, n), 3x2 (x-1, 2, …, n), and the lower plate of the Cs1x (x-1, 2, …, n) positive-end signal sampling capacitor is respectively and correspondingly connected with two switches 1x1 (x-1, 2, …, n), 1x2 (x-1, 2, …, n); the upper plate of the Cs2x (x ═ 1, 2, …, n) negative-end signal sampling capacitor is respectively connected with three switches, namely 2x (x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n), 4x2(x ═ 1, 2, …, n), and the lower plate of the Cs2x (x ═ 1, 2, …, n) negative-end signal sampling capacitor is respectively connected with two switches, namely 2x1(x ═ 1, 2, …, n), 2x2(x ═ 1, 2, …, n); the other end of the 1x1(x ═ 1, 2, …, n), 2x2(x ═ 1, 2, …, n) switches is connected to the positive end Vip of the input signal, the other end of the 1x2(x ═ 1, 2, …, n), 2x1(x ═ 1, 2, …, n) switches is connected to the negative end Vin of the input signal, the other end of the 3x2(x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n) switches is connected to the positive end REFP of the reference voltage, the other end of the 3x1(x ═ 1, 2, …, n), 4x2(x ═ 1, 2, …, n) switches is connected to the negative end REFN of the reference voltage.
And the control switch is arranged between each sampling capacitor and the operational amplifier.
And the sampling switch and the control switch are controlled by non-overlapping clocks, and comprise phi 1 and phi 2, and phi 1s and phi 2 s. The sampling switch and the control switch can also be realized by a single PMOS tube or a single NMOS tube, a single CMOS tube and other switches.
The integrating capacitor is divided into a positive end integrating capacitor and a negative end integrating capacitor, wherein the upper electrode plate of the positive end integrating capacitor is connected with the other end of the 1x (x is 1, 2, …, n) switch and the positive input end of the operational amplifier, and the lower electrode plate of the positive end integrating capacitor is connected with the positive output end Vop of the integrator and the negative output end of the operational amplifier; the upper plate of the negative end integrating capacitor is connected with the other end of the 2x (x is 1, 2, …, n) switch and the negative input end of the operational amplifier, and the lower plate of the negative end integrating capacitor is connected with the negative output end Von of the integrator and the positive output end of the operational amplifier 30.
A measuring method of a sigma delta integrator with a DAC is characterized in that the method is used for adding a reference voltage proportional variable DAC value to a measured signal through a sampling capacitor and then carrying out ADC conversion.
Further, the value of the DAC is determined by a control switch 3x1(x is 1, 2, …, n) or 3x2(x is 1, 2, …, n), 4x1(x is 1, 2, …, n) or 4x2(x is 1, 2, …, n) (assuming that m capacitors out of n capacitors at the positive end are connected to REFN, n-m capacitors are connected to REFP, m capacitors out of n capacitors at the corresponding negative end are connected to REFP, n-m capacitors are connected to REFN, and m is 0, 1, 2, …, n). The corresponding DAC value is: - (1-2m/n) (REFP-REFN)/(REFP-REFN), the resolution of the DAC being: log (n)/log 2.
The ADC value output after ADC conversion is as follows:
(2(Vip-Vin)-(1-2m/n)*(REFP-REFN))/(REFP-REFN)。
the value obtained by ADC conversion is that the tested signal is added with a DAC signal and then ADC converted.
A better match between n of the sampling capacitances Cs1x (x ═ 1, 2, …, n) and between n of the sampling capacitances Cs2x (x ═ 1, 2, …, n) is also achieved by means of dynamic matching.
The implementation of the invention can add a reference voltage proportional variable to the measured signal and then carry out ADC conversion, which can help the measured signal to have a larger DC component signal, and the ADC with a DAC can firstly subtract the larger DC signal and then carry out conversion by the ADC, thereby realizing the accurate measurement of the signal with smaller variation on the large signal.
Drawings
Fig. 1 is a circuit diagram of an ADC integrator with its own DAC according to the present invention.
Fig. 2 is a phase diagram of the clock used by the integrator control switch of the ADC with DAC technology implemented by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 shows an ADC integrator with its own DAC implemented according to the above. In fig. 1, the circuit includes: sampling capacitors Cs11, Cs12, …, Cs1n, Cs21, Cs22, …, Cs2n, an operational amplifier 30, integrating capacitors 33, 34, switches 1x1(x ═ 1, 2, …, n), 1x2(x ═ 1, 2, …, n), 2x1(x ═ 1, 2, …, n), 2x2(x ═ 1, 2, …, n), 3x1(x ═ 1, 2, …, n), 3x2(x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n), 4x2(x ═ 1, 2, …, n), 1x (x ═ 1, 2, …, n), and 2x (x ═ 1, 2, …, n).
Fig. 2 shows a respective phase clock illustration of the switches in the integrator circuit, as follows:
the clock phi 1 phase switch 3x1(x ═ 1, 2, …, n) or 3x2(x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n) or 4x2(x ═ 1, 2, …, n) is turned on.
The clock phi 2 phase switch 1x (x is 1, 2, …, n), 2x (x is 1, 2, …, n) is on.
The clock phi 1s phase switch 1x1(x 1, 2, …, n), 2x1(x 1, 2, …, n) is on.
The clock phi 2s phase switch 1x2(x 1, 2, …, n), 2x2(x 1, 2, …, n) is on.
The switched capacitor circuit is connected as follows:
the upper plate of the Cs1x (x ═ 1, 2, …, n) positive side signal sampling capacitor is respectively connected with three switches, namely 1x (x ═ 1, 2, …, n), 3x1(x ═ 1, 2, …, n), 3x2(x ═ 1, 2, …, n), and the lower plate of the Cs1x (x ═ 1, 2, …, n) positive side signal sampling capacitor is respectively connected with two switches, namely 1x1(x ═ 1, 2, …, n), 1x2(x ═ 1, 2, …, n); the upper plate of the Cs2x (x ═ 1, 2, …, n) negative-side signal sampling capacitor is connected with three switches, 2x (x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n), 4x2(x ═ 1, 2, …, n), and the lower plate of the Cs2x (x ═ 1, 2, …, n) negative-side signal sampling capacitor is connected with two switches, 2x1(x ═ 1, 2, …, n), 2x2(x ═ 1, 2, …, n). The other end of the 1x1(x ═ 1, 2, …, n), 2x2(x ═ 1, 2, …, n) switches is connected to the positive end Vip of the input signal, the other end of the 1x2(x ═ 1, 2, …, n), 2x1(x ═ 1, 2, …, n) switches is connected to the negative end Vin of the input signal, the other end of the 3x2(x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n) switches is connected to the positive end REFP of the reference voltage, the other end of the 3x1(x ═ 1, 2, …, n), 4x2(x ═ 1, 2, …, n) switches is connected to the negative end REFN of the reference voltage.
The integrating capacitors are divided into 33 positive side integrating capacitors and 34 negative side integrating capacitors. The upper electrode plate of the 33 positive-end integrating capacitor is connected with the other end of the 1x (x is 1, 2, …, n) switch and the positive input end of the 30 operational amplifier, and the lower electrode plate of the 33 positive-end integrating capacitor is connected with the positive output end Vop of the integrator and the negative output end of the 30 operational amplifier; the upper plate of the 34 negative-end integrating capacitor is connected with the other end of the 2x (x is 1, 2, …, n) switch and the negative input end of the 30 operational amplifier, and the lower plate of the 34 negative-end integrating capacitor is connected with the negative output end Von of the integrator and the positive output end of the 30 operational amplifier.
In addition, the switches are controlled by 2 sets of non-overlapping clocks, including φ 1 and φ 2, φ 1s and φ 2s, as shown in FIG. 2.
The integrator is implemented as follows:
during one integrator period:
sampling phase: Φ 1 and Φ 1S open switches (two switches of Cs3x1 and Cs3x2 for each sampling capacitance Cs1x, or two switches of Cs4x1 and Cs4x2 for the sampling capacitance Cs2x, only one of which will be opened depending on the value of the DAC). The voltages across the Cs1x (x ═ 1, 2, …, n) sampling capacitors are Vip and REFN (or REFP), respectively, and the voltages across the Cs2x (x ═ 1, 2, …, n) sampling capacitors are Vin and REFP (or REFN), respectively.
Integrating phases: Φ 2 and Φ 2S open the switch.
The voltages across the Cs1x (x 1, 2, …, n) sampling capacitor are Vin and VCM, respectively, and the voltages across the Cs2x (x 1, 2, …, n) sampling capacitor are Vip and VCM, respectively.
Then after the integration phase is integrated, the integrator output voltage difference is: (assume that m capacitors of the n capacitors at the positive terminal are connected to REFN, n-m capacitors are connected to REFP, m capacitors of the n capacitors at the corresponding negative terminal are connected to REFP, n-m capacitors are connected to REFN, m is 0, 1, 2, …, n)
(m*(Vip-REFN)+(n-m)*(Vip-REFP)-(m*(Vin-VCM)+(n-m)*(Vin-VCM))-m*(Vin-REFP)-(n-m)*(Vin-REFN)+(m*(Vip-VCM)+(n-m)*(Vip-VCM)))/Ch
The integrator implements the value of the DAC of the differential signal minus/plus a reference voltage (REFP-REFN).
The ADC value output after sigma-delta ADC conversion is as follows:
(2(Vip-Vin)-(1-2m/n)*(REFP-REFN))/(REFP-REFN)
the value obtained by ADC conversion is that the tested signal is added with a DAC signal and then ADC converted.
This DAC signal is: - (1-2m/n) (REFP-REFN)/(REFP-REFN)
The resolution of the DAC is: log (n)/log 2.
The DAC is integrated in the sigma-delta modulator, so that a measured signal can be added with a reference voltage proportional variable and then subjected to ADC conversion, measurement of a larger direct-current component signal of the measured signal can be facilitated, the larger direct-current signal can be subtracted by the ADC with the DAC, and then conversion is performed through the ADC, and accurate measurement of a signal with smaller variation on a large signal is achieved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. An ADC integrator with a DAC function is characterized in that the integrator circuit comprises a sampling capacitor, 2 integrating capacitors, 1 operational amplifier and a switch group; the sampling capacitor is provided with two groups, one group is connected with the positive input end of the operational amplifier, and the other group is connected with the negative input end of the operational amplifier; 2 integrating capacitors respectively connected to the positive input end and the negative input end of the operational amplifier; the switch group is arranged between the operational amplifier and the sampling circuit, and between the sampling capacitor and the input signal;
the switch group comprises a plurality of sampling switches, wherein two sampling switches are connected in series with a sampling capacitor and are respectively connected with the positive end of a VIP input signal and the negative end of a VIN input signal; the two sampling switches are connected in parallel with a sampling capacitor and are respectively connected with the positive end REFP of the reference voltage and the negative end REFN of the reference voltage;
the sampling capacitors are divided into n positive-end signal sampling capacitors such as Cs 11-Cs 1n and n negative-end signal sampling capacitors such as Cs 21-Cs 2n, wherein the upper plates of the Cs1x (x ═ 1, 2, …, n) positive-end signal sampling capacitors are respectively and correspondingly connected with three switches 1x (x ═ 1, 2, …, n), 3x1(x ═ 1, 2, …, n), 3x2(x ═ 1, 2, …, n), and the lower plates of the Cs1x (x ═ 1, 2, …, n) positive-end signal sampling capacitors are respectively and correspondingly connected with two switches 1x1(x ═ 1, 2, …, n), 1x2(x ═ 1, 2, …, n); the upper plate of the Cs2x (x ═ 1, 2, …, n) negative-end signal sampling capacitor is respectively connected with three switches, namely 2x (x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n), 4x2(x ═ 1, 2, …, n), and the lower plate of the Cs2x (x ═ 1, 2, …, n) negative-end signal sampling capacitor is respectively connected with two switches, namely 2x1(x ═ 1, 2, …, n), 2x2(x ═ 1, 2, …, n); the other end of the 1x1(x ═ 1, 2, …, n), 2x2(x ═ 1, 2, …, n) switches is connected to the positive end Vip of the input signal, the other end of the 1x2(x ═ 1, 2, …, n), 2x1(x ═ 1, 2, …, n) switches is connected to the negative end Vin of the input signal, the other end of the 3x2(x ═ 1, 2, …, n), 4x1(x ═ 1, 2, …, n) switches is connected to the positive end REFP of the reference voltage, the other end of the 3x1(x ═ 1, 2, …, n), 4x2(x ═ 1, 2, …, n) switches is connected to the negative end REFN of the reference voltage.
2. The ADC integrator with DAC as claimed in claim 1, wherein said sampling capacitors comprise 2x n sampling capacitors, i.e. each group of sampling capacitors comprises n sampling capacitors, and the n sampling capacitors are connected in series to the operational amplifier.
3. The ADC integrator with DAC of claim 1, wherein said switch bank further comprises a plurality of control switches.
4. The ADC integrator with DAC function of claim 3, wherein said control switch is disposed between each sampling capacitor and said operational amplifier.
5. The ADC integrator with DAC as claimed in claim 1, wherein the integrating capacitor is divided into a positive integrating capacitor and a negative integrating capacitor, wherein the upper plate of the positive integrating capacitor is connected to the other end of 1x (x ═ 1, 2, …, n) switch and the positive input terminal of the operational amplifier, and the lower plate of the positive integrating capacitor is connected to the positive output terminal Vop of the integrator and the negative output terminal of the operational amplifier; the upper plate of the negative end integrating capacitor is connected with the other end of the 2x (x is 1, 2, …, n) switch and the negative input end of the operational amplifier, and the lower plate of the negative end integrating capacitor is connected with the negative output end Von of the integrator and the positive output end of the operational amplifier 30.
6. A measurement method of an ADC integrator with a DAC function is characterized in that the method is applied to the ADC integrator with the DAC function of claim 1, and ADC conversion is carried out after a measured signal is added with a reference voltage proportional variable DAC value through a sampling capacitor; the value of the DAC is determined by control switches 3x1(x is 1, 2, …, n) or 3x2(x is 1, 2, …, n), 4x1(x is 1, 2, …, n) or 4x2(x is 1, 2, …, n), m capacitors of positive n capacitors are connected to REFN, n-m capacitors are connected to REFP, m capacitors of negative n capacitors are connected to REFP, n-m capacitors are connected to REFN, m is 0, 1, 2, …, n, and the value of the DAC is: - (1-2m/n) (REFP-REFN)/(REFP-REFN), the resolution of the DAC being: log (n)/log 2.
7. The method of claim 6, wherein the ADC integrator with DAC function outputs ADC values of:
(2(Vip-Vin)-(1-2m/n)*(REFP-REFN))/(REFP-REFN)。
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102983863A (en) * | 2012-12-18 | 2013-03-20 | 天津大学 | First-stage circuit structure of pipelined analog-to-digital converter |
| CN103067015A (en) * | 2012-12-20 | 2013-04-24 | 天津大学 | Circulation analog-digital converter and conversion method for complementary metal oxide semiconductor (CMOS) image sensor |
| CN104901700A (en) * | 2015-05-12 | 2015-09-09 | 清华大学 | Fully digital Sigma-Delta modulator based on phase inverter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102983863A (en) * | 2012-12-18 | 2013-03-20 | 天津大学 | First-stage circuit structure of pipelined analog-to-digital converter |
| CN103067015A (en) * | 2012-12-20 | 2013-04-24 | 天津大学 | Circulation analog-digital converter and conversion method for complementary metal oxide semiconductor (CMOS) image sensor |
| CN104901700A (en) * | 2015-05-12 | 2015-09-09 | 清华大学 | Fully digital Sigma-Delta modulator based on phase inverter |
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