JP2015191120A - display drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent burning of a liquid crystal, even while applying spread-spectrum such that a line frequency is fluctuated to a clock in a display drive circuit.SOLUTION: A display drive circuit for driving a liquid crystal display panel which is constituted of a plurality of lines in one frame includes a clock generation circuit for supplying a clock for generating a horizontal synchronization signal as a reference timing for driving the plurality of lines. The clock generation circuit spectrum-spreads the clock so that the cycle (1/line frequency) of a horizontal synchronization signal corresponding to each of the plurality of lines is dispersed within the same frame and becomes equal for every corresponding line between successive frames.

Description

  The present invention relates to a display driving circuit connected to a display panel, and can be suitably used particularly for a display driving circuit capable of suppressing generation of noise.

  Mobile terminals such as smartphones, tablet terminals, and PDAs (Personal Digital Assistants) include a display panel, a touch panel, and a wireless or wired communication interface as input / output means in addition to high-performance data processing functions. The display panel is required to have high definition, and the touch panel is required to have high sensitivity. With the high definition of the display panel, a large amount of image data is supplied to a display drive circuit such as a display driver IC (Integrated Circuit) at high speed. The display driving circuit generates a clock synchronized with image data in units of pixels, and performs signal processing and control for display. The frequency of this clock tends to increase with the higher definition of the display panel. Radiation noise (EMI: Electro-Magnetic Interference) caused by this clock and noise to the integrated touch panel controller and communication interface Mixing is a problem. For example, there is a possibility that the harmonics of the display drive clock coincide with the signal frequency at the communication interface and become an interference wave, or the harmonics of the sampling frequency of the detection circuit in touch detection coincide with the aliasing frequency. .

  Patent Document 1 discloses a liquid crystal display (LCD) driving circuit including an oscillation circuit that spreads a spectrum of a clock frequency. The oscillation circuit described in this document is configured by a spread spectrum PLL (Phase Locked Loop) that modulates the oscillation frequency with a triangular wave or a stepped triangular wave at the period of the horizontal synchronization signal (Hsync). Thereby, the power at the specific frequency of EMI is spread in the frequency direction, and the peak is suppressed.

US Pat. No. 7,142,187

  As a result of examination of the patent document 1 by the present inventors, it has been found that there are the following new problems.

  Dispersion of interference wave power in the spread spectrum of the oscillation circuit described in this document is limited by the horizontal synchronization signal (Hsync) that is the modulation period, and accordingly, the extent to which the peak of the interference wave is suppressed is also limited. Will be. In other words, the interference wave at the frequency of the clock generated by the oscillation circuit is spread spectrum, but the line frequency is not spread spectrum and there is an interference wave having a large peak. In order to spread the interference wave over a wider range than the oscillation circuit described in Patent Document 1, it is necessary to perform modulation so large that the line frequency, which is the frequency of the horizontal synchronization signal, is also changed.

  However, as a result of studies by the present inventors, it has been found that there is a possibility that a problem of burn-in of the liquid crystal may occur when spectrum spreading is applied also to the line frequency. In the first place, in order to prevent liquid crystal burn-in, a liquid crystal display device employs a driving method such as column inversion driving or dot inversion driving that inverts the polarity of the driving voltage in each pixel for each frame. When spread spectrum is applied to the line frequency of such a liquid crystal display device, the time during which the positive drive voltage is applied to the negative drive voltage is not necessarily the same for each pixel. It has been found that there is a possibility that liquid crystal burn-in may occur at the pixel where the balance has occurred.

  An object of the present invention is to prevent liquid crystal burn-in while applying a large spread spectrum that changes the line frequency to the clock in the display driving circuit.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, a display driving circuit for driving a liquid crystal display panel in which one frame is composed of a plurality of lines, and a clock that supplies a clock for generating a horizontal synchronizing signal that serves as a reference for timing of driving the plurality of lines A generation circuit is provided. The clock generation circuit spreads the clock spectrum so that the period of the horizontal synchronization signal corresponding to each of the plurality of lines is dispersed within the same frame and is equal for each corresponding line between consecutive frames.

  The effect obtained by the one embodiment will be briefly described as follows.

  In other words, liquid crystal burn-in can be prevented while applying a large spread spectrum that changes the line frequency to the clock in the display drive circuit.

FIG. 1 is a block diagram showing a configuration example of a display driving circuit 1 according to the present invention. FIG. 2 is a plan view illustrating the electrode configuration of the display panel 2. FIG. 3 is an explanatory diagram showing the spread pattern of the spread spectrum according to the present invention. FIG. 4 is an explanatory diagram for explaining inversion driving of the liquid crystal display panel. FIG. 5 is a circuit diagram showing a configuration example of a clock generation circuit that performs spectrum spreading according to the present invention. FIG. 6 is a timing chart showing an operation example of the A phase of the first spread spectrum pattern. FIG. 7 is a timing chart showing an operation example of the B phase of the first spread spectrum pattern. FIG. 8 is a timing chart showing the panel noise waveform in the first spread spectrum pattern (A phase). FIG. 9 is a frequency distribution diagram of radiation noise in the first spread spectrum pattern. FIG. 10 is a frequency distribution diagram of radiation noise when spectrum spreading is not performed (comparative example). FIG. 11 is an explanatory diagram showing the first spread spectrum pattern. FIG. 12 is an explanatory diagram showing the second spread spectrum pattern. FIG. 13 is an explanatory diagram showing a third spread spectrum pattern. FIG. 14 is an explanatory diagram showing the fourth spread spectrum pattern. FIG. 15 is a timing chart showing the A phase of the second spread spectrum pattern. FIG. 16 is a timing chart showing the B phase of the second spread spectrum pattern. FIG. 17 is a timing chart showing the panel noise waveform in the second spread spectrum pattern (A phase). FIG. 18 is a circuit diagram showing a second configuration example of the clock generation circuit that performs spectrum spreading according to the present invention. FIG. 19 is a circuit diagram showing a third configuration example of the clock generation circuit that performs spectrum spreading according to the present invention.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Spread spectrum in which the line period is dispersed within a frame and equalized between consecutive frames>
A typical embodiment disclosed in the present application is a display drive circuit (1) for driving a liquid crystal display panel (2) in which one frame is composed of a plurality of lines, and includes a clock generation circuit (4). The configuration is as follows. The clock generation circuit generates a clock (CLK) for generating a horizontal synchronization signal (HSYNC) serving as a reference for driving the plurality of lines. The clock generation circuit spreads the clock spectrum so that the period of the horizontal synchronizing signal corresponding to each line in the frame is dispersed within the same frame and equal for each line between two consecutive frames.

  As a result, liquid crystal burn-in can be prevented while applying a large spread spectrum that changes the line frequency to the clock in the display drive circuit.

[2] <Constant frame frequency>
In item 1, the clock generation circuit spreads the clock spectrum so as to keep the frame frequency constant.

  Accordingly, it is possible to suppress the occurrence of each of the problems that flicker occurs when the frame frequency decreases and power consumption increases when the frame frequency increases.

[3] <Uniform spread spectrum pattern>
In the item 2, the clock generation circuit is the same for all the lines in the frame when the period of the horizontal synchronizing signal corresponding to each line in the frame is integrated over a plurality of predetermined frames for each line. Spread the clock to a value.

  Accordingly, it is possible to control the pixel so as not to cause a bias in the length of time that each pixel is driven for display while preventing the liquid crystal from burning. The period of the horizontal synchronizing signal corresponding to each line corresponds to the time during which the pixels of that line are driven to display. At this time, when viewed within one frame, the period of the horizontal synchronization signal becomes a different value for each line due to spread spectrum, but the integrated value over a plurality of frames for the same line is made uniform by configuring as described above. Because it is done.

[4] <Dispersion of line period at 8 line period>
In item 2, the clock generation circuit spreads the clock spectrum so that a frequency spreading pattern of a horizontal synchronizing signal having a period corresponding to each line in the frame is repeated in a period of eight lines adjacent in the frame. .

  Accordingly, it can be widely applied with good consistency to various display panels that are widely used. This is because many display panels such as WVGA, qHD, HD720, F-HD, and WQHD have a line number that is a multiple of eight.

[5] <Spread spectrum oscillation circuit>
In item 1, the clock generation circuit includes an oscillation circuit (6) that generates the clock, and an oscillation frequency control circuit that can change an oscillation frequency (f _OSC ) of the oscillation circuit from a center frequency (ft). 7). The oscillation frequency control circuit switches whether the oscillation frequency is increased or decreased from the center frequency in synchronization with the horizontal synchronization signal.

  Thereby, a clock oscillation circuit capable of accurately controlling the cycle of the horizontal synchronizing signal for each corresponding line can be realized with a simple circuit.

[6] <Uniform display drive period for each line>
In item 5, the oscillation frequency control circuit is configured to reduce the number of lines corresponding to a horizontal synchronization signal generated based on a clock whose oscillation frequency is increased from the center frequency, and to decrease the oscillation frequency from the center frequency. The number of lines corresponding to the horizontal synchronization signal generated based on the generated clock is the same number in the same frame, and the horizontal synchronization corresponding to each line when viewed over a plurality of frames. The oscillation frequency is switched so that the frequency of the clock generating the signal is equal to the frequency increased from the center frequency and the frequency decreased from the center frequency.

  Accordingly, it is possible to control the pixel so as not to cause a bias in the length of time that each pixel is driven for display while preventing the liquid crystal from burning. This is the same effect as in item 3.

[7] <Oscillation frequency control circuit>
In item 5, the oscillation frequency (f _OSC ) of the oscillation circuit is designated by an input control value (C _OSC ). The oscillation frequency control circuit includes a selector (21) and a select timing control circuit (8) for controlling the selector. The selector (21) includes a trimming value (Nt) that defines the center frequency of the oscillation circuit, a value obtained by adding a first value to the trimming value (Nt + Nup), and a second value from the trimming value. One control value is selected from a plurality of control values including a value obtained by subtracting (Nt−Ndw) and supplied to the oscillation circuit. The select timing control circuit causes the selector to select one control value from the plurality of control values in synchronization with the horizontal synchronization signal.

  This is because the oscillation frequency control circuit is configured by a logic circuit that operates in synchronization with the horizontal synchronization signal, and the spread spectrum can be digitally controlled. For example, the oscillation frequency is alternately switched between ft + Δf and ft−Δf for each line with respect to the center frequency ft of the oscillator, or switched to repeat ft, ft + Δf, f0, ft−Δf, ft, or For example, ft, ft + Δf1, ft + Δf2, ft + Δf1, ft, ft−Δf1, ft−Δf2, ft−Δf1, and ft are switched in multiple stages. In this way, a control circuit that accurately generates a desired repetitive pattern can be realized with a simple circuit.

[8] <Register for setting spread frequency>
In Item 7, the display driving circuit further includes a memory (19) that can store the trimming value, and registers (25 to 28) that can store the first value and the second value, respectively.

  Thus, the display drive circuit can be configured so that the center frequency of spread spectrum in the clock generation circuit and the upper and lower frequency adjustment values can be set. For example, the center frequency (ft) can be obtained as a trimming value (Trim value, Nt) by obtaining an appropriate value by a test at the time of shipment, and the frequency adjustment value (Δf) is optimized for each mounted device. The values (Nup, Ndw, etc.) can be specified by writing them in the registers (25-28).

[9] <Spread spectrum in which the line period is dispersed within a frame and equalized between successive frames>
A typical embodiment disclosed in the present application is a display driving circuit (1) for driving a liquid crystal display panel (2) in which one frame is composed of a plurality of lines, and the timing for driving the plurality of lines. And a clock generation circuit (4) for supplying a clock (CLK) serving as a reference for the above, and is configured as follows. The clock generation circuit includes an oscillation circuit (6) for generating the clock and an oscillation capable of switching a change amount (0 ± Δf) for changing the frequency (f _OSC ) of the clock from the center frequency (ft) for each line. And a frequency control circuit (7). The oscillation frequency control circuit controls the oscillation circuit so that the amount of change corresponding to each line in the frame is dispersed within the same frame and is equal for each line between two consecutive frames.

  As a result, liquid crystal burn-in can be prevented while applying a large spread spectrum that changes the line frequency to the clock in the display drive circuit.

[10] <Constant frame frequency>
In item 9, the oscillation frequency control circuit controls the oscillation circuit so that the total amount of change corresponding to all lines in the frame is constant between different frames.

  Thereby, the frame frequency can be kept constant. It is possible to suppress the occurrence of each problem in which flicker occurs when the frame frequency decreases and power consumption increases when the frame frequency increases.

[11] <Uniform spread spectrum pattern>
In item 10, the oscillation frequency control circuit causes the change amount corresponding to each line in the frame to have the same value for all lines when integration is performed over a plurality of predetermined frames for each line. In addition, the oscillation circuit is controlled.

  Thus, the oscillation circuit can be controlled so as not to cause a bias in the length of time each pixel is driven for display while preventing the liquid crystal from burning. This is the same effect as in item 3.

[12] <Dispersion of line period in 8 line periods>
In item 10, the oscillation frequency control circuit controls the oscillation circuit so that the change amount corresponding to each line in the frame periodically changes in a period of eight lines adjacent in the frame.

  Accordingly, it can be widely applied with good consistency to various display panels that are widely used. This is the same effect as in item 4.

[13] <Uniform display drive period for each line>
In item 9, the oscillation frequency control circuit reduces the number of lines for generating a horizontal synchronization signal based on a clock in which the oscillation frequency is increased from the center frequency, and the oscillation frequency is decreased from the center frequency. The number of lines of the horizontal sync signal generated based on the clock is the same in the same frame, and when viewed over a plurality of frames, for each line, the corresponding clock is from the center frequency. The oscillation frequency is controlled so that the increased frequency is equal to the decreased frequency.

  Thus, the oscillation circuit can be controlled so as not to cause a bias in the length of time each pixel is driven for display while preventing the liquid crystal from burning. This is the same effect as in item 3.

[14] <Oscillation frequency control circuit>
In item 9, an oscillation frequency (f _OSC ) of the oscillation circuit is designated by an input control value (C _OSC ). The oscillation frequency control circuit includes a selector (21) and a select timing control circuit (8) for controlling the selector. The selector (21) includes a trimming value (Nt) that defines the center frequency of the oscillation circuit, a value obtained by adding a first value to the trimming value (Nt + Nup), and a second value from the trimming value. One control value is selected from a plurality of control values including a value obtained by subtracting (Nt−Ndw) and supplied to the oscillation circuit. The select timing control circuit causes the selector to select one control value from the plurality of control values in synchronization with the horizontal synchronization signal.

  This is because the oscillation frequency control circuit is configured by a logic circuit that operates in synchronization with the horizontal synchronization signal, and the spread spectrum can be digitally controlled. This is the same effect as in item 7.

[15] <Register for setting spread frequency>
Item 14 further includes a memory (19) that can store the trimming value, and registers (25 to 28) that can store the first value and the second value, respectively.

  Thus, the display drive circuit can be configured so that the center frequency of spread spectrum in the clock generation circuit and the upper and lower frequency adjustment values can be set. This is the same effect as in item 8.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 is a block diagram illustrating a configuration example of a display drive circuit 1 of the present invention, and FIG. 2 is a plan view illustrating an electrode configuration of a display panel 2 to which the display drive circuit 1 is connected.

  The display driving circuit 1 is connected to the display panel 2 and the host processor 3 and is not particularly limited. For example, a single semiconductor substrate such as silicon is used by using a known CMOS (Complementary Metal-Oxide-Semiconductor) semiconductor manufacturing technique. Formed on top. A touch panel controller or MPU may be mixedly mounted on the same chip and configured as a display driver with a built-in touch panel controller (composite IC). The composite IC is connected to the display panel 2 on which the touch panel is stacked, and the coordinated operation such as detecting that the coordinate corresponding to the icon displayed on the display panel 2 is touch-operated is detected on the stacked touch panel. Suitable for. The method of laminating the display panel 2 and the touch panel may be an in-cell method in which the display panel 2 and the touch panel are integrally mounted, or may be an on-cell type cover glass integrated configuration in which the touch panel and a cover glass installed on the upper surface are integrated.

  FIG. 2 illustrates the configuration of the display panel 2 to which the display drive circuit 1 is connected. In the display panel 2, gate wirings G1 to Gm as scanning electrodes formed in the horizontal direction and source wirings S1 to Sn as signal electrodes formed in the vertical direction are arranged, and selection terminals correspond to the intersections. A large number of display cells are arranged, which are connected to the scanning electrode and the input terminal is connected to the corresponding signal electrode. The display cell includes a transfer gate Tr having a gate terminal connected to a gate line and a source terminal connected to a source line, and a pixel capacitor C formed by a liquid crystal element formed between the drain terminal of the transfer gate Tr and the common voltage Vcom. . The structure of the transfer gate Tr is symmetric, and the relationship between the drain terminal and the source terminal described above may be reversed. The gate lines G <b> 1 to Gm that are scanning electrodes are sequentially scanned by a gate drive circuit (Gate In Panel) 18 formed in the display panel 2. The gate driving circuit 18 is not particularly limited, and includes, for example, a shift register and an amplifier for driving the gate wirings G1 to Gm, and includes a thin film transistor (TFT) formed on the glass substrate of the display panel 2. Constructed using. A signal Gctl for controlling the gate drive circuit 18 and source lines S1 to Sn as signal electrodes are supplied from the display drive circuit 1. A signal having a voltage level (display level) corresponding to the luminance (image data) to be displayed is applied to the source lines S1 to Sn directly or via a demultiplexer, and the line selected by the gate lines G1 to Gm. Of the pixel capacitors C are charged in parallel. The magnitude of the polarization of the liquid crystal is determined by the magnitude of the electric field formed by the charge held in the pixel capacitor C, and the amount of transmitted light, that is, the luminance of the pixel is determined. The pixel capacitor C holds the charge and displays the same luminance until the same line is selected in the next frame and a new display level is charged. Driving the scanning electrode and the signal electrode as described above in order to transfer the charge corresponding to the display level to the pixel capacitor C is referred to as display driving and includes a display driving period (also referred to as a display period for short). Means a period during which display driving is performed. The configuration of the display panel 2 is not limited to the illustrated example and is arbitrary. For example, instead of providing the gate drive circuit, the gate lines G1 to Gm may be directly driven by the display drive circuit 1.

  Returning to the description of FIG.

  The display drive circuit 1 includes a control signal interface 16, an image data interface 17, a control unit (TCON) 5, a gate control driver 14, a memory 13, a data latch circuit 12, a gradation voltage selection circuit 11, The source driver 10, the power supply circuit 15, and the clock generation circuit 4 are included. In FIG. 1, signals for controlling gate wiring and image data signals for display are indicated by wide arrows, and main control signals and timing signals for controlling the operation of each circuit are indicated by solid arrows. The power supply wiring is not shown. Further, although the bus display of the signal lines is omitted in the figure, each signal line is constituted by one or a plurality of analog or digital signal wirings. The display drive circuit 1 is connected to the host processor 3 through a control signal interface 16 via a system bus, receives control commands, and transmits and receives various internal parameters. The image data interface 17 is an interface compliant with MIPI-DSI (Mobile Industry Processor Interface Display Serial Interface), which is one of standard communication interfaces of display devices, for example. The display driving circuit 1 is connected to the host processor 3 via the image data interface 17 and receives image data to be displayed on the display panel 2 at high speed, and includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and the like. Timing information is also received.

  The control unit (TCON) 5 includes a command register (not shown) for holding control commands and parameters received from the host processor 3 and a parameter register (not shown), and controls the operation of each circuit based thereon. When MPUs or touch panel controllers are mixedly mounted or externally attached, control commands and parameters received from the host processor 3 are transferred to them, and data such as touch positions and states are transmitted from the MPU to the host processor 3. Relay.

  The clock generation circuit 4 generates an internal clock CLK and supplies it to the control unit 5, and the control unit 5 generates a vertical synchronization signal (VSYNC) and a horizontal synchronization signal (HSYNC) as internal synchronization signals from the internal clock CLK. . The vertical synchronization signal (VSYNC) and the horizontal synchronization signal (HSYNC) as the internal synchronization signal are received by the image data interface 17 and are a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync) for synchronizing with the host processor 3. Can be asynchronous. The control unit 5 controls the gate control driver 25 based on the internal clock CLK and the vertical synchronization signal (VSYNC) and the horizontal synchronization signal (HSYNC) as the internal synchronization signal, and outputs a control signal Gctl that is supplied to the display panel 2. Then, the source driver signals S1 to Sn supplied to the display panel 2 are controlled by controlling the source driver 10 and the like. The signal Gctl for controlling the gate driving circuit 18 of the display panel 2 includes, for example, a clock for the shift operation of the shift register, a start flag G_ST input to the first stage, G_UP / G_DN that defines the shift direction, and a shift It consists of signals such as G_EN (enable) that temporarily stops the operation.

  The control unit 5 writes the image data received by the image data interface 17 in the memory 13 based on the internal clock CLK and the vertical synchronization signal (VSYNC) and the horizontal synchronization signal (HSYNC) which are internal synchronization signals. The memory 13 is an SRAM (Static Random Access Memory) and functions as a frame memory. One line of image data is read from the memory 13 to the data latch 12. The gradation voltage selection circuit 11 converts image data for one line supplied as a digital value from the data latch 12 into a corresponding analog gradation voltage in parallel, and supplies the converted analog gradation voltage to the source driver 10. The gradation voltage selection circuit 11 is one analog level corresponding to digital image data among multi-gradation analog gradation voltages generated and supplied by a gradation voltage generation circuit (not shown). An adjusted gradation voltage is selected and output, or an intermediate gradation voltage is newly generated from a plurality of gradation voltages to be selected and supplied to the source driver 10. The source driver 10 amplifies the input gradation voltage and drives the source lines S1 to Sn of the display panel 2. In this specification, the voltage at this time is called a source drive voltage or abbreviated drive voltage.

  The power supply circuit 15 includes a booster circuit, a step-down circuit, a stabilization circuit (regulator), and the like, and generates an internal power supply used in each circuit in the display drive circuit 1 from a power supply supplied from the outside.

  The above-described display drive circuit 1 has been described with respect to the configuration example in which the frame memory 13 is incorporated, but a configuration in which the frame memory is not incorporated may be employed. However, since the line frequency is spectrum-modulated in the present invention, a buffer (for example, a line memory) that can absorb the fluctuation is required. In the configuration example in which the frame memory 13 is built in, when the image to be displayed is a still image, the still image of one frame is held in the frame memory 13 and repeatedly read out and displayed, thereby displaying the host during the period in which the still image is displayed. Transfer of image data from the processor 3 can be omitted. On the other hand, a configuration without a built-in frame memory requires a small chip area and reduces costs.

  The host processor 3 generates image data, and the display driving circuit 1 performs display control for displaying the image data received from the host processor 3 on the display panel 2. Although not particularly limited, the host processor 3 is connected to the touch controller and the MPU that controls the touch controller directly or via the control unit 5 of the display drive circuit 1. The position coordinate data when the touch event occurs is obtained from the MPU, and the input by the operation of the touch panel is analyzed from the relationship between the position coordinate data on the display panel 2 and the display screen displayed on the display drive circuit 1. To do. The host processor 3 includes a communication control unit, an image processing unit, an audio processing unit, other accelerators, and the like, which are not shown, and a portable terminal is configured, for example.

  The operation of the display drive circuit 1 will be described.

  In the display drive circuit 1, the clock generation circuit 4 supplies a clock CLK for generating a horizontal synchronization signal HSYNC that is a reference for timing for driving a plurality of lines. The clock generation circuit 4 spreads the spectrum of the clock CLK so that the period of the horizontal synchronization signal HSYNC corresponding to each line in the frame is dispersed in the same frame and is equal for each line between two consecutive frames.

As a result, it is possible to prevent liquid crystal burn-in while applying a spectrum spread that is large enough to change the line frequency to the clock in the display driving circuit. Since the line frequency is the reciprocal of the period of the horizontal synchronization signal HSYNC, the distribution of the line frequency within the frame is spread spectrum, and the peak power of the line frequency is reduced. Similarly, for the clock CLK for generating the horizontal synchronization signal HSYNC, the oscillation frequency (f _OSC ) of the clock is spectrum-spread within the frame, and the peak power is reduced. Further, by making the horizontal synchronization signal HSYNC equal for each line between two consecutive frames, liquid crystal burn-in can be prevented. A liquid crystal display panel employs a driving method in which the polarity of the source driving voltage in each pixel is inverted for each frame in order to prevent liquid crystal burn-in. There are various types of inversion driving, such as column inversion driving and dot inversion driving. In any of the methods, the polarity of the driving voltage applied to the pixels connected to one line is different in the next frame. Inverted. The time during which the drive voltage is applied to the pixels connected to one line is determined by the period of the horizontal synchronization signal HSYNC for that line. Therefore, by making the period of the horizontal synchronization signal HSYNC of the same line equal between two consecutive frames, the time when the positive drive voltage is applied and the time when the negative drive voltage is applied for each pixel Can be matched. Thereby, image sticking of the liquid crystal is prevented. The above-mentioned “sequentially between two consecutive frames (similarly)” may be equivalent to every two consecutive frames, and each of the first frame and the second frame, the third frame and the fourth frame,. As long as they are equal, the period of the horizontal synchronization signal HSYNC on the same line may be different between the first and second frames and the third and fourth frames. In addition, “equal” and “match” do not mean that they are mathematically completely equal, and include errors of such a degree as long as they are within a range where liquid crystal burn-in can be allowed. You can leave.

  At this time, the frame frequency can be changed for each frame. Thereby, spread spectrum is applied to the frame frequency, and the peak power can be reduced. However, when the frame frequency is increased, power consumption increases, and when the frame frequency is decreased, flicker may occur. In order to prevent this, it is preferable to keep the frame frequency constant. That is, the spread spectrum in the clock generation circuit 4 is controlled so that the total amount of change in the clock frequency corresponding to all the lines in the frame is constant between different frames. A specific control method will be described later. Thereby, the frame frequency can be kept constant. It is possible to suppress the occurrence of each problem in which flicker occurs when the frame frequency decreases and power consumption increases when the frame frequency increases.

  The clock generation circuit 4 has the same value for all the lines in the frame when the period of the horizontal synchronization signal HSYNC corresponding to each line in the frame is integrated over a plurality of predetermined frames for each line. As described above, it is more preferable to spread the spectrum of the clock CLK.

  This is because it is possible to control so as not to cause a bias in the length of time each pixel is driven for display while preventing liquid crystal burn-in. The period of the horizontal synchronization signal HSYNC corresponding to each line corresponds to the time during which the pixels of that line are driven for display. At this time, when viewed within one frame, the period of the horizontal synchronization signal HSYNC becomes a different value for each line due to spectrum spreading, but the integrated value over a plurality of frames for the same line is uniform by configuring as described above. It is because it becomes.

  More preferably, the clock generation circuit 4 spreads the clock CLK so that the spread pattern of the frequency of the horizontal synchronization signal HSYNC having a period corresponding to each line in the frame is repeated in a period of eight lines adjacent in the frame. is there.

  Accordingly, it can be widely applied with good consistency to various display panels that are widely used. WVGA is 480 pixels x 800 lines, qHD is 540 pixels x 960 lines, HD720 is 720 pixels x 1280 lines, F-HD is 1080 pixels x 1920 lines, and WQHD is 1440 pixels x 2560 lines. This is because the number of lines is a multiple of eight.

[Embodiment 2]
A more specific embodiment will be described.

  FIG. 3 is an explanatory diagram showing the spread pattern of the spread spectrum according to the present invention. The horizontal axis is time, and a display period of 4 frames is shown. In the vertical axis direction, a driving pattern for inversion driving in each frame is schematically illustrated in the uppermost stage, and below that, in order from the top, a vertical synchronization signal VSYNC, a diffusion pattern, and a control signal Phase INV for controlling inversion driving. Is shown. At times t10 to t20, t20 to t30, t30 to t40, and t40 to t50, frame1, frame2, frame3, and frame4 are shown, respectively. The driving pattern of the inversion driving is reversed for each frame, and frame1 (time t10 to t20) and frame3 (time t30 to t40), frame2 (time t20 to t30) and frame4 (time t40 to t50) are the same pattern and continuous. The frames to be played are inverted patterns. The spread pattern for spread spectrum of the clock in the clock generation circuit 4 changes the frequency for each line, and two types of A phase and B phase are prepared for four frames of frames 1 to 4. The same A phase is applied to consecutive frames 1 and 2, and the B phase is applied to subsequent frames 3 and 4. Phase INV is a control signal for controlling the switching of the phase, and is asserted at times t10 and t30 at intervals of two frames. Since the polarities of the drive voltages applied to the same line by frame inversion 1 and frame 2 are inverted between frames, the same diffusion pattern (same phase) is applied, so that the positive polarity drive is applied to each pixel. The time during which the voltage is applied and the time during which the negative drive voltage is applied can be made coincident with each other, so that liquid crystal burn-in can be prevented.

  FIG. 4 is an explanatory diagram for explaining inversion driving of the liquid crystal display panel. The driving pattern of inversion driving shown in FIG. 3 is an example in which driving voltages having the same polarity are applied in line units, but FIG. 4 shows a scheme in which the polarity of driving voltage is further inverted in pixel units. Shown schematically. The polarity of the drive voltage is inverted between adjacent pixels on the same line and between adjacent pixels on the adjacent line. However, since the applied pattern is further inverted between successive frames, the polarity of the drive voltage is inverted between successive frames when viewed in pixel units. As described above, there are various inversion driving methods for preventing the burn-in of the liquid crystal. In any of the methods, the polarity of the driving voltage is inverted between successive frames when viewed in units of pixels. By applying the same diffusion pattern to the liquid crystal, burn-in of the liquid crystal is prevented.

  FIG. 5 is a circuit diagram showing a configuration example of the clock generation circuit 4 capable of performing spread spectrum according to the present invention.

The clock generation circuit 4 includes an oscillation circuit 6 that generates the clock CLK, and an oscillation frequency control circuit 7 that can change the oscillation frequency (f _OSC ) of the oscillation circuit 6 from the center frequency (ft). The The oscillation frequency control circuit 7 switches whether the oscillation frequency (f _OSC ) of the oscillation circuit 6 is increased or decreased from the center frequency (ft) in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC.

The oscillation circuit 6 is an oscillation circuit whose oscillation frequency (f _OSC ) can be adjusted by an input control value (C _OSC ), and as shown in the figure, an RC low-pass inserted in the ring oscillator and its feedback path. The frequency characteristic of the RC low-pass filter is controlled by an input control value (C _OSC ). In the ring oscillator, five-stage inverters INV1 to INV5 and ladder resistors whose resistance values are variable by resistors R0 and R1 to R63 are connected in series, and a capacitor C0 is connected between the input of the first-stage inverter INV1 and the ground potential. Has been. The variable resistance ladder resistors R0 and R1 to R63 are connected to switches s0 to s63 for each tap, and to which tap the output of the inverter INV5 in the final stage is fed back by the control value C _OSC inputted. The resistance value can be adjusted. Selector 20 by decoding the control value _{C OSC} of 6 bits, which activates one of selection signals S0~S63 switch S0～s63. The RC low-pass filter has its time constant adjusted in 64 gradations from C0 × R0 to C0 × (R0 + R1 + R2 +... R63) according to the selected tap. The oscillation frequency (f _OSC ) of the ring oscillator is adjusted by the time constant of the RC low-pass filter. The clock CLK supplied to each circuit including the control unit (TCNT) 5 of the display drive circuit 1 is output via an inverter INV0 functioning as a buffer.

The oscillation frequency control circuit 7 includes a selector 21, a select timing control circuit 8, an adder 22, a subtractor 23, and registers 24-26. Although not shown in FIG. 1, the trimming value (Trim value, Nt) of the oscillation circuit 6 is supplied from the nonvolatile memory 19 in the display drive circuit 1. The trimming value (Trim value, Nt) is a value of a control value (C _OSC ) obtained so as to absorb the manufacturing variation so that the oscillation frequency (f _OSC ) of the oscillation circuit 6 becomes a predetermined center frequency (ft). is there. The adder 22 adds a predetermined value Nup held in the register 25 to the trimming value (Trim value, Nt) and outputs Nt + Nup to the selector 21, and the subtractor 23 calculates the trimming value (Trim value, Nt). A predetermined value Ndw held in the register 26 is subtracted to output Nt−Ndw to the selector 21. When the control value (C _OSC ) = Nt, the oscillation frequency (f _OSC ) of the oscillation circuit 6 becomes a predetermined center frequency (ft), and when the control value (C _OSC ) = Nt + Nup, the oscillation frequency (f _OSC ) = ft + Δf, control The values of the registers 25 and 26 are set so that the oscillation frequency (f _OSC ) = ft−Δf when the value (C _OSC ) = Nt−Ndw. The select timing control circuit 8 controls a 2-bit control signal Cmod for controlling the selector 21 in accordance with a predetermined pattern in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC. The selector 21 switches the control value (C _OSC ) for controlling the clock frequency for each corresponding line between Nt, Nt + Nup, and Nt−Ndw according to the control signal Cmod. By synchronizing with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC, the corresponding clock frequency can be appropriately and accurately assigned to each line in one frame. For example, by providing a counter in the select timing control circuit 8 that is initialized with the vertical synchronization signal VSYNC and counts up with the horizontal synchronization signal HSYNC, the line numbers in the frame can be managed accurately. The pattern of the control signal Cmod selected by the select timing control circuit 8 is a spread spectrum pattern of the oscillation frequency, and is set in the register 24, for example.

  Thereby, since the clock oscillation circuit 4 can be realized by a simple digital circuit, the cycle of the horizontal synchronization signal HSYNC can be accurately controlled for each corresponding line.

  The operation of the clock oscillation circuit 4 will be described in more detail.

6 and 7 are timing charts showing examples of operations of the A phase and the B phase, respectively, of the first spread spectrum pattern. 6 and 7 correspond to FIG. As described in FIG. 3, since the same A phase is applied to frame1 and frame2, an enlarged view of the first 8 lines from time t10 and t20 is shown in FIG. 6, and the same B phase is used for frame3 and frame4. FIG. 7 shows an enlarged view of the first eight lines from time t30 and t40. 6 and FIG. 7, the horizontal axis represents time, and in the vertical axis direction, the control signal Cmod of the selector 21, the control value C _OSC of the oscillation circuit 6, the oscillation frequency f _OSC, and the horizontal synchronization signal HSYNC are shown in order from the top. .

In the A phase shown in FIG. 6, in the first line (time t10 to t11 in frame1, time t20 to t21 in frame2), the control signal Cmod = 1 of the selector 21 is controlled, and the control value C _OSC = Nt (Trim value), oscillation frequency f _OSC = center frequency (ft). In the next second line (time t11 to t12, t21 to t22), Cmod = 0 is controlled, and the control values C _OSC = Nt + Nup and the oscillation frequency f _OSC = ft + Δf are obtained. In the next third line (time t12 to t13, t22 to t23), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft are obtained. In the next fourth line (time t13 to t14, t23 to t24), Cmod = 2 is controlled, and the control value C _OSC = Nt−Ndw and the oscillation frequency f _OSC = ft−Δf are obtained. Thereafter, the same pattern as the first line to the fourth line is repeated from the fifth line to the eighth line. Thereafter, the same pattern is repeated every 8 lines.

In the B phase shown in FIG. 7, in the first line (time t30 to t31 in frame 3, time t40 to t41 in frame 4), the control signal Cmod = 1 of the selector 21 is controlled, and the control value C _OSC = Nt (Trim value), oscillation frequency f _OSC = center frequency (ft). In the next second line (time t31 to t32, t41 to t42), Cmod = 2 is controlled, and the control value C _OSC = Nt−Ndw and the oscillation frequency f _OSC = ft−Δf are obtained. In the next third line (time t32 to t33, t42 to t43), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft. In the next fourth line (time t33 to t34, t43 to t44), Cmod = 0 is controlled, and the control values C _OSC = Nt + Nup and the oscillation frequency f _OSC = ft + Δf are obtained. Thereafter, the same pattern as the first line to the fourth line is repeated from the fifth line to the eighth line. Thereafter, the same pattern is repeated every 8 lines.

By controlling as described above, when the pixels of the first line and the third line are driven to display, the oscillation frequency f _OSC = center frequency (ft) is set in each frame. For the second line, the oscillation frequency f _OSC = ft + Δf is set for frame 1 and frame 2, and the oscillation frequency f _OSC = ft−Δf is set for frame 3 and frame 4. Contrary to the second line, the fourth line has the oscillation frequency f _OSC = ft−Δf at frame 1 and frame 2 and the oscillation frequency f _OSC = ft + Δf at frame 3 and frame 4. As for the second line, when the line cycle is shortened because the oscillation frequency f _OSC = ft + Δf in frame 1, the polarity of the drive voltage is inverted by inversion driving, and the same is shortened in the next frame 2 as well. Therefore, there is no bias depending on the polarity to which the drive voltage is applied, and liquid crystal burn-in is prevented. Similarly for the fourth line, when the line period is expanded because the oscillation frequency f _OSC = ft−Δf in frame 1, the polarity of the drive voltage is inverted by the inversion drive, and similarly in the next frame 2. Since it is enlarged, it is not biased by the polarity to which the drive voltage is applied, and the burn-in of the liquid crystal is prevented.

Further, in both the A phase shown in FIG. 6 and the B phase shown in FIG. 7, the number of lines with the oscillation frequency f _OSC = ft + Δf and the oscillation frequency f _OSC = ft−Δf are set within one frame. Since the number of lines is the same, the frame frequency is constant. Further, regarding the same second line, when the line cycle is shortened because the oscillation frequency f _OSC = ft + Δf in frame 1 and frame 2, the oscillation frequency f _OSC = ft−Δf is increased in frame 3 and frame 4, and the line cycle is expanded. Is done. On the other hand, regarding the fourth line, contrary to the second line, when the line period is expanded because the oscillation frequency f _OSC = ft−Δf in frame 1 and frame 2, the oscillation frequency f in frame 3 and frame 4. _OSC = ft + Δf and the line period is shortened. When integration is performed over a plurality of frames, the integrated value (total value) of the line periods for all lines is made uniform.

  Further, as described in the first embodiment, since the spread spectrum pattern is repeated in a cycle of 8 lines, it can be widely applied to various commonly used display panels with good consistency.

FIG. 8 is a timing chart showing the panel noise waveform in the first spread spectrum pattern (A phase). FIG. 7 shows the same time axis corresponding to FIG. 6, and in the vertical axis direction, in order from the top, the line period, the line number (line num.), The control value C _OSC and the oscillation frequency f _{OSC of the} oscillation circuit 6. , Horizontal synchronization signal HSYNC, source line drive signal Source, and panel noise due to current flowing in the source line are shown. Since the line period, line number (line num.), The control value C _OSC of the oscillation circuit 6 and the control pattern (spread spectrum pattern) of the oscillation frequency f _OSC are as in the A phase described with reference to FIG. Description is omitted. In the first line (time t10 to t11, t20 to t21), the source wiring is driven to the positive side (Posi), and a current in the positive direction flows as panel noise (Panel Noise) with the rising waveform. In the next second line (time t11 to t12, t21 to t22), the source wiring is driven to the negative side (Nega), and with the falling waveform, a current in the negative direction is generated as panel noise (Panel Noise). Flowing. Thereafter, positive and negative panel noises (Panel Noise) appear alternately for each line. The absolute value varies depending on the image data of the pixel for each of the source lines S1 to Sn.

FIG. 9 is a frequency distribution diagram of radiation noise in the first spread spectrum pattern. As a comparative example, FIG. 10 shows a frequency distribution diagram of radiation noise when spectrum spreading is not performed. The horizontal axis represents frequency, and the vertical axis represents the power of radiation (EMI) due to panel noise. When spectrum spread is not performed (FIG. 10), the oscillation frequency f _OSC of the oscillation circuit 6 is constant at the center frequency ft adjusted by trimming, and radiation (EMI) due to noise caused by the clock CLK of the oscillation circuit 6 Has a large peak at its oscillation frequency ft. Further, the radiation (EMI) due to panel noise has a large peak at the center frequency f0p because the line frequency is not spectrum spread. As shown in FIG. 10, the allowable value may be exceeded in some cases. As shown in the first embodiment, the oscillation frequency f _OSC of the oscillation circuit 6 is diffused in three ways of the center frequency ft, ft + Δf, and ft−Δf, so that as shown in FIG. Radiation (EMI) due to noise caused by the clock CLK is diffused to the three frequencies ft, ft + Δf, and ft−Δf. Since the total power of the clock CLK itself is equal to the case where it is not spread, the power is divided into three by spectrum spreading, and the peak becomes low. According to the present invention, the line frequency is similarly spectrum spread, so that the radiation (EMI) due to the panel noise is also divided into three and the peak is lowered.

[Embodiment 3]
A modification of the spread spectrum pattern will be described. The spread spectrum pattern can be implemented by various other combinations as long as the conditions described in the first embodiment are satisfied.

  FIG. 11 is an explanatory diagram showing the first spread spectrum pattern shown in the second embodiment, and FIGS. 12 to 14 are explanatory views showing second to fourth spread spectrum patterns different from the first spread spectrum pattern. Each figure shows a spread spectrum pattern with the first 8 lines as representatives for consecutive frames 1 to 4. For each line number (line num.), The oscillation frequency control “f-control” of the oscillation circuit 6, the line period “1H”, the oscillation frequency “fOSC” of the oscillation circuit 6, and the polarity “Source” of the source drive voltage are shown. It is. In “f-control”, “typ” with the oscillation frequency of the oscillation circuit 6 as the center frequency (ft), “f-up” with ft + Δf, and “f-down” with ft-Δf are shown. 1H "and" fOSC "indicate the corresponding line period and the oscillation frequency of the oscillation circuit 6, respectively. “Source” indicates either the positive electrode “Posi.” Or the negative electrode “Nega.”. Although only the first 8 lines are shown, it is preferable that the subsequent lines are repeated with a period of 8 lines as described above.

  In the first spread spectrum pattern shown in FIG. 11, as described in the second embodiment, in frame 1, f-control is type, f-up, type, f-down, type, f-up, type, f-down. The same pattern (A phase) is applied to frame 2 that is controlled in this order (A phase) and is driven in the reverse direction. In subsequent frames 3 and 4, f-control is controlled in the order of typ, f-down, type, f-up, type, f-down, type, and f-up in the reverse phase (B phase).

  In the second spread spectrum pattern shown in FIG. 12, in frame 1, the f-control is controlled in the order of type, f-up, type, f-up, type, f-down, type, f-down (A The same pattern (A phase) is applied to frame 2 that is driven to be inverted. In subsequent frames 3 and 4, f-control is controlled in the order of typ, f-down, type, f-down, type, f-up, type, and f-up in the reverse phase (B phase). In the first spread spectrum pattern, the control direction of the oscillation frequency in the fourth line and the eighth line is reversed, but the same pattern is applied to the same line in two consecutive frames. The effect of preventing liquid crystal burn-in can be obtained as in the case of the spectrum spread pattern 1. Also, in each frame, the number of lines that increase the oscillation frequency is the same as the number of lines that decrease, and when the same line is viewed across multiple frames, the number of controls that increase the oscillation frequency is equal to the number of controls that decrease the frequency. The same effect can be obtained.

  In the third spread spectrum pattern shown in FIG. 13, in frame 1, f-control is controlled in the order of type, f-up, f-up, type, type, f-down, f-down, type (A The same pattern (A phase) is applied to frame 2 that is driven to be inverted. In subsequent frames 3 and 4, f-control is controlled in the order of typ, f-down, f-down, type, type, f-up, f-up, and typ in the reverse phase (B phase). The first spread spectrum pattern is different in the control direction of the oscillation frequency between the third and fourth lines and the seventh and eighth lines, but the obtained effect is the same.

  In the fourth spread spectrum pattern shown in FIG. 14, in frame 1, f-control is controlled in the order of f-up, type, type, f-up, f-down, type, type, f-down (A phase). ), The same pattern (A phase) is applied to frame 2 that is driven to be inverted. In subsequent frames 3 and 4, f-control is controlled in the order of f-down, type, type, f-down, f-up, type, type, and f-up in reverse phase (B phase). Although the control direction of the oscillation frequency in all lines is different from the third spread spectrum pattern, the obtained effect is the same.

  The second spread spectrum pattern will be described in more detail.

FIGS. 15 and 16 are timing charts showing operation examples of the A phase and the B phase, respectively, of the second spread spectrum pattern. 15 and FIG. 16 correspond to FIG. 3 like FIG. 6 and FIG. As described with reference to FIG. 3, the same A phase is applied to frame1 and frame2, and an enlarged view of the first eight lines from time t10 and t20 is shown in FIG. Further, the same B phase is applied to frame 3 and frame 4, and an enlarged view of the first eight lines from time t30 and t40 is shown in FIG. The horizontal axis of FIGS. 15 and 16 is time, and in the vertical axis direction, the control signal Cmod of the selector 21, the control value C _OSC of the oscillation circuit 6, the oscillation frequency f _OSC, and the horizontal synchronization signal HSYNC are shown in order from the top. .

In the A phase shown in FIG. 15, the control signal Cmod = 1 of the selector 21 is controlled at the first line (time t10 to t11 in frame1, time t20 to t21 in frame2), and control value C _OSC = Nt (Trim value), oscillation frequency f _OSC = center frequency (ft). In the next second line (time t11 to t12, t21 to t22), Cmod = 0 is controlled, and the control values C _OSC = Nt + Nup and the oscillation frequency f _OSC = ft + Δf are obtained. In the next third line (time t12 to t13, t22 to t23), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft are obtained. In the next fourth line (time t13 to t14, t23 to t24), Cmod = 0 is controlled, and the control values C _OSC = Nt + Nup and the oscillation frequency f _OSC = ft + Δf are obtained. In the next fifth line (time t14 to t15, t24 to t25), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft. In the next sixth line (time t15 to t16, t25 to t26), Cmod = 2 is controlled, and the control value C _OSC = Nt−Ndw and the oscillation frequency f _OSC = ft−Δf are obtained. In the next seventh line (time t16 to t17, t26 to t27), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft. In the next eighth line (time t17 to t18, t27 to t28), Cmod = 2 is controlled, and the control value C _OSC = Nt−Ndw and the oscillation frequency f _OSC = ft−Δf are obtained. Thereafter, the same pattern is repeated every 8 lines. In the first spread spectrum pattern shown in FIG. 6, the same pattern as the first line to the fourth line is repeated from the fifth line to the eighth line, but in the second spread spectrum pattern, from the first line. The pattern of the fourth line is different from the pattern of the fifth to eighth lines.

In the B phase shown in FIG. 16, in the first line (time t30 to t31 in frame 3, time t40 to t41 in frame 4), the control signal Cmod = 1 of the selector 21 is controlled, and the control value C _OSC = Nt (Trim value), oscillation frequency f _OSC = center frequency (ft). In the next second line (time t31 to t32, t41 to t42), Cmod = 2 is controlled, and the control value C _OSC = Nt−Ndw and the oscillation frequency f _OSC = ft−Δf are obtained. In the next third line (time t32 to t33, t42 to t43), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft. In the next fourth line (time t33 to t34, t43 to t44), Cmod = 2 is controlled, and the control value C _OSC = Nt−Ndw and the oscillation frequency f _OSC = ft−Δf are obtained. In the next fifth line (time t34 to t35, t44 to t45), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft. In the next sixth line (time t35 to t36, t45 to t46), Cmod = 0 is controlled, and the control values C _OSC = Nt + Nup and the oscillation frequency f _OSC = ft + Δf are obtained. In the next seventh line (time t36 to t37, t46 to t47), Cmod = 1 is controlled, and the control value C _OSC = Nt and the oscillation frequency f _OSC = ft. In the next eighth line (time t37 to t38, t47 to t48), Cmod = 0 is controlled, and the control values C _OSC = Nt + Nup and the oscillation frequency f _OSC = ft + Δf are obtained. Thereafter, the same pattern is repeated every 8 lines. In the first spread spectrum pattern shown in FIG. 7, the same pattern as the first line to the fourth line is repeated from the fifth line to the eighth line. However, in the second spread spectrum pattern, from the first line. The pattern of the fourth line is different from the pattern of the fifth to eighth lines.

As described in the second embodiment with reference to FIG. 6 and FIG. 7, the first spread spectrum pattern is a pattern with a period of 4 lines, whereas the second spectrum pattern has no period for 4 lines. This is a line cycle pattern. Thus, although the spread spectrum patterns are different, the obtained effects are the same. By controlling as described above, the oscillation frequency f _OSC = center frequency (ft) is set to the first, third, fifth, and seventh lines in each frame. As for the second line and the fourth line, the oscillation frequency f _OSC = ft + Δf is set at frame 1 and frame 2, and the oscillation frequency f _OSC = ft−Δf is set at frame 3 and frame 4. Contrary to the second and fourth lines, the sixth line and the eighth line have an oscillation frequency f _OSC = ft−Δf at frame 1 and frame 2 and an oscillation frequency f _OSC = ft + Δf at frame 3 and frame 4. As for the second and fourth lines, when the line period is shortened in frame 1 because the oscillation frequency f _OSC = ft + Δf, the polarity of the drive voltage is inverted by the inversion drive, and similarly in the next frame 2 Since it is shortened, it is not biased depending on the polarity to which the drive voltage is applied, and the burn-in of the liquid crystal is prevented. Similarly, for the pixels of the sixth and eighth lines, when the line cycle is expanded in frame 1 because the oscillation frequency f _OSC = ft−Δf, the polarity of the drive voltage is inverted by the inversion drive. Since the frame 2 is similarly enlarged, it is not biased by the polarity to which the drive voltage is applied, and the burn-in of the liquid crystal is prevented.

Further, in both the A phase shown in FIG. 15 and the B phase shown in FIG. 16, the number of lines with the oscillation frequency f _OSC = ft + Δf and the oscillation frequency f _OSC = ft−Δf are set within one frame. Since the number of lines is the same, the frame frequency is constant. Further, regarding the same second and fourth lines, when the line period is shortened because the oscillation frequency f _OSC = ft + Δf in frame 1 and frame 2, the oscillation frequency f _OSC = ft−Δf is set in frame 3 and frame 4. The period is expanded. On the other hand, regarding the sixth and eighth lines, on the contrary to the second and fourth lines, when the line period is expanded because the oscillation frequency f _OSC = ft−Δf in frame 1 and frame 2, frame 3 And frame4, the oscillation frequency f _OSC = ft + Δf and the line period is shortened. When integration is performed over a plurality of frames, the integrated value (total value) of the line periods for all lines is made uniform.

  Further, as described in the first and second embodiments, since the spread spectrum pattern is repeated at a cycle of 8 lines, it can be widely applied to various commonly used display panels with good consistency.

FIG. 17 is a timing chart showing the panel noise waveform in the first spread spectrum pattern (A phase). FIG. 15 shows the same time axis corresponding to FIG. 15. In the vertical axis direction, the line period and line number (line num.), The control value C _OSC of the oscillation circuit 6 and the oscillation frequency f _OSC are shown in order from the top. , Horizontal synchronization signal HSYNC, source line drive signal Source, and panel noise due to current flowing in the source line are shown. Since the line period, line number (line num.), The control value C _OSC of the oscillation circuit 6 and the control pattern (spread spectrum pattern) of the oscillation frequency f _OSC are as in the A phase described with reference to FIG. Description is omitted. In the first line (time t10 to t11, t20 to t21), the source wiring is driven to the positive side (Posi), and a current in the positive direction flows as panel noise (Panel Noise) with the rising waveform. In the next second line (time t11 to t12, t21 to t22), the source wiring is driven to the negative side (Nega), and with the falling waveform, a current in the negative direction is generated as panel noise (Panel Noise). Flowing. Thereafter, positive and negative panel noises (Panel Noise) appear alternately for each line. The absolute value varies depending on the image data of the pixel for each of the source lines S1 to Sn. At this time, the frequency distribution of the radiation noise becomes low due to the dispersion of the peak power, similarly to the frequency distribution in the first spread spectrum pattern of the second embodiment shown in FIG.

  As described above, the second spread spectrum pattern is different from the first spread spectrum pattern. However, the second spread spectrum pattern is the same in that the conditions described in the first embodiment are satisfied. Although a detailed description is omitted, the same effect can be obtained for the other third and fourth spread spectrum patterns.

[Embodiment 4]
In Embodiments 2 and 3, the oscillation frequency (f _OSC ) is lower than the center frequency (ft) defined by the trimming value (Trim value, Nt), the higher frequency ft + Δf, and lower due to spread spectrum. An example in which switching control is performed between three frequencies ft−Δf is shown. However, the present invention is not limited to that form, and other control forms may be employed. For example, the center frequency (ft) may be excluded from the options, and the switching control may be performed between two frequencies of ft + Δf and ft−Δf. Conversely, options other than the center frequency (ft) may be changed to ft ± Switching control that increases in multiple stages, such as Δf1, ft ± Δf2, and ft ± Δf3, may be performed. Furthermore, the spread spectrum may not necessarily specify the center frequency clearly. Various spread spectrum patterns shown in the third embodiment are appropriately changed according to the choice of frequency.

FIG. 18 is a circuit diagram showing a second configuration example of the clock generation circuit that performs spectrum spreading according to the present invention. The center frequency (ft) can be excluded from the options, and switching control can be performed between two frequencies of ft + Δf and ft−Δf. Similarly to the clock generation circuit shown in FIG. 5, the clock generation circuit 4 can change the oscillation circuit 6 that generates the clock CLK and the oscillation frequency (f _OSC ) of the oscillation circuit 6 from the center frequency (ft). And an oscillation frequency control circuit 7. The oscillation frequency control circuit 7 switches whether the oscillation frequency (f _OSC ) of the oscillation circuit 6 is increased or decreased from the center frequency (ft) in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC. The configuration of the oscillation circuit 6 is the same as that shown in FIG.

The oscillation frequency control circuit 7 includes a selector 21, a select timing control circuit 8, an adder 22, a subtractor 23, and registers 24-26, as in the clock generation circuit shown in FIG. Is different in that it is changed to 2 inputs. The trimming value (Trim value, Nt) of the oscillation circuit 6 is supplied from the nonvolatile memory 19 to the oscillation frequency control circuit 7, and the adder 22 is held in the register 25 at this trimming value (Trim value, Nt). The subtracter 23 subtracts the predetermined value Ndw held in the register 26 from the trimming value (Trim value, Nt) and supplies Nt−Ndw to the selector 21 by adding the predetermined value Nup to Nt + Nup. However, the trimming value (Trim value, Nt) itself is not input to the selector 21. The select timing control circuit 8 controls the control signal Cmod for controlling the selector 21 in accordance with a predetermined pattern in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC, but the number of bits of the control signal Cmod may be 1 bit. . The selector 21 switches the control value (C _OSC ) for controlling the clock frequency for each corresponding line between Nt + Nup and Nt−Ndw according to the control signal Cmod.

  Thereby, the clock oscillation circuit 4 can be realized by a simpler digital circuit. In this clock oscillation circuit 4, although the center frequency (ft) is excluded from the choices depending on the circuit configuration, by setting zero in the registers 25 and 26, spectrum spreading is not performed (the oscillation is performed at a constant center frequency ft). It is also possible to operate in the operation mode.

FIG. 19 is a circuit diagram showing a third configuration example of the clock generation circuit that performs spectrum spreading according to the present invention. In order to perform switching control for increasing the options other than the center frequency (ft) to ft ± Δf1, ft ± Δf2, and ft ± Δf3 in multiple stages, FIG. 19 shows five examples including the center frequency (ft) as an example. A configuration of the clock generation circuit 4 that enables switching control is shown. Similarly to the clock generation circuit shown in FIGS. 5 and 18, the clock generation circuit 4 changes the oscillation circuit 6 that generates the clock CLK and the oscillation frequency (f _OSC ) of the oscillation circuit 6 from the center frequency (ft). And an oscillating frequency control circuit 7 capable of performing the same. The oscillation frequency control circuit 7 switches whether the oscillation frequency (f _OSC ) of the oscillation circuit 6 is increased or decreased from the center frequency (ft) in five stages in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC. . The configuration of the oscillation circuit 6 is the same as that shown in FIG.

The oscillation frequency control circuit 7 includes a selector 21, a select timing control circuit 8, two adders 22_1 and 22_2, two subtractors 23_1 and 23_2, and registers 24-28, and the selector 21 has five inputs. The number of bits of the control signal Cmod is changed to 3 bits. The trimming value (Trim value, Nt) of the oscillation circuit 6 is supplied from the nonvolatile memory 19 to the oscillation frequency control circuit 7, and the adder 22_1 is held in the register 25 at this trimming value (Trim value, Nt). Nup1 is added to Nt + Nup1, and the adder 22_2 adds Nup2 held in the register 27 to supply Nt + Nup2 to the selector 21, respectively. The subtractor 23_1 subtracts Ndw1 held in the register 26 from the trimming value (Trim value, Nt) to obtain Nt-Ndw1, and the subtractor 23_1 subtracts Ndw2 held in the register 28 to obtain Nt-Ndw2. This is supplied to the selector 21. The trimming value (Trim value, Nt) itself is also input to the selector 21. The selector 21 selects one of the five types Nt, Nt + Nup1, Nt + Nup2, Nt-Ndw1, and Nt-Ndw2, and supplies the control value (C _OSC ) to the oscillation circuit 6. The select timing control circuit 8 controls the selector 21 in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC.

  As a result, the clock oscillation circuit 4 can be realized with a simple digital circuit even when controlling the oscillation frequency for spread spectrum in multiple stages.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

For example, an example in which the oscillation frequency of the oscillation circuit 6 is configured using a ring oscillator capable of controlling the oscillation frequency by a 6-bit control value (C _OSC ) has been shown. Needless to say, the number of bits can be changed. The frequency control method can be changed to, for example, a method of changing the number of inverter stages constituting the ring oscillator, a method of controlling the size of the current source inserted in series with the power source of the inverter, or another control method. it can. Further, instead of the ring oscillator, another clock signal inputted from the outside is multiplied by a multiplication circuit having a PLL (Phase Locked Loop) or the like to change to a circuit that generates the internal clock CLK, and the multiplication number at that time It may be changed so as to realize spread spectrum by controlling. Further, an analog spread spectrum circuit using an original oscillation circuit and a frequency modulation circuit may be used.

1 Display drive circuit (display driver)
2 Display panel 3 Host processor 4 Clock generation circuit 5 Control unit (TCON)
6 Oscillation Circuit 7 Oscillation Frequency Control Circuit 8 Select Timing Control Circuit 10 Source Driver 11 Gradation Voltage Selection Circuit 12 Data Latch 13 Memory 14 Gate Control Driver 15 Power Supply Circuit 16 Control Interface 17 Image Data Interface 18 Gate Drive Circuit (Gate In Panel)
19 Nonvolatile memory (NV memory)
20, 21 Selector 22 Adder 23 Subtractor 24-28 Register INV0-INV5 Inverter C0 Capacitance R0-R63 Resistor s0-s63 Switch

Claims (15)

A display driving circuit for driving a liquid crystal display panel in which one frame is composed of a plurality of lines, comprising a clock generation circuit,
The clock generation circuit generates a clock for generating a horizontal synchronization signal that is a reference of timing for driving the plurality of lines;
The clock generation circuit spreads the clock in such a manner that the period of the horizontal synchronization signal corresponding to each line in the frame is dispersed in the same frame and equal for each line between two consecutive frames. Display drive circuit.   2. The display driving circuit according to claim 1, wherein the clock generation circuit spreads the clock spectrum so as to keep the frame frequency constant.   The clock generation circuit according to claim 2, wherein the period of the horizontal synchronizing signal corresponding to each line in the frame is integrated over a plurality of predetermined frames for each line, for all lines in the frame. A display drive circuit that spreads the clock spectrum so as to have the same value.   3. The clock generation circuit according to claim 2, wherein the clock generation circuit spreads the clock so that a spread pattern of a frequency of a horizontal synchronizing signal having a period corresponding to each line in the frame is repeated in a period of 8 lines adjacent in the frame. A display driving circuit.   2. The clock generation circuit according to claim 1, further comprising: an oscillation circuit that generates the clock; and an oscillation frequency control circuit that can change an oscillation frequency of the oscillation circuit from a center frequency. A display drive circuit that switches whether the oscillation frequency is higher or lower than the center frequency in synchronization with the horizontal synchronization signal.   6. The oscillation frequency control circuit according to claim 5, wherein the oscillation frequency control circuit is configured to determine the number of lines corresponding to a horizontal synchronization signal generated based on a clock having the oscillation frequency increased from the center frequency, and the oscillation frequency from the center frequency. The number of lines corresponding to the horizontal synchronization signal generated based on the lowered clock is the same in the same frame, and when viewed over a plurality of frames, the corresponding horizontal A display driving circuit for switching the oscillation frequency so that a frequency of generating a synchronization signal is equal to a frequency of being increased from a center frequency and a frequency of being decreased.   6. The oscillation circuit according to claim 5, wherein an oscillation frequency is designated by an input control value, the oscillation frequency control circuit includes a selector and a select timing control circuit for controlling the selector, and the selector includes the oscillation circuit. One of a plurality of control values, including a trimming value that defines the center frequency, a value obtained by adding a first value to the trimming value, and a value obtained by subtracting a second value from the trimming value And a selection timing control circuit for causing the selector to select one control value from the plurality of control values in synchronization with the horizontal synchronization signal. .   8. The display driving circuit according to claim 7, further comprising: a memory capable of storing the trimming value; and a register capable of storing the first value and the second value. A display driving circuit for driving a liquid crystal display panel in which one frame is composed of a plurality of lines, comprising a clock generation circuit for supplying a clock as a reference for timing for driving the plurality of lines;
The clock generation circuit includes an oscillation circuit that generates the clock, and an oscillation frequency control circuit that can switch a change amount of the frequency of the clock from a center frequency for each line,
The oscillation frequency control circuit controls the oscillation circuit so that the amount of change corresponding to each line in the frame is dispersed within the same frame and equal for each line between two consecutive frames. .   The display drive circuit according to claim 9, wherein the oscillation frequency control circuit controls the oscillation circuit so that a total of the change amounts corresponding to all lines in the frame is constant between different frames.   11. The oscillation frequency control circuit according to claim 10, wherein when the amount of change corresponding to each line in a frame is integrated over a plurality of predetermined frames for each line, the same value is obtained for all lines. A display driving circuit for controlling the oscillation circuit.   11. The display drive according to claim 10, wherein the oscillation frequency control circuit controls the oscillation circuit so that the change amount corresponding to each line in the frame periodically changes in a period of 8 lines adjacent in the frame. circuit.   10. The oscillation frequency control circuit according to claim 9, wherein the oscillation frequency control circuit lowers the number of lines for generating a horizontal synchronization signal based on a clock whose oscillation frequency is increased from the center frequency, and the oscillation frequency is decreased from the center frequency. The number of lines in which the horizontal synchronization signal is generated based on the same clock is the same in the same frame, and when viewed over a plurality of frames, the corresponding clock is the center frequency for each line. A display driving circuit that controls the oscillation frequency so that the frequency increased and decreased are equal to each other.   10. The oscillation circuit according to claim 9, wherein an oscillation frequency is designated by an input control value, the oscillation frequency control circuit includes a selector and a select timing control circuit that controls the selector, and the selector includes the oscillation circuit. One of a plurality of control values, including a trimming value that defines the center frequency, a value obtained by adding a first value to the trimming value, and a value obtained by subtracting a second value from the trimming value And a selection timing control circuit for causing the selector to select one control value from the plurality of control values in synchronization with the horizontal synchronization signal. .   15. The display driving circuit according to claim 14, further comprising a memory capable of storing the trimming value, and a register capable of storing the first value and the second value, respectively.

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