JP2015187833A - Information processor, information processing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of analyzing problems caused by writing data to a specific wiring-forbidden area of a storage region of a storage unit, in a system for reading data from the storage unit and transferring the data to a transfer destination device.SOLUTION: The information processor includes a transfer unit and a control unit, the transfer unit writing data as transfer target to a first storage unit according to a transfer instruction from an external control unit and then reading and transferring to the transfer destination device the data from the first storage unit according to the data processing rate of a transfer destination device; and a control unit notifying the external control unit of abnormal writing of data to the first storage unit if there is detected writing of data to a specific writing-forbidden area of a storage region of the first storage unit and writing to the first storage unit first information that allows identification of an area of the storage region of the first storage unit where data has been written.

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program.

  The system configuration of an electrophotographic image forming apparatus includes a memory such as a RAM (Random Access Memory) and a semiconductor integrated circuit such as a CPU (Central Processing Unit) that performs arithmetic processing. A system program for controlling a semiconductor integrated circuit such as a CPU and data to be transferred (for example, image data to be printed or image data obtained by scanning a document) are written in a memory such as a RAM. It is.

  When the system program and the transfer target data are stored in the same memory, the transfer target data is written into the memory. In such a case, the data to be transferred may be erroneously written in an area of the memory where the system program is stored, causing the image forming apparatus system to freeze. In addition, data to be transferred may be written in an area where other data is stored in the memory, and the data stored in the memory may become abnormal data. Therefore, a technique for prohibiting writing of data to be transferred to a predetermined write-protected area in the memory is disclosed.

  As described above, writing of data to be transferred to a predetermined write-protected area in the memory is prohibited. In this technique, a start address and an end address of a predetermined write-protected area are set in advance, and when data to be transferred is written to the predetermined write-protected area, a semiconductor integrated circuit such as a CPU is used. However, it is limited to notifying interrupts. Writing of data to be transferred to the memory is performed by a semiconductor integrated circuit such as a CPU. In such a case, it is possible to detect the address (hereinafter referred to as the last access address) of the area in the memory where the semiconductor integrated circuit last written data in the semiconductor integrated circuit.

  However, it is difficult for the CPU to detect the final access address when data to be transferred is written to a predetermined write-protected area by a DMA (Direct Memory Access) controller. For this reason, the information is insufficient to analyze a problem caused by writing data to a predetermined write-protected area. In particular, when the image forming apparatus is operated in accordance with an incomplete system program in the product development stage, there are the following problems. That is, problems such as destruction of the system program, destruction of image data or DMA transfer information (information that can specify the area in which data to be transferred is written in the memory) may occur. It depends.

  For example, DMA transfer information and image data are written in different address areas in the memory. In the product development stage, because the memory management is incomplete, the data to be transferred is overwritten on other data to be transferred or a part of the DMA transfer information of the data, and the data to be transferred There are cases where the DMA transfer information is destroyed. In addition, due to incomplete management of the area in which the data to be transferred is written in the memory, the data to be transferred is written in a predetermined write-protected area such as an area in which the system program is stored. In some cases, damage may occur.

  The present invention has been made in view of the above, and an object of the present invention is to improve the efficiency of analysis of a defect caused by writing data to a predetermined write-protected area in a storage area of a storage unit.

  In order to solve the above-described problems and achieve the object, the present invention writes the data to be transferred to the first storage unit in accordance with the transfer instruction from the external control unit and according to the data processing speed of the transfer destination device. A transfer unit that reads data from the first storage unit and transfers the data to the transfer destination device; and when the first storage unit detects writing of data to a predetermined write-protected area in the storage area of the first storage unit A control unit for notifying the external control unit of abnormal data writing to the first control unit, and writing first information to the first storage unit that enables specification of a write region in which data is written out of the storage regions of the first storage unit And.

  The present invention has an effect that it is possible to improve the efficiency of analyzing a failure caused by writing data to a predetermined write-protected area in the storage area of the storage unit.

FIG. 1 is a block diagram illustrating a hardware configuration of an image forming apparatus that is an example of an information processing apparatus according to the present embodiment. FIG. 2 is a block diagram illustrating a functional configuration of the ASIC included in the image forming apparatus according to the present embodiment. FIG. 3 is a block diagram illustrating a configuration example of the register access monitoring unit. FIG. 4 is a diagram illustrating an example of a data configuration of DMA transfer information written in a RAM included in the image forming apparatus according to the present embodiment. FIG. 5 is a diagram illustrating an example of a data configuration of register access information transmitted to the access history storage control unit of the image forming apparatus according to the present embodiment. FIG. 6 is a diagram illustrating an example of a data configuration of DMA transfer information transmitted to the access history storage control unit of the image forming apparatus according to the present embodiment. FIG. 7 is a flowchart showing a flow of trace data writing processing by the ASIC included in the image forming apparatus according to the present embodiment. FIG. 8 is a flow chart for analyzing a problem occurring in the system according to the present embodiment.

  Exemplary embodiments of an information processing apparatus, an information processing method, and a program according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment)
FIG. 1 is a block diagram illustrating a hardware configuration of an image forming apparatus that is an example of an information processing apparatus according to the present embodiment. An image forming apparatus according to the present embodiment includes an application specific integrated circuit (ASIC) 101, a central processing unit (CPU) 102, a random access memory (RAM) 103, a scanner 104, and a printer 105. Yes.

  The ASIC 101 controls input / output of various data between the peripheral device such as the scanner 104 and the printer 105 and the RAM 103. The various data is, for example, read data that is image data input from the scanner 104, write data that is image data output to the printer 105, and the like. The ASIC 101 also has a function of performing image processing by hardware on image data such as read data and write data.

  In the present embodiment, the ASIC 101 writes data to be transferred (for example, read data and write data) in the RAM 103 in response to a transfer start instruction (an example of a transfer instruction) from the CPU 102. The ASIC 101 also has a DMA (Direct Memory Access) transfer function that reads data from the RAM 103 according to the data processing speed of a transfer destination device (for example, a peripheral device such as the printer 105, an external storage device, etc.) and transfers the data to the transfer destination device. Have. Further, the ASIC 101 sets a predetermined write prohibition area that prohibits data writing in the storage area of the RAM 103. When the ASIC 101 monitors (detects) the writing of data to the write-protected area, the ASIC 101 notifies the CPU 102 of an abnormality in writing data to the RAM 103.

  The CPU 102 controls the operation of the entire image forming apparatus by executing various programs such as a system program stored in the RAM 103. In the present embodiment, the CPU 102 has a function of writing various information to a register included in the ASIC 101 and performing image processing by software.

  The RAM 103 (an example of a first storage unit) is a storage unit that can store data to be transferred. In this embodiment, the RAM 103 includes DMA transfer information including information to be transferred and information that can specify an area (hereinafter referred to as a write area) in which the data to be transferred is written in the storage area of the RAM 103. Store various programs. The scanner 104 is a reading unit that reads an original and outputs image data (read data) obtained by reading the original to the ASIC 101. The printer 105 is a printing unit that prints an image based on the image data (write data) input from the ASIC 101 on a recording medium.

  FIG. 2 is a block diagram illustrating a functional configuration of the ASIC included in the image forming apparatus according to the present embodiment. The ASIC 101 includes a first interface control unit 201, a second interface control unit 202, an arbiter 203, image processing units 204 to 206, a register control unit 207, a register access monitoring unit 208, a DMA transfer information monitoring unit 209, and an access history storage control unit. 210 and an interrupt control unit 211. Note that all or part of the functions of the ASIC described above may be configured by hardware.

  The first interface control unit 201 includes a general-purpose interface such as a CPU bus or PCI Express, for example, and receives various instructions from the CPU 102 (for example, a transfer start instruction from the CPU 102).

  The second interface control unit 202 is configured by a general-purpose interface such as DDR (Double Data Rate) -SDRAM (Synchronous Dynamic Random Access Memory), and transmits / receives various information to / from the RAM 103.

  The arbiter 203 controls communication between each unit (device) connected by the internal bus of the ASIC 101.

  The image processing units 204 to 206 perform image processing on the transfer target data written to the RAM 103. In the present embodiment, the image processing units 204 to 206 (an example of a transfer unit) realize a DMA transfer function in the ASIC 101. In the following description, the DMA transfer function realized by the image processing unit 204 will be described, but the DMA transfer function is similarly realized in the other image processing units 205 and 206.

  The image processing unit 204 performs the next transmission when a transfer start instruction is written in a register of a later-described register control unit 207 by the CPU 102 (an example of an external control unit) via the first interface control unit 201. That is, a DMA transfer information read instruction (descriptor read flag) for instructing the arbiter 203 to read DMA transfer information is transmitted. Next, the image processing unit 204 acquires DMA transfer information from the access history storage control unit 210 described later via the arbiter 203. Then, the image processing unit 204 writes data to be transferred to the RAM 103 based on the acquired DMA transfer information. At that time, the image processing unit 204 writes DMA transfer information (an example of third information) that enables the transfer target data to be specified in the RAM 103 together with the transfer target data.

  Furthermore, the image processing unit 204 reads the transfer target data from the RAM 103 according to the data processing speed in the transfer destination device that is the transfer destination of the transfer target data, and transfers the data to the transfer destination device. At that time, the image processing unit 204 accesses the DMA transfer information stored in the RAM 103, specifies the writing area of the data to be transferred, reads the data from the specified writing area, and transfers it to the transfer destination device. .

  When a register access request is issued from the CPU 102, the register control unit 207 performs register access to each module.

  The register access monitoring unit 208 extracts only the write access to each register from the CPU 102 and transfers information to the access history storage control unit 210. Further, the register access monitoring unit 208 monitors the contents of register access, and transfers information to the access history storage control unit 210 in the case of register access within a specified range.

  When the DMA transfer information monitoring unit 209 receives the descriptor read flag from the image processing units 204 to 206 having the respective DMA functions, the descriptor transfer request information is based on the ID information attached to the image processing units 204 to 206. To extract. The extracted data is added with time information, ID information, and descriptor address information, and transferred to the access history storage control unit 210.

  When the DMA transfer information monitoring unit 209 detects a write access request to the write prohibited area, the DMA transfer information monitoring unit 209 issues a write address error notification to the image processing unit being transferred. Upon receiving the error notification, the image processing unit forcibly stops the DMA transfer of the internal DMA transfer unit and stops the transfer. Further, the image processing unit issues an interrupt notification to the interrupt control unit 211.

  The access history storage control unit 210 arranges information sent from the DMA transfer information monitoring unit 209 in time series and stores it in an internal buffer. When receiving a write address error notification from the DMA transfer information monitoring unit 209, the access history storage control unit 210 executes the following operation. The access history storage control unit 210 issues a DMA transfer request to the storage unit (for example, the RAM 103) connected to the second interface control unit 202 to the arbiter 203, and registers access history data and descriptor history data. Transfer to storage.

  The interrupt control unit 211 performs interrupt control inside the ASIC, for example, notifies the CPU 102 of an interrupt and notifies that it is abnormal.

  FIG. 3 is a block diagram illustrating a configuration example of the register access monitoring unit 208. The register access monitoring unit 208 as an access monitoring unit includes a register information input unit 220, a storage range designation unit 221, an activation information acquisition unit 222, and an output unit 223. Note that all or part of the above-described functions may be configured by hardware.

  When the register information input unit 220 detects a register write access from the register control unit 207, the register information input unit 220 transfers the register access data to the storage range designation unit 221 and the activation information acquisition unit 222. The storage range designation unit 221 filters the designated address range. The activation information acquisition unit 222 filters other than the DMA activation register. The output unit 223 notifies the access history storage control unit 210 of the register access data that has passed the filters of the storage range specification unit 221 and the activation information acquisition unit 222.

  The control signal 225 is a control signal for controlling an address range designation signal sent from the register control unit 207 and whether to select the inside or outside of the range. For example, when the control signal is High, a filter is applied outside the designated address range, and when the control signal is Low, the filter is applied within the designated address range. Either logic setting is acceptable. The control signal 225 includes a register for designating an address range by the register control unit 207, and a signal for transmitting the designated address there, or a register control signal for controlling the register having the register in the storage range designating unit 221. ,either will do. In the case of an address designated for storage, the address is transmitted to the output unit 223, and in other cases, the address is transmitted to the activation information acquisition unit 222.

  The control signal 225 is a control signal for controlling whether or not to save the address of the activation register of each of the image processing units 204 to 206 sent from the register control unit 207. The control signal 225 includes a register for designating which start register address of the image processing units 204 to 206 is stored in the register control unit 207, and may be a signal for transmitting the designated address. Further, either a register control signal that has a register in the storage range designation unit 221 and controls the register may be used. The register access data transmitted from the storage range designation unit 221 is filtered again by the activation information acquisition unit 222, and if it is the address of the activation register, it is transmitted to the output unit 223. Otherwise, the data is discarded.

  The register access monitoring unit 208 includes a storage range specifying unit 221 that specifies an address range of a first storage unit (RAM 103) that stores access information from the external control unit (CPU 102). As a result, it is possible to extract only really necessary information by not storing unnecessary register write access information during failure analysis.

  The register access monitoring unit 208 selects within or out of the address range specified based on the control signal 225. As a result, it is possible to flexibly cope with a case where it is desired to collect information at the time of failure analysis and delete unnecessary information.

  The register access monitoring unit 208 includes an activation information acquisition unit 222 that acquires only the registers that activate the image processing units 204 to 206. This is effective when only the activation timing of the image processing units 204 to 206 is analyzed, and the analysis can be performed more efficiently.

  The activation information acquisition unit acquires the activation registers of the image processing units 204 to 206 designated based on the control signal 225. This is effective when it is desired to intensively analyze only the designated image processing unit, and the analysis can be performed more efficiently.

  When the register access monitoring unit 208 selects an address outside the address range, the register access monitoring unit 208 acquires a start register outside the address range. This is effective when it is desired to acquire a start register arranged outside the address range to be acquired, and analysis can be performed more efficiently.

  FIG. 4 is a diagram illustrating an example of a data configuration of DMA transfer information written in a RAM included in the image forming apparatus according to the present embodiment. The DMA transfer information includes address information 301 which is information that can specify an area in which the next DMA transfer information is written in the storage area of the RAM 103, and the start address (start address) information of the write area of the data to be transferred. 302, line number information 303 indicating the number of lines in the write area of the data to be transferred, and other information 304 regarding the data to be transferred. In this embodiment, each piece of information 301 to 304 included in the DMA transfer information is 32-bit width data. Therefore, the DMA transfer information is 128-bit data.

  Returning to FIG. 2, the image processing unit 204 receives a write address error notification when the DMA transfer information monitoring unit 209 described later detects the writing of data in the write-protected area. Then, data writing to the RAM 103 and data reading from the RAM 103 are stopped (in other words, data transfer is stopped). Further, the image processing unit 204 instructs an interrupt control unit 211 (to be described later) to transmit an interrupt notification to the CPU 102 (notification of abnormal data writing to the RAM 103).

  The register control unit 207 includes a register in which various instructions are written by the CPU 102 via the first interface control unit 201. The register access monitoring unit 208 detects writing of various instructions to the register included in the register control unit 207. Then, register access information (an example of second information) that is information that can specify various instructions for the register (for example, a transfer start instruction corresponding to data writing to the RAM 103) is transmitted to the access history storage control unit 210. To do.

  FIG. 5 is a diagram illustrating an example of a data configuration of register access information transmitted to the access history storage control unit of the image forming apparatus according to the present embodiment. In the present embodiment, the register access information includes address information 401 and instruction information 402 as shown in FIG. The address information 401 is information that makes it possible to specify a storage area in which various instructions from the CPU 102 are written in a register included in the register control unit 207. The instruction information 402 is information indicating various instructions written in a register included in the register control unit 207. In the present embodiment, the address information 401 and the instruction information 402 included in the register access information are 32-bit data. Therefore, the register access information is 64-bit data.

  Returning to FIG. 2, when the descriptor read flag is transmitted from the image processing unit 204 to the arbiter 203, the DMA transfer information monitoring unit 209 reads the DMA transfer information from the RAM 103. Then, the DMA transfer information monitoring unit 209 transmits the read DMA transfer information to the access history storage control unit 210.

  FIG. 6 is a diagram illustrating an example of a data configuration of DMA transfer information transmitted to the access history storage control unit of the image forming apparatus according to the present embodiment. In the present embodiment, as shown in FIG. 6, the DMA transfer information monitoring unit 209 adds ID information 501, address information 502, and time information 503 to the DMA transfer information shown in FIG. To the access history storage control unit 210.

  Here, the ID information 501 is an example of information that makes it possible to specify the image processing unit (any one of the image processing units 204 to 206) that has written the data specified by the read DMA transfer information. The address information 502 is information that enables the storage area of the DMA transfer information in the RAM 103 to be specified. The time information 503 is information that makes it possible to specify the time when the DMA transfer information is accessed. That is, the time information 503 is a time counted by using a 1 / 256-divided clock input to the DMA transfer information monitoring unit 209, for example. In this embodiment, each piece of information 501 to 503 and 301 to 304 included in the DMA transfer information transmitted to the access history storage control unit 210 is 32-bit data. Therefore, the DMA transfer information transmitted to the access history storage control unit 210 is 256-bit data.

  Returning to FIG. 2, the DMA transfer information monitoring unit 209 detects writing of data to the write-protected area by the image processing units 204 to 206. Here, as described above, the write-inhibited area is an area in which data writing is prohibited in the storage area of the RAM 103. In the present embodiment, the write-inhibited area is an area in which the system program is stored, an area in which DMA transfer information is stored, among the storage areas in the RAM 103. When the DMA transfer information monitoring unit 209 detects writing of data to the write-protected area, the DMA transfer information monitoring unit 209 sends an error notification (hereinafter referred to as a write address error notification) to the image processing unit 204 that is writing the data. Send.

  The access history storage control unit 210 arranges the register access information and the DMA transfer information input from the register access monitoring unit 208 and the DMA transfer information monitoring unit 209 in the order of input and writes them in the internal buffer (an example of the second storage unit). . As a result, the image processing unit 204 described above can acquire the DMA transfer information via the arbiter 203. In addition, when writing of data to the write-protected area is detected, a failure analysis can be performed using the DMA transfer information and the register access information stored in the internal buffer. Thus, it is possible to easily detect that an erroneous transfer start instruction has been issued and that data has been written to the write-protected area.

  The access history storage control unit 210 (an example of a control unit) performs the following operation when the DMA transfer information monitoring unit 209 detects writing of data in the write-protected area. That is, the access history storage control unit 210 writes the trace data including the register access information and DMA transfer information (an example of the first information) stored in the internal buffer to the RAM 103. In the present embodiment, the access history storage control unit 210 writes the trace data in a predetermined storage area of the storage area of the RAM 103. Here, the predetermined storage area is a storage area other than the write area of the transfer target data, the area where the DMA transfer information of the transfer target data is written, and the write prohibition area among the storage areas of the RAM 103. In this embodiment, the access history storage control unit 210 writes both the DMA transfer information and the register access information in the RAM 103. However, at least the DMA transfer information may be written in the RAM 103.

  When the DMA transfer information monitoring unit 209 detects writing of data in the write-protected area, the following operation is performed. That is, the interrupt control unit 211 (an example of a control unit) notifies the CPU 102 of an interrupt via the first interface control unit 201 when an instruction to transmit an interrupt notification is issued from the image processing units 204 to 206. Send.

  Next, a trace data writing process by the ASIC included in the image forming apparatus according to the present embodiment will be described with reference to FIG. FIG. 7 is a flowchart showing a flow of trace data writing processing by the ASIC included in the image forming apparatus according to the present embodiment.

  When the DMA transfer information monitoring unit 209 starts writing data to be transferred to the RAM 103 by the image processing unit 204 in response to a transfer start instruction from the CPU 102, has the data been written to a predetermined write-protected area? It is determined whether or not (step S601). When the DMA transfer information monitoring unit 209 detects writing of data in the write-protected area (step S601: Yes), the DMA transfer information monitoring unit 209 transmits a write address error notification to the image processing unit 204 (step S602).

  In addition, when a transfer start instruction is written in the register of the register control unit 207, the DMA transfer information monitoring unit 209 determines whether or not a descriptor read flag is transmitted from the image processing unit 204 to the arbiter 203 (step). S603). When the descriptor read flag is transmitted to the arbiter 203 (step S603: Yes), the DMA transfer information monitoring unit 209 reads the DMA transfer information written in the RAM 103 from the RAM 103 (step S604). Then, the DMA transfer information monitoring unit 209 adds the ID information 501, the address information 502 and the time information 503 to the read DMA transfer information according to the data format shown in FIG. 6 and transmits it to the access history storage control unit 210. To do.

  ID information 501 is added to the read DMA transfer information. For this reason, when data writing to the write-protected area is detected, it is possible to easily identify which image processing unit 204 to 206 has an abnormality in memory management (data writing processing to the RAM 103). it can. As a result, it is possible to reduce the burden of the trouble analysis work caused by the data writing to the RAM 103.

  Further, address information 502 and time information 503 are added to the read DMA transfer information. For this reason, when data writing to the write-protected area is detected, it is possible to specify when and what data is transferred by the image processing unit 204. Thereby, it is possible to easily detect whether or not the data transfer by the image processing unit 204 is directly related to the malfunction caused by the data writing to the RAM 103.

  The access history storage control unit 210 stores the DMA transfer information received from the DMA transfer information monitoring unit 209 in the internal buffer. In addition, the DMA transfer information monitoring unit 209 determines whether an error due to data writing to the write-protected area is detected (step S605). The DMA transfer information monitoring unit 209 repeats the processes shown in steps S603 and S604 when no error due to data writing to the write-protected area is detected (step S605: No).

  The register access monitoring unit 208 determines whether or not a transfer start instruction is written in the register included in the register control unit 207 (step S606). When the transfer start instruction is written to the register included in the register control unit 207 (step S606: Yes), the register access monitoring unit 208 acquires the register access information illustrated in FIG. 5 and stores it in the access history storage control unit 210. Transmit (step S607). As a result, the access history storage control unit 210 writes the register access information received from the register access monitoring unit 208 to the internal buffer. Further, the register access monitoring unit 208 determines whether or not an error due to data writing to the write-protected area has been detected (step S608). The register access monitoring unit 208 repeats the processes shown in step S606 and step S607 when an error due to the writing of data to the write-protected area is not detected (step S608: No). In the ASIC 101, the processes shown in steps S <b> 601 to S <b> 608 described above are performed in parallel until an error due to data writing in the write-protected area is detected.

  When an error due to data writing to the write-protected area is detected (step S601: Yes, step S605: Yes, step S608: Yes), the following operation is performed. In other words, the interrupt control unit 211 transmits an interrupt notification to the CPU 102 via the first interface control unit 201 in response to an interrupt notification transmission instruction from the image processing unit 204 (step S609). .

  In addition, when the DMA transfer information monitoring unit 209 detects writing of data in the write prohibited area, the DMA transfer information monitoring unit 209 prohibits (forcibly stops) data transfer. That is, the DMA transfer information monitoring unit 209 transmits a write address error notification to the image processing unit 204. By this transmission, writing of data into the RAM 103 and reading of data from the RAM 103 by the image processing unit 204 are stopped, and data transfer is prohibited (forced stop) (step S610). As a result, when writing of data to the write protected area is detected, writing of trace data to the RAM 103 can be started without delay. Therefore, it is possible to immediately enter a state in which a failure analysis work by writing data to the RAM 103 can be performed.

  Further, the access history storage control unit 210 performs the following operation when an error due to data writing to the write-protected area is detected. That is, the access history storage control unit 210 writes (traces) the trace data including the register access information and the DMA transfer information stored in the access history storage control unit 210 in a predetermined storage area of the RAM 103 (step S611). .

  FIG. 8 is a flow chart for analyzing a problem occurring in the system according to the present embodiment. First, after setting a trace in the system including the ASIC described above, an actual machine analysis test is performed based on predetermined evaluation items (step S801). Subsequently, trace information is acquired from the result of the test, and the trace information is acquired (step S802). Subsequently, the analyst determines whether or not all information necessary for the actual machine analysis test has been acquired (step S803). When it is determined in step S803 that the information is insufficient (step S803: No), the image forming system designates the address range and the acquisition range of the activation register of each of the image processing units 204 to 206 in order to narrow down the address range to be traced. (Step S804), and the actual machine test is performed again. On the other hand, if sufficient information is obtained in step S803 (step S803: Yes), acquisition of information for analysis is terminated.

  As described above, according to the present embodiment, when data is written to the write-protected area of the RAM 103, the problem of data writing to the RAM 103 can be easily performed using the DMA transfer information written to the RAM 103. Can be detected. Accordingly, in the system in which the image processing unit 204 writes the data to be transferred to the RAM 103 in response to the transfer start instruction from the CPU 102, the efficiency of the analysis of the trouble caused by the writing of the data to the write protected area in the storage area of the RAM 103 is improved. Can be improved.

  A program executed by the image forming apparatus of the present embodiment is provided by being incorporated in advance in a ROM (Read Only Memory) or the like. A program executed by the image forming apparatus is an installable or executable file and can be read by a computer such as a CD-ROM, a flexible disk (FD), a CD-R, or a DVD (Digital Versatile Disk). You may comprise so that it may record and provide on a recording medium.

  Furthermore, the program executed by the image forming apparatus according to the present embodiment may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Further, the program executed by the image forming apparatus of the present embodiment may be provided or distributed via a network such as the Internet.

  The programs executed by the ASIC 101 of the image forming apparatus according to the present embodiment include the above-described units (first interface control unit 201, second interface control unit 202, arbiter 203, image processing units 204 to 206, register control unit 207, The module configuration includes a register access monitoring unit 208, a DMA transfer information monitoring unit 209, an access history storage control unit 210, and an interrupt control unit 211). As actual hardware, a control unit such as a CPU included in the ASIC 101 reads the program from the ROM and executes the program, so that the respective units are loaded on the main storage device, and the first interface control unit 201 and the second interface control unit 202 are loaded. , The arbiter 203, the image processing units 204 to 206, the register control unit 207, the register access monitoring unit 208, the DMA transfer information monitoring unit 209, the access history storage control unit 210, and the interrupt control unit 211 are generated on the main storage device. It is like that.

  In the above description, the information processing apparatus, the information processing method, and the program according to the present embodiment are applied to the image forming apparatus. However, the present invention is not limited to this. For example, the present invention can be applied to an image processing apparatus such as a mobile phone, a portable information terminal, a projector, or a video conference system.

101 ASIC
102 CPU (an example of an external control unit)
103 RAM (an example of a first storage unit)
DESCRIPTION OF SYMBOLS 104 Scanner 105 Printer 201 1st interface control part 202 2nd interface control part 203 Arbiter 204,205,206 Image processing part (an example of a transfer part)
207 Register control unit 208 Register access monitoring unit 209 DMA transfer information monitoring unit 210 Access history storage control unit (an example of a control unit and a second storage unit)
211 Interrupt control unit (an example of a control unit)
220 register information input unit 221 storage range designation unit 222 activation information acquisition unit 223 output unit 225 control signal

JP 2006-011645 A JP 2011-243185 A

Claims (13)

A transfer unit that writes data to be transferred to the first storage unit according to a transfer instruction from the external control unit, reads the data from the first storage unit according to the data processing speed of the transfer destination device, and transfers the data to the transfer destination device When,
When detecting data writing to a predetermined write-inhibited area in the storage area of the first storage section, the external control section is notified of an abnormality in data writing to the first storage section, and the first storage section A control unit that writes first information to the first storage unit that enables specification of a write region in which data is written, among the storage regions of
An information processing apparatus comprising:   The information processing apparatus according to claim 1, wherein the control unit writes, in the first storage unit, second information that makes it possible to specify the transfer instruction corresponding to data writing to the first storage unit. .   The information processing apparatus according to claim 2, further comprising a second storage unit that stores the first information and the second information.   The information processing according to any one of claims 1 to 3, wherein the first information is added with information that makes it possible to specify the transfer unit that has written data to the first storage unit. apparatus. The transfer unit writes third information enabling the identification of the write area of data to be transferred to the first storage unit, accesses the third information, reads data from the first storage unit,
The first information includes information that makes it possible to specify the area in which the third information is written in the storage area of the first storage unit, and information that makes it possible to specify the time when the third information was accessed. The information processing apparatus according to claim 1, wherein the information processing apparatus is added.   The said control part prohibits transfer of the data read from the said 1st memory | storage part, when the writing of the data with respect to the said write-protection area | region is detected. Information processing device.   The information processing apparatus according to claim 1, further comprising an access monitoring unit including a storage range designating unit that designates an address range of the first storage unit that stores access information from the external control unit.   The information processing apparatus according to claim 7, wherein the access monitoring unit selects an address within or outside a range designated based on a predetermined control signal.   The information processing apparatus according to claim 7, wherein the access monitoring unit includes an activation information acquisition unit that acquires only a register that activates the transfer unit.   The information processing apparatus according to claim 9, wherein the activation information acquisition unit acquires an activation register of the transfer unit designated based on a predetermined control signal.   The information processing apparatus according to claim 8, wherein the access monitoring unit acquires an activation register outside the address range when selecting the address outside the address range. In response to a transfer instruction from the external control unit, the data to be transferred is written to the first storage unit, and the data is read from the first storage unit according to the data processing speed of the transfer destination device and transferred to the transfer destination device.
When detecting data writing to a predetermined write-inhibited area in the storage area of the first storage section, the external control section is notified of an abnormality in data writing to the first storage section, and the first storage section Writing the first information enabling the identification of the writing area in which the data has been written to the first storage unit.
Information processing method including the above. Computer
A transfer unit that writes data to be transferred to the first storage unit according to a transfer instruction from the external control unit, reads the data from the first storage unit according to the data processing speed of the transfer destination device, and transfers the data to the transfer destination device When,
When detecting writing of data to a predetermined write-protected area in the storage area of the first storage unit, notifies the external control unit of an abnormality in writing data to the first storage unit,
A control unit that writes, to the first storage unit, first information that makes it possible to specify a write region in which data is written in the storage region of the first storage unit;
A program for running

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