JP2006011645A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor having a memory arbiter generating an interrupt to memory access to a specific position or a specific area on a memory to perform more diversified interrupt processing. <P>SOLUTION: This semiconductor integrated circuit has: a DMA controller 4 delivering inputted image data to the memory 5 not through a CPU; and the memory arbiter 3 connected to the externally installed CPU and memory 5. The memory arbiter 3 is provided with a register designating the specific area on the memory by an address. When write access of the image data from the DMA controller 4 is the access to the specific area, the memory arbiter 3 generates the interrupt in reference to the designation address of the register to notify the CPU. The designation address of the register is a start address and an end address of an area forbidden with writing of the image data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit having a memory arbitration function for generating an interrupt for memory access when image data from a scanner or the like is written to or read from a memory.

  For image data sent from an engine such as a scanner, buffer 1 and buffer 2 (start address and end address are designated by buffers 1 and 2 respectively) which are specific areas of the memory space. When storing, when the end address of the buffer 1 is reached by write access to the memory, this is detected, an interrupt is generated and notified to the CPU, and the CPU activates the DMAC by the interrupt and reads the buffer 1 At the same time, a method of starting write access to the buffer 2 from the start address of the buffer 2 has been proposed (see, for example, Patent Document 1).

In addition, the arbitration between DMACs for access from multiple sources and arbitration between the DMA request and the CPU request that have acquired the right to occupy the memory bus, and which external memory the CPU request accessed There has been proposed a technique that enables efficient use of the memory bus by dividing each of the divided CPU requests and prioritizing the DMA requests that are simultaneously input to each of the divided CPU requests ( For example, see Patent Document 2).
JP 2003-283710 A JP 2001-51943 A

  However, in the prior art as shown in Patent Document 1, in order to use the buffer 1 and the buffer 2 in the memory space as a toggle, an interrupt is generated due to write access to the final address of the buffer. The cause of the occurrence was limited to the buffer toggle usage mode. Further, in Patent Document 1, when a write access is made, an interrupt is generated regardless of whether the access is from the CPU or the direct memory access from the scanner, but the number of toggles of the buffer is used. Since a method of determining the number of original reading lines is employed, if the number of toggles is counted even for access from the CPU, the number of original lines is erroneously calculated.

Further, the prior art as shown in Patent Document 2, when the simultaneous occurrence of CPU requests and DMA requests, and the invention object of prevention of comprising such overrun can not guarantee the normal print data, CPU requests and DMA requests of are those that is arbitrating the prioritization count to access the respective access, the viewpoint of the occurrence of the interruption in the access to the memory is different.

An object of the present invention is to provide a semiconductor integrated circuit including a memory arbiter capable of generating an interrupt for a memory access to a specific location or a specific area on a memory and performing various interrupt processing. It is to provide.

In order to solve the above problems, the present invention mainly adopts the following configuration.
A DMA controller for transferring the image data to be input to the memory without passing through the CPU, a semiconductor integrated circuit including a memory arbiter coupled to the external the installed CPU and memory, wherein the memory arbiter A register for designating a specific area on the memory by an address is provided. When the write access of the image data from the DMA controller is an access to the specific area, the memory arbiter refers to the designated address of the register. The interrupt is generated and notified to the CPU.

  In the semiconductor integrated circuit, the designated address of the register is a start address and an end address of an area where writing of image data is prohibited.

Further, a DMA controller for transferring the image data to be input to the memory without passing through the CPU, a semiconductor integrated circuit including a memory arbiter coupled to the external the installed CPU and memory, the memory arbiter Is provided with a register for designating a periodic repetition location on the memory by an address, and when the write access of the image data from the DMA controller is an access to the periodic repetition location, the memory arbiter An interrupt is generated by referring to the designated address of the register and notified to the CPU.

  Further, in the semiconductor integrated circuit, the memory is a memory having a dual port, and the image data is written and read through the dual port in parallel.

  According to the present invention, in data transfer to a memory, various types of interrupts can be generated by setting various registers in the memory arbiter and monitoring access requests from the DMAC.

  Further, when writing to or reading from the memory, it is possible to eliminate writing of data in the overwrite-inhibited area by the generation of an interrupt by the memory arbiter and the activation of the DMAC by the CPU.

Further, when performing simultaneous operations of writing and reading using a dual port memory, an interrupt is generated every time a certain amount of data is transferred, and each time a read DMAC is activated to read data. As a result, the memory utilization efficiency can be improved.

A semiconductor integrated circuit according to an embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a block diagram showing an internal configuration of a semiconductor integrated circuit (ASIC: Applied Specific IC) according to an embodiment of the present invention and an external configuration connected to the internal configuration. FIG. 2 is a diagram showing a configuration example of a memory space connected to the semiconductor integrated circuit according to the present embodiment. FIG. 3 is a view showing various registers in the memory arbiter in the semiconductor integrated circuit according to the present embodiment. FIG. 4 is a diagram showing a configuration example of a memory space in a RAM having a dual port and the occurrence of an interrupt. FIG. 5 is a diagram showing another configuration example of a memory space in a RAM having a dual port and the occurrence of an interrupt.

Here, 1 is a general-purpose bus (PCI bus or the like), 2 is an interrupt signal, 3 is a memory arbiter, 4 is a DMA controller ( Direct Memory Access Controller: DMAC), 5 is a memory device (SDRAM or the like), 6 is at least a memory arbiter ASIC including 3 and DMAC4 , 7 is an address set in the start address register, 8 is an address set in the end address register, 9 is a look-up table area in an area for monitoring access, and 10 in an area for monitoring access Represents the descriptor data area . The memory arbiter 3 includes a start address register, an end address register, an error status register, and a mask address register for setting an access monitoring area.

In FIG. 1, image data from an engine such as a scanner is sent to an ASIC 6 including at least a DMAC 4 and a memory arbiter 3 through a general-purpose bus 1 such as a PCI bus, and is written in a memory 5 . Further, data from the memory 5 is read and output to the plotter via the ASIC 6. Further, the ASIC 6 reads data from the memory 5 and stores it in the HDD or SD card. The ASIC 6 includes a memory arbiter 3 that has various registers and arbitrates access to the memory 5 and an external device such as a scanner, plotter, HDD, SD card, or the like, such as PCI II / F, HDD I / F, SDI / F, a read DMAC and a write DMAC 4 that exchange data between each I / F and the memory arbiter 3, and a compression / expansion unit that compresses and decompresses the data read from the memory 5 (the compressed data is encoded data) And may be stored in the memory 5 again, and this compression / decompression device is not necessarily an essential element). In addition, the memory arbiter 3 generates an interrupt signal 2 and notifies the CPU of this so that another process can be performed during the write or read process by accessing the memory 5. The CPU that has received the interrupt signal 2 activates an appropriate DMAC 4 to execute a required process.

Figure 2 shows the memory space in the memory 5, this memory space, and the realm of monitoring access, for example, to implement a lookup table area 9 (image processing showing a table for dithering The table area is designated by the start address (SA1) 7 and the end address (EA1) 8 to secure the area. Similarly, for example, the descriptor data area 10 in which the start address, the number of lines, and the image type (code data, etc.) which are instructions to the DMAC 4 are written is designated by the start address (SA2) 7 and the end address (EA2) 8 . This indicates that the area is reserved and is a data area in which image data from an engine such as a scanner is to be prohibited from being written. Note that the DMAC 4 activated by the CPU that has been notified of the occurrence of an interrupt (the CPU activates the DMAC 4 by an interrupt) is a descriptor data area in which contents of instructions to the DMAC 4 (for example, a start address, the number of lines, etc.) are described. 10 is read out and data is transferred to the memory in accordance with the contents of the instruction.

The memory arbiter 3 shown in FIG. 1, as shown in FIG. 3, and equipped with a start address register and the end address register to set the start address 7 and end address 8 of the above-mentioned write-protected to the memory 5, Fig. 2 reference numeral 7 shown in is the address set in the start address register in the memory arbiter 3, reference numeral 8 is an address set in the end address register in the memory arbiter 3. That is, the memory arbiter 3 includes a mask address register and an error status register in addition to the start address register and end address register for the access monitoring area. Here, the memory arbiter 3 monitors the start address 7 for prohibiting writing to the memory 5 set by the start address register and the designated address for writing the read data from the scanner by the DMAC 4 , and the write designated address is determined. When the start address 7 is reached, the memory arbiter 3 generates an interrupt signal 2 to notify the CPU, and the image data from the scanner is stored in the lookup table area 9 (in this area) by subsequent processing (described later). Overwriting is prohibited for data protection).

As described above, the memory arbiter 3 is provided with a function for monitoring an overwriting-prohibited area and a function for retaining error information (for example, the content of the error that caused the interrupt signal 2 ). Then, as shown in FIG. 2, image data from the scanner (not limited to data sent from outside the ASIC 6 but may be data from the compression / decompressor inside the ASIC 6 ) is sequentially from the empty part of the memory space. When it is stored and reaches SA1 (7) (see FIG. 2), an interrupt signal 2 is generated and notified to the CPU, and the CPU notifies the error register of the memory arbiter 3 (whether the error bit flag of overwriting is set) No)) is read and overwriting to the lookup table area 9 is detected. In such a case, the CPU updates the address by software so as not to read and overwrite the start address 7 which is an instruction content to the DMAC 4 , for example, in the descriptor data area 10 (write data storing the image data in the memory 5). The CPU updates the address) . The DMAC 4 can prevent overwriting to the monitoring area by writing data based on the updated instruction content. Data overwriting by the DMAC 4 to the look-up table area 9 and the descriptor data area 10 , which are monitoring areas, is prohibited, but updating by the CPU is possible by the function of the memory arbiter 3.

FIG. 3 is a diagram for explaining a mask address register in the memory arbiter 3. The memory arbiter 3 has a mask address register in addition to a start address register and an end address register. The upper address in the 32-bit address can be arbitrarily masked by the value specified in the mask address register. In the example of FIG. 3, the upper 16 bits are set to be masked, and the address set in the mask address register The target address to be compared with the address requested to be accessed is the lower 16 bits. This mask address register is used to specify a periodic repetition location on the memory by an address.

The memory arbiter 3 watches the address of the access request from each DMAC 4 and the CPU, that is, the lower 16 bits not masked by the mask address register are compared, and when the addresses become equal, the interrupt signal 2 Is generated. In the mask setting of the mask address register of FIG. 3, since the request address from the DMAC 4 is incremented, every fixed data transfer (every 256 bytes in the setting example shown) in the range from the start address to the end address. In the configuration example, the lower 16 bits become 0x0000 and an interrupt occurs. In other words, the interrupt signal 2 is generated when the address set in the mask address register and the request address from the DMAC 4 become equal in the effective address portion after masking. For example, if the mask address register is set to mask the upper 23 bits (lower 9 bits are to be compared) , an interrupt signal 2 is generated for every 512 bytes transferred as shown in FIG.

FIG. 4 shows an operation mode in which writing and reading are simultaneously performed in parallel using a dual port in a memory space such as a RAM having a dual port. The write area is defined as a start address (start address SA). First, the final address (end address EA) is specified. Further, every time the upper-order arbitrary bits are masked by the mask address register in the memory arbiter 3 and the lower-order arbitrary number of addresses match, that is, every time a certain amount of data is transferred, for example, the data for every 512 bytes in FIG. Each time an address corresponding to the amount appears from the write DMAC (shown in FIG. 4) (every time the address from the write DMAC matches the low-order bit of the mask address), the memory arbiter 3 sends an interrupt signal 2 To notify the CPU.

The CPU notified of the interrupt reads the register of the memory arbiter 3 to detect that a certain amount of data has been written to the memory, and activates an appropriate read DMAC (shown in FIG. 4) . In the example of FIG. 4, when the write for every 512 bytes is reached, the read DMAC is activated to transfer the read data to the HDD or SD card. Here, a certain amount of data of 512 bytes is a unit amount (sector unit) of data handled by the HDD or SD card. As described above, by simultaneously writing to and reading from the memory 5 , the data processing speed is increased and the utilization efficiency of the memory 5 is improved. In the operation description of FIG. 4, it has been described that data written to the memory 5 is read and written to the HDD or SD card. However, the present invention is not limited to this, and when a certain amount of data is transferred to the memory 5 . Alternatively, the data may be read by the read DMAC, compressed, converted into code data, and written back to another area of the memory.

FIG. 5 shows an example in which a counter is provided in the memory arbiter 3 and an interrupt signal 2 is generated when a certain amount of data writing (a certain amount of memory access) to the memory 5 shown in FIG. It is. Since the amount of data to be written at one time with one access to the HDD is defined by the number of sectors (for example, 256 sectors), an interrupt is generated by accessing this amount of data, and the read DMAC by the CPU is activated to transfer data to the HDD. Forward. That is, when data such as an HDD having the concept of a sector is handled, an interrupt is periodically generated in units of (sector size × N).

When the memory 5 is used as a ring buffer, a predetermined amount of data writing reaches the designated number N, and it is detected that the reading of the data for the designated number N has been completed, and an interrupt signal 2 is generated. In response to the signal 2 , the CPU activates the DMAC 4 so that new data is written in an area corresponding to the designated number N. This is because if new data is written to the area at a stage where data reading for the specified number of times has not been completed, the old data may be destroyed. In this case, the cause of the interrupt generation is the completion of reading.

1 is a block diagram showing an internal configuration of a semiconductor integrated circuit according to an embodiment of the present invention and an external configuration connected to the internal configuration. FIG. It is a figure which shows the structural example of the memory space connected to the semiconductor integrated circuit which concerns on this embodiment. It is a figure which shows the various registers which exist in the memory arbiter in the semiconductor integrated circuit which concerns on this embodiment. It is a figure which shows the structural example of memory space in RAM etc. which have a dual port, and an interrupt generation. It is a figure which shows the other structural example of memory space in RAM etc. which have a dual port, and interruption generation | occurrence | production.

Explanation of symbols

1 General-purpose bus (PCI bus, etc.)
2 Interrupt signal 3 Memory arbiter 4 DMA controller 5 Memory device (SDRAM etc.)
6 ASIC (semiconductor integrated circuit)
7 Address set in the start address register 8 Address set in the end address register 9 Look-up table area in the area where access is monitored
10 Descriptor data area in the area to monitor access

Claims (7)

A semiconductor integrated circuit including a DMA controller that transfers input image data to a memory without using a CPU, a CPU that is externally installed, a memory arbiter that is connected to the memory, and various I / Fs. ,
The memory arbiter is provided with a register for designating a specific area on the memory by an address,
When the write access of the image data from the DMA controller is an access to the specific area, the memory arbiter generates an interrupt with reference to a specified address of the register and notifies the CPU. Semiconductor integrated circuit. In claim 1,
The semiconductor integrated circuit, wherein the designated address of the register is a start address and an end address of an area where writing of image data is prohibited. A semiconductor integrated circuit including a DMA controller that transfers input image data to a memory without using a CPU, a CPU that is externally installed, a memory arbiter that is connected to the memory, and various I / Fs. ,
The memory arbiter is provided with a register for designating a specific periodic part on the memory by an address,
When the write access of the image data from the DMA controller is an access to the periodic specific portion, the memory arbiter generates an interrupt with reference to a specified address of the register and notifies the CPU. A semiconductor integrated circuit. In claim 3,
The specified address of the register is an address of lower bits by a mask address register that masks upper bits. In claim 3 or 4,
The memory is a memory having a dual port, and the writing and reading of the image data are simultaneously performed in parallel through the dual port. A semiconductor integrated circuit including a DMA controller that transfers input image data to a memory without using a CPU, a CPU that is externally installed, a memory arbiter that is connected to the memory, and various I / Fs. ,
The memory is a memory having a dual port;
The memory arbiter is provided with a register for designating a specific periodic part on the memory by an address,
Further, the memory arbiter counts the number of times that the write access of the image data from the DMA controller accesses the periodic specific location, and the memory arbiter issues an interrupt when the count reaches the specified number. A semiconductor integrated circuit characterized in that it is generated and notified to the CPU. A semiconductor integrated circuit including a DMA controller that transfers input image data to a memory without using a CPU, a CPU that is externally installed, a memory arbiter that is connected to the memory, and various I / Fs. ,
The memory is a memory having a dual port and used as a ring buffer;
The memory arbiter is provided with a register for designating a specific periodic part on the memory by an address,
Further, the memory arbiter counts the number of times that the read access to the memory accesses the periodic specific location, and when the count reaches the specified number, the memory arbiter generates an interrupt to the CPU. Notify
The semiconductor integrated circuit, wherein the image data is written in a memory area that has reached the specified number of times according to an instruction from the CPU.

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