JP2015184508A - display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an erratic operation due to a gap in data position as much as possible, even when a gap in data position that would cause a command to be mistakenly recognized due to a power supply or GND voltage change, noise, etc., occurs.SOLUTION: The present invention includes: a format in which command data, each consisting of 6 bits, is transmitted on 11ch (C[0]-C[10]) in a reference clock period as a NOP period, and six (6-bit) pixel data per channel are transmitted respectively on 10ch (C[1]-C[10]) in 35 periods ENA0-ENA34 following the reference clock period; a data format in which a most important command CD0 is assigned, all with the same value, to one channel C[0] in the reference clock period and in all of other periods; and a data format in which one command data per channel (CD1-CD10) are assigned, successively with the same value, to 10 other channels C[1]-C[11] than the channel C[0] in the reference clock period.

Description

  The present invention relates to a display device, and more particularly to a display device that displays an image by a digital drive method.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. As a display method of this LCOS type liquid crystal display device, digital video data obtained by subjecting a video signal to pulse width modulation (PWM) to a semiconductor element such as a complementary metal oxide semiconductor (CMOS) is used as a pixel electrode of the liquid crystal display element. There is a digital driving method in which the liquid crystal is driven by switching the alignment of the liquid crystal in time. The digital driving method has an advantage that it is strong against burn-in, although it is inferior in gradation display as compared with the analog driving method in which an analog video signal is applied to the pixel electrode of the liquid crystal display element.

  In such a digital drive type display device, when a large number of pixels are handled, the amount of pixel data to be input is extremely large. Therefore, it is necessary to input pixel data at a high data rate. For example, in a display device having a horizontal pixel count of 4096 and a vertical pixel count of 2400 (hereinafter referred to as a “4K2K panel”), when subframe display is performed at a rate of 64 subframes per screen, 60 Hz progressive is used. The data rate of the subframe data necessary for display is as extremely high as 37.749 Gbps (≈ 1/60/64 / (4096 × 2400)).

  On the other hand, a low-amplitude differential signaling (LVDS) is generally and optimally used as an interface that can be used at present. There are other higher-speed interfaces, but LVDS, which is the most unique from the cost viewpoint, is easy to use. The LVDS basically operates by supplying data and a clock for fetching the data from the outside of the chip. For example, in the case of 44-bit parallel input, there are four clock signal lines, and the number of clock signal lines is reduced by assigning one clock signal line to 11 bits. Therefore, a CDR (Clock Data Recovery) circuit that adjusts the phase of the clock and data may be used. As a CDR circuit, a circuit that extracts a clock from input data and adjusts the frequency of the clock when restoring the data is known (for example, see Patent Document 1).

  In a digital drive type display device, when pixel data is input using LVDS, a pixel drive circuit unit that drives an image display unit of the display device is a custom LSI (Large Scaled Integrated circuit). Therefore, it is difficult to mount a very complicated circuit. Therefore, normally, a command indicating timing for moving the signal generation logic in the pixel driving circuit unit in synchronization with the pixel data is included in the LVDS input pixel data.

  As the above commands, at least four types of “write to pixel”, “signal transfer within the pixel”, “read during test”, and “do not execute command” are necessary. Therefore, 2 bits are required for the LVDS data bits. If the LVDS or the like does not malfunction, these command bits may be assigned to any place in the LVDS data string that is easy to use. There is no problem if other commands and timing adjustment signals are assigned to appropriate data bits. Actually, commands to be input in synchronization with LVDS input pixel data include switching of the shift direction of a vertical shift register (hereinafter referred to as V shift) that outputs a row scanning signal to each pixel of the image display unit, and shifting of the V shift. A start bit for starting the operation and a bit indicating the driving voltage of the liquid crystal are required.

JP 2012-156740 A

  However, the pixel data interface using the LVDS including the command bits has the following problems.

  (1) In order to correctly capture data by LVDS, the phase of the clock and the data is adjusted using a CDR circuit or the like, but the data position shifts depending on the operating state of the CDR circuit due to noise such as power supply and GND voltage fluctuations. One to two bits may be generated.

  There is a method for recognizing the correct start position of the data by inserting a special pattern indicating where the data position is in the data format against the data position shift. However, in this method, it is necessary to create a special pattern that is not used in general data, and in order to create the data, a conversion circuit for converting the data itself into 8-10 is necessary, and the circuit also causes a delay. Therefore, it is difficult to actually use it.

  Further, there is a method of resetting and returning the shift when the data position shift occurs. However, this method is not practical because it is necessary to recognize the occurrence of deviation by some means, and a circuit for the recognition is required, and a delay is generated by the circuit.

  (2) As for fluctuations in the power supply, GND, etc., the operating rate of the CMOS logic circuit varies depending on the type of signal, and as a result, the current flowing through the circuit increases and decreases, and voltage fluctuations occur due to the impedance of the power supply and GND wiring.

  Due to a malfunction that occurs in these LVDS, the command bit is erroneously recognized by the logic of the control circuit in the drive circuit, and the displayed video is disturbed as a result. In some cases, an incorrect command is taken in and the operation becomes strange, and the correct operation cannot be continued.

  Here, the biggest problem with the above-described LVDS data position deviation is erroneous recognition of command bits. If the command bits are not recognized incorrectly, systematic display errors will not occur. In addition to command bits, misalignment of the data position of the display part is also a problem, but it only gives an incorrect display rather than causing a system failure.

  Therefore, the basic concept for the LVDS data position shift is as follows. The first is a format that does not malfunction as much as possible even if a data position shift occurs in a command bit. The second is to avoid making a mistake as much as possible when making a data position shift. The third is to adjust the data position once by inserting a specific pattern in a NOP period (period without pixel data).

  The present invention has been made in view of the above points, and by generating data in a format compliant with the above basic concept and outputting it to a high-speed interface circuit, a command can be sent due to voltage fluctuations, noise, etc. of the power supply and GND. It is an object of the present invention to provide a display device that can prevent a malfunction caused by a data position shift as much as possible even if a data position shift that causes erroneous recognition occurs.

In order to achieve the above-described object, the present invention provides command data for a plurality of commands for controlling the operation of the pixel driving circuit unit, with respect to a pixel driving circuit unit that drives an image display unit in which a plurality of pixels are regularly arranged. Digital data generating means for generating digital data consisting of pixel data to be displayed and supplying the digital data to the pixel driving circuit section through a high-speed interface circuit;
The digital data generation means assigns, as the most important command, a command indicating writing of pixel data to a pixel among a plurality of commands as command data having the same bit value to a predetermined channel of the plurality of channels. For commands other than the most important command, the command data of one command is continuously the same for each channel other than a predetermined one of a plurality of channels in a reference clock period that is a plurality of data bit transmission periods that are not pixel data transmission periods. A signal having a format in which pixel data is allocated in each channel other than a predetermined channel in a plurality of data bit transmission periods other than the reference clock period is generated as digital data.

  According to the present invention, even if a data position shift that causes a command to be erroneously recognized due to voltage fluctuations, noise, or the like of the power supply or GND occurs, a malfunction due to the data position shift can be prevented as much as possible.

It is a block diagram of one embodiment of a display device of the present invention. It is a figure which shows one Embodiment of the format of the digital data which the digital data generation circuit in the display apparatus of this invention produces | generates. It is a figure which shows the list of the command and the value of a command bit which were allocated. FIG. 2 is a block diagram of an embodiment of a command bit determination circuit in FIG. 1. 5 is a timing chart for explaining the operation of the command bit determination circuit of FIG. 4. It is a block diagram of an example of a majority circuit. It is a figure which shows the relationship between the signal for LVDS data shift adjustment, and a clock. It is a figure which shows the 1st example of a data shift. It is a figure which shows the 2nd example of a data shift. It is a figure which shows the 3rd example of a data shift. It is a figure which shows the 4th example of data shift. It is a figure which shows the 5th example of a data shift. It is a figure which shows the 6th example of a data shift. FIG. 10 is a diagram for explaining an operation for correcting a data shift when there is no data shift. It is correction operation explanatory drawing of the other example of data shift. It is a figure explaining the decoding output and the output of the decoder for data selector selection at that time. FIG. 2 is a circuit diagram of an embodiment of an LVDS data deviation adjustment circuit in FIG. 1. 18 is a timing chart for explaining the operation of FIG.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of an embodiment of a display device according to the present invention. In the figure, a display device 10 according to this embodiment includes a digital data generation circuit 11, a plurality of pixels 12 arranged in a two-dimensional matrix and constituting an image display unit 100, and a high-speed interface (I / F) circuit 13. A parallel D-type flip-flop (DFF) 14 with a data selector (D / S), a pixel adjustment shift register 15, a horizontal signal driver 16, a control circuit 17, and address decoders or shift registers 18 and 19. This is a digital drive type liquid crystal display device.

  The image display units 100 are arranged m (m is a natural number of 2 or more) in the row direction (horizontal direction) and n (n is a natural number of 2 or more) in the column direction (vertical direction). In this configuration, n pixels 12 are arranged in a two-dimensional matrix. Each pixel 12 is schematically shown as one rectangle in FIG. Each pixel 12 has a liquid crystal display element (not shown) having a known structure in which liquid crystal is filled and sealed between a common electrode and a pixel electrode (or a liquid crystal driving electrode) that are provided facing each other. As is well known, pixel electrodes are provided separately for each pixel, and a common electrode is provided in common for all pixels.

  The m pixels 12 arranged in the horizontal direction are parallel to the address decoder or shift registers 18 and 19 respectively connected to both ends in the horizontal direction, and are alternately arranged in row scanning lines of n / 2. It is connected. On the other hand, the n pixels 12 arranged in the vertical direction are separately connected to m column data lines arranged in parallel in the vertical direction, one end of which is connected to the horizontal signal driver 16.

  The digital data generation circuit 11 and the high-speed I / F circuit 13 are circuits that characterize the present invention. The digital data generation circuit 11 constitutes the digital data generation means of the present invention, and command data and pixel data (command data for controlling the operation of the pixel drive circuit unit) and the pixel data (to the pixel drive circuit unit that drives the image display unit 100). Here, digital data composed of subframe data) is generated and output in the format shown in FIG.

  The high-speed I / F circuit 13 is supplied with the LVDS reception circuit 131 that receives the digital data supplied from the digital data generation circuit 11 with the LVDS that is the high-speed I / F, and the data output from the LVDS reception circuit 131. The command bit determination circuit 132 and the LVDS data deviation adjustment circuit 133 are configured. The command bit determination circuit 132 and the LVDS data deviation adjustment circuit 133 will be described in detail later.

  The parallel DFF 14 with D / S correctly arranges pixel data supplied from the high-speed I / F circuit 13 through, for example, a 64-bit digital signal bus at a horizontal pixel position in units of 64 bits by a data selector (D / S). It is held and output to the pixel adjustment shift register 15. The pixel adjustment shift register 15 shifts the pixel data supplied from the D / S-attached parallel DFF 14 and adjusts the horizontal position. Here, for example, when the number m of pixels for one line is “4096”, if about four adjustment pixels for adjusting the display position are arranged on both sides, the pixel adjustment shift register 15 is 4104. A shift operation is performed by a shift register of (= 4096 + 4) stages. As a result, pixel data can be written to the pixel to be displayed as a result.

  The horizontal signal driver 16 constitutes the pixel data generating means of the present invention, and outputs each subframe data of one line supplied from the pixel adjustment shift register 15 to the column data line of the corresponding pixel. The control circuit 17 controls the operations of the parallel DFF with D / S 14, the pixel adjustment shift register 15, and the horizontal direction signal driver 16 based on the signal supplied from the high-speed I / F circuit 13.

  For example, the control circuit 17 generates an enable signal for selecting a signal by D / S and a clock for latching in the D / S-attached parallel DFF 14. Further, the control circuit 17 generates a shift clock and a load signal for parallel input to the pixel adjustment shift register 15. For the address decoder or shift registers 18 and 19 corresponding to the vertical drive circuit, a shift clock and a control signal for adjusting timing are generated. Command data (hereinafter also referred to as command bits) input from the high-speed I / F circuit 13 is the basis of them. The reason why two address decoders or shift registers having the same configuration are provided on the left and right sides of the image display unit 100 as indicated by 18 and 19 is that the number of pixels of the image display unit 100 is large, and one of them has a drive capability. This is due to the problem of shortage. However, in principle, one is sufficient.

  Next, the format of digital data generated by the digital data generation circuit 11 will be described.

  FIG. 2 shows an embodiment of a format of digital data generated by the digital data generation circuit 11 in the display device according to the present invention. This data format assumes that data is input to FHD pixels using an 11-channel LVDS receiver circuit. The basic configuration of this data format consists of 11 channels (ch) of data input (C [0] to C [10]) and a reference clock for data capture in one system. One channel has an LVDS data rate of Y Mbps, and a reference clock for fetching one system for fetching it is X MHz. Serialization (Serialize) is performed in which six data are input in one clock using a 1/6 frequency XMHz reference clock with respect to a 1ch data rate YMbps.

  In the data format shown in FIG. 2, the 6-bit command data is transmitted in 11ch (C [0] to C [10]) as the NOP period (period without pixel data) in the reference clock period, and the reference clock period Subsequent 35 periods ENA0 to ENA34 are formats for transmitting 6 (6 bits) pixel data for each channel in 10 channels (C [1] to C [10]).

  Here, there may be a difference in the bits output between the channels. This does not mean that the cycle of the system clock (LVDS reference clock) is deviated, but the position within all deserialized data (for example, 6 bits when LVDS is multiplied by 6) within one cycle of the system clock. Therefore, the command will be wrong because the correct value does not enter the command bit position.

  On the other hand, in order to recognize a correct command even if the position is shifted within one cycle of the system clock, when assigning command bits within one cycle, all six bits are the same without changing the command for each bit. With the value, mistakes can be drastically reduced. In other words, command bits are assigned in units of one cycle of the system clock, and all six bits in one cycle are set to the same value.

  Therefore, in the present embodiment, as shown in FIG. 2 in view of the above points, the most important command CD0 serving as a reference is all the same for one channel C [0] in the reference clock period and all other periods. The data format is assigned by value. In the present embodiment, as shown in FIG. 2, in the reference clock period, for 10 channels C [1] to C [11] other than C [0], one command data (CD1) is assigned to each channel. ˜CD10) is a data format assigned continuously with the same value.

  The command bit CD0 that is the most standard is command data for assigning commands as follows, for example.

    CD0 = 0: NOP or pixel 12 temporarily stores pixel data to which pixel data is written (for example, static random access memory (SRAM) and pixel data transferred from the first-stage storage unit, and applies it to the pixel electrode In the case of a second-stage storage unit (for example, a dynamic random access memory (DRAM)), it is a command for transferring data from the SRAM to the DRAM and reading data from the pixels.

    CD0 = 1: WRITE (writes data input to the pixel at the same timing as this command bit). In the case of WRITE, the value of the command bit of CD1 is ignored, and data transfer from the SRAM to the DRAM and data reading from the pixel are not performed.

  The purpose of this command assignment of CD0 is to prevent a malfunction caused by recognizing it as another command during writing with the writing operation to the pixel having the highest priority.

  In addition, data transfer from the SRAM to the DRAM is performed using the command bits CD0 and CD1 at the following values.

When CD0 = 0 and CD1 = 1, data transfer from SRAM to DRAM Data reading from the pixel is performed using command bits CD0, CD1, and CD2 at the following values.

CD0 = 0, CD1 = 0, CD2 = 1
Therefore, the NOP is accurately performed using the command bits CD0, CD1, and CD2 at the following values.

CD0 = 0, CD1 = 0, CD2 = 0
Other command bits are used by assigning command bits CD3 to CD10 to the remaining 8 channels other than command bits CD1 and CD2 during a period of NOP. Also for CD3 to CD10, it is the same as CD1 and CD2 that the 6 bits in the NOP period have the same value and indicate the command bits.

  FIG. 3 shows a list of commands and command bit values assigned as described above. The five command bits CD0 to CD4 shown in the figure are control flag signals used in the drive circuit of the display device, and an internal command of the drive circuit of the display device is created by the combination thereof, and the control circuit 17 is controlled.

  Thus, in this embodiment, since the command bits in the data format are all the same value in units of 6 bits, the command is determined by majority vote. In other words, if 4 bits out of 6 bits are correct, the value is valid. Otherwise, it is determined that there is a data position shift or malfunction, and processing is performed.

  In addition, the data position shift can be adjusted using one reference clock period of NOP. Conventionally, a fixed 1-bit data is put in a specific place in 6-bit data of NOP by an external circuit, and the shift of the data position is examined, and the process of shifting the input position as the LVDS data by the shift is performed. . In this embodiment, the adjustment can be performed within the chip. However, since the data required for the command bits increases, the necessary image data cannot be input unless the LVDS data rate is increased as a result.

  Next, the configuration and operation of the command bit determination circuit 132 will be described. FIG. 4 shows a block diagram of one embodiment of command bit decision circuit 132. The command bit determination circuit 132 is a circuit for determining whether or not data having the same value is input in units of 6 bits. As shown in FIG. 4, the command bit determination circuit 132 is a 6-bit parallel D flip-flop ( DFF) 1321 and a majority circuit 1322.

  Next, the operation of the command bit determination circuit 132 will be described with reference to the timing chart of FIG. The 6-bit parallel DFF 1321 receives data of a predetermined channel from the LVDS receiving circuit 131 as a receiver in parallel with 6 bits. Here, it is assumed that the data C [0] of ch0 is received by the LVDS receiving circuit 131 in a value as shown in FIG. 5B in synchronization with the LVDS reference clock shown in FIG. The 6-bit parallel DFF 1321 constitutes the command data acquisition means of the present invention, and the command data input from the LVDS receiving circuit 131 in parallel as shown in FIG. 5C is shown in FIG. Latch by latch clock.

  The majority circuit 1322 determines that NOP, transfer, or read is performed as shown in FIG. 3 if there is 3 or more “0” in the 6-bit parallel data latched and output by the 6-bit parallel DFF 1321. As shown in FIG. 5E, command bits CD0 such as NOP are generated and output. If “1” is 4 bits or more, it is determined as WRITE as shown in FIG. 3, and a command bit CD0 indicating WRITE as shown in FIG. 5E is generated and output. The control circuit 17 outputs a control signal for controlling the operation of the pixel driving circuit based on the command bit determined by the command bit determination circuit 132.

  FIG. 6 shows a block diagram of an example of the majority circuit 1322. The majority circuit 1322 includes an adder 21 and a comparator 22. If the input 6-bit parallel input is represented by A [5: 0], the adder 21 is A [0] + A [1] + A [2] + A [3] + A [4] + A [5]. In this way, an addition process is performed in which the input is divided into bits. Subsequently, the comparator 22 sets “0” when the 3-bit addition value output from the adder 21 is 3 or less (determines that the command bit is “0” by majority decision) and is 4 or more. If it is “1” (command bit is determined to be “1” by majority vote). The comparator 22 outputs a command bit CD0 having a value indicating the comparison result.

  Here, if the 6 data in the NOP period, that is, if all 6 bits are not the same value, data misalignment or malfunction has occurred, but the command itself is necessary for system operation. Even if the position is shifted, a control flag is output and a command is executed to operate (or NOP) the pixel drive circuit. In the meantime, the data position shift is adjusted.

  In the above description, the channel C [0] is used. However, for each data of the channels C [1] and C [2], a command bit determination circuit having the same configuration is used to determine whether the data is the same value for 3 bits or more. The bit is judged and CD1 and CD2 are output. The command bit determination circuit may have any number of command bits required by the system.

  Next, a method of adjusting a data position shift (hereinafter referred to as “data shift”) of general LVDS data output from the LVDS reception circuit 131 will be described. Specific data for adjustment (6 bit all “0” and 6 bit all “1” are continuously output) is input to the LVDS data deviation adjustment circuit 133 through the LVDS reception circuit 131 as an LVDS data deviation adjustment signal. To do. The LVDS data deviation adjustment circuit 133 checks whether there is a data deviation between the channels. If there is a deviation, the LVDS data deviation holding circuit 133 holds the output data of the LVDS in a register (or memory or the like) and uses a data selector (memory In this case, change the address) and correct the gap by controlling the output data.

  FIG. 7 shows the relationship between the LVDS data deviation adjustment signal and the clock. As shown in the figure, the LVDS data deviation adjustment signal is a signal in which the 6-bit values of D0 to D5 are alternately switched to the same “1” or “0” in synchronism with the clock. The LVDS data deviation adjustment signal in FIG. 7 is a correct signal with no data deviation.

  However, it is assumed that the following deviation occurs when the correct signal without data deviation is received by the LVDS receiving circuit 131 and used in the pixel driving circuit.

  FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, and FIG. 8 shows bit D5, FIG. 9 shows bits D4 and D5, FIG. 10 shows bits D3 to D5 and D0 to D2, FIG. 11 shows bit D0, FIG. 12 shows bits D0 and D1, and FIG. In this example, D0 to D2 and D3 to D5 are shifted from each other. When such a shift occurs, if the data can be selected as shown in FIG. 14 or FIG. 15 using 12-bit data corresponding to 2 bytes of the data received by the LVDS receiving circuit 131, the data shift is eliminated. It can be corrected. If the CDR circuit in the LVDS receiving circuit 131 is operating normally, such a shift does not change in real time, so that the selection of the data position can be fixed.

  FIG. 14 shows that received 6-bit data is held in M [5] to M [0], and subsequently received 6-bit data is held in N [5] to N [0]. . Further, FIG. 14 shows that when there is no data deviation, the retained data D6 to D11 of N [5] to N [0] are output as D0 to D5, whereas when the data deviation as shown in FIG. 8 occurs. , M [0], N [5] to N [1] are output as D0 to D5, and the data shift can be corrected. Similarly, when the data deviation of FIG. 9 occurs, the holding data D4 to D9 are output, and when the data deviation of FIG. 10 occurs, the holding data D3 to D8 are output to correct the data deviation. .

  15 holds the received 6-bit data in M [5] to M [0], and subsequently holds the received 6-bit data in N [5] to N [0]. When such a data deviation occurs, the data deviation can be corrected by outputting the retained data D1 to D6 of M [4] to M [0] and N [5] as D0 to D5. Similarly, when the data deviation of FIG. 12 occurs, the holding data D2 to D7 are output, and when the data deviation of FIG. 13 occurs, the holding data D3 to D8 are output to indicate that the data deviation can be corrected. Yes.

  FIG. 16A shows a decode output for controlling the data selector (D / S) for data selection shown in FIGS. 14 and 15, and FIG. 16B shows a case of decode outputs 1-6. A specific selection signal is shown. That is, the values of the 6-bit data D0 to D5 are examined, and the data position that changes from “0” to “1” or “1” to “0” is extracted and used as a decode output. Select the data to be modified. If there is no change point, the processing is not performed because there is no problem because the position is correct.

  FIG. 17 is a circuit diagram of an embodiment of the LVDS data deviation adjustment circuit 133 in FIG. 1, and FIG. 18 is a timing chart for explaining the operation in FIG. The LVDS data shift adjustment circuit 133 requires the number of LVDS channels. In FIG. 17, the LVDS data deviation adjustment circuit 133 receives the LVDS signal, which is input from the outside of the chip after being multiplied by 6 and received by the LVDS reception circuit 131 in FIG. 1, in the LVDS receiver and deserializer 31 first. A signal used in a pixel driving circuit as schematically shown in FIG. 18A is generated and output in parallel with 6 bits. As schematically shown in FIG. 18A, when the output signal from the LVDS receiver and deserializer 31 is a correct signal with no data shift, “00” (6-bit all “0”) and “3F” ( 6-bit all “1”) is a signal that is repeated alternately. This repetitive signal is a special data shift adjustment signal for adjusting the LVDS data shift, and is used as initialization when the display device 10 is first turned on to start operation.

  Here, for example, when a data shift advanced by 1 bit as shown in FIG. 8 occurs in the data received by the LVDS receiving circuit 131 in FIG. 18B, the data is schematically shown in FIG. 18B from the LVDS receiver and deserializer 31. A 6-bit signal having the value shown in FIG. The value of the 6-bit signal shown in FIG. 18B is different from the value of the signal without data deviation shown in FIG. 18A according to the data deviation position.

  The 6-bit parallel DFF 32 captures the 6-bit signal output in parallel from the LVDS receiver and deserializer 31 in synchronization with the clock shown in FIG. 18C, and supplies the captured signal to the second-stage 6-bit parallel DFF 33 Then, it is taken in (that is, shifted) at the next rising edge of the clock. As a result, the 6-bit parallel DFF 32 outputs the 6-bit signal N [5: 0] shown in FIG. 18D, and the 6-bit parallel DFF 33 outputs the 6-bit signal M [5: 0] shown in FIG. Output. The 6-bit signal M [5: 0] is a signal delayed by one clock cycle from the 6-bit signal N [5: 0].

  On the other hand, the data selector (D / S) selection decoder 34 is supplied with the 6-bit signal output in parallel from the LVDS receiver and the deserializer 31, and the table shown in FIG. A 3-bit decoded output shown in FIG. 18D of the value obtained by referring to (or by comparing and comparing the delay correction patterns) is generated. The D-type flip-flop (DFF) 35 is latched by the 3-bit decode output shown in FIG. 18 (D) output in parallel from the D / S selection decoder 34 at the rising edge of the latch clock shown in FIG. 18 (D). As a result, a 3-bit selection signal SELA [2: 0] shown in FIG. 18D is generated. Here, the value of the selection signal SELA [2: 0] is “5” corresponding to the data shift. The D / S selection decoder 34 and the DFF 35 constitute delay correction control signal generation means of the present invention, and the DFF 35 outputs a selection signal SELA [2: 0], which is a delay correction control signal.

  The 12-bit input 6-bit output data selector (D / S) 36 receives the 6-bit signal N [5: 0] from the 6-bit parallel DFF 32 and the 6-bit signal M [5: 0] from the 6-bit parallel DFF 33. The signal of 12 bits is received as an input signal, and M [0] and N [5: 1] shown in FIGS. 14 and 16B are selected according to the value of the selection signal SELA [2: 0]. Thus, data O [5: 0] (command data D0 to D5) in which the data deviation is corrected is output. Here, the D / S selector 36 constitutes the output means of the present invention, and adjusts the 6-bit read bit position of the command data on the basis of the selection signal SELA [2: 0] to obtain a 6-bit logic. Command data D0 to D5 consisting only of bit values having the same value are output.

  Here, the data position selected by the 12-bit input 6-bit output data selector (D / S) 36 is shifted by one clock depending on how the data is shifted. If the data does not shift to the shifted data position, the data O [5: 0] is latched again by the 6-bit DFF 38 with the clock 3 shown in FIG. 18E, and the last 12-bit input 6-bit output data This is supplied to the input terminal B of the selector (D / S) 39. Data O [5: 0] is input to the other input terminal A of the 12-bit input 6-bit output data selector (D / S) 39.

  The 12-bit input 6-bit output data selector (D / S) 39 outputs the data O [5: 0] input to the input terminal B as the LVDS parallel signal when the selection signal SELB is “0”. When SELB is “1”, data O [5: 0] input to the input terminal A is output as an LVDS parallel signal. As the selection signal SELB, the most significant bit signal M [5] (D0) of the 6-bit signal M [5: 0] output in parallel from the 6-bit parallel DFF 33 is output by the DFF 37 at the rising edge of the clock 2 shown in FIG. Obtained by latching.

  As a result, when a data shift as shown in FIG. 8 occurs in the input LVDS signal, a 6-bit signal N [5: 0] is output from the 6-bit parallel DFF 32 as shown in FIG. The selection signal SELB becomes a logical value “1”, and an LVDS parallel signal in which the data shift is corrected is output from the 12-bit input 6-bit output data selector (D / S) 39.

  On the other hand, when the data shift as shown in FIG. 13 occurs in the input LVDS signal, as shown in FIG. 18E, the 6-bit parallel DFF 32 outputs the 6-bit signal N [5: 0], and the DFF 37 The signal M [5] input to is shifted by 1 bit from the time of data shift occurrence in FIG. For this reason, the selection signal SELB becomes a logical value “0”, and the data shift in which the data position in the 6-bit unit is delayed by the 6-bit DFF 38 from the 12-bit input 6-bit output data selector (D / S) 39 to obtain the correct timing. The corrected LVDS parallel signal is output from the 12-bit input 6-bit output data selector (D / S) 39.

  If there is no data shift, the D-type flip-flop (DFF) 35 outputs a 3-bit value “6” as shown in FIG. 16A output from the D / S selection decoder 34. The selection signal SELA [2: 0] is latched and output. As a result, the 12-bit input 6-bit output data selector (D / S) 36 selects N [5: 0] shown in FIGS. 14 and 16B and selects data in which no data shift has occurred. To do.

  In this way, the LVDS data shift adjustment circuit 133 adjusts the data shift even if there is a data shift in the LVDS signal and outputs the LVDS parallel signal at the correct data position. It can be supplied to the pixel drive circuit after the D / S-attached parallel DFF 14. As a result, even if a data position shift that erroneously recognizes a command due to a voltage fluctuation or noise of the power supply or GND occurs, a malfunction due to the data position shift can be prevented as much as possible, and a stable image display can be performed. .

  Note that the present invention is not limited to a liquid crystal display device, and can be applied to an organic EL display device and other display devices. Further, the present invention is provided with the digital data generation circuit 11 connected to the display device or to the display device, but only the digital data generation source for generating the digital data generated by the digital data generation circuit 11 is provided independently. Is also possible.

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 11 Digital data generation circuit 12 Pixel 13 High-speed interface (I / F) circuit 14 Parallel D type flip-flop (DFF) with data selector (D / S)
15 pixel adjustment shift register 16 horizontal signal driver 17 control circuit 18, 19 address decoder or shift register 21 adder 22 comparator 31 LVDS receiver and deserializer 32, 33 6-bit parallel D-type flip-flop (DFF)
34 Data selector (D / S) selection decoder 35, 37 D-type flip-flop (DFF)
36, 39 12-bit input 6-bit output data selector (D / S)
38 6-bit D-type flip-flop (DFF)
DESCRIPTION OF SYMBOLS 100 Image display part 131 LVDS receiving circuit 132 Command bit judgment circuit 133 LVDS data shift adjustment circuit

Claims (4)

Digital data composed of command data of a plurality of commands for controlling the operation of the pixel driving circuit unit and pixel data to be displayed for a pixel driving circuit unit that drives an image display unit in which a plurality of pixels are regularly arranged. Digital data generation means for generating and supplying the pixel drive circuit unit through the high-speed interface circuit,
The digital data generation means includes
Of the plurality of commands, a command indicating the writing of the pixel data to the pixel is assigned as command data having the same bit value to a predetermined channel of the plurality of channels as the most important command, and the command among the plurality of commands is the highest. For commands other than the important command, command data of one command is continuously provided for each channel other than the predetermined one channel among the plurality of channels in a reference clock period which is a plurality of data bit transmission periods other than the pixel data transmission period. Each of which is assigned with the same bit value, and in a plurality of data bit transmission periods other than the reference clock period, a signal having a format in which the pixel data is assigned in each channel other than the predetermined one channel is generated as the digital data. A display device. The high-speed interface circuit includes:
Command data obtaining means for obtaining command data for each of the plurality of data bits for each channel in the reference clock period of the supplied digital data;
Command determining means for determining command values from bit values obtained by majority determination of the bit values of the plurality of data bits for each of the command data for each channel acquired by the command data acquiring means. The display device according to claim 1. The high-speed interface circuit includes:
Command data acquisition means for acquiring command data for each of the plurality of data bits for each channel of the supplied digital data;
Delay correction control signal generation means for generating a delay correction control signal by comparing with a preset delay correction pattern for each of the command data for each channel acquired by the command data acquisition means,
An output that adjusts read bit positions of the plurality of data bits of the command data based on the delay correction control signal and outputs command data including only bit values having the same logical value of the plurality of data bits The display device according to claim 1, further comprising a data shift adjustment unit comprising:   2. The command other than the most important command among the plurality of commands includes at least a signal transfer command in a pixel, a read command at the time of a test, and a command indicating that the command is not executed. 4. The display device according to any one of items 3 to 3.