JP2015176979A - Semiconductor light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor light emitting device.SOLUTION: A semiconductor light emitting element constituting a semiconductor light emitting device includes: a photosemiconductor laminated layer in which an n-type semiconductor layer, an active layer and a p-type semiconductor layer are laminated; an n-side electrode and a p-side electrode formed on one surface of the photosemiconductor laminated layer; an insulation film formed on the n-side electrode and the p-side electrode and including an n-contact hole and a p-contact hole; a first conductive member formed on the insulation film and brought into contact with the n-side electrode through the n-contact hole; and a second conductive member brought into contact with the p-side electrode through the p-contact hole. The p-contact hole is arranged in a region corresponding to a corner region of the photosemiconductor laminated layer.

Description

  The present invention relates to a semiconductor light emitting device including a via type semiconductor light emitting element.

  A semiconductor light emitting device using a nitride semiconductor such as GaN can emit ultraviolet light or blue light, and can emit white light by using a phosphor. Such a semiconductor light emitting element is used for lighting equipment such as a vehicular lamp.

  The semiconductor light emitting device is, for example, an n-type GaN layer, an optical semiconductor laminate in which a light emitting active layer and a p-type GaN layer are laminated, and an electric current is injected into the optical semiconductor laminate in contact with the n-type and p-type GaN layers. And an electrode that can. Semiconductor light emitting devices are classified into via types (for example, Patent Documents 1 to 3), counter electrode types, flip chip types, and the like according to the structure and arrangement position of the electrodes.

JP 2011-066644 A JP 2011-249501 A JP 2011-199221 A

    An object of the present invention is to provide a semiconductor light emitting device including a via type semiconductor light emitting element and having high reliability.

  According to the main aspect of the present invention, a first conductivity type first semiconductor layer, a light emitting active layer, and a second conductivity type second semiconductor layer different from the first conductivity type are sequentially stacked. An optical semiconductor stack comprising a via hole penetrating the second semiconductor layer and the active layer, wherein the first semiconductor layer is exposed on the bottom surface of the via hole; and disposed in the via hole, A via electrode electrically connected to the first semiconductor layer exposed on the bottom surface of the via hole, and a surface electrically disposed on the surface of the second semiconductor layer so as to avoid the via hole and electrically connected to the second semiconductor layer An insulating film including an electrode, a first contact hole that is disposed on the surface electrode and from which the via electrode is exposed, and a second contact hole in which a part of the surface electrode is exposed; and the insulating film is disposed on the insulating film. The first A first conductive member in contact with the via electrode in a contact hole; a second conductive member disposed on the insulating film with a gap from the first conductive member; and in contact with the surface electrode in the second contact hole; The optical semiconductor stack includes a first edge having a first length L1 and a second edge having a second length L2 facing the first edge in a plan view. Coupled to one end of the first and second edges, to a third edge having a third length L3, and to the other end of the first and second edges And an outer edge including a fourth edge having a fourth length L4, and the second contact hole is projected from the third edge when projected into the optical semiconductor stacked surface. Up to a range 0.15 × L1 apart and 0.06 × L3 away from the first edge. Up to the corner region and up to 0.15 × L1 away from the fourth edge, and within the corner region up to 0.06 × L4 away from the first edge, Disposed semiconductor light emitting devices are provided.

  A highly reliable semiconductor light emitting device can be obtained.

and, 1A to 1F are cross-sectional views illustrating how a semiconductor light emitting device (semiconductor light emitting element) according to an embodiment is manufactured. 2A to 2C are plan views showing the arrangement relationship between via electrodes and surface electrodes on the optical semiconductor stack, the arrangement relationship between first contact holes and second contact holes on the insulating film surface, and the pattern of the conductive layer. . and, 3A to 3C are cross-sectional views illustrating a state in which the semiconductor light-emitting device (semiconductor light-emitting element) according to the embodiment is manufactured, and FIG. 3D is a plan view illustrating the pattern of the bonding layer formed on the support substrate. FIG. 3E is a plan view generally showing the semiconductor light emitting device according to the embodiment. 4A is a plan view showing a part of a semiconductor light emitting device according to a reference example, and FIG. 4B is a graph showing a current density distribution in the optical semiconductor stack of the semiconductor light emitting device. FIG. 5A is a plan view showing a part of the semiconductor light emitting device according to the example, and FIG. 5B is a graph showing a current density distribution in the optical semiconductor stack of the semiconductor light emitting device.

  First, a method for manufacturing a semiconductor light emitting device (LED device) according to an embodiment of the present invention will be described. The LED device has a configuration in which a plurality of semiconductor light emitting elements (LED elements), for example, four LED elements are arranged in one direction on a support substrate. All four LED elements shall have the same configuration. In the following, focusing on a single LED element, its manufacturing method will be mainly described.

  1A to 1F are cross-sectional views showing how the device structure 102 is formed on the growth substrate 10. Note that the relative sizes and positional relationships of the components shown in the figure are different from the actual ones.

  First, a C-plane sapphire substrate is prepared as the growth substrate 10. In addition to the sapphire substrate, a spinel substrate, a ZnO (zinc oxide) substrate, or the like can be used as the growth substrate 10. Thereafter, the growth substrate 10 is thermally cleaned. Specifically, the growth substrate 10 is heated at 1000 ° C. for 10 minutes in a hydrogen atmosphere.

Next, as shown in FIG. 1A, Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y) is formed on the growth substrate 10 by MOCVD (metal organic chemical vapor deposition) or the like. A nitride semiconductor layer (optical semiconductor stack 20) expressed by ≦ 1) is formed.

Specifically, first, the substrate temperature is set to 500 ° C., TMG (trimethylgallium) is supplied at a flow rate of 10.4 μmol / min, and NH ₃ is supplied at a flow rate of 3.3 SLM for 3 minutes. As a result, a buffer layer made of GaN grows on the growth substrate 10. Subsequently, the substrate temperature is set to 1000 ° C. to crystallize the buffer layer.

Thereafter, while maintaining the substrate temperature, TMG is supplied at a flow rate of 45 μmol / min and NH ₃ is supplied at a flow rate of 4.4 SLM for 20 minutes. Thereby, an underlayer made of GaN grows on the buffer layer. The buffer layer and the base layer constitute the base buffer layer 21.

Thereafter, while maintaining the substrate temperature, TMG is supplied at a flow rate of 45 μmol / min, NH ₃ is supplied at a flow rate of 4.4 SLM, and SiH ₄ is supplied at a flow rate of 2.7 × 10 ⁻⁹ μmol / min for 120 minutes. As a result, a Si-doped GaN layer (n-type GaN layer) having a thickness of about 7 μm is grown on the underlying buffer layer 21. The n-type GaN layer constitutes the n-type semiconductor layer 22.

Thereafter, the substrate temperature is set to 700 ° C., TMG is supplied at a flow rate of 3.6 μmol / min, TMI (trimethylindium) is supplied at a flow rate of 10 μmol / min, and NH ₃ is supplied at a flow rate of 4.4 SLM for 33 seconds. A well layer (with a thickness of about 2.2 nm) is grown. Subsequently, the supply of TMI is stopped, TMG and NH ₃ are supplied for 320 seconds, and a barrier layer (layer thickness of about 15 nm) made of GaN is grown. Then, the growth of the well layer and the barrier layer is repeated alternately (for example, for five periods) to form the active layer 23 having a multiple quantum well structure on the n-type semiconductor layer 22.

Thereafter, the substrate temperature is set to 870 ° C., TMG at a flow rate of 8.1 μmol / min, NH ₃ at a flow rate of 4.4 SLM, and CP2Mg (biscyclopentadienyl at a flow rate of 2.9 × 10 ⁻⁷ μmol / min. Magnesium) is fed for 5 minutes. As a result, an Mg-doped GaN layer (p-type GaN layer) having a thickness of about 500 nm is grown on the active layer 23. The p-type GaN layer constitutes the p-type semiconductor layer 24.

  As described above, the optical semiconductor stack 20 in which the n-type semiconductor layer 22, the active layer 23, and the p-type semiconductor layer 24 are sequentially stacked is formed on the growth substrate 10 via the base buffer layer 21.

  Next, the p-side electrode (surface electrode) 30 including the opening 30h is formed on the surface of the optical semiconductor stack 20 (p-type semiconductor layer 24) by a lift-off method. The p-side electrode 30 is made of, for example, a conductive multilayer film of ITO (indium tin oxide) film / Ag film / TiW film / Ti film / Pt film / Au film / Ti film. The p-side electrode 30 is electrically connected to the p-type semiconductor layer 24 on the surface of the p-type semiconductor layer 24. In the drawing, the p-side electrode 30 is shown as including a single opening 30h, but actually includes a large number of openings 30h (see FIG. 2).

  Next, as shown in FIG. 1B, the region corresponding to the opening 30h and the region outside the p-side electrode 30 in the optical semiconductor stack 20 are removed by dry etching with chlorine gas using a resist mask. To do. As a result, the via 20 b and the outer groove 20 d are formed in the optical semiconductor stack 30. The via 20b and the outer groove 20d penetrate at least the p-type semiconductor layer 24 and the active layer 23, and the n-type semiconductor layer 22 is exposed on the bottom surfaces thereof.

Next, as shown in FIG. 1C, the float layer 40 is formed in a region excluding the bottom surface of the via 20b. First, a SiO ₂ film having a thickness of about 300 nm is formed on the entire upper surface of the optical semiconductor stack 20 including the p-side electrode 30 by sputtering or the like. The SiO ₂ film may be replaced with a SiN film or the like. Subsequently, the SiO ₂ film formed on the bottom surface of the via 20b is etched by a dry etching method using a CF ₄ / Ar mixed gas using a resist mask. At this time, the n-type semiconductor layer 22 is exposed on the bottom surface of the via 20b. As a result, an SiO ₂ film that covers at least the side surfaces of the p-side electrode 30 and the via 20b, that is, the float layer 40 is formed.

  Next, as shown in FIG. 1D, an n-side electrode (via electrode) 50 is formed in the via 20b by a lift-off method. The n-side electrode 50 is made of, for example, a metal multilayer film of Ti film / Al film / Ti film / Pt film / Au film. The n-side electrode 50 is electrically connected to the n-type semiconductor layer 22 at the bottom surface of the via 20b. Since the side surface of the via 20b is covered with the float layer 40, the n-side electrode 50 is not electrically connected to the active layer 23 and the p-type semiconductor layer 24.

  Next, as shown in FIG. 1E, a portion of the float layer 40 located above the p-side electrode 30 is removed by dry etching using chlorine gas using a resist mask, and a portion of the p-side electrode 30 is removed. Expose. Here, for convenience, a portion of the float layer 40 located above the p-side electrode 30 (a surface portion of the float layer 40) is referred to as an insulating film 41. Further, on the surface of the insulating film 41, a portion where the p-side electrode 30 is exposed is referred to as a p-contact hole 41p, and a portion where the n-side electrode 50 is exposed is referred to as an n-contact hole 41n.

  Next, as shown in FIG. 1F, a conductive layer 60 made of a metal multilayer film of Ti film / Pt film / Au film is formed on the float layer 40, particularly on the insulating film 41, by a lift-off method. The conductive layer 60 includes a first conductive member 61 in contact with the n-side electrode 50 in the n contact hole 41n, and a second conductive member 62 in contact with the p-side electrode 30 in the p contact hole 41p. The first conductive member 61 and the second conductive member 62 are formed with a gap 60g therebetween and are electrically insulated from each other.

  Thereafter, a separation groove 20 i penetrating the float layer 40 and the optical semiconductor stack 20 is formed in the outer groove 20 d by a dry etching method using chlorine gas using a resist mask. The separation groove 20i defines the outer edge of the LED element.

  As described above, the device structure 102 including the components from the optical semiconductor stack 20 to the conductive layer 60 is formed on the growth substrate 10.

  2A to 2C show the arrangement relationship of the p-side electrode 30 and the n-side electrode 50 on the surface of the optical semiconductor stack 20, the arrangement relationship of the p-contact hole 41p and the n-contact hole 41n on the surface of the insulating film 41, and the conductive layer, respectively. It is a top view which shows 60 patterns. The optical semiconductor stack 20 defined by the separation groove 20i has, for example, a rectangular planar shape having a short side of about 650 to 700 μm and a long side of about 1300 to 1350 μm. Here, the edge (outer edge) constituting the short side of the optical semiconductor stack 20 is referred to as the first and second edges S1 and S2, respectively, and the edge (outer edge) constituting the long side is respectively the third and third edges. The four edges S3 and S4 will be referred to.

  As shown in FIG. 2A, a p-side electrode 30 (shown in a hatched pattern with a relatively large pitch) and an n-side electrode 50 (shown in a hatched pattern with a relatively narrow pitch in the figure). Are formed on the surface of the optical semiconductor laminate 20. The p-side electrode 30 is provided on the entire surface of the optical semiconductor stack 20 while avoiding the n-side electrode 50. The n-side electrode 50 (or the via 20b) has, for example, a circular planar shape, and is provided so as to be uniformly distributed in the surface of the optical semiconductor laminate 20. In the drawing, the n-side electrode 50 is shown to be distributed in a matrix of 3 rows and 5 columns, but actually, it is provided to be distributed in a matrix of 6 rows and 11 columns, for example. The planar shape of the n-side electrode 50 is not limited to a circular shape, and may be an elliptical shape or a rectangular shape. Also, the distribution mode is not limited to a matrix.

  As shown in FIG. 2B, the float layer 40 is formed so as to entirely cover the optical semiconductor stack 20. In the float layer 40 (or in the insulating film 41 positioned above the p-side electrode 30 in the float layer 40), the p-contact hole 41p through which the p-side electrode 30 can be seen and the n-side electrode 50 can be seen. An n contact hole 41n that can be formed is provided. The p contact hole 41p is provided in a corner region near the first and third edge portions S1 and S3 of the optical semiconductor stack 20 and a corner region near the first and fourth edge portions S1 and S4.

  As shown in FIG. 2C, the conductive layer 60 is formed on the surface of the float layer 40, particularly on the insulating film 41. The conductive layer 60 is a first conductive member 61 that is in contact with the n-side electrode 50 (shown by a broken line in the drawing) and a first contact member 61 that is in contact with the p-side electrode 30 (shown by a broken line in the drawing). The two conductive members 62 are patterned. The first conductive member 61 and the second conductive member 62 are patterned with a gap 60g.

  3A to 3C are cross-sectional views showing a state in which the growth substrate 10 is separated from the device structure 102 and the LED element 101 and the LED device 100 are completed.

First, a support substrate 71 for supporting the device structure 102 is prepared (see FIG. 3A). For example, a Si substrate is used as the support substrate 71. For the support substrate 71, a member having a thermal expansion coefficient close to that of sapphire (7.5 × 10 ⁻⁶ / K) or GaN (5.6 × 10 ⁻⁶ / K) and having high thermal conductivity is used. preferable. For example, besides Si, Ge, Mo, CuW, AlN, etc. can be used. When a Si substrate is used as the support substrate 71, for example, the insulating layer 71a made of SiO ₂ is formed by thermally oxidizing the surface of the Si substrate.

  Thereafter, a bonding layer 72 made of AuSn (Sn: 20 wt%) is formed on the surface of the support substrate 71 (insulating layer 71a) by a lift-off method or the like. The bonding layer 72 includes a first bonding member 72a and a second bonding member 72b. The first joining member 72a and the second joining member 72b are formed with a gap 72g therebetween and are electrically insulated from each other (see FIG. 3D).

  Next, as shown in FIG. 3A, the prepared support substrate 71 and the device structure 102 that has already been prepared are arranged so that the bonding layer 72 and the conductive layer 60 face each other. At this time, the bonding layer 72 and the conductive layer 60 are arranged so that the position of the gap 72g of the bonding layer 72 and the position of the gap 60g of the conductive layer 60 coincide with each other, and the first conductive member 61 and the first bonding member 72a Are arranged so that the second conductive member 62 and the second joining member 72b face each other.

  Next, as shown in FIG. 3B, the support substrate 71 and the device structure 102 are bonded together and held for 10 minutes while being heated to 300 ° C. while being pressurized at 3 MPa. Subsequently, the bonding layer 72 and the conductive layer 60 are fusion bonded to each other by cooling to room temperature.

Thereafter, the growth substrate 10 and the device structure 102 (the optical semiconductor stack 20) are separated by a laser lift-off method. Specifically, KrF excimer laser light (wavelength 248 nm, irradiation energy density 800 to 900 mJ / cm ² ) is irradiated from the growth substrate 10 (sapphire substrate) side. The laser light passes through the growth substrate 10 and is absorbed by the underlying buffer layer 21 (GaN layer). The base buffer layer 21 is decomposed by heat generated by light absorption. As a result, the growth substrate 10 and the optical semiconductor stack 20 are separated, and the n-type semiconductor layer 22 is exposed.

  Hereinafter, for convenience, the arrangement relationship between the support substrate 71 and the device structure 102 is shown upside down.

  Next, as shown in FIG. 3C, a so-called microcone structure layer 22 a is formed on the surface of the n-type semiconductor layer 22 of the optical semiconductor stack 20. Specifically, the surface of the n-type semiconductor layer 22 is wet-etched with, for example, a TMAH (phenyltrimethylammonium hydroxide) aqueous solution (temperature about 70 ° C., concentration about 25%). The formation of the microcone structure layer 22a contributes to the improvement of the light extraction efficiency (the amount of light emitted from the surface of the n-type semiconductor layer / the amount of light emitted from the active layer) of the LED element.

Next, a surface protective film 80 made of SiO ₂ or the like is formed on the surface of the n-type semiconductor layer 22 (microcone structure layer 22a) by a chemical vapor deposition (CVD) method or the like. Thus, the individual LED elements 101 constituting the LED device 100 are completed.

  FIG. 3D is a plan view showing a pattern of the bonding layer 72 formed on the support substrate 71. The bonding layer 72 is connected to the first bonding member 72a connected to the first conductive member 61 (shown by a broken line in the drawing) and the second conductive member 62 (shown by a broken line in the drawing). The second bonding member 72b to be patterned is patterned. The bonding layer 72 is patterned so that the gap 72 g overlaps the gap 60 g of the conductive layer 60.

  The first bonding member 72a is electrically connected to the p-side electrode of the adjacent LED element. The second bonding member 72b is electrically connected to the n-side electrode of the adjacent LED element (see FIG. 3E).

  After the LED elements 101 are completed, for example, the support substrate 71 is divided by laser scribing or dicing at a size in which four LED elements 101 are arranged. Thus, the LED device 100 is completed. After that, for example, a resin containing a yellow phosphor may be dropped over the entire surface of the support substrate 71 so as to cover the plurality of LED elements 101 and cured to form a fluorescent layer.

  FIG. 3E is a plan view showing the LED device 100. The LED device 100 has a configuration in which, for example, four LED elements 101 are arranged in one direction on a support substrate 71. The four LED elements 101 are electrically connected in series via the bonding layer 72.

  The bonding layers 72 disposed at both ends of the support substrate 71 constitute pad electrodes 72 a connected to the power source 103. The power supply 103 can supply power to the LED element 101 via the pad electrode 72a (bonding layer 72).

  Reference is again made to FIG. 3C. Electrons supplied from the power source 103 move from the first bonding member 72a of the bonding layer 72 to the first conductive member 61 of the conductive layer 60 in each LED element 101, and are further connected at the n contact hole 41n on the n side. Move to electrode 50. In addition, the holes supplied from the power source 103 move from the second bonding member 72b of the bonding layer 72 to the second conductive member 62 of the conductive layer 60 in each LED element 101, and are further connected in the p contact hole 41p. Move to the p-side electrode 30. Holes and electrons injected from the p-side electrode 30 and the n-side electrode 50 into the optical semiconductor stack 20 are recombined in the active layer 23, and energy for this recombination is released as light (and heat). At this time, the current flows from the second bonding member 72b toward the first bonding member 72a.

  In addition to the LED device by an Example, the present inventors produced the LED device by a reference example, and measured the current density of these LED devices (or LED element), and evaluated reliability.

  FIG. 4A is a plan view showing an arrangement relationship between the optical semiconductor stack 20, and the p contact hole 41p and the n contact hole 41n in the LED element according to the reference example. In the LED element of the reference example, three p contact holes 41p are provided near the center of the first edge S1. The n contact holes 41n are provided, for example, in a matrix form in the surface of the optical semiconductor stack 20.

  Here, each of the p contact holes 41p has a length Lv in the direction along the first edge S1, and a length (width) in the direction along the third to fourth edges S3 and S4 is Lh. Suppose there is. Each of the p contact holes 41p is separated from the first edge S1 by a distance Dh, and the p contact holes 41p on both sides close to the third and fourth edges S3 and S4 are in the third and fourth edges S3. , S4 are separated from each other by a distance Dv. The optical semiconductor stack 20 has a short side length (that is, the length of the first and second edge portions S1 and S2) of Ls, and a long side length (that is, the third and fourth edge portions). Assume that the length of S3 and S4 is Ll.

  In addition, an X axis parallel to the first edge S1 is defined. In the X-axis direction, the end on the third edge S3 side in the first edge S1 is defined as a position Ps1, and the end on the fourth edge S4 side is defined as a position Ps2. Further, in the X-axis direction, the center of the n contact hole 41n closest to the third edge S3 is defined as a position Pe1, and the center of the n contact hole 41n closest to the fourth edge S4 is defined as a position Pe2.

  The present inventors measured the current density distribution in the IVB-IVB cross section of the optical semiconductor lamination 20 about the LED element which has the following conditions. The IVB-IVB cross section of the optical semiconductor stack 20 is a cross section along the first edge S1 (that is, the X-axis direction) and corresponding to the arrangement position of the p contact hole 41p.

  In the LED element of the reference example related to the measurement, the length Ls of the first and second edge portions S1 and S2 (the length of the short side, the length from the position P1 to the position P2 in the X-axis direction) Ls is about 700 μm. The length (long side length) Ll of the third and fourth edge portions S3 and S4 is about 1350 μm. Each p contact hole 41p has a length Lv of about 55 μm and a width Lh of about 40 μm. The distance Dh from the first edge S1 to each of the p contact holes 41p is about 50 μm, and the distance Dv from the third and fourth edges S3, S4 to the p contact holes 41p on both sides is about 120 μm. is there. The LED device (four LED elements directly connected) is supplied with electric power of about 10 W (voltage 10 V, current 1 A).

  FIG. 4B is a graph showing a current density distribution in the IVB-IVB cross section of the optical semiconductor stack 20. The horizontal axis indicates the position along the X-axis direction of the optical semiconductor stack, and the vertical axis indicates the current density normalized by the peak value. From this graph, it can be seen that a relatively large amount of current flows in the central portion of the cross section IVB-IVB of the optical semiconductor stack 20. When the difference between the current density at the peak value and the current density at the positions Pe1 and Pe2 is defined as the current concentration degree Id, the current concentration degree Id in the IVB-IVB cross section of the optical semiconductor stack 20 is about 17%.

  The present inventors further performed reliability evaluation on an LED device including an LED element having the above conditions. Specifically, a test was conducted in which the LED device was continuously energized in a hot and humid environment. As a result, it was confirmed that when the energization was continued for about 100 hours, the optical semiconductor stack 20 was damaged, in particular, the vicinity of the first edge S1 of the optical semiconductor stack 20 was significantly damaged. This is presumably because the current concentrates on the portion of the optical semiconductor stack 20 corresponding to the position where the p contact hole 41p is arranged (the central portion in the IVB-IVB cross section).

  FIG. 5A is a plan view showing in detail an arrangement relationship between the optical semiconductor stack 20, and the p contact hole 41p and the n contact hole 41n in the LED element according to the embodiment. In the LED element of the embodiment, the p contact hole 41p has a corner area close to the first and third edges S1 and S3 of the optical semiconductor stack 20, and an angle close to the first and fourth edges S1 and S4. Two places are provided in the region.

  The present inventors measured the current density distribution in the VB-VB cross section of the optical semiconductor lamination 20 about the LED element which has the following conditions. The VB-VB cross section of the optical semiconductor stack 20 is a cross section along the first edge S1 (that is, in the X-axis direction) and corresponding to the arrangement position of the p contact hole 41p.

  In the LED element according to the measurement example, the length Ls of the first and second edges S1 and S2 is about 700 μm, and the length Ll of the third and fourth edges S3 and S4 is about 1350 μm. is there. The length Lv of the p contact hole 41p is about 20 μm, and the width Lh is about 20 μm. The distance Dh from the first edge S1 to the p contact hole 41p is about 20 μm, and the distance Dv from each of the third and fourth edges S3, S4 to the p contact hole 41p is about 20 μm. The LED device (four LED elements directly connected) is supplied with electric power of about 10 W (voltage 10 V, current 1 A).

  FIG. 5B is a graph showing a current density distribution in the VB-VB cross section of the optical semiconductor stack 20. From this graph, it can be seen that the current density distribution in the VB-VB cross section of the optical semiconductor stack 20 is relatively flat. That is, it can be seen that in the VB-VB cross section of the optical semiconductor stack 20, the current does not flow in a specific portion but flows widely and relatively uniformly. The current concentration Id in the VB-VB cross section of the optical semiconductor stack 20 was about 6%.

  The present inventors further performed reliability evaluation on an LED device including an LED element having the above conditions. As a result, it was confirmed that the optical semiconductor laminate 20 was not damaged even when energized continuously for 1000 hours or more. This is considered to be because current does not flow in a specific part but flows widely in a specific portion in the cross section of the optical semiconductor stack 20 corresponding to the arrangement position of the p contact hole 41p.

  From such a measurement result, the p contact hole 41p is provided in the corner region of the optical semiconductor stack 20 in plan view, whereby the current density distribution of the optical semiconductor stack 20 is made uniform, and the LED element (or LED device). It was found that the reliability of improved. In addition, the homogenization of the current density distribution in the optical semiconductor stack 20 will contribute to the uniform emission intensity distribution (luminance distribution) in the LED element in addition to the improvement in the reliability of the LED element.

  The size, shape, arrangement position, etc. of the p contact hole 41p are not limited to the above conditions. The p contact hole 41p is at least up to a range 40 μm (= Dh + Lh) away from the first edge S1, and up to a range 40 μm (= Dv + Lv) away from each of the third and fourth edges S3 and S4. It is considered that the reliability of the LED element is improved by being disposed in the corner region. In other words, the p contact hole 41p is at least up to a range separated from the first edge S1 by L1 × 3% (≈ (Dh + Lh) / L1), and from each of the third and fourth edges S3, S4. It is considered that the reliability of the LED element is improved by being disposed in a corner region up to a range separated by Ls × 6% (≈ (Dv + Lv) / Ls).

  Furthermore, according to the estimation by the present inventors, the p contact hole 41p is in a range (range Ah shown in FIG. 5A) that is about 80 μm away from the first edge S1, and the third and fourth edges. The reliability of the LED element can be improved by being disposed in a region (region 20c shown in FIG. 5A) up to a range (range Av shown in FIG. 5A) separated from each of the parts S3 and S4 by about 100 μm. That is, the p contact hole 41p is in a range of L1 × 6% (≈80 μm / 1350 μm) away from the first edge S1, and Ls × 15% from each of the third and fourth edges S3, S4. The reliability of the LED element can be improved by being disposed in the region 20c up to a distance (≈100 μm / 700 μm). It should be noted that within the region 20c, the shape, size, number of arrangements, etc. of the p contact hole 41p will not be particularly limited.

  As mentioned above, although this invention was demonstrated along the Example and the modification, this invention is not limited to these. For example, the planar shape of the LED elements is not limited to a rectangular shape, and the number of LED elements arranged is not limited to four. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like are possible.

DESCRIPTION OF SYMBOLS 10 ... Growth substrate, 20 ... Optical semiconductor lamination | stacking, 21 ... Base buffer layer, 22 ... N-type semiconductor layer, 23 ... Active layer (light emitting layer), 24 ... P-type semiconductor layer, 30 ... P side electrode (surface electrode), 40 ... float layer, 41 ... insulating film, 41n ... n contact hole, 41p ... p contact hole, 50 ... n-side electrode (via electrode), 60 ... conductive layer, 71 ... support substrate, 72 ... bonding layer, 80 ... surface Protective film, 100 ... LED device, 101 ... LED element, 102 ... device structure, 103 ... power source.

Claims (5)

An optical semiconductor stack in which a first semiconductor layer of a first conductivity type, an active layer having a light emitting property, and a second semiconductor layer of a second conductivity type different from the first conductivity type are sequentially stacked, A semiconductor layer and a via hole penetrating the active layer, and an optical semiconductor stack in which the first semiconductor layer is exposed on a bottom surface of the via hole;
A via electrode disposed in the via hole and electrically connected to the first semiconductor layer exposed on a bottom surface of the via hole;
A surface electrode disposed on the surface of the second semiconductor layer so as to avoid the via hole, and electrically connected to the second semiconductor layer;
A first contact hole disposed on the surface electrode and exposing the via electrode; and an insulating film comprising a second contact hole exposing a part of the surface electrode;
A first conductive member disposed on the insulating film and in contact with the via electrode in the first contact hole;
A second conductive member disposed on the insulating film with a gap from the first conductive member and contacting the surface electrode in the second contact hole;
Including
The optical semiconductor stack includes a first edge having a first length L1, a second edge having a second length L2, opposite to the first edge, and the second edge in the plan view. Coupled to one end of the first and second edges, coupled to a third edge having a third length L3, and to the other end of the first and second edges; An outer edge including a fourth edge having a length L4 of
The second contact hole has a range of 0.06 × L3 away from the first edge when projected into the optical semiconductor stack, and is 0.15 away from the third edge. × L1 in the angular region up to the range and up to 0.06 × L4 away from the first edge, up to 0.15 × L1 away from the fourth edge Arranged in the corner area,
Semiconductor light emitting device.   The second contact hole has a distance of 0.03 × L3 from the first edge when projected into the optical semiconductor stacked surface, and is 0.06 × L3 away from the third edge. × L1 in the angular region up to the range and up to 0.03 × L4 away from the first edge, up to 0.06 × L1 away from the fourth edge The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is disposed in a corner region.   3. The planar shape of the optical semiconductor stack is a rectangular shape in which the first and second edges constitute a short side and the third and fourth edges constitute a long side. Semiconductor light emitting device.   4. The semiconductor light emitting device according to claim 3, wherein the first and second lengths L1 and L2 are 650 μm to 700 μm, and the third and fourth lengths L3 and L4 are 1300 μm to 1350 μm.   Furthermore, the power supply which is electrically connected to the said 1st conductive member and the said 2nd conductive member, and can supply the electric current of 1 A or more to the said optical-semiconductor lamination | stacking is included. Semiconductor light emitting device.

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