JP2015172530A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently implement a test of ICs by arranging test pads less than the number of terminals with multiple pins and narrow pitches on a film in the IC having a COF mounted.SOLUTION: Short circuit wire shunting a terminal with multiple pins/narrow pitches every plural terminals and one test pad for each short circuit wire are configured to be disposed outside a cut line on a film. In an IC, a switch is provided that can control so that only one terminal out of all the terminals is independently connected to an internal circuit for each of the plurality of terminals to be externally shunted, and the other terminals are blocked from the internal circuit. The plurality of terminals to be shunted by the same short circuit wire are connected to the internal circuit by every one terminal and measure an electric characteristic via a corresponding short circuit wire and test pad, which implements a test of the IC.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a semiconductor chip having a multi-pin, narrow-pitch terminal such as a display driver IC (Integrated Circuit) that can be connected to a high-definition display panel is a COF (Chip On Film). It can be suitably used for a mounted semiconductor device.

  In recent years, the trend toward higher definition of display panels is also remarkable in small and medium portable terminals such as smartphones and tablets. A display panel such as a liquid crystal display (LCD) or an organic light-emitting diode (OLED) generally has a plurality of scanning lines (also referred to as gate lines) and a plurality of signal lines (also referred to as source lines). A display element is provided at each point where. The definition of a display panel is defined by the number of scanning lines per screen (number of lines) and the number of display elements per line (number of pixels). As the definition becomes higher, the number of gate lines and the number of source lines The number increases. One or more display driver ICs are mounted on one side of the display panel, and drive the source lines in parallel.

  The display driver IC is mounted on the glass substrate of the display panel by flip chip mounting, for example, a mounting method called COG (Chip On Glass), or on a film-like flexible wiring substrate connected to the display panel. There is a mounting method called COF (Chip On Film). A test for selecting non-defective products of the display driver IC is performed in a wafer state when the display driver IC is shipped as a bare chip for COG mounting, and in the case of COF mounting, in addition to the test in a wafer state similar to COG. In many cases, the test is performed even when mounted on a reel-like flexible wiring board. This is because defective products resulting from COF mounting are selected by testing the electrical continuity between the COF wiring and the display driver IC.

  Patent Document 1 discloses a COF package having a test pad for evaluating electrical characteristics. Patent Document 2 discloses an inspection method using a probe card in a semiconductor device such as a COF that requires a large number of pins and a narrow pitch, and a semiconductor device suitable for the inspection. Patent Document 3 discloses a COF substrate that eliminates local thinning of wiring in a test pad portion. Patent Document 4 discloses a display device in which a test terminal is provided on a display panel substrate to which a COF is connected.

JP 2002-313847 A JP 2002-196036 A JP 2010-010375 A JP 2012-226058 A

  As a result of examination of Patent Documents 1, 2, 3, and 4, the inventors have found that there are the following new problems.

  In a semiconductor chip having a multi-pin, narrow-pitch terminal such as a display driver IC connected to a high-definition display panel, the multi-pin, narrow-pitch, such as a terminal for driving a source line, should be implemented after COF mounting. It was found that testing for terminals was difficult. As shown in Patent Document 1 and Patent Document 2, a test for a terminal of a semiconductor chip such as a display driver IC is performed by applying a probe to a test pad provided on a COF film via a wiring that is electrically connected to the terminal of the semiconductor chip. This is done by contacting a probe such as a card. At this time, when a multi-pin, narrow-pitch terminal is targeted, if the technique disclosed in Patent Document 2 is adopted, the test pad is placed on the film as shown in FIGS. The measurement is performed in a plurality of steps within a range in which the probes are arranged in a dispersed manner and the probes do not contact each other. The wiring from the terminal of the semiconductor chip to the test pad and the arrangement of the test pad can be shaped as shown in Patent Document 3, for example.

  As the display panel becomes higher in definition, the number of source lines to be driven increases and its terminals are arranged on one side of the display driver IC. Become. For example, in full high vision, even if RGB is multiplexed, the number of source lines is 1080. In the case where the effective area of the COF is 60 mm, in order to arrange the test pads for each terminal, the pitch allowed per test pad is 55.6 μm (60 mm ÷ 1080). On the other hand, the test pad normally allowed by COF is 90 μm at the minimum, and as many as 1080 test pads cannot be arranged in a row. Thus, when the terminals of the semiconductor chip are multi-pin and narrow pitch, as shown in Patent Document 3, a plurality of rows of test pads will be arranged side by side, depending on the size of the test pads allowed, The number of columns is very large. Further, as shown in Patent Document 2, the test is performed by dividing the measurement into a plurality of steps, so that the test time becomes long. Therefore, when the test cannot be completed in the COF mounting state because a sufficient number of test pads cannot be arranged on the film due to cost constraints, as shown in Patent Document 4, the COF The test is performed by providing a test pad on the substrate of the display panel on which is mounted. However, in that case, a defect that has not been detected in the COF mounting stage is found after mounting on the display panel, which may reduce the yield of the display panel more than necessary.

  An object of the present invention is to appropriately carry out a non-defective product selection test in a state where a multi-pin, narrow-pitch terminal semiconductor chip is mounted on a COF, using a smaller number of test pads than the number of the terminals. It is to provide a semiconductor chip and a test method thereof that can be used.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, a short-circuit wiring that short-circuits a plurality of terminals having multiple pins and narrow pitches and one test pad for each short-circuit wiring are arranged outside the cut line on the film. The semiconductor chip can be controlled so that, for each of a plurality of terminals that are short-circuited externally, all the terminals are connected to the internal circuit, and other terminals are disconnected from the internal circuit. Provide an appropriate switch. A plurality of terminals that are short-circuited by the same short-circuit wiring are connected to an internal circuit for each terminal, and the electrical characteristics are measured through the corresponding short-circuit wiring and test pads, thereby testing the semiconductor chip. The short-circuit wiring and the test pad are cut off at the cut line after the test.

  The effect obtained by the one embodiment will be briefly described as follows.

  That is, in a semiconductor chip mounted with COF, the test of the semiconductor chip can be efficiently performed by disposing test pads on the film that are smaller than the number of terminals of multi-pin, narrow pitch terminals.

FIG. 1 is a block diagram showing an overall configuration of a display and input device as an example of an electronic apparatus to which the present invention is applied. FIG. 2 is a perspective view showing a connection example of the display panel 2, the display driver IC 4 constituting the display panel controller, and the substrate 61 on which the host processor 6 is mounted. FIG. 3 is a schematic diagram schematically showing a configuration example of a semiconductor device in which a semiconductor chip according to the present invention is COF-mounted. FIG. 4 is a more detailed schematic diagram showing a circuit configuration in a semiconductor chip and an arrangement example of wirings and electrodes on a film of the semiconductor device according to the present invention. FIG. 5 is a flowchart showing an example of a method for manufacturing a semiconductor device of the present invention. FIG. 6 is an explanatory view showing a cross section of the semiconductor device in the probe test. FIG. 7 is an explanatory view showing a cross section of the semiconductor device in the chip mounting process. FIG. 8 is an explanatory diagram showing a cross section of a semiconductor device in a test in a COF mounted state. FIG. 9 is an explanatory view showing a cross section after the substrate mounting process. FIG. 10 is a block diagram illustrating a detailed configuration example of the display driver IC. FIG. 11 is a more detailed schematic diagram showing a circuit configuration in a semiconductor chip and an example of arrangement of wirings and electrodes on a film of the semiconductor device according to the second embodiment. FIG. 12 is a logic block diagram showing the configuration of the test circuit. FIG. 13 is an explanatory diagram of a truth table showing the operation of the test circuit in the test in the COF mounted state. FIG. 14 is an explanatory diagram of a truth table showing the operation of the test circuit in the probe test. FIG. 15 is a more detailed schematic diagram showing a circuit configuration in a semiconductor chip and an example of arrangement of wirings and electrodes on a film of the semiconductor device according to the third embodiment. FIG. 16 is a more detailed schematic diagram showing a circuit configuration in a semiconductor chip and an example of arrangement of wirings and electrodes on a film of the semiconductor device according to the fourth embodiment.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Semiconductor chip (IC) mounted with COF>
A typical embodiment disclosed in the present application includes a film (7), wirings (8, 11) by conductors (20) printed on the film, and a plurality of electrical connections to the wirings. A semiconductor device (21) including terminals (S6n to S6n-5) and a semiconductor chip (4) mounted on the film, and configured as follows.

  Outside the region where the semiconductor chip is mounted on the film, the connection region (11_0 to 11_5) for the wiring to be electrically connected to another substrate, and the connection region on the film Short-circuit wiring (8_1 and 8_2; 8_3 and 8_4; 8_5 and 8_6) that electrically short-circuits a predetermined number of the terminals among the plurality of terminals in a region that is further outside and separable from the connection region; At least one test pad (9_1 and 9_2) is provided which is electrically connected to the short-circuit wiring and provided for one short-circuit wiring.

  The semiconductor chip includes a cutoff switch (14, 15) that can cut off an electrical connection between each of the predetermined number of terminals and an internal circuit (12, 13) of the semiconductor chip.

  Thereby, the test in the state where the multi-pin, narrow-pitch terminals of the semiconductor chip are mounted in the COF mounting state can be appropriately performed using a smaller number of test pads than the number of the terminals. . Since the switch can be controlled and the predetermined number of terminals can be sequentially electrically connected to one test pad one by one, measurement can be performed. This is because it is sufficient.

[2] <Alternating short-circuit wiring = Connect to test pad>
In item 1, wirings adjacent to each other among the wirings from the plurality of terminals to the corresponding connection regions (wirings from S6n and S6n-1, S6n-2 and S6n-3, S6n-4 and S6n-5) are: They are connected to different short-circuit lines (8_1 and 8_2).

  Thereby, an open / short test can be performed between terminals adjacent to each other for lead wiring (wiring from each terminal to a connection region for electrical connection to another substrate; the same applies hereinafter).

[3] <Short-circuit wiring for short-circuiting a plurality of adjacent terminals>
In item 1, the predetermined number of terminals connected to the same short-circuit wiring (S6n, S6n-1 and S6n-2 connected to the short-circuit wiring 8_3, S6n-3 and S6n-4 connected to the short-circuit wiring 8_4, In S6n-5), the wiring from the terminal to the corresponding connection region is adjacent to each other.

  Thereby, the lead-out wiring from each terminal of the semiconductor chip, all the short-circuit wirings, and the test pad can be formed by using a single wiring layer on the film, and the cost of the COF substrate can be reduced. . Furthermore, in the COF mounting state, an open test of each terminal can be performed, and a short test between adjacent terminals connected to different short-circuit wirings can also be performed.

[4] <Short-circuit wiring for short-circuiting both ends of three adjacent terminals>
In item 1, among the three terminals adjacent to each other in the wiring to the connection region, the terminals at both ends are connected to the same short-circuited wiring, and the other one terminal is opened (S6n, S6n-1 adjacent to each other). , S6n-2, S6n and S6n-2 at both ends are short-circuited by a short-circuit wiring 8_5, and S6n-3 and S6n-5 at both ends of S6n-3, S6n-4, S6n-5 adjacent to each other are short-circuited wiring 8_6. Is short-circuited).

  Thereby, the lead-out wiring from each terminal of the semiconductor chip, all the short-circuit wirings, and the test pad can be formed by using a single wiring layer on the film, and the cost of the COF substrate can be reduced. . Furthermore, in the COF mounting state, it is possible to perform an open test of terminals at both ends of the same short-circuit wiring and a short test between adjacent terminals connected to different short-circuit wiring, and terminals between both terminals of the same short-circuit wiring and terminals sandwiched between them. The short test can be implemented by a simple short test using an internal circuit of a semiconductor chip.

[5] <Common with probe test with thinned probe>
In Item 4, the semiconductor chip further includes a short-circuit switch (PIN0, PIN1) capable of electrically short-circuiting the three terminals.

  Thereby, in the probe test of the semiconductor chip, it is possible to perform a test on all the predetermined number of terminals by using a probe card having a probe only on one of the predetermined number of terminals. Further, as a test circuit necessary for controlling the cutoff switch at this time, a test circuit common to the test in the state where the COF is mounted in the item 1 can be used.

[6] <Display driver IC>
Item 6. The device according to any one of Items 1 to 5, wherein the semiconductor chip is a display driver IC (4), and the plurality of terminals are source output terminals for driving source electrodes of a connected display panel (2). (S6n to S6n-5).

  The semiconductor chip includes a plurality of positive-side source amplifiers (AP1 to AP3) and a plurality of negative-side source amplifiers (AN1 to AN3) as internal circuits, and a plurality of first, second, and second elements operable as the cutoff switches. 3 and a fourth switch (APnOD, APnEV, ANnOD, ANnEV, where n = 1 to 3).

  Two adjacent source output terminals (S6n-5 and S6n-4, S6n-3 and S6n-2, S6n-1 and S6n) are connected to the first and second switches (AP1OD and AP1EV, AP2OD, respectively). Connected to one positive side source amplifier (AP1, AP2, AP3) via AP2EV, AP3OD and AP3EV), and via third and fourth switches (AN1OD and AN1EV, AN2OD and AN2EV, AN3OD and AN3EV), respectively. It is connected to one negative side source amplifier (AN1, AN2, AN3).

  Thereby, the present invention can be applied to the display driver IC. The straight / cross switches (first to fourth switches) for dot inversion driving can be configured to operate as a cut-off switch in the test in the COF mounted state, and are used only for the test purpose. It is possible to prevent the overhead caused by mounting the switch.

[7] <Method for manufacturing COF-mounted IC including testing>
A typical embodiment disclosed in the present application includes a film (7), a plurality of wirings (8, 11) and a plurality of test pads (9) by a conductor (20) printed on the film, A method of manufacturing a semiconductor device (21) comprising a semiconductor chip (4) having a plurality of terminals electrically connected to a plurality of wirings and mounted on the film, and configured as follows: .

  A chip mounting step (S34) for mounting the semiconductor chip on the film, and a probe (92) is brought into contact with at least one test pad (9) of the test pads to thereby electrically connect the terminals of the semiconductor chip. And an implementation test (S37) for measuring the physical characteristics. The chip mounting step includes a step (S35) of electrically connecting the plurality of wirings to each of the plurality of terminals.

  The film has a connection region (11) for physically and electrically connecting the wiring to another wiring (22) outside the region where the semiconductor chip is mounted. Furthermore, it has a short circuit wiring (8) for electrically short-circuiting a predetermined number of the terminals among the plurality of terminals in a region that is outside and separable from the connection region, And at least one test pad (9) is electrically connected.

  The semiconductor chip includes a cutoff switch (14, 15) capable of electrically disconnecting a plurality of terminals (S6n to S6n-5) that are short-circuited to each other by the short-circuit wiring from the internal circuit (12, 13) individually. .

  In the mounting test, terminals other than one of the plurality of terminals short-circuited by the short-circuit wiring are electrically disconnected from the corresponding internal circuit by the cutoff switch, and the terminals and the terminals are connected to each other. Electrically connecting a corresponding internal circuit and measuring an electrical characteristic of the internal circuit via a corresponding test pad.

  Thus, in the method of manufacturing the semiconductor device 21 in which the semiconductor chip having the multi-pin / narrow-pitch terminals is COF-mounted, the test in the COF-mounted state for the multi-pin / narrow-pitch terminals (S37). Can be appropriately implemented using a smaller number of test pads than the number of the terminals. Since the switch can be controlled and the predetermined number of terminals can be electrically connected to one test pad one by one in order, measurement can be performed, so one test pad is provided for the predetermined number of terminals. That is enough.

[8] <Alternating short-circuit wiring = Connect to test pad>
In item 7, the semiconductor chip has a protection diode (16) for each terminal, and wirings adjacent to each other (S6n and S6n-1, S6n-2) among the wirings from the plurality of terminals to the corresponding connection region. And S6n-3, wirings from S6n-4 and S6n-5) are connected to different short-circuiting wirings (8_1 and 8_2).

  The implementation test includes an open test and a short test. In the open test, a terminal other than one of the plurality of terminals short-circuited by the short-circuit wiring is electrically disconnected from the corresponding internal circuit by the cutoff switch and connected to the terminal. The forward characteristic of the protection diode is measured via the corresponding test pad. In the short test, the terminals adjacent to each other from the plurality of terminals to the corresponding connection region are electrically disconnected from the corresponding internal circuit by the cutoff switch, and different currents are applied by applying different potentials to each other. Measure presence or absence.

  As a result, in the mounting test (S37), an open / short test can be performed between the terminals where the lead wires are adjacent to each other.

[9] <Short-circuit wiring for short-circuiting a plurality of adjacent terminals>
In the item 7, the predetermined number of terminals connected to the same short-circuit wiring (S6n, S6n-1 and S6n-2 connected to the short-circuit wiring 8_3, S6n-3 and S6n-4 connected to the short-circuit wiring 8_4, In S6n-5), the wiring from the terminal to the corresponding connection region is adjacent to each other.

  Thereby, the lead-out wiring from each terminal of the semiconductor chip, all the short-circuit wirings, and the test pad can be formed by using a single wiring layer on the film, and the cost of the COF substrate can be reduced. . Furthermore, in the mounting test (S37), an open test of each terminal can be performed, and a short test between adjacent terminals connected to different short-circuit wirings can also be performed.

[10] <Short-circuit wiring for short-circuiting both ends of three adjacent terminals>
In item 7, among the three terminals adjacent to each other in the wiring to the connection region, the terminals at both ends are connected to the same short-circuited wiring, and the other one terminal is opened (S6n, S6n-1 adjacent to each other). , S6n-2, S6n and S6n-2 at both ends are short-circuited by a short-circuit wiring 8_5, and S6n-3 and S6n-5 at both ends of S6n-3, S6n-4, S6n-5 adjacent to each other are short-circuited wiring 8_6. Is short-circuited).

  Thereby, the lead-out wiring from each terminal of the semiconductor chip, all the short-circuit wirings, and the test pad can be formed by using a single wiring layer on the film, and the cost of the COF substrate can be reduced. . Furthermore, in the mounting test (S37), it is possible to perform an open test of terminals at both ends of the same short-circuit wiring and a short test between adjacent terminals connected to different short-circuit wirings.

[11] <Simple short test>
In item 10, the mounting test includes a simple short test. In the simple short test, among the adjacent three terminals, terminals at both ends (S6n and S6n-2, S6n-3 and S6n-5) and terminals sandwiched between them (S6n-1 and S6n-4) are used. Then, different potentials are applied from the corresponding internal circuits, and the current consumption of the power supply circuit that supplies power to the internal circuits is measured.

  As a result, the short test between the terminals at both ends of the same short-circuit wiring and the terminals sandwiched between them can be performed by a simple short test using the internal circuit of the semiconductor chip.

[12] <Common with probe test with thinned probe>
Item 7 further includes a probe test (S32) for inspecting the semiconductor chip in a wafer state before the chip mounting step.

  The semiconductor chip further includes a shorting switch (PIN0, PIN1) capable of electrically short-circuiting the predetermined number of terminals inside each other, and in the probe test, one of the predetermined number of terminals is connected to the semiconductor chip. Omit contact of the probe with the other terminals.

  Thereby, in the probe test (S32) of the semiconductor chip, a test can be performed for all the predetermined number of terminals using a probe card having a probe only in one of the predetermined number of terminals. it can. Further, the test circuit necessary for controlling the cutoff switch at this time can use the same test circuit as the mounting test (S37) in the state where the COF is mounted in Item 1.

[13] <Display driver IC>
In any one of Items 7 to 12, the semiconductor chip is a display driver IC (4), and the plurality of terminals are source output terminals for driving source electrodes of the connected display panel (2). (S6n to S6n-5).

  The semiconductor chip includes a plurality of positive-side source amplifiers (AP1 to AP3) and a plurality of negative-side source amplifiers (AN1 to AN3) as internal circuits, and a plurality of first, second, and second elements operable as the cutoff switches. 3 and a fourth switch (APnOD, APnEV, ANnOD, ANnEV, where n = 1 to 3).

  Two adjacent source output terminals (S6n-5 and S6n-4, S6n-3 and S6n-2, S6n-1 and S6n) are connected to the first and second switches (AP1OD and AP1EV, AP2OD, respectively). Connected to one positive side source amplifier (AP1, AP2, AP3) via AP2EV, AP3OD and AP3EV), and via third and fourth switches (AN1OD and AN1EV, AN2OD and AN2EV, AN3OD and AN3EV), respectively. It is connected to one negative side source amplifier (AN1, AN2, AN3).

  Thereby, the manufacturing method of the semiconductor device according to the present invention can be applied to the display driver IC. The straight / cross switch (first to fourth switches) for dot inversion driving can be configured to operate as a cut-off switch in the test (mounting test S37) in the COF mounted state. It is possible to prevent the overhead caused by mounting a switch that is used only for the switch.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 illustrates the overall configuration of a display and input device 100 to which the present invention is applied. A display and input device 100 shown in the figure is an example of an electronic apparatus according to the present invention, and constitutes a part of a portable terminal such as a PDA (Personal Digital Assistant) or a mobile phone, and includes a touch panel (TP) 1 and a display. A panel (DP) 2, a touch panel controller (TPC) 3, a display panel controller (DPC) 4, a sub processor (SMPU) 5, and a host processor (HMPU) 6 are provided. The touch panel controller 3 and the display panel controller 4 are further formed as a single semiconductor chip including a sub-processor 5 as necessary, or mounted on a single package as, for example, a multi-chip module, to form a single semiconductor. The devices 101 and 102 can be realized. For example, by mounting the touch panel controller 3 and the display panel controller 4 as a one-chip IC 101, the display panel 2 and the touch panel 1 are stacked and integrated, for example, connected to an in-cell type display / touch panel, It becomes easy to coordinate touch sense control with each other. Further, by further integrating the sub processor (SMPU) 5 on the same chip 102, it becomes easier to coordinate display driving and touch sense control with each other, and the burden on the external host processor (HMPU) 6 is increased. Can be reduced.

  The touch panel 1 is a mutual capacitive touch panel that enables multi-touch detection, and includes a plurality of intersections formed by a plurality of drive electrodes (Y electrodes) and a plurality of detection electrodes (X electrodes). A capacitance component (cross capacitance) is formed at the intersection. The touch panel controller 3 sequentially supplies drive pulses to the drive electrodes, and thereby obtains detection data corresponding to fluctuations in capacitance components at each intersection based on signals sequentially obtained from the detection electrodes. A sub processor (SMPU) 5 that is a microprocessor for the sub system controls the driving of the touch panel 1 and performs a process of detecting a touch state and coordinates from detection data acquired by the touch panel controller 3. For example, a digital filter operation is performed on the detected data, and the position coordinates of the intersection where the capacity variation has occurred are calculated based on the data from which noise has been removed. In short, a touch event occurred to indicate where the stray capacitance changed at the intersection, that is, where the finger approached (touched or touch event occurred) at the intersection. Calculate the position coordinates.

  The touch panel 1 is configured using a transmissive (translucent) electrode or a dielectric film, and is disposed, for example, on the display surface of the display panel 2. The touch panel 1 and the display panel 2 may have an in-cell configuration that is mounted integrally, or may have a cover glass integrated configuration in which the touch panel 1 and a cover glass installed on the upper surface are integrated.

  The host processor (HMPU) 6 generates display data, and the display panel controller 4 performs display control for displaying the display data received from the host processor 6 on the display panel 2. The host processor 6 obtains the position coordinate data when the contact event occurs from the sub-processor 5, and from the relationship between the position coordinate data on the display panel 2 and the display screen displayed on the display panel controller 4, Analyzes input by operating the touch panel 1.

  Although not particularly limited, the host processor 6 includes, for example, a communication control unit, an image processing unit, an audio processing unit, and other accelerators, which are not shown, and thus, for example, a portable terminal is configured.

  FIG. 2 is a perspective view showing a connection example of the display panel 2, the display driver IC 4 constituting the display panel controller, and the substrate 61 on which the host processor 6 is mounted. The substrate 61 on which the display panel 2 and the host processor 6 are mounted is connected by a film 7 on which a display driver IC 4 is mounted by COF. The film 7 is, for example, a polyimide film, and wiring is formed by copper (Cu) printed on the surface. A plurality of wiring layers and insulating layers may be stacked to be multilayered. Instead of the display driver IC 4, the IC 101 in which the touch panel controller 3 and the display panel controller 4 are integrated on one chip, or the IC 102 in which the sub processor 5 is integrated on one chip may be COF-mounted. A semiconductor chip such as the display driver IC 4 is flip-chip mounted after bumps (projection electrodes) such as gold (Au) are formed on pads as terminals, and a resin is underfilled and bonded.

  Although the display panel 2 is not particularly limited, for example, a gate line (scanning line) 25 formed in the horizontal direction and a source line (signal line) 24 formed in the vertical direction are wired on the glass substrate 23, and an intersection thereof. In the portion, a large number of display cells (not shown) are arranged in which a selection terminal is connected to a corresponding gate line (scanning line) and an input terminal is connected to a corresponding source line (signal line). A circuit (GIP: Gate In Panel) 26 for driving the gate line (scanning line) 25 is configured by a circuit using a thin film transistor formed on the glass substrate 23. The gate driver IC may be flip-chip mounted on the glass substrate 23. The display panel 2 may be configured using an organic EL (OLED: organic electroluminescence display) as a display element. In the case of OLED, it can be formed on a flexible substrate 23 such as a film instead of the glass substrate.

  For the wiring on the display panel 2 and the wiring of the substrate 61 on which the host processor 6 is mounted, the wiring of the film 7 on which the display driver IC 4 is mounted and the anisotropic conductive film (ACF: Anisotropic Conductive Film), for example, are used. Used to be electrically connected and mechanically bonded.

  FIG. 3 is a schematic diagram schematically showing a configuration example of the semiconductor device 21 in which the semiconductor chip is COF-mounted according to the present invention. The film 7 has a tape shape (or a reel shape indicating that the film 7 is wound on a reel), and feed holes 27 for conveyance are provided on both sides, and an effective area inside thereof is made of copper or the like. The formed wiring is printed. Wiring is drawn out from the region where the display driver IC 4 is mounted, a connection region 11 electrically connected to the display panel 2 is formed on the source terminal side, and a short-circuit wiring 8 and a test pad 9 are formed outside thereof. They are formed of the same or different wiring layers. The short-circuit wiring 8 and the test pad 9 will be described in detail later. Wiring is also drawn out to the input terminal side connected to the host processor 6, and a connection region 11 and a test pad 9 are formed. The inner part on which the display driver IC 4 is mounted is punched at the position of the cut line 10 and connected to the substrate 61 on which the display panel 2 and the host processor 6 are mounted.

  As described above, the number of source lines wired from the display driver IC 4 to the display panel 2 is 1080 even if RGB is multiplexed in full high vision, for example. For example, when the effective area of the COF is 60 mm, when the test pad 9 is arranged for each terminal, the pitch allowed per test pad is 55.6 μm. On the other hand, the test pad normally permitted by COF is at least 90 μm, for example, and 1080 test pads cannot be arranged in a row. For this reason, according to the prior art, as shown in Patent Document 3, the test pads are arranged in a plurality of rows in a direction sequentially away from the semiconductor chip.

  FIG. 4 is a more detailed schematic diagram showing a circuit configuration in the semiconductor chip 4 and an arrangement example of wirings and electrodes on the film 7 of the semiconductor device according to the present invention. The semiconductor chip 4 includes terminals (pads) S6n to S6n-5, an internal circuit 12 including internal circuit groups 13_0 to 13_5 connected to each of the terminals, and switches 15_0 to control electrical continuity and interruption between them. And a cut-off switch 14 including 15_5. In this specification, reference numerals 13_0 to 13_5 are used to indicate individual internal circuits, reference numerals 12 are used to indicate the entire internal circuit, reference numerals 15_0 to 15_5 are used to indicate individual switches, and reference numerals are used to indicate the entire cutoff switch. 14 is used. Each of the internal circuits 13_0 to 13_5 is a drive circuit that outputs a signal, an input circuit that receives a signal, or an input / output circuit that can input and output bidirectional signals. The terminals S6n to S6n-5 are pads formed by a metal wiring layer formed on a semiconductor substrate and having an insulating film on the surface opened. Although not particularly limited, the staggered arrangement is used to cope with the multi-pin and narrow pitch. Here, the staggered arrangement means that adjacent pads are arranged at a position far from the side of the chip, staggered or sequentially shifted, and since the bump formation area is larger than the wiring area, the adjacent bump formation area The pitch can be narrowed by shifting each other.

  On the film 7, wirings are formed outward from positions corresponding to the terminals S6n to S6n-5, and another substrate, for example, the substrate 61 on which the display panel 2 and the host processor are mounted is provided in the middle. Connection regions 11_0 to 11_5 are provided for connection to the. Further, short-circuit wirings 8_1 and 8_2 for short-circuiting wirings from a plurality of terminals are provided on the outer side, and test pads 9_1 and 9_2 are respectively wired. The connection regions 11_0 to 11_5 are arranged inside the cut line 10, and the short-circuit wirings 8_1 to 8_2 and the test pads 9_1 to 9_2 are arranged outside the cut line 10. The cut line 10 is a position for punching out the film 7 in order to cut a feed hole or the like from the COF before mounting, and does not indicate a physical structure.

  In the mounting test (S37) after the semiconductor chip 4 is mounted, the probe of the semiconductor tester is brought into contact with the test pads 9_1 and 9_2, and the electrical characteristics of the internal circuits 13_0 to 13_5 of the semiconductor chip 4 are measured. In order to measure the characteristics of the internal circuit 13_0, by turning on the switch 15_0 and turning off the switches 15_1 and 15_2, the internal circuit 13_0 and the test pad 9_1 are electrically connected via the terminal S6, and short-circuit wiring is performed. The internal circuits 13_1 and 13_2 are disconnected by electrically cutting off the other terminals S6n-1 and S6n-2 that are electrically connected to the test pad 9_1 by 8_1. In the next step, the switch 15_1 is turned on, the switches 15_0 and 15_2 are turned off to test the terminal S6n-1 and the internal circuit 13_1, and in the next step, the switch 15_2 is turned on and the switches 15_0 and 15_1 are turned off. The terminal S6n-2 and the internal circuit 13_2 are tested. Similarly, the terminals S6n-3 to S6n-5 and the internal circuits 13_3 to 13_5 that are short-circuited by the same short-circuit wiring 8_2 are tested in three steps using the switches 15_3 to 15_5. Three-step test of the terminals S6n to S6n-2 and the internal circuits 13_0 to 13_2 that are short-circuited by the short-circuit wiring 8_1, and the terminals S6n-3 to S6n-5 and the internal circuits 13_3 to 13_5 that are short-circuited by the short-circuit wiring 8_2 The three-step test is performed in parallel at the same time. Short-circuit wiring that provides a cutoff switch 14 so that all terminals arranged at a narrow pitch on one side of the semiconductor chip 4 can be cut off from the internal circuit 12 and short-circuits by a predetermined number k (k is a natural number). 8_1 to 8_m (for example, m is a natural number corresponding to the number of terminals ÷ k) and test pads 9_1 to 9_m connected thereto are provided, and the test is performed in k steps in parallel, thereby reducing the number of terminals 1 / The test after COF mounting of all the terminals can be performed only by providing k test pads 9_1 to 9_m. The short-circuit wirings 8_1 and 8_2 and the test pads 9_1 and 9_2 are disconnected at the position of the cut line 10 before the COF is mounted.

  FIG. 4 shows an example in which the short-circuit wirings 8_1 and 8_2 are provided so as to short-circuit three terminals adjacent to each other, but there is no particular limitation on the arrangement of the terminals to be short-circuited.

<Manufacturing method>
FIG. 5 is a flowchart showing an example of the method for manufacturing the semiconductor device 21 of the present invention, and FIGS. 6 to 9 are explanatory views showing cross sections of the semiconductor device in each step.

  The semiconductor chip 4 such as a display driver IC is manufactured by the semiconductor wafer manufacturing step S31. The semiconductor wafer manufacturing step S31 is, for example, a known complementary metal-oxide-semiconductor field effect transistor (CMOS) semiconductor manufacturing technique, and the semiconductor chip 4 is formed on a single semiconductor substrate (wafer) such as silicon. The

  The probe test S32 is performed in the completed wafer state. FIG. 6 is an explanatory diagram showing a cross section of the semiconductor device in the probe test S32. A probe 91 is brought into contact with a terminal (pad) 72 formed on the surface of the semiconductor chip 4 in a wafer state, and electrical characteristics are tested by a semiconductor tester.

  Next, it is separated into pieces by dicing S33. At this time, the defective product found in the probe test S32 is eliminated, and only the semiconductor chip 4 determined to be non-defective is sent to the chip mounting step S34. FIG. 7 is an explanatory view showing a cross section of the semiconductor device 21 in the chip mounting step S34. Bumps (projection electrodes) 71 such as gold (Au) are formed on terminals (pads) (not shown) of the semiconductor chip 4 and bonded to the wirings 20 on the film 7 as a substrate (S35). Thereafter, an epoxy resin or the like is underfilled (S36), and the electrical connection between the semiconductor chip 4 and the wiring 20 on the film 7 and the mechanical adhesion are completed.

  Next, a mounting test (S37) is performed. FIG. 8 is an explanatory diagram showing a cross section of the semiconductor device 21 in the test (mounting test) S37 in the COF mounting state. Terminals (pads) of the semiconductor chip 4 are connected to the wiring 20 through bumps 71, and the connection region 11, the short-circuit wiring 8, and the test pad 9 are formed by the wiring 20. As described above, the connection region 11 is formed inside the cut line 10, and the short-circuit wiring 8 and the test pad 9 are formed outside the cut line 10. The probe 92 is brought into contact with the test pad 9, and the electrical characteristics are tested by a semiconductor tester. Here, although not shown in the figure, each terminal on the input side of the semiconductor chip 4 is provided with a corresponding test pad, and is connected to the semiconductor tester by a probe 92. A test command and an input pattern are input from the input side of the semiconductor chip 4, and the electrical characteristics of each terminal on the input side and the source electrode side of the semiconductor chip 4 are measured.

  The COF determined to be non-defective in the mounting test S37 is disconnected from the outside of the cut line 10 in the punching process (S38) and connected to another substrate such as the substrate 61 on which the display panel 2 and the host processor 6 are mounted. FIG. 9 is an explanatory view showing a cross section after the substrate mounting step (S39). For example, the wiring 20 on the COF is connected in the connection region 11 to the wiring 22 on the glass substrate 23 of the display panel 2 using an anisotropic conductive film (ACF) 73 or the like.

  Only chips that are determined to be non-defective in the probe test S32 are supplied to the mounting test S37. In the mounting test S37, however, an initial failure that has turned into a defect in the subsequent dicing S33 and the chip mounting step S34, or a semiconductor chip. 4 and the wiring 20 on the film 7, and the disconnection or short circuit of the wiring 20 on the film 7 can be detected.

[Embodiment 2]
An embodiment in which the present invention is applied to a display driver IC 4 of a liquid crystal display (LCD) panel will be described in more detail.

  FIG. 10 is a block diagram illustrating a detailed configuration example of the display driver IC 4. The display driver IC 4 includes a system interface 40 and an external display interface 41, receives display data and control commands supplied from the host processor 6, and includes a scan electrode driver 59 to display the gate line (scanning) of the display panel 2. A control signal for driving the line), and a signal for driving the source line (signal line) of the display panel 2 provided with the source amplifier circuit 12. The display driver IC 4 includes a command register 17, a parameter register 18, and a nonvolatile memory 54. Based on the control command supplied from the host processor 6, the values of the command register 17 and the parameter register 18 are set. Some parameters stored in the parameter register 18 are stored in the nonvolatile memory 54 provided inside, and are read out to the parameter register 18 when the power supply is resumed next after the power supply is once cut off. And reused.

  The external display interface 41 is an interface conforming to MIPI-DSI (Mobile Industry Processor Interface Display Serial Interface), which is one of standard communication interfaces of display devices, for example, and is adapted to display data, vertical synchronization signal Vsync, and horizontal synchronization. The signal Hsync is supplied from the host processor 6 at high speed. The received display data is input to the data compression circuit 43 via the write data latch 42, and after being subjected to data compression, it is written to the frame memory 44. The frame memory 44 is configured by an SRAM (Static Random Access Memory), and a write address and a read address are supplied from an address counter 55. The display data read from the frame memory 44 is input to the data expansion circuit 46 via the latch circuit 45, and the result of the data expansion is sent to the backlight control circuit 56. The display data is input from the data development circuit 46 to the source amplifier circuit 12 via the two-stage latch circuits 47_1 and 47_2. The latch circuit 47_1 is a latch circuit controlled by the backlight control circuit 56, and the latter latch circuit 47_2 is a line latch circuit that holds data for one line in parallel. When the source amplifier circuit 12 receives data for one line, it converts it into a source line drive signal having an analog signal level corresponding to it and outputs it. The gradation voltage generation circuit 58 supplies the multi-gradation analog signal level appropriately corrected by the gamma correction circuit 57 to the source amplifier circuit 12. The source amplifier circuit 12 selects one analog signal level from the multi-gradation analog signal levels supplied from the gradation voltage generation circuit 58 based on the display data supplied as digital values from the latch circuit 47_2, or One analog signal level is generated from analog signal levels of a plurality of gradations, and is output to source output terminals such as S6n to S6n-5 through the source output terminal switching circuit 14. The source output terminal switching circuit 14 is controlled by the decoder 19 and performs switching for the test in the probe test and the mounting test as well as the switching for performing the dot inversion driving. The configuration and operation will be described in detail later.

  Synchronization signals such as a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync input to the external display interface 41 are input to the timing control circuit 48. The internal clock generated by the clock generation circuit 51 is input to the timing control circuit 48. The logic circuit built in the display driver IC 4 including the timing control circuit 48 operates in synchronization with the internal clock. The timing control circuit 48 outputs control signals VOUT and HOUT for synchronously controlling the touch panel controller 3, and supplies various timing control signals to the internal frame memory 44, the data expansion circuit 46, and the like. The display driver IC 4 includes the internal reference voltage generation circuit 52, thereby operating the internal logic power supply regulator 53 to supply stable power to the built-in logic circuit. The liquid crystal drive level generation circuit 49 includes a power boosting circuit and a stabilized power supply circuit, and generates and supplies various levels of power in the display driver IC 4. For example, a power source, a clock, and other signal levels supplied to the gate-in-panel circuit that drives the gate electrode are generated and supplied to the scan electrode driver 59.

  FIG. 11 is a more detailed schematic diagram showing a circuit configuration in the IC of the display driver IC 4 mounted with COF, and an arrangement example of wirings and electrodes on the film 7. The display driver IC 4 includes a source amplifier circuit 12, which is an internal circuit 12, a source output terminal switching circuit 14, a protection element 16 provided for each terminal (pad), and six source output terminals S6n to S6n-5. Is shown. The display driver IC 4 has 1080 source output terminals S0 to S1079 as a whole, for example, assuming that RGB is multiplexed in full high-definition, but this can be configured as shown in FIG. That is, n is an integer of n = 0 to 180. As the protection element 16, diodes in opposite directions are provided at the source output terminals S6n to S6n-5 toward the high potential side power supply SVDD and the low potential side power supply SVSS, respectively.

  The source amplifier circuit 12 that is an internal circuit includes six elements AN3, AP3, AN2, AP2, AN1, and AP1 corresponding to the source output terminals S6n to S6n-5. Among these, three of AP3, AP2, and AP1 are positive side source amplifiers that output a signal on the positive side higher than the common voltage (Vcom), and the other three of AN3, AN2, and AN1 are from the common voltage (Vcom). A negative-side source amplifier that outputs a low negative-side signal, and is alternately arranged with respect to the source output terminals S6n to S6n-5 adjacent to each other.

  The source output terminal switching circuit 14 connects the outputs of a pair of source amplifiers AN3 and AP3 on the negative electrode side and the positive electrode side straight to terminals S6n and S6n-1, or crosses them to terminals S6n-1 and S6n, respectively. It includes four switches AN3EV, AN3OD, AP3EV, and AP3OD that function as a so-called straight / cross changeover switch that can be switched for connection. Four other switches AN2EV, AN2OD, AP2EV, AP2OD and four switches AN1EV, AN1OD, AP1EV, AP1OD are also provided in the other two sets of source amplifiers AN2 and AP2 and source amplifiers AN1 and AP1, respectively. It has been. The source output terminal switching circuit 14 can further short-circuit adjacent terminals S6n and S6n-1, and terminals S6n-1 and S6n-2, respectively, and short-circuit switches PIN1-2 and PIN0-2, and adjacent terminal S6n. -3 and S6n-4 and terminals S6n-4 and S6n-5 are provided with short-circuit switches PIN1-1 and PIN0-1. The operation of the short-circuit switches PIN1-1 and PIN2 and PIN0-1 and PIN2 will be described later.

  On the film 7, wirings connected to the source output terminals S6n to S6n-5 and drawn to connection regions 11_0 to 11_5 with the wirings of the display panel 2 are arranged. Further, outside the cut line 10, a short-circuit wiring 8_1 that short-circuits the terminals S6n, S6n-2, and S6n-4, a short-circuit wiring 8_2 that short-circuits the terminals S6n-1, S6n-3, and S6n-5, and a short-circuit wiring Test pads 9_1 and 9_2 connected to 8_1 and 8_2, respectively, are arranged.

  A test circuit for controlling the source output terminal switching circuit 14 will be described. FIG. 12 is a logic block diagram showing the configuration of the test circuit. A command register 17, a parameter register 18, and a decoder 19, which generate control signals for controlling each switch of the source output terminal switching circuit 14. The parameter register 18 holds a switch control signal T_SDEC_0 / 1B and is simultaneously supplied to the decoder 19 together with a control mode signal MODEEEP / EN for dot inversion driving generated by internal logic. FIG. 14 shows a truth table of the decoder 19, and FIG. 12 shows an example of a logic circuit for realizing the logic of the truth table.

  The operation of the display driver IC 4 will be described.

  During normal operation, dot inversion driving is performed in which the source amplifiers on the positive and negative sides alternately drive the source terminals. That is, the negative side source amplifiers AN3, AN2, and AN1 drive the even-numbered source output terminals S6n, S6n-2, and S6n-4, and the positive side source amplifiers AP3, AP2, and AP1 are the odd-numbered source output terminals S6n-1. S6n-3 and S6n-5 are driven, and at the next scanning timing of the same line, on the contrary, the negative side source amplifiers AN3, AN2 and AN1 are odd-numbered source output terminals S6n-1, S6n-3 and S6n. -5 is driven, and the positive side source amplifiers AP3, AP2, and AP1 drive even-numbered source output terminals S6n, S6n-2, and S6n-4. In the truth table shown in FIG. 14, when “normal” state (T_SDEC [1: 0] = 00b), MODEP = 1, and MODEEN = 0, the negative side source amplifier sets the odd-numbered source output terminal to the positive side. The source output terminal switching circuit 14 is controlled so that the source amplifier drives the even-numbered source output terminals. In the “normal” state (T_SDEC [1: 0] = 00b), when MODEEP = 0 and MODEEN = 1, the negative-side source amplifier has an even-numbered source output terminal and the positive-side source amplifier has an odd-numbered source. The source output terminal switching circuit 14 is controlled so as to drive the output terminals. Here, T_SDEC [1: 0] is a signal representing a 2-bit digital value, and the above-mentioned “00b” represents binary 2-bit 00. In the present specification, the same applies hereinafter. As described above, the dot inversion driving described above can be performed by switching the value of MODEEEP / EN set in the command register 17.

  Next, the probe test 32 will be described. As described with reference to FIG. 5 in the first embodiment, the probe test 32 is a test performed by bringing the probe 91 into contact with the source output terminals S6n to S6n-5 of the display driver IC4 in the wafer state. In the display driver IC4, the source output terminals have a very large number of pins and a narrow pitch, and the number of terminals that can be measured simultaneously by the semiconductor tester is limited. It is not realistic physically or economically. Therefore, in this embodiment, the probe is brought into contact with only one terminal with respect to the three terminals, and an internal circuit connected to the three terminals is tested.

  By using the truth table shown in FIG. 14, it is possible to control the source output terminal switching circuit 14 for the probe test 32 performed by bringing the probe into contact with only the terminals S6n-2 and S6n-5.

  When MODEP = 1 and MODEEN = 0 in the “TEST” state, T_SDEC [1: 0] = 01b is set so that only AN1OD and AP2EV are ON and the other switches are OFF, and the source is connected to the terminal S6n-5. The output of the amplifier AN1 can be measured, and the output of the source amplifier AP2 can be measured at the terminal S6n-2. By setting T_SDEC [1: 0] = 10b, only AP1EV and PIN0-1, AN3OD and PIN0-2 are controlled to be ON, and the other switches are controlled to be OFF, and the output of the source amplifier AP1 is measured at the terminal S6n-5. The output of the source amplifier AN3 can be measured at the terminal S6n-2. By setting T_SDEC [1: 0] = 11b, only AN2OD, PIN0-1, PIN1-1, AP3EV, PIN0-2, and PIN1-2 are controlled to be ON, and other switches are controlled to be OFF, and terminal S6n-5 The output of the source amplifier AN2 can be measured, and the output of the source amplifier AP3 can be measured at the terminal S6n-2.

  When MODEEP = 0 and MODEEN = 1 in the “gradation test” state, by setting T_SDEC [1: 0] = 01b, only AP1OD, AN1EV, AP2OD, AN2EV, AP3OD and AN3EV are ON, and other switches are The output of the source amplifier AP1 can be measured at the terminal S6n-5, and the output of the source amplifier AN2 can be measured at the terminal S6n-2. The outputs of the other source amplifiers AN2, AP2, AP3, AN3 are also output to the terminals S6n-4, S6n-3, S6n-1, and S6n, respectively, but cannot be measured because the probe is not in contact. By setting T_SDEC [1: 0] = 10b, only AN1EV and PIN0-1, AN3OD and PIN0-2, and AP2OD and AP3EV are controlled to be ON, and the other switches are controlled to be OFF, and the source amplifier is connected to terminal S6n-5 The output of AN1 can be measured, and the output of the source amplifier AN3 can be measured at the terminal S6n-2. Since AP2OD and AP3EV are controlled to be ON, the outputs of the source amplifiers AP2 and AP3 are output to the terminals S6n-3 and S6n, respectively, but cannot be measured because the probe is not in contact. By setting T_SDEC [1: 0] = 11b, only AN2OD, PIN0-1, PIN1-1, AP3EV, PIN0-2, and PIN1-2 are controlled to be ON, and other switches are controlled to be OFF, and terminal S6n-5 The output of the source amplifier AP2 can be measured, and the output of the source amplifier AP3 can be measured at the terminal S6n-2.

  As described above, in the probe test S32, for the six terminals S6n to S6n-5, the probe is brought into contact with only the two terminals S6n-5 and S6n-2, thereby corresponding six source amplifiers AP1, The electrical characteristics of the outputs of all of AN1, AP2, AN2, AP3 and AN3 can be measured.

  Next, the mounting test S37 will be described. The mounting test S37 is a test performed by bringing the probe 92 into contact with the test pad 9 in a state where the display driver IC 4 is COF mounted as described with reference to FIG. 5 in the first embodiment.

  FIG. 13 is an explanatory diagram of a truth table showing the operation of the test circuit in the test (mounting test) S37 in the COF mounted state. The decoder 19 performs the same operation as in the case of the probe test S32. However, MODEEEP = 1 and MODEEN = 0, and PIN0-1 and PIN0-2, PIN1-1 and PIN1-2 are always OFF. By setting T_SDEC [1: 0] = 01b, only AN1OD and AP2EV are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AN1 can be measured at the test pad 9_2 via the terminal S6n-5. The output of the source amplifier AP2 can be measured with the test pad 9_1 through the terminal S6n-2. By setting T_SDEC [1: 0] = 10b, only AP1EV and AN3OD are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AP1 can be measured with the test pad 9_1 via the terminal S6n-4. The output of the source amplifier AN3 can be measured with the test pad 9_2 via the terminal S6n-1. By setting T_SDEC [1: 0] = 11b, only AN2OD and AP3EV are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AN2 can be measured with the test pad 9_2 via the terminal S6n-3. The output of the source amplifier AP3 can be measured with the test pad 9_1 through the terminal S6n.

  In the mounting test S37 of this embodiment, a short test and an open test of each terminal can also be performed. Since adjacent terminals are connected to different short-circuit wirings, MODEP = 0 and MODEEN = 0 are set to HiZ state in which all terminals are disconnected from the internal circuit, and different potentials are applied to the test pads 9_1 and 9_2 to be adjacent. Measure current flowing between terminals and between adjacent wires. When MODEEP = 0 and MODEEN = 0, as shown in the truth table shown in FIG. 14, switches AP1OD / EV, AN1OD / EV, AP2OD / EV, AN2OD / EV, AP3OD / EV, AN3OD / EV, and PIN0-1 / 2 and PIN 1-1 / 2 are all controlled to be OFF, and each terminal is disconnected from the internal source amplifier. Since each terminal is in a HiZ state in which the internal circuit is disconnected, no current flows between the test pads 9_1 and 9_2 unless there is a short circuit between adjacent terminals or wirings. In this way, a short test can be performed. Similarly, the open test is performed in a HiZ state in which each terminal is disconnected from the internal circuit. A potential higher than the high-potential power supply SVDD by the forward voltage of the protection diode is applied to each terminal, the current flowing toward SVDD is measured, and the forward voltage of the protection diode is applied to each terminal from the low-potential power supply SVSS. A potential lower than that is applied, and the current flowing from the SVSS toward the terminal is measured. If there is no open terminal, the current is the current value of three protection diodes. In this way, the open / short test of each terminal can be performed together. In the present embodiment, the description of the open / short test is described in the latter half, but the actual implementation test S37 is performed first. This is because the open / short test is completed in a relatively short time, so that defective products can be excluded from the test target at an early stage, and the entire test time can be shortened.

[Embodiment 3]
In the method for forming a short-circuit wiring shown in the second embodiment, since the adjacent wirings are connected to different short-circuit wirings, the open / short test can be performed on each terminal as described above. This wiring requires at least two layers.

  FIG. 15 shows a configuration of the semiconductor device 21 according to the third embodiment, and is a more detailed schematic diagram showing a circuit configuration in the IC of the display driver IC 4 mounted with COF, and an arrangement example of wirings and electrodes on the film 7. FIG. The display driver IC 4 has the same configuration as the display driver IC 4 of the second embodiment shown in FIG. The adjacent terminals S6n, S6n-1, and S6n-2 are short-circuited by the same short-circuited wiring 8_3 and connected to the test pad 9_1, and the adjacent terminals S6n-3, S6n-4, and S6n-4 are the same short-circuited wiring Shorted by 8_4 and connected to the test pad 9_2. Since the wiring for realizing this circuit configuration on the film 7 does not cross each other, it can be realized by a single wiring layer.

  The test in the COF mounting state can be performed in the same manner as in the second embodiment. MODEEEP = 1 and MODEEN = 0, and PIN0-1 and PIN0-2 and PIN1-1 and PIN1-2 are always OFF. By setting T_SDEC [1: 0] = 01b, only AN1OD and AP2EV are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AN1 can be measured at the test pad 9_2 via the terminal S6n-5. The output of the source amplifier AP2 can be measured with the test pad 9_1 through the terminal S6n-2. By setting T_SDEC [1: 0] = 10b, only AP1EV and AN3OD are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AP1 can be measured with the test pad 9_2 via the terminal S6n-4. The output of the source amplifier AN3 can be measured with the test pad 9_1 through the terminal S6n-1. By setting T_SDEC [1: 0] = 11b, only AN2OD and AP3EV are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AN2 can be measured with the test pad 9_2 via the terminal S6n-3. The output of the source amplifier AP3 can be measured with the test pad 9_1 through the terminal S6n. Further, the open test can be performed similarly to the second embodiment.

[Embodiment 4]
FIG. 16 is a configuration of the semiconductor device 21 according to the fourth embodiment, and is a more detailed schematic diagram illustrating a circuit configuration in the IC of the display driver IC 4 mounted with COF, and an arrangement example of wirings and electrodes on the film 7. FIG. The display driver IC 4 has the same configuration as the display driver IC 4 of the second embodiment shown in FIG. Of the adjacent terminals S6n, S6n-1, and S6n-2, S6n and S6n-2 at both ends are short-circuited by the same short-circuit wiring 8_5 and connected to the test pad 9_1, and adjacent terminals S6n-3 and S6n- 4 and S6n-4, S6n-3 and S6n-5 at both ends are short-circuited by the same short-circuit wiring 8_6 and connected to the test pad 9_2. Since the wiring for realizing this circuit configuration on the film 7 does not cross each other as in the case of the third embodiment shown in FIG. 15, it can be realized by a single wiring layer.

  By setting MODEE = 1 and MODEEN = 0, and controlling the short-circuit switches PIN0-1 and PIN0-2 and PIN1-1 and PIN1-2 as appropriate, the test in the COF mounted state is the same as in the second embodiment. Can be implemented. By setting T_SDEC [1: 0] = 01b, only AN1OD and AP2EV are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AN1 can be measured at the test pad 9_2 via the terminal S6n-5. The output of the source amplifier AP2 can be measured with the test pad 9_1 through the terminal S6n-2. By setting T_SDEC [1: 0] = 10b, only AP1EV and AN3OD and PIN0-1 and PIN0-2 are controlled to be ON, and the other switches are controlled to be OFF, and the source amplifier is connected to the test pad 9_2 via the terminal S6n-5. The output of AP1 can be measured, and the output of the source amplifier AN3 can be measured with the test pad 9_1 via the terminal S6n-2. By setting T_SDEC [1: 0] = 11b, only AN2OD and AP3EV are controlled to be ON, and other switches are controlled to be OFF, and the output of the source amplifier AN2 can be measured with the test pad 9_2 via the terminal S6n-3. The output of the source amplifier AP3 can be measured with the test pad 9_1 through the terminal S6n.

  For the terminals S6n, S6n-2, S6n-3, and S6n-5, an open test can be performed in the same manner as in the second embodiment, but for the terminals S6n-1 and S6n-4, an open test is performed. I can't. On the other hand, a simple short test using an internal circuit can be performed. The source output terminal switching circuit 14 is controlled to make a straight connection, and the short-circuit switches PIN0-1 and PIN0-2 and PIN1-1 and PIN1-2 are all turned OFF. Positive voltages are output from the positive-side source amplifiers AP1, AP2, AP3 to the odd-numbered source output terminals S6n-5, S6n-3, S6n-1, and the negative-side source amplifiers AN1, AN2, AN3 output even-numbered source outputs. Negative voltages are output to the terminals S6n-4, S6n-2, and S6n. At this time, a simple short test can be performed by measuring the current values of the currents flowing through all the source amplifiers including the positive side source amplifiers AP1, AP2, AP3 and the negative side source amplifiers AN1, AN2, AN3. In the short-circuit wiring described above, since the outputs of the positive-side or negative-side source amplifiers that output the same voltage are short-circuited, no current flows through the short-circuit wirings 8_5 and 8_6. Since the terminals S6n-1 and S6n-4 that are not connected to the short-circuit lines 8_5 and 8_6 are not connected to the short-circuit line, no current flows through these terminals. That is, as long as there is no short circuit due to a failure between adjacent terminals and wiring, the current value of the current flowing through all the source amplifiers is only the current flowing inside the display driver IC 4. Therefore, if the current value is within the allowable value calculated based on the design value, it can be determined that there is no short circuit due to the failure. As described above, according to the fourth embodiment, it is possible to determine the presence or absence of a short-circuit failure between adjacent terminals and wires by a simple short test using an internal circuit instead of a short test in which a voltage is applied from the outside. .

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the case where the display driver IC is mainly connected to the liquid crystal display panel has been described, but the display driver IC can be changed to a display driver IC for driving the OLED. Further, in the detailed configuration example of the display driver IC shown in FIG. 10, the configuration example in the case of including the frame memory 44 and further including the backlight control is shown. It is possible to appropriately change to a highly functional configuration including other functions.

1 Touch panel (TP)
2 Display panel (DP)
3 Touch panel controller (TPC)
4 Display panel controller (DPC)
5 Subprocessor (SMPU)
6 Host processor (HMPU)
7 Film 8 Short-circuit wiring 9 Test pad 10 Cut line 11 Connection area 12, 13 Internal circuit (source amplifier circuit)
14, 15 Cutoff switch 16 Protection element 17 Command register 18 Parameter register 19 Decoder 20 Wiring on film 21 Semiconductor device (COF on which semiconductor chip is mounted)
22 Wiring of display panel 2 23 Substrate of display panel 2 24 Source line (signal line)
25 Gate line (scanning line)
26 Gate drive circuit (GIP)
27 Feeding hole S30 Semiconductor device (COF-mounted semiconductor chip) manufacturing process S31 Semiconductor wafer manufacturing process S32 Probe test process S33 Dicing process S34 Chip mounting process S35 Bonding process S36 Underfill process S37 Mounting test process S38 Punching process S39 Substrate mounting Process 40 System interface 41 External display interface 42, 45, 47 Latch circuit 43 Data compression circuit 44 Frame memory 46 Data expansion circuit 48 Timing control circuit 49 Liquid crystal drive level generation circuit 50 Periodic signal output circuit 51 Clock generation circuit 52 Internal reference voltage generation Circuit 53 Internal logic power supply regulator 54 Non-volatile memory 55 Address counter 56 Backlight control circuit 57 γ correction circuit 58 Grayscale voltage generation Substrate 71 bumps circuit 59 scan electrode driver 61 host processor (HMPU) is mounted (protruding electrodes)
72 terminals (pads)
73 Anisotropic Conductive Film (ACF)
91, 92 Probe 100 Display and input device (electronic equipment)
101, 102 Semiconductor device (IC, multichip module)

Claims (13)

A semiconductor device comprising a film, a wiring formed by a conductor printed on the film, and a semiconductor chip having a plurality of terminals electrically connected to the wiring and mounted on the film,
On the film, outside the region where the semiconductor chip is mounted, a connection region for the wiring to be electrically connected to another substrate,
On the film, on the outer side of the connection region and in a region separable from the connection region, a short-circuit wiring that electrically short-circuits a predetermined number of the plurality of terminals, and the short-circuit wiring A test pad that is electrically connected and provided for at least one short-circuit wiring;
The semiconductor chip has a cut-off switch that can cut off an electrical connection between each of the predetermined number of terminals and an internal circuit of the semiconductor chip.
Semiconductor device. In Claim 1, wiring adjacent to each other among the wiring from the plurality of terminals to the corresponding connection region is connected to different short-circuit wirings.
Semiconductor device. In claim 1, the predetermined number of terminals connected to the same short-circuit wiring, the wiring from the terminal to the corresponding connection region are adjacent to each other,
Semiconductor device. In claim 1, among the three terminals adjacent to each other to the connection region, the terminals at both ends are connected to the same short-circuit wiring, and the other one terminal is opened.
Semiconductor device. 5. The semiconductor chip according to claim 4, further comprising a short-circuit switch capable of electrically short-circuiting the three terminals inside each other.
Semiconductor device. The semiconductor chip according to any one of claims 1 to 5, wherein the semiconductor chip is a display driver IC.
The plurality of terminals are source output terminals that drive a source electrode of a display panel to be connected,
The semiconductor chip includes a plurality of positive-side source amplifiers and a plurality of negative-side source amplifiers as internal circuits, and a plurality of first, second, third, and fourth switches that can operate as the cutoff switches.
The two adjacent source output terminals are connected to one positive side source amplifier via the first and second switches, respectively, and one negative side source via the third and fourth switches, respectively. Connected to the amplifier,
Semiconductor device. A film, a plurality of wirings and a plurality of test pads by a conductor printed on the film, and a semiconductor chip having a plurality of terminals electrically connected to the plurality of wirings and mounted on the film A method for manufacturing a semiconductor device comprising:
A chip mounting process for mounting the semiconductor chip on the film; and a mounting test for measuring electrical characteristics of terminals of the semiconductor chip by bringing a probe into contact with at least one of the test pads. Including
The chip mounting step includes a step of electrically connecting the plurality of wirings to each of the plurality of terminals,
The film has a connection region for the wiring to be physically and electrically connected to another wiring outside the region where the semiconductor chip is mounted, and further outside the connection region, In the region separable from the connection region, a short-circuit wiring for electrically short-circuiting a predetermined number of the plurality of terminals is provided, and at least one test pad is electrically connected to the one short-circuit wiring. Connected,
The semiconductor chip includes a cutoff switch capable of electrically disconnecting a plurality of terminals short-circuited to each other by the short-circuit wiring from an internal circuit individually,
In the mounting test, terminals other than one of the plurality of terminals short-circuited by the short-circuit wiring are electrically disconnected from the corresponding internal circuit by the cutoff switch, and the terminals and the terminals are connected to each other. Electrically connecting a corresponding internal circuit and measuring an electrical characteristic of the internal circuit through a corresponding test pad,
A method for manufacturing a semiconductor device. In Claim 7, the semiconductor chip has a protection diode for each terminal, wiring adjacent to each other among the wiring from the plurality of terminals to the corresponding connection region is connected to different short-circuit wiring,
In the mounting test, terminals other than one of the plurality of terminals that are short-circuited to each other by the short-circuit wiring are electrically disconnected from the corresponding internal circuit by the cutoff switch and connected to the terminals. An open test for measuring the forward characteristics of the protection diode through a corresponding test pad, and a terminal where wirings from the plurality of terminals to the corresponding connection region are adjacent to each other are electrically connected from the corresponding internal circuit by the cutoff switch. And a short test that measures the presence or absence of current between terminals by applying different potentials to each other,
A method for manufacturing a semiconductor device. In claim 7, the predetermined number of terminals connected to the same short-circuit wiring, the wiring from the terminal to the corresponding connection region are adjacent to each other,
A method for manufacturing a semiconductor device. In claim 7, among the three terminals adjacent to each other to the connection region, the terminals at both ends are connected to the same short-circuit wiring, and the other one terminal is opened.
A method for manufacturing a semiconductor device. 11. The mounting test according to claim 10, wherein the mounting test is performed by applying different potentials from the corresponding internal circuits to the terminals at both ends and the terminals sandwiched between the adjacent three terminals, and supplying power to the internal circuits. Including a simple short test to measure the current consumption of the power supply circuit
A method for manufacturing a semiconductor device. The probe test according to claim 7, further comprising a probe test for inspecting the semiconductor chip in a wafer state before the chip mounting step.
The semiconductor chip further includes a short-circuit switch capable of electrically short-circuiting the predetermined number of terminals inside each other,
In the probe test, the contact of the probe with other terminals excluding one terminal of the predetermined number of terminals is omitted.
A method for manufacturing a semiconductor device. The semiconductor chip according to any one of claims 7 to 12, wherein the semiconductor chip is a display driver IC.
The plurality of terminals are source output terminals that drive a source electrode of a display panel to be connected,
The semiconductor chip includes a plurality of positive-side source amplifiers and a plurality of negative-side source amplifiers as internal circuits, and a plurality of first, second, third, and fourth switches that can operate as the cutoff switches.
The two adjacent source output terminals are connected to one positive side source amplifier via the first and second switches, respectively, and one negative side source via the third and fourth switches, respectively. Connected to the amplifier,
A method for manufacturing a semiconductor device.

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