JP2015169600A - Radio wave timepiece - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make adjustments of a desired frequency without halting an oscillation circuit upon reception of a radio wave timepiece and non-reception thereof.SOLUTION: A radio wave timepiece includes: an oscillation circuit 2; a frequency adjustment circuit 3 that is connected to the oscillation circuit 2; a first constant voltage generation circuit 4; a second constant voltage generation circuit 5; and a voltage switch circuit 6 that mutually different two voltages generated from the first constant voltage generation circuit 4 and the second constant voltage generation circuit 5. When changing a load capacity value of the oscillation circuit 2 upon reception of the radio wave timepiece, a voltage to be applied to the oscillation circuit is switched to a greater voltage, which in turn improves a characteristic of the oscillation circuit 2.

Description

  The present invention relates to a radio timepiece. In particular, the present invention relates to a radio timepiece having a heterodyne receiving circuit.

  Conventionally, a radio timepiece that receives a standard radio wave including time information and corrects the time using the acquired standard time information is known.

  The radio clock receives the standard radio wave transmitted from the radio transmitting station by the antenna built in the clock, then amplifies the received signal by the receiving IC, converts the received signal from analog to digital, and converts the digital data This time code is transmitted to the microcomputer, the time information is analyzed by the microcomputer, the timepiece motor is driven based on the time information, and the time is corrected.

One of the receiving circuit configurations of a radio timepiece is a heterodyne system.
The standard radio wave has a plurality of carrier frequencies. For example, JJY used in Japan is operated at 40 kHz and 60 kHz.
In that case, a receiving circuit is usually required for each carrier frequency. However, since the heterodyne system converts different carrier frequencies into one intermediate frequency, the time signal can be extracted by one receiving circuit.
However, since the heterodyne method requires a high-precision oscillation circuit for the local oscillator, there are problems of high cost, increased power consumption, and increased circuit scale.
In Patent Document 1, even when the signal from the clock oscillation circuit is shared with the reference frequency of the local oscillation circuit of the heterodyne receiver and the clock signal of the clock, sensitivity deterioration can be minimized and the frequency adjustment circuit can be simplified. Thus, there is disclosed a radio timepiece having a small circuit scale with a reduced cost by reducing the number of frequency adjustment operations.

WO2011 / 118820 (FIG. 1)

In Patent Document 1, in order to suppress sensitivity deterioration, the oscillation frequency is adjusted by changing the load capacity of the oscillation circuit to suppress the frequency deviation of the local oscillation circuit. However, the load capacity of the oscillation circuit is large. When switching to, there is a problem that the noise resistance, the output signal distortion due to the change of the DC bias, and the signal transmission performance due to the change of the bias occur, the frequency stability is lowered, and the oscillation is stopped. Moreover, the above problem becomes significant when the surrounding environment is at a high temperature.

  An object of the present invention is to perform a desired frequency adjustment at the time of receiving a standard radio wave without stopping the oscillation circuit due to the above problem when the load capacity of the oscillation circuit is changed during reception and non-reception of the radio timepiece. And

In order to solve the above problems, the present invention provides:
A clock oscillation circuit as a reference signal source in timekeeping,
A heterodyne receiving circuit for receiving external radio waves;
A PLL circuit for creating a local oscillation frequency used in the heterodyne receiver circuit,
A radio timepiece in which the clock oscillation circuit also serves as a reference frequency generation means for generating a reference frequency of the PLL circuit;
A control means for changing an oscillation condition of the timepiece oscillation circuit;
In the radio timepiece that changes the oscillation condition of the timepiece oscillation circuit so that the oscillation frequency of the timepiece oscillation circuit differs between when the external radio wave is received and when it is not received,
The control means is characterized in that the driving capability of the timepiece oscillation circuit at the time of receiving the external radio wave is increased as compared with the time of non-reception.

According to the present invention, the characteristics of the oscillator itself can be improved by increasing the driving capability of the oscillation circuit at the time of radio wave reception as compared to when not receiving, more specifically, by increasing the voltage applied to the oscillator at the time of radio wave reception. Even if the load capacity connected to the oscillator increases to adjust the frequency when receiving radio waves, and the oscillator can no longer satisfy the oscillation conditions, the oscillation does not stop or stop. In addition, since oscillation startability is improved even when oscillation is difficult due to temperature changes in the surrounding environment, it is possible to adjust the oscillation frequency while maintaining normal oscillation.
In addition, by increasing the voltage applied to the switch that controls the value of the load capacitance connected to the oscillator when receiving radio waves, the impedance of the switch itself decreases, making it easier to switch, and the oscillation frequency with the desired set capacitance added Can be obtained immediately.

In addition, the variable width of the adjustable frequency can be increased by increasing the voltage applied to the oscillator during radio wave reception.
This makes it possible to expand the delivery standards for crystal units, and can be expected to reduce the cost of crystal unit delivery.

It is a block diagram in a 1st embodiment of the present invention. FIG. 3 is a detailed diagram of a peripheral portion of the oscillation circuit in the first embodiment of the present invention. 1 is a voltage switching circuit according to a first embodiment of the present invention. It is a timing chart of each output at the time of a normal state and electric wave reception in a 1st embodiment of the present invention. 4 is a flowchart from the start of radio wave reception to the end of radio wave reception according to the first embodiment of the present invention. It is a frequency adjustment amount calculation step in the first embodiment of the present invention. It is an oscillator applied voltage and frequency change in the 1st Embodiment of this invention. 4 is a correspondence table between the load capacity to the oscillator and the number of bits in the first embodiment of the present invention. It is a frequency adjustment amount calculation process in the 2nd Embodiment of this invention. It is a correspondence table of the receiving station and the oscillator applied voltage in the second embodiment of the present invention. It is a block diagram in the 3rd Embodiment of this invention. It is a block diagram in the 4th Embodiment of this invention. It is a constant voltage generation circuit in the 5th Embodiment of this invention. It is a detailed view of the periphery of the oscillation circuit in the sixth embodiment of the present invention. 1 is a system configuration diagram of a conventional invention disclosed in Patent Document 1. FIG.

[First Embodiment]
FIG. 1 is a block diagram around an oscillation circuit of a radio timepiece 1 according to the first embodiment. In FIG. 1, the oscillation circuit of the radio timepiece 1 in the first embodiment includes an oscillation circuit 2, a frequency adjustment circuit 3 applied to the oscillation circuit 2, a first constant voltage generation circuit 4, and a second constant voltage generation circuit. 5 and a voltage switching circuit 6 for switching between the first constant voltage generation circuit 4 and the second constant voltage generation circuit 5.
As will be described later, the output voltage of the first constant voltage generation circuit 4 is 33, and the output voltage of the second constant voltage generation circuit 5 is 32.

  The oscillation circuit 2 is a circuit that generates a constant waveform at a constant period without adding a signal from the outside. It is used to create a basic clock for performing various processes when a system is assembled with an electric circuit.

  When extremely high accuracy is required as in a watch, an oscillation circuit using a crystal resonator is often used. The crystal resonator used is generally 32768 kHz. The reference clock generated by the oscillation circuit is also used in a reception circuit of a radio wave clock (not shown).

As described in Patent Document 1, the reference clock input to the local oscillation circuit in the receiving circuit is often not at an optimal frequency due to variations in the oscillation circuit and variations in the crystal resonator.
Even when the oscillation conditions of the oscillator are optimized except for the above variations, the clock generated by the local oscillation circuit is determined by the specified division ratio for each receiving station. It is necessary to match.
The reception sensitivity can be improved by finely adjusting the reference clock for each receiving station and adjusting it to the optimum value.

  FIG. 15 is a block diagram of the prior art disclosed in Patent Document 1, which is rewritten without departing from the gist.

  In FIG. 15, reference numeral 1501 denotes a crystal resonator, 1502 denotes an oscillation circuit, 1503 denotes an oscillation condition adjustment circuit, 1504 denotes a frequency dividing circuit, 1505 denotes a logic slow / fast circuit, 1506 denotes a control circuit, and 1507 denotes a receiving circuit unit.

  The oscillation frequency of the oscillation circuit 1502 is changed by the oscillation condition adjustment circuit 1503, and a reference clock suitable for reception enters the reception circuit 1507. Further, the frequency dividing ratio of the frequency dividing circuit is adjusted by the logic slow / fast circuit 1505.

The first constant voltage generation circuit 4 can be configured by a voltage regulator circuit.
The output 33 of the first constant voltage generation circuit 4 can be set to −0.85 V, for example, and is hereinafter referred to as VREG in this specification.
The output 32 of the second constant voltage generation circuit 5 may also be configured by a voltage regulator circuit, and can be set to −1.15 V, for example, and is hereinafter referred to as VMIC in the present specification. The voltage switching circuit 6 is a circuit for switching between VREG and VMIC, and supplies VREG or VMIC as a power source for the oscillator.

In general, the clock circuit often has VDD set to GND (0 V), and therefore, the power supply voltage is represented by − (minus).
As described above, the reason why the voltage switching circuit is provided and the voltage supplied to the oscillation circuit is changed will be described later.
Hereinafter, a watch state in which standard radio waves are not received is referred to as a normal state, and a state in which standard radio waves are received, including a state in which preparations for receiving standard radio waves are completed, is referred to as a reception state.

Circuits such as microcomputer ICs and reception ICs used in radio timepieces are generally not driven by one type of power supply, but generally have a plurality of power supply systems.
Therefore, in addition to VREG that is the power source of the oscillation circuit 2 in the normal state, the voltage of the VMIC that satisfies VREG <VMIC is also used, for example, as the voltage used as the power source of the microcomputer as the control means (not shown). Just do it.
Note that VREG and VMIC need to satisfy VREG <VMIC, and any voltage value can be used as long as the above relationship is satisfied.
Here, as described above, since the power source is a negative potential, the comparison of voltages is performed with an absolute value. Further, because of the negative potential, VMIC should be expressed as “deeper” than VREG, but in this specification it is expressed as “high” for convenience.
Normally, the present invention can be configured without preparing a plurality of constant voltage generation circuits by using the voltage used for the power source or the like as the output of the constant voltage circuit having this configuration.

The frequency adjustment circuit 3 is a circuit that finely adjusts the reference clock of the oscillation circuit 2. As will be described later, the power source of the switch means in the frequency adjustment circuit 3 is a VMIC.
In order to finely adjust the reference clock of the oscillation circuit 2 for each receiving station, the load capacity of the oscillation circuit is adjusted.
However, it may be difficult to maintain oscillation due to an increase in load capacity or temperature change. The present invention solves this problem.

FIG. 2 is a circuit diagram showing a detailed configuration of the oscillation circuit 2, the voltage switching circuit 6, and the frequency adjustment circuit 3.
Reference numeral 202 denotes a frequency adjustment circuit, and 208 and 209 are load capacities that are preset and added to the oscillator.
In the present specification, the load capacity 208 is referred to as Cin, and 209 as Cout.
203 is an oscillator using an oscillation inverter, which is often used in a timepiece, 204 is a feedback resistor, 205 is an oscillation inverter as an amplifier circuit, 206 is a crystal oscillator, and 207 is a stabilization resistor.
Reference numerals 210 and 212 denote switch units that turn on / off in response to the frequency adjustment signal 201. Reference numerals 211 and 213 denote load capacitors connected to the oscillator when the switch units 210 and 212 are turned on.
Reference numeral 201 denotes a frequency adjustment circuit that receives a signal from a microcomputer IC inside a radio timepiece (not shown) and sends a signal to the switch means 210 and 212.
In addition, 211 is a load capacity connected to the Cin side, 213 is a load capacity connected to the Cout side, 210 is a switch means for switching the Cin side load capacity, and 212 is a switch means for switching the Cout side load capacity.
The frequency of the reference clock of the oscillator is changed by changing the load capacity connected to the oscillator by turning ON / OFF the switch means 210 and 212.

Next, the operation of FIG. 2 will be described.
In the normal state, the output of the voltage switching circuit 6 is VREG, and the power source of the oscillation inverter 205 is also VREG.
At that time, the switching means 210 and 212 are turned off by the frequency adjusting circuit 201, and the load capacitors are connected to the oscillator only by the preset capacitors Cin and Cout.
During radio wave reception, the output of the voltage switching circuit 6 is a VMIC, and the power source of the oscillator 203 is also a VMIC. At that time, the switching means 210 and 212 are selectively turned ON / OFF by the frequency adjusting circuit 201, and the load capacitors 211 and 213 are connected to the oscillator in addition to the preset capacitors Cin and Cout. Connected selectively.
The switch means 210 and 212 are driven by a VMIC.

The oscillation circuit 203 is an oscillation circuit using an inverter that is commonly used, and the terminals of the crystal oscillator are P1 and P2, respectively, as shown in FIG. A necessary frequency can be obtained by changing the load capacity connected to P1 and P2 in stages.
Here, capacitance is added to both terminals P1 and P2, but either one may be used depending on the design of the oscillation circuit.

When only the load capacitor 211 is used as a load capacitor connected at the time of reception, for example, by dividing the size into 0.2 pF, 0.4 pF, 0.8 pF, 1.6 pF, 3.2 pF, etc. The load capacity to be connected can be finely determined by the number of ON / OFF, and detailed frequency adjustment is possible.
It should be noted that the frequency adjustment becomes possible in detail as the number of the switch means 210 and the load capacity 211 increases.

As described in Patent Document 1, the reference clock input to the local oscillation circuit in the receiving circuit is often not at an optimal frequency due to variations in the oscillation circuit and variations in the crystal resonator.
Even when the oscillation conditions of the oscillator are optimized except for the above variations, the clock generated by the local oscillation circuit is determined by the specified division ratio for each receiving station. It is necessary to match.
The output of VREG or VMIC by the voltage switching circuit 6 is applied to the oscillation inverter 205 of the oscillator 203, and VMIC is used as the drive voltage for the switch means 210 and 212. The oscillation inverter 205 is configured by, for example, a MOSFET, and VREG or VMIC is applied to the source and bulk of an Nch transistor (not shown).
Further, the switch means 210 or 212 is constituted by, for example, a TG (transmission gate), and it is also desirable that the VMIC is applied to the source and bulk of the Nch transistor constituting the TG.
By applying the VMIC to the bulk, the impedance of the switching means 210 and 212 is lowered, and the current flowing therethrough is increased, thereby facilitating switching, and at the same time, a large voltage is applied to the load capacitance (for example, MOS capacitance). As a result, a capacity close to a preset load capacity can be connected.

FIG. 3 is a diagram showing details of the voltage switching circuit 6 that generates the drive voltage of the oscillation inverter 205.
Reference numeral 32 denotes a VMIC which is an output of the second constant voltage generation circuit 5, and 33 denotes a VREG which is an output of the first constant voltage generation circuit 4, so that the drive voltage of the oscillation inverter 205 can be changed by the switch means 34. It has become.
Reference numeral 31 denotes a voltage control signal for switching ON / OFF of the switch means 34, and 35 and 36 denote resistors for limiting the current to the oscillation inverter 205.

In the normal state, the voltage control signal 31 turns on the switch on the VREG side and turns off the switch on the VMIC side. At this time, VREG is connected to the power supply of the oscillation inverter 205 via the resistors 35 and 36. When receiving radio waves, the voltage control signal 31 turns off the switch on the VREG side and turns on the switch on the VMIC side. At this time, the VMIC is connected to the power source of the oscillation inverter 205 only through the resistor 36. Therefore, at the time of radio wave reception, not only the high power supply voltage VMIC is supplied to the oscillation inverter 205 but also a large amount of current is supplied. By supplying a larger voltage and current to the oscillation inverter 205, the oscillation margin of the oscillation circuit 2 is increased, and it becomes easy to start oscillation and maintain oscillation.
Note that the switch means 34 always operates in a complementary manner, and is composed of, for example, a MOSFET.

FIG. 4 shows the timing of each output signal when shifting from the normal state to the time of receiving the standard radio wave.

First, in the normal state, the output of the voltage control circuit 31 is VREG (−0.85 V). At this time, the voltage applied to the oscillator is also VREG (−0.85 V).
Then, the output of the voltage control circuit 31 is switched to High (VDD level) when shifting from the normal state to the standard radio wave.
When the output of the voltage control circuit 31 is switched to High, the voltage applied to the oscillator increases from VREG (−0.85 V) to VMIC (−1.15 V).
When the radio wave reception state ends and the normal state is restored, the output of the voltage control circuit 31 changes to Low (VREG level), and the oscillator applied voltage also decreases from VMIC to VREG.

FIG. 5 is a flowchart showing a flow from the start of radio wave reception to the end of radio wave reception.
When the radio wave reception process starts (S501), the voltage switching circuit 6 starts operating (S502), the voltage switching circuit 6 receives the voltage control signal 31, and changes the voltage applied to the oscillation inverter 205 from VREG to VMIC. . (S503)
Thereafter, the frequency adjustment circuit 3 operates (S504), and before the reception process starts, the set value of the frequency adjustment circuit 3 is changed to the adjustment value of the standard radio wave reception state. (S505)
Thereafter, a reception process is performed (S506). When the reception process is completed, the setting value of the frequency adjustment circuit 3 is changed to a normal value by a microcomputer IC as a control unit (not shown). (S507)
Thereafter, the frequency adjusting circuit 3 is stopped (S508), the voltage switching circuit 6 is operated (S509), the oscillator applied voltage is changed to VREG (S510), and the radio wave receiving process is ended (S511).

There are individual differences in the crystal oscillator used in the oscillation circuit, and the oscillation frequency varies.
Therefore, in order to correct the frequency variation, the oscillation frequency is adjusted by increasing or decreasing the load capacitance added to the oscillation circuit as in the frequency adjustment circuit in FIG.
In the normal state, the clock operation is performed using the frequency corrected as described above.

On the other hand, when receiving a standard radio wave, the constant voltage of the second constant voltage generation circuit 5, that is, a large constant voltage (VMIC) in the negative voltage direction is applied to the oscillation inverter 205 of the oscillation circuit. The operating threshold of the transistor changes and the frequency changes.
Accordingly, the oscillation frequency when the VMIC is applied to the oscillation inverter 205 at the time of receiving the standard radio wave is measured in advance, and the capacity added to the oscillation circuit for correcting the frequency is stored. Based on the information stored at the time of receiving the standard radio wave, The oscillation frequency is adjusted by adding a capacitor to the oscillation circuit.

FIG. 6 is a flowchart showing the flow until the frequency adjustment amount is calculated and determined.
When the frequency adjustment process is started (S601), first, the frequency of the reference 32768 Hz crystal oscillation circuit is measured (S602).
Then, the correction amount in the normal state is determined according to the measured oscillation frequency (S603).
Subsequently, the VMIC is applied to the oscillation inverter 205 of the crystal oscillator 203 (S604), the frequency in the reception state is measured in that state (S605), and the frequency correction amount is determined. (S606)
When the correction amount at the time of reception is determined (S607), the receiving station is changed, and the correction amount is determined with respect to the carrier frequencies of the East, West, German, and Chinese stations in Japan (S608).
When the correction amount is determined, the correction amount is stored in a microcomputer IC (not shown) (S609), and the adjustment is completed (S610).

As the load capacitances 211 and 213 connected at the time of receiving the standard radio wave increase, the load on the oscillation circuit 203 increases (oscillation conditions change), so that oscillation is less likely.
Also, the oscillation conditions change depending on the temperature of the surrounding environment.
FIG. 7 shows the number of bits and the frequency change amount Δf [ppm].
The number of bits referred to here is determined by the number of ON / OFF states of the switch means 210 and 212, and the larger the number of bits, the greater the load capacity connected to the oscillator. The relationship between the number of bits and the load capacity to the oscillator is as shown in FIG.

In FIG. 7, when the voltage applied to the oscillating inverter 205 and the switch means 210 and 212 is small (−0.84 V in FIG. 7), a portion where the frequency change becomes discontinuous appears as the number of bits increases. The overall frequency change width is small. This is because, since the supplied voltage is low, the resistance values of the switch means 210 and 212 are high, and the parasitic capacitance is also large, so that the value is different from the capacitance value that should be originally set by the load capacitance. Conceivable.
On the other hand, when the voltage applied to the oscillation circuit 203 and the switch means 210 and 212 becomes large (−1.20 V in FIG. 7), the discontinuous part accompanying the increase in the number of bits is the oscillation inverter 205 and the switch means 210 and The voltage applied to 212 is suppressed to be smaller than that when the voltage is −0.85 V, and the entire frequency variable width is increased, approaching the ideal curve indicated by the bold line in FIG. This is presumably because the supplied voltage is high, the resistance values of the switch means 210 and 212 are low, and the parasitic capacitance is also small, so that it approaches the capacitance value that should be originally set by the load capacitance.
By increasing the overall variable width, it becomes possible to adjust the frequency even if there is a large variation in crystal resonators from sample to sample, and it is possible to expand the delivery standards for crystal resonators.

  As described above, the voltage applied to the oscillation inverter 205 of the oscillation circuit when receiving the standard radio wave of the radio timepiece is switched from VREG to VMIC, and the voltage applied to the switch means 210 and 212 of the frequency adjustment circuit 3 is VMIC. Thus, even when the load capacitance of the oscillation circuit is added, the center frequency closest to the ideal value can be obtained without stopping the oscillation circuit.

In the present embodiment, the embodiment uses a plurality of constant voltage generation circuits. However, the present invention is not limited to this. One constant voltage generation circuit capable of generating a constant voltage having a plurality of values may be used.
The same applies to the following embodiments.

[Second Embodiment]
FIG. 9 is a flowchart showing the flow of the frequency adjustment process in the second embodiment.
In the frequency adjustment step in the ninth embodiment, first, the frequency of a 32768 Hz crystal oscillation circuit serving as a reference is measured for each sample. (S902)
Then, the frequency correction amount in the normal state is determined. (S903)
Subsequently, without switching the voltage applied to the oscillator, VREG is used as it is, the crystal oscillation frequency is measured, and the correction amount of the first standard radio wave reception state is determined. (S905)
If there is another receiving station whose applied voltage is VREG, the receiving station is switched, the crystal oscillation frequency is measured, and the correction amount of the first standard radio wave receiving state is determined. (S907)
Subsequently, the voltage switching circuit 6 switches the voltage applied to the oscillator in the reception state to the VMIC, measures the crystal oscillation frequency in that state, and determines the correction amount in the second standard radio wave reception state (S910).
If there is another receiving station whose oscillator applied voltage is VMIC, the receiving station is switched, the crystal oscillation frequency is measured, and the correction amount of the second standard radio wave receiving state is determined. (S912)
Dividing the applied voltage to the oscillator for each receiving station as described above is to calculate in advance the receiving station that is assumed to have a small frequency correction amount and the receiving station that is assumed to have a large frequency correction amount in advance. In other words, the frequency adjustment process is divided.
The normal frequency correction amount and the frequency correction amount of the standard radio wave reception state for each receiving station are stored in the microcomputer IC of the radio timepiece, not shown, and the frequency adjustment process is completed.

  FIG. 10 shows an example of setting of the receiving station and the oscillator applied voltage. In the case of a receiving station (JJY40, BPC) whose frequency correction amount is assumed to be small in advance, the oscillator applied voltage is VREG, and in the case of a receiving station (JJY60, WWVB, DCF) where the frequency correction amount is assumed to be relatively large, The oscillator applied voltage is VMIC.

The magnitude of the frequency correction amount for each receiving station can be theoretically estimated from the amount of deviation of the local oscillation frequency for each receiving station.
Since the local oscillation frequency is generated by multiplying a 32768 Hz signal from a microcomputer IC (not shown) by a certain constant for each receiving station, a slight deviation inevitably occurs.
By estimating this deviation in advance, the magnitude of the frequency correction amount can be determined.

In the case of the second embodiment, the voltage switching circuit 6 in the first example is used, and the voltage applied to the oscillator in the reception state for each receiving station can be divided into VREG and the case where the VMIC is used.
With this configuration, lower power consumption during standard radio wave reception can be expected by using VREG as a reception state oscillation voltage, which is a lower voltage than when the VMIC is continuously used as a reception state oscillation voltage. .
Also, in terms of circuit configuration, it is only necessary to determine the voltage applied to the oscillator for each receiving station, which can be implemented without significant changes from the first embodiment.

  Therefore, in the second embodiment, the voltage applied to the oscillation inverter 205 of the oscillation circuit is switched from VREG to VMIC when the standard time signal of the radio timepiece is received, and the voltage applied to the switch means 210 and 212 of the frequency adjustment circuit 3 is changed to VMIC. In addition, the voltage applied to the oscillator in the reception state for each receiving station is divided into the case where the voltage is VREG and the case where the VMIC is used, so that the oscillation circuit is not stopped even when the load capacity of the oscillation circuit is added. As a result, the center frequency closest to the ideal value can be obtained, and at the same time, the power consumption can be reduced when receiving standard radio waves.

[Third Embodiment]
FIG. 11 shows a circuit block in the third embodiment. The difference from FIG. 1 is that a third constant voltage generation circuit 1107 is added to the input of the voltage switching circuit 6 and an oscillation detection circuit 1108 is added.
The oscillation detection circuit 1108 monitors the signal of the oscillation circuit 2 and outputs a determination result of the oscillation state to the voltage switching circuit 6.
Circuit blocks other than the third constant voltage generation circuit 1107 and the oscillation detection circuit 1108 are the same as those in FIG.

Next, the operation of FIG. 11 will be described.
The voltage switching circuit 6 selects one constant voltage from the first constant voltage generation circuit 4, the second constant voltage generation circuit 5, and the third constant voltage generation circuit 1107 and applies it to the oscillation circuit 2.
In a normal state where standard radio wave reception is not performed, the first constant voltage generation circuit 4 is selected. When standard radio wave reception is performed, the second constant voltage generation circuit 5 or the third constant voltage generation circuit 1107 is selected according to the selected station. And apply the selected constant voltage to the oscillation circuit.
As an example of the constant voltage to be set, the output VREG (−0.85 V) of the first constant voltage generation circuit 4, the output voltage of the second constant voltage generation circuit 5 is VMIC (−1.15 V), and the third The output voltage of the constant voltage generation circuit 1107 is −1.05V.
Hereinafter, the output voltage of the third constant voltage generation circuit 1107 is referred to as VMEM.
Each voltage value shown here is used for the sake of simplicity of explanation, and this voltage value is satisfied if the output voltage of the first, second, and third constant voltage generation circuits satisfies the magnitude relationship. It is not limited to.

  In addition to VREG and VMIC, the voltage of VMEM satisfying VREG <VMEM <VMIC may be combined with, for example, a voltage used as a power source for a memory (not shown). Normally, the present invention can be configured without preparing a plurality of constant voltage generation circuits by using a voltage used for a power supply, a memory, or the like as an output of the constant voltage circuit having this configuration.

The voltage switching circuit 6 measures the oscillation frequency of the oscillation circuit in advance before receiving the standard radio wave, and determines the load capacity that can obtain the optimum frequency.
Specifically, the voltage switching circuit 6 selects the output voltage of the third constant voltage generation circuit 1107, applies it to the oscillation circuit 2, and measures the oscillation frequency while changing the load capacitance.
This measurement is performed for each frequency corresponding to the standard radio wave transmission station.

At this time, if there is an abnormality in the oscillation characteristics such as the oscillation stops or the oscillation frequency is abnormally low, the oscillation detection circuit 1108 detects this and the constant voltage selected by the voltage switching circuit 6 Instruct to change.
That is, the voltage switching circuit 6 changes the output of the second constant voltage generation circuit 5 from the third constant voltage generation circuit 1107 and applies a constant voltage to the oscillator.
The oscillation detection circuit 1108 may use a microcomputer (not shown) that controls the clock operation.

Thereafter, the oscillation frequency is measured again, and the load capacity that is closest to the set oscillation frequency is determined.
The data indicating the load capacity is included in the standard radio wave transmission station together with data indicating which of the outputs of the second constant voltage generation circuit 5 or the third constant voltage generation circuit 1107 is selected by the voltage switching circuit 6. Are stored in a storage device (not shown).

  At the time of standard radio wave reception, load capacity data and selection data of the voltage switching circuit 6 are read from the storage device, and a load capacity in the oscillation circuit 2 and a constant voltage applied to the oscillation circuit are selected. The oscillation circuit 2 oscillates at a preselected frequency without stopping the oscillation.

As described above, there are a plurality of frequencies of the standard radio wave, but it is not necessary to add a large load capacity to the oscillation circuit 2 at all the frequencies.
That is, depending on the standard radio wave frequency, it is only necessary to finely adjust the frequency by adding a relatively small capacity, so that it is not necessary to apply a large voltage such as the output voltage of the second constant voltage generation circuit 5 -1.15V. However, a sufficiently normal oscillation is possible.
Since the oscillation circuit repeats switching at a high frequency, it is a block that consumes a large amount of power, and the power consumption increases as the applied voltage increases.
Therefore, in the above case, it is possible to reduce the power consumption by applying the output voltage VMEM of the third constant voltage generation circuit 87 which is smaller than the VMIC.

  Since it is desirable that the power consumption is small, the oscillation frequency measurement performed before receiving the standard radio wave is started from the state in which the output voltage VMEM of the third constant voltage generation circuit 1107 is applied, and only when an oscillation abnormality occurs, The output voltage VMIC of the second constant voltage generation circuit 5 is applied to perform re-measurement.

By adopting such a configuration, the oscillation circuit 2 can obtain the center frequency closest to the ideal value while reducing the power supply voltage when receiving the standard radio wave.
That is, it is possible to reduce power consumption accompanying oscillation.
When there is no concern about the oscillation abnormality of the oscillation circuit 2, the oscillation detection circuit 1108 is omitted, and the output voltage of the second constant voltage generation circuit 5 and the third constant voltage generation circuit 1107 are preliminarily set for each frequency of the standard radio wave. It is also possible to determine which output voltage to select and operate the oscillation circuit with a constant voltage selected during frequency measurement.

[Fourth Embodiment]
FIG. 12 shows a circuit block in the fourth embodiment.
The difference from FIG. 11 is that an oscillation frequency measurement circuit 1208 and a local frequency generation circuit 1209 are added instead of the oscillation detection circuit 1108. Circuit blocks other than the oscillation frequency measurement circuit 1208 and the local frequency generation circuit 1209 are the same as those in FIG.

In the heterodyne system, local frequencies corresponding to respective standard radio wave frequencies are mixed and frequency conversion is performed to one intermediate frequency.
The local frequency generation circuit 1209 is a circuit that generates the local frequency, and is configured using a phased lock loop circuit and a voltage controlled oscillator.
The phased lock loop circuit is hereinafter referred to as a PLL.
The PLL divides the input oscillation frequency to create a low cycle frequency, compares the phase of the frequency generated by the voltage controlled oscillator with the phase of the low cycle frequency, and corrects the frequency. To improve the accuracy of the local frequency.
In FIG. 12, the low-frequency frequency obtained by dividing the oscillation frequency is output to the oscillation frequency measurement circuit 1208.
The oscillation frequency measuring circuit 1208 receives the low cycle frequency as input and counts the cycle to obtain the load capacitance and a constant voltage applied to the oscillation circuit so that an intermediate frequency closest to the set intermediate frequency is obtained. decide.

As described with reference to FIG. 2, the frequency that can be selected for adjustment is determined by a combination of capacitors that select a capacitor added to the oscillation circuit 2 with a switch and adjust the oscillation frequency.
Therefore, even if it is attempted to adjust the oscillation frequency so as to obtain an intermediate frequency closest to the set intermediate frequency, the frequency must be intermittently selected as described above, and thus the oscillation frequency cannot be adjusted in detail. .
The frequency that cannot be adjusted leads to a shift amount of the intermediate frequency, and the signal component of the frequency shifted by the frequency filter of the subsequent circuit (not shown) is deleted, so that the signal-to-noise ratio is deteriorated and the reception success rate is adversely affected.
The fourth embodiment solves the above problem.

As shown in FIG. 7, the oscillation frequency also changes depending on the voltage applied to the oscillator.
Therefore, by increasing the number of constant voltages applied to the oscillator, the number of oscillation frequencies can be selected and the oscillation frequency can be adjusted more finely.

Next, the operation will be described.
In the oscillation frequency measurement performed in advance before receiving the standard radio wave, a plurality of constant voltages to be applied to the oscillator are prepared as in the second constant voltage generation circuit 5 and the third constant voltage generation circuit 1107 in FIG. Apply oscillation sequentially while changing the capacitance, and measure the oscillation frequency.
The oscillation frequency of the oscillation circuit 2 is divided by the local frequency generation circuit 1209 and converted into a low cycle frequency. The oscillation frequency measurement circuit 1208 measures the low cycle frequency, and is an intermediate frequency closest to the set intermediate frequency. And the constant voltage applied to the oscillation circuit are determined and stored as data in a storage device (not shown).
At the time of standard radio wave reception, a standard radio wave reception is performed by selecting a load capacity and a constant voltage to be applied to the oscillation circuit based on the stored data.
By adopting such a configuration, the oscillation circuit 2 can optimally adjust the oscillation frequency so as to obtain an intermediate frequency closest to the set intermediate frequency when receiving the standard radio wave.
That is, it is possible to improve the standard radio wave reception success rate.

[Fifth Embodiment]
FIG. 13 shows a constant voltage generation circuit 1309 according to the fifth embodiment. Reference numeral 1301 denotes a current control circuit for changing the amount of current of the constant voltage generation circuit 1309 by a microcomputer IC inside the radio timepiece (not shown), 1302 is a reference voltage generation circuit unit, 1303 is an amplification circuit unit, and 1304 is an output circuit unit. Reference numerals 1305 and 1307 denote Pch MOSFETs for controlling the current to a preset current amount when turned on, and reference numerals 1306 and 1308 denote Pch MOSFETs whose ON / OFF is determined by the current control circuit 1301.

The constant voltage generation circuit 1309 outputs VREG in a state where the Pch MOSFETs 1305 and 1307 are in the normal state.
At the time of standard radio wave reception, in addition to the state where the Pch MOSFETs 1305 and 1307 are ON, the current control circuit 1301 causes the Pch MOSFETs 1306 and 1308 to be ON.

With this configuration, the amount of VREG current can be changed between the normal state and the standard radio wave reception state.
Accordingly, in the fifth embodiment, the oscillation condition of the oscillator in the radio wave reception state is changed by switching the amount of VREG current applied to the oscillator when receiving the standard radio wave of the radio clock between the normal state and the standard radio wave reception state. The center frequency closest to the ideal value can be obtained without stopping the oscillation circuit even when a large load capacity is added to the oscillation circuit during standard radio wave reception.

[Sixth Embodiment]
FIG. 14 shows a detailed view of the periphery of the oscillation circuit in the sixth embodiment.
Reference numeral 1414 denotes a second oscillation inverter, which is characterized in that the size of the Pch MOSFET and the Nch MOSFET constituting the inverter is larger than the size of the oscillation inverter 205.
Reference numeral 1415 denotes switch means for switching between the oscillation inverters 205 and 1414. The switch means 1415 is composed of, for example, a MOSFET, and operates in a complementary manner so that when one is turned on, the other is turned off.
Reference numeral 1416 denotes an oscillation inverter switching circuit, which sends a signal to the switch means 1415.
Circuit components other than the second oscillation inverter 1414, the oscillation inverter switching circuit 1415, and the oscillation inverter switching circuit 1416 are the same as those in FIG.

  The oscillating inverter switching circuit switches the switching means 1415 so that the oscillating inverter 205 is driven in a normal state, and the size of the oscillating inverter of the crystal oscillator is changed when a high load capacity is connected when receiving a standard radio wave or in a high temperature environment. By switching to a larger second oscillation inverter 1414, the oscillation margin can be increased, oscillation can be maintained normally, and a desired frequency can be adjusted.

The frequency adjustment data is determined by calculating an adjustment amount when the oscillation inverter is changed in the frequency adjustment step.
The frequency adjustment data is recorded in a storage device inside the microcomputer (not shown).
When a high load capacity is connected during standard radio wave reception or when it is difficult to connect the load capacity in a high temperature environment, the adjustment amount when the oscillation inverter is enlarged is used, and the high load capacity Connection is possible.

  In the present embodiment, a plurality of oscillation inverters having different driving capabilities (amplification capabilities) are used, but the present invention is not limited to this. One inverter may be configured to increase the driving capability of the MOS that constitutes the inverter during reception.

DESCRIPTION OF SYMBOLS 1 ... Radio clock 2 ... Oscillation circuit 3 ... Frequency adjustment circuit 4 ... 1st constant voltage generation circuit 5 ... 2nd constant voltage generation circuit 6 ... Voltage switching circuit 201 ... Frequency adjustment circuit 202 ... Frequency adjustment mechanism 203 ... Crystal oscillation Circuit 204 ... Feedback resistor 205 ... Oscillation inverter 206 ... Crystal oscillator 207 ... Stabilizing resistor 31 ... Voltage control circuit 32 ... Output of second constant voltage generation circuit 33 ... Output of first constant voltage generation circuit 34 ... Voltage switching Circuit 1301 ... Current control circuit 1302 ... Reference voltage generation circuit unit 1303 ... Amplification circuit unit 1304 ... Output circuit unit 1309 ... Constant voltage generation circuit 1414 ... Second oscillation inverter 1415 ... Switch means 1416 ... Oscillation inverter switching circuit

Claims (7)

A clock oscillation circuit as a reference signal source in timekeeping,
A heterodyne receiving circuit for receiving external radio waves;
A PLL circuit for creating a local oscillation frequency used in the heterodyne receiver circuit,
A radio timepiece in which the clock oscillation circuit also serves as a reference frequency generation means for generating a reference frequency of the PLL circuit;
A control means for changing an oscillation condition of the timepiece oscillation circuit;
In the radio timepiece that changes the oscillation condition of the timepiece oscillation circuit so that the oscillation frequency of the timepiece oscillation circuit differs between when the external radio wave is received and when it is not received,
The radio timepiece characterized in that the control means increases the driving capability of the timepiece oscillation circuit when receiving the external radio wave as compared with when not receiving. A power supply circuit for the clock oscillation circuit capable of outputting a plurality of different voltages;
A voltage switching circuit for supplying any one of the plurality of voltage outputs to the clock oscillation circuit;
The control means has a power supply voltage of the timepiece oscillation circuit at the time of receiving the external radio wave,
The radio-controlled timepiece according to claim 1, wherein the voltage switching circuit is controlled to be higher than that at the time of non-reception. A power supply circuit for the clock oscillation circuit capable of outputting a plurality of different power supply current amounts;
A current control circuit that controls the power supply circuit so as to supply any one of the plurality of power supply current amounts to the clock oscillation circuit;
The said control means controls the said current control circuit so that the amount of power supply currents to the said clock oscillation circuit at the time of reception of the said external radio wave may become larger than at the time of non-reception. Radio clock. An oscillation amplifier circuit having different amplification capabilities in the clock oscillation circuit;
A switching circuit for changing the amplification capability of the oscillation amplifier circuit;
2. The radio timepiece according to claim 1, wherein the control unit controls the switching circuit so that an amplification capability of the oscillation amplifier circuit at the time of receiving the external radio wave is larger than that at the time of non-reception. The heterodyne receiving circuit is configured to be capable of receiving the external radio wave having a plurality of frequencies,
5. The radio timepiece according to claim 1, wherein the control unit changes a driving capability of the timepiece oscillation circuit for each of the frequencies. 6. 6. The radio timepiece according to claim 1, wherein the control unit changes a load capacitance value of the timepiece oscillation circuit as an oscillation condition of the timepiece oscillation circuit. 7. The system according to claim 1, further comprising a local oscillation frequency measurement circuit for measuring the local oscillation frequency, wherein the driving capability of the clock oscillation circuit is changed based on a measurement result of the local oscillation frequency measurement circuit. Radio wave clock as described in one.

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