JP2015169588A - Failure analysis program, failure analysis method, and failure analysis device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To identify the cause of a plurality of failures.SOLUTION: There is provided a failure analysis program for causing a computer to execute a selection process, an identification process, an extraction process, and a deletion process. The selection process uses failure information indicating failure candidate wiring and cause information indicating the candidate cause of failure. The selection process selects, one at a time for each semiconductor device, first wiring having a high possibility of failure from among the failure information. The identification process performs a regression analysis using the first wiring and identifies the candidate cause corresponding to the degree of contribution indicating a high value as the cause of failure. The extraction process extracts, for each semiconductor device, second wiring that indicates the same result as the first wiring from among the failure information when subjected to failure simulation. The deletion process deletes the first wiring and the second wiring from the failure information. In the failure analysis program, the selection process, the identification process, the extraction process, and the deletion process are executed using the failure information of each semiconductor device, with the first wiring and the second wirings deleted therefrom.

Description

  The present invention relates to a technique for analyzing a failure of a semiconductor device.

  In the failure analysis of semiconductor devices, candidates for physical failures are narrowed down by performing logical diagnosis on semiconductor devices in which a failure is detected in a shipping test or on the market. In mass failure diagnosis of semiconductor devices, processing is performed to statistically analyze failure candidates narrowed down in failure analysis and identify the cause of systematic failure. The semiconductor device is, for example, an integrated circuit (IC: Integrated Circuit) or a large scale integration (LSI: Large Scale Integration) circuit. A systematic failure is, for example, a failure caused by design or process that occurs between a plurality of defective semiconductor devices of the same type. The cause of systematic failure is, for example, information indicating a position, configuration, and state where a physical failure occurs in a semiconductor device. The cause of the systematic failure includes, for example, an open failure of a via connecting between layers and a bridge failure of a dense wiring. In the following description, a systematic failure is also simply referred to as a failure. The cause of systematic failure is also called failure factor. Furthermore, the position and configuration that cause systematic failure are also referred to as features or factor candidates.

  As another related technique, the defect observation apparatus collates a hot spot (HS) point that can be simulated in advance with a defect point obtained as a result of an appearance inspection. Further, the defect observation apparatus classifies the defect points into groups based on the similarity of the circuit shapes at the defect points with respect to the defect points that have not been verified. Then, the defect observation apparatus detects a systematic defect by specifying a defect belonging to the circuit shape in which the defect is frequently generated. Further, the defect observation apparatus is known to be capable of detecting a systematic defect caused by the topography of the wafer by detecting the uneven distribution of the defect occurrence distribution on the wafer.

  As another related technique, a technique is known in which a yield prediction system measures the film quality characteristics of a semiconductor device and predicts the yield of the semiconductor device using the measured data during the manufacturing process of the semiconductor device. (For example, Patent Document 1 and Patent Document 2).

JP 2010-258353 A JP 2009-32855 A

  In the analysis technique described above, only the dominant failure factors that are likely to cause the failure of the semiconductor device are identified. Therefore, even if the design considering the identified failure factors is performed, other failure factors remain, and the semiconductor device May not be able to improve the yield to the target value.

  As one aspect, the present invention provides a technique for identifying a plurality of failure factors.

  One of failure analysis programs disclosed in this specification is a failure analysis program that causes a computer to execute selection processing, identification processing, extraction processing, and deletion processing. The selection process uses failure information indicating failure candidate wiring that may fail for each of a plurality of semiconductor devices, and factor information indicating a plurality of factor candidates that may cause systematic failure. In the selection process, the first wiring that has a high possibility of failure is selected from the failure information for each semiconductor device. In the specific process, a regression analysis is performed using the selected first wiring, and a high value is selected from among the contributions indicating the strength of the influence on the failure of the semiconductor device corresponding to the plurality of candidate systematic failures. Factor candidates corresponding to the contributions shown are identified as systematic failure factors. The extraction process extracts, from the failure information, the second wiring for each semiconductor device, which is the failure simulation result when the first wiring is assumed to have failed and the same failure simulation result when the failure is assumed. In the deletion process, the first wiring and the second wiring are deleted from the failure information. Further, in the failure analysis program, selection processing, identification processing, extraction processing, and deletion processing are executed using the failure information of each semiconductor device from which the first wiring and the second wiring are deleted.

  According to one embodiment, a plurality of failure factors can be identified.

It is a functional block diagram which shows one Example of a failure analysis apparatus. It is a figure which shows the semiconductor device on a wafer. It is a figure which shows an example of factor information. It is a figure which shows an example of failure information. It is a figure explaining the production | generation of division | segmentation information. It is a figure which shows an example of a regression equation. It is a figure which shows the failure rate obtained from the result of regression analysis. It is a figure which shows the contribution corresponding to a factor candidate. It is a figure which shows an example of specific information. It is a figure explaining extraction of the accompanying failure candidate wiring using a failure difference function. It is a flowchart (the 1) which shows the process which specifies a failure factor. It is a flowchart (the 2) which shows the process which specifies a failure factor. It is a flowchart (the 3) which shows the process which specifies a failure factor. It is a block diagram which shows one Example of a computer apparatus.

[Embodiment]
A failure analysis apparatus according to an embodiment will be described.

  The failure analysis apparatus according to the embodiment is assumed to be used for, for example, a shipping test or a failure factor analysis of a semiconductor device in which a failure is detected in the market. Therefore, it is assumed that the types of semiconductor devices subjected to failure analysis are in a state where a certain yield is obtained, and a plurality of failure factors included in the semiconductor devices are independent from each other. Further, it is assumed that the failure wiring in the semiconductor device has failed due to one failure factor. However, the failure analysis apparatus of the embodiment may be used for failure analysis other than semiconductor devices in which a failure is detected in a shipping test or in the market.

FIG. 1 is a functional block diagram showing an embodiment of the failure analysis apparatus.
The failure analysis apparatus 1 will be described with reference to FIG.

  The failure analysis apparatus 1 includes, for example, a control unit 10, a storage unit 20, and an input / output unit 30. The failure analysis device 1 is, for example, a computer device described later.

  The control unit 10 includes an acquiring unit 11, a processing unit 12, a dividing unit 13, a selecting unit 14, a calculating unit 15, a generating unit 16, a specifying unit 17, an extracting unit 18, and a deleting unit 19. Including. The storage unit 20 stores connection information 21, factor information 22, arrangement information 23, failure information 24, division information 25, division arrangement information 26, and specific information 27. The input / output unit 30 includes an input unit 31 and an output unit 32.

  The acquisition unit 11 acquires connection information 21 storing connection relationships such as a plurality of elements included in the semiconductor device and input / output terminals, and stores the connection information 21 in the storage unit 20. The connection information 21 is, for example, a net list. The connection relationship is, for example, a net corresponding to wiring between elements. The semiconductor device is, for example, an integrated circuit mounted on each rectangular portion (die) of the wafer 2 shown in FIG. Semiconductor devices of the same product type are mounted on each rectangular portion shown on the wafer 2. In addition, the semiconductor devices indicated by diagonal lines on the wafer 2 indicate, for example, semiconductor devices that are determined to be defective in a shipping test. In the following description, the connection relationship stored in the connection information 21 is also referred to as a net stored in the connection information 21 or a wiring stored in the connection information 21.

  The acquisition unit 11 acquires factor information 22 indicating a plurality of factor candidates that can be a cause of a systematic failure. Then, the acquisition unit 11 stores the acquired factor information 22 in the storage unit 20. The factor candidates are, for example, vias in the second to third layers, dense wiring in the fifth layer, and the like, and are information indicating characteristics in the semiconductor device that cause failure. In the factor information 22, for example, as shown in FIG. 3, a factor candidate ID for identifying a factor candidate and a feature of the factor candidate are stored in association with each other. Although four factor candidates are stored in the factor information 22 of FIG. 3, it is an example, and an arbitrary number of factor candidates may be stored. In the factor information 22, a feature that may cause a failure in the design stage of the semiconductor device may be stored by the user as a factor candidate. In the factor information 22, the characteristics that the processing unit 12 has determined to be a cause of failure using information such as the distance between the wirings, the size of the transistor, and the material at the design stage of the semiconductor device are displayed. May be stored as factor candidates. In the following description, it is assumed that there are four factor candidates.

  The processing unit 12 includes, for example, connection information 21, element information indicating the configuration and characteristics of the elements, terminal information indicating the positions of the input / output terminals of the semiconductor device, and constraint information indicating the constraints on the design of the semiconductor device, Are used to place and wire elements in the semiconductor device and input / output terminals. Thereby, the processing unit 12 generates arrangement information 23 indicating the arrangement of elements and input / output terminals in the semiconductor device and the shape of the wiring connecting the elements and the input / output terminals. Then, the processing unit 12 stores the generated arrangement information 23 in the storage unit 20. Note that the constraint conditions include element-related restrictions such as element area, element performance, and element power consumption, and wiring-related restrictions such as distance between wirings, wiring length, and wiring width. The element information, terminal information, and constraint information may be, for example, information input from the input unit 31 and stored in the storage unit 20 or information included in a failure analysis program described later, although not shown. good.

  In addition, the processing unit 12 performs failure diagnosis on a semiconductor device in which a failure is detected in, for example, a shipping test or a market, for example, so that a failure candidate that may have failed for each of a plurality of semiconductor devices is obtained. Fault information 24 indicating wiring is generated. Then, the processing unit 12 stores the generated failure information 24 in the storage unit 20. The logic fault diagnosis is executed using, for example, logic simulation or a fault dictionary method. Therefore, the wiring that may have failed includes not only the wiring that has actually failed, but also wiring that has not actually failed but is detected by the logic fault diagnosis. In the following description, a wiring that may have failed is also referred to as a failure candidate wiring.

  The failure information 24 is generated, for example, for a semiconductor device in which a failure is detected among a plurality of semiconductor devices mounted on the wafer 2. Therefore, as shown in FIGS. 1 and 4, the storage unit 20 stores a plurality of pieces of failure information 24-1 to 24-n. For example, as shown in FIG. 4, the failure information 24 stores a net ID for identifying a failure candidate wiring, a characteristic of a wiring failure location, and a state of the wiring failure location in association with each other.

  The dividing unit 13 generates division information 25 obtained by dividing the connection information 21 indicating the connection relation of a plurality of elements included in the semiconductor device. Then, the dividing unit 13 stores the generated division information 25 in the storage unit 20. For example, the division information 25 is a collection of connection relationships included in a semiconductor device for each predetermined number, and a plurality of pieces of division information 25 are generated. The storage unit 20 stores a plurality of pieces of division information 25-1 to 25-n as illustrated in FIG. In the following description, the connection relationship stored in the division information 25 is also referred to as a net stored in the division information 25 or a wiring stored in the division information 25.

  When the division information 25 is generated by the division unit 13, the processing unit 12 acquires the corresponding wiring shape from the arrangement information 23 for the wiring stored in the division information 25. Then, the processing unit 12 generates divided arrangement information 26 that stores the shape of the wiring stored in the division information 25. The division arrangement information 26 is generated for each of the plurality of division information 25. Accordingly, the storage unit 20 stores a plurality of division arrangement information 26 (not shown) corresponding to each of the plurality of division information 25.

  The dividing unit 13 may divide the connection information 21 into divided information 25 by combining a plurality of wirings in descending order of feature values for each of a plurality of systematic failure factor candidates. The characteristic value may be, for example, a value that increases in proportion to the influence of the factor candidate included in the wiring stored in the connection information 21. The magnitude of the influence of the factor candidate is proportional to the number of vias included in the wiring, for example, when the factor candidate is a via in the second to third layers. The influence of the factor candidate is, for example, when the factor candidate is the fifth layer dense wiring, the distance that the wiring passes through the dense wiring area, and the other wiring adjacent to the dense wiring area. Is proportional to the distance. The feature values are also set as appropriate for the features of candidate factors other than the number of vias and the shape of dense wiring. For example, when the feature values of a plurality of factor candidates indicate the same value, the degree of influence of each factor candidate on the failure of the semiconductor device is the same even if the features of the factor candidates are different. Is set to be

FIG. 5 is a diagram for explaining generation of division information.
With reference to FIG. 5, generation of the division information 25 by the division unit 13 will be described. In the following description, it is assumed that 2 million connection relationships (wiring) are stored in the connection information 21. That is, description will be made assuming that the number of wirings included in the semiconductor device is 2 million. In addition, a description will be given of a process in which the dividing unit 13 divides the connection information 21 into a plurality of pieces of division information 25 using a factor candidate whose feature is a via in the second to third layers. For example, the dividing unit 13 divides the connection information 21 into a plurality of pieces of divided information 25 not only for the vias in the second to third layers but also for the factor candidates stored in the factor information 22.

  For example, the dividing unit 13 refers to the arrangement information 23 and obtains the number of passing through the second to third layer vias for each wiring stored in the connection information 21.

  Then, as illustrated in the connection information 21 in FIG. 5, the dividing unit 13 rearranges the wirings stored in the connection information 21 in the descending order of the number of vias in the second to third layers. The connection information 21 shown in FIG. 5 shows only the net IDs included in the net list stored in the connection information 21 for the sake of simplicity of explanation. The net ID is information for identifying the wiring stored in the connection information 21. Therefore, the connection information 21 illustrated in FIG. 5 indicates that the wiring of the net ID 54345 includes 48 vias. In the connection information 21 shown in FIG. 5, the number of vias in the second to third layers is stored in association with the net ID, but in order of increasing number of vias in the second to third layers, If the wirings stored in the connection information 21 are arranged, the connection information 21 may not include the number of vias in the second to third layers. For example, when there is a wiring including the same number of vias in the second and third layers, the dividing unit 13 may arrange the wiring in the order of the net ID.

  Then, for example, the dividing unit 13 may group each 100,000 wirings in the descending order of the number of vias in the second to third layers, and each group may be used as the division information 25. In this case, as illustrated in FIG. 5, the dividing unit 13 divides the connection information 21 into 20 and generates 20 pieces of division information 25-1 to division information 25-20. Note that the number of wirings included in one division information 25 is not limited to 100,000, and may be set as appropriate, for example, increasing in proportion to the number of failure candidate wirings included in each failure information 24. good.

  Similarly, for the other factor candidates, the dividing unit 13 may rearrange the wirings stored in the connection information 21 to divide the connection information 21. For example, as illustrated in FIG. 3, when there are four factor candidates, the dividing unit 13 may divide the connection information 21 into 20 for each factor candidate. In this case, the division unit 13 generates 80 pieces of division information 25.

  Using the failure information 24 and the factor information 22, the selection unit 14 selects, from the failure information 24, the first wiring that has a high possibility of failure for each semiconductor device.

  FIG. 6 is a diagram illustrating an example of a regression equation. FIG. 7 is a diagram showing a failure rate obtained from the result of regression analysis.

  With reference to FIGS. 6 and 7, an example of processing in which the selection unit 14 selects the first wiring will be described. The operations of the calculation unit 15 and the generation unit 16 will also be described together.

  The selection unit 14 selects one failure candidate wiring from each of the plurality of failure information 24. That is, for example, when 100 pieces of failure information 24 are stored in the storage unit 20, the selection unit 14 selects 100 failure candidate wirings.

  Then, the calculation unit 15 calculates a first failure rate indicating the ratio of the plurality of selected failure candidate wirings for each of the plurality of pieces of division information 25 obtained by dividing the connection information 21.

  For example, when 80 pieces of division information 25 are stored in the storage unit 20, the calculation unit 15 calculates 80 first failure rates. When the 100,000 pieces of wiring are stored in the division information 25 and the number of failure candidate wirings selected by the selection unit 14 is 100, the calculation unit 15 selects the same wiring as the 100 failure candidate wirings out of the 100,000 wirings. Search for. For example, when 50 fault candidate wirings are included in 100,000 wirings stored in the division information 25, the calculation unit 15 calculates the first failure rate as 50 / 100,000. Also good. The calculation unit 15 may normalize the value of each first failure rate after obtaining the first failure rate for the plurality of pieces of division information 25.

  Further, for each piece of the division information 25, the calculation unit 15 uses the division arrangement information 26 indicating the arrangement of the wiring corresponding to the division information 25, so that each wiring corresponding to the division information 25 includes a feature that causes a failure. A feature value indicating the degree is calculated for a plurality of factor candidates.

  For example, the feature value indicating the degree to which a failure factor is included in each wiring corresponding to the division information 25 increases in proportion to the influence of the factor candidate included in the wiring stored in the division information 25. Value may be used.

  The magnitude of the influence of the factor candidate is proportional to the number of vias included in the wiring, for example, when the factor candidate is a via in the second to third layers. The influence of the factor candidate is, for example, when the factor candidate is the fifth layer dense wiring, the distance that the wiring passes through the dense wiring area, and the other wiring adjacent to the dense wiring area. Is proportional to the distance. The feature values are also calculated as appropriate for the features of candidate factors other than the number of vias and the shape of dense wiring. For example, when the feature values of a plurality of factor candidates indicate the same value, the degree of influence of each factor candidate on the failure of the semiconductor device is the same even if the features of the factor candidates are different. Is set to be

  As illustrated in FIG. 6, the generation unit 16 generates a regression equation indicating the relationship between the first failure rate y and the value obtained by adding the contribution w to each calculated feature value x for each piece of the division information 25. For example, when 80 pieces of division information 25 are stored in the storage unit 20, the generation unit 16 generates 80 regression equations (1) to (80).

  The first failure rate y and the feature value x are values calculated by the calculation unit 15, respectively. The first failure rate is calculated for each division information 25. In addition, as many feature values as the number of factor candidates stored in the factor information 22 are calculated for each piece of division information 25. When the factor information 22 is the factor information 22 shown in FIG. 3, the calculation unit 15 calculates four feature values for each piece of divided information 25. Further, the contribution degree w is a variable that is given to the feature value x of each factor candidate and the value is obtained by regression analysis. The contribution degree w indicates the strength of the influence on the failure of the semiconductor device. Therefore, the factor candidate is determined to be a factor candidate that has a stronger influence on increasing the failure rate y of the semiconductor device as the value of the contribution w given to the feature value x of the factor candidate obtained by regression analysis is higher. The That is, if the feature value x of a factor candidate having a high contribution w obtained by regression analysis is increased by changing the design or process, the feature value x of a factor candidate having a low contribution w obtained by regression analysis is increased. Rather than doing so, the possibility of failure of the semiconductor device is increased. C is a summary of the degree of influence of neglected factor candidates because the influence of the failure on the semiconductor device is small. C is, for example, a disturbance term for regression analysis.

  And the calculation part 15 calculates the contribution corresponding to each factor candidate by performing regression analysis using the produced | generated several regression formula.

  Further, the calculation unit 15 calculates a determination coefficient indicating a correlation between the first failure rate and the second failure rate obtained using the calculated contribution.

With reference to FIG. 7, the second failure rate obtained using the contribution will be described.
The regression equation (1) shown in FIG. 7 corresponds to, for example, the regression equation (1) shown in FIG. However, the second failure rate may be calculated using any one of the other regression equations (2) to (n). In addition, it is assumed that the first failure rate in the regression equation (1) is normalized. In the regression equation (1), for example, 80 as the first failure rate y1, 30 as the feature value x11, 20 as the feature value x12, 10 as the feature value x13, and 40 as the feature value x14 of the division information 25-1. Assume that it is assigned. Note that the value substituted into the regression equation (1) is calculated using, for example, the first wiring selected one by one from the plurality of failure information 24, the division information 25-1, and the division arrangement information 26. This is the value calculated by the unit 15.

  As a result of the regression analysis using the regression equation (1) shown in FIG. 7, the calculation unit 15 has a contribution w1 = 0.9, a contribution w2 = 1.0, a contribution w3 = 1.0, and a contribution w4 = Assume that 0.5 is calculated. At this time, the second failure rate is, for example, a value obtained by substituting the contribution calculated by the regression analysis into the regression equation (1). In this case, the second failure rate is 77 shown in the regression equation (1 ′).

  The determination coefficient is a value close to 1 when the selection of the failure candidate wiring selected from the plurality of pieces of failure information 24 by the selection unit 14 is appropriate and the degree of coincidence between the first failure rate and the second failure rate increases. Set it. For example, the determination coefficient may be a value obtained by substituting the first failure rate and the second failure rate into a predetermined formula. The determination coefficient may be calculated by, for example, a determination coefficient calculation formula used in regression analysis.

  That is, the determination coefficient is a value that approaches 1 when the degree of coincidence between the first failure rate based on the actual measurement value and the second failure rate based on the result of the regression analysis increases. The equation fits well, indicating that the contribution obtained as a result of the regression analysis is highly reliable.

  Then, the selection unit 14 repeatedly performs a process of selecting a failure candidate wiring so that the calculated determination coefficient is high, and selects a failure candidate wiring having a high determination coefficient as the first wiring.

  An example of a process of selecting a failure candidate wiring having a high determination coefficient as the first wiring by the selection unit 14 will be described.

  The selection unit 14 selects failure candidate wirings one by one from the plurality of failure information 24. When the selection unit 14 selects a combination of failure candidate wirings, the generation unit 16 generates a regression equation using the selected failure candidate wirings. When the generation unit 16 generates a regression equation, the calculation unit 15 calculates a determination coefficient by regression analysis. The failure analysis apparatus 1 repeatedly executes a selection process by the selection unit 14, a generation process by the generation unit 16, and a calculation process by the calculation unit 15. Then, the selection unit 14 may detect a combination of failure candidate wirings having the highest determination coefficient, and select a failure candidate wiring included in the combination as the first wiring from each failure information 24.

  The selection unit 14 may use an annealing method or a hill-climbing method when selecting candidate failure wirings one by one from the plurality of failure information 24 in order to reduce the processing burden in the process of selecting the first wiring. .

  The specifying unit 17 uses a first wiring selected by the selection unit 14 to select a factor candidate corresponding to a contribution showing a high value among a plurality of contributions obtained by performing regression analysis as a systematic failure. Specific to the factors. For example, as illustrated in FIG. 8, the specifying unit 17 specifies the factor candidate 4 as a failure factor when the contribution degree of each factor candidate is obtained. In FIG. 8, the factor candidate 4 has a higher contribution than the factor candidates 1 to 3. Therefore, when the feature value corresponding to the feature of the factor candidate 4 increases, the possibility that the semiconductor device will fail becomes higher than when the feature values corresponding to the features of the factor candidates 1 to 3 increase.

  The specifying unit 17 may specify a candidate factor having a contribution level equal to or greater than a predetermined threshold as a failure factor. For example, when the predetermined threshold is the contribution level 30, as illustrated in FIG. 8, the specifying unit 17 specifies the candidate factor 1 and the candidate factor 4 as failure factors when the contribution level of each candidate factor is obtained.

  Furthermore, the specifying unit 17 may specify a plurality of factor candidates as failure factors in descending order of contribution. For example, when specifying the two factor candidates in the descending order of contribution as failure factors, the specifying unit 17 determines the candidate factors 1 and 4 as shown in FIG. Is specified as a failure factor.

  As illustrated in FIG. 9, the identification unit 17 stores the identified systematic failure factor in the identification information 27. FIG. 9 shows an example of the specific information 27. The factor ID is information for identifying the specified failure factor. The feature is information indicating the configuration of the specified failure factor. The state is information indicating the state of the specified failure factor.

  Further, the specifying unit 17 ends the specification of the failure factor when the determination coefficient obtained by performing the regression analysis using the first wiring selected by the selecting unit 14 is equal to or less than a predetermined threshold. good. The predetermined threshold value may be set such that the reliability of the regression equation is maintained, for example, the determination coefficient is set to 0.5.

  And the specific | specification part 17 outputs the cause of the specified systematic failure, when the cause of a systematic failure is specified. Further, the specifying unit 17 may output the cause of the systematic failure stored in the specifying information 27 when the specification of the cause of the systematic failure is completed. For example, the specifying unit 17 may output a failure factor to the storage unit 20 or a display device 407 described later.

  The extraction unit 18 extracts, from the plurality of pieces of failure information 24, second wirings that make the output of the semiconductor device the same as the output when the first wiring fails, when a failure occurs. When extracting the second wiring, for example, the extraction unit 18 searches the connection information 21 and extracts a failure candidate wiring having a failure difference function that matches the failure difference function of the selected first wiring as the second wiring. Also good. In addition, when the connection information 21 includes a plurality of failure candidate wirings having a failure difference function that matches the failure difference function of the selected first wiring, the extraction unit 18 extracts the plurality of failure candidate wirings as the second wiring. May be. That is, the second wiring is a failure candidate wiring that is detected along with the failure of the first wiring in the logical fault diagnosis even if the second wiring is not faulty when the first wiring fails. .

FIG. 10 is a diagram for explaining extraction of accompanying failure candidate wirings using a failure difference function.
With reference to FIG. 10, the process of extracting the second wiring using the failure difference function will be described. In the logic circuit 300 shown in FIG. 10, wirings 1 to 3 are wirings corresponding to net ID1 to net ID3 stored in the failure information 24 shown in FIG. Note that the FF 301 to FF 303 may be scan flip-flops. Further, x1 is a signal output from the FF 301. x2 is a signal output from the FF 302.

  When the selection unit 14 selects the wiring 1 corresponding to the net ID 1 of the failure information 24 as the first wiring, the extraction unit 18 obtains a failure difference function = x1 + x2 assuming that the wiring 1 has a 0 stuck-at fault. Further, the extraction unit 18 obtains a failure difference function = x1 + x2 assuming that the wiring 2 has a 0 stuck-at fault. Further, the extraction unit 18 obtains a failure difference function = notx1 · x2 assuming that the wiring 3 has a 0 stuck-at fault. Then, since the wiring 1 and the wiring 2 have the same failure difference function, the extraction unit 18 uses the second wiring detected as a failure candidate wiring in association with the failure of the first wiring in the logical fault diagnosis. The wiring 2 is extracted.

  In the above description, since the 0 stuck-at fault is stored in the record corresponding to the wiring 1 to the wiring 3 of the fault information 24 shown in FIG. Seeking a function. When other types of faults other than 0 stuck-at fault are stored in the records corresponding to the wiring 1 to the wiring 3 of the fault information 24 shown in FIG. 10, the extraction unit 18 displays other types of faults stored. A fault difference function may be obtained assuming each wiring.

  The deletion unit 19 deletes the first wiring selected by the selection unit 14 and the second wiring extracted by the extraction unit 18 from the plurality of pieces of failure information 24, respectively.

  Then, the processing unit 12 uses the failure information 24 from which the first wiring and the second wiring are deleted, to the selection unit 14, the specifying unit 17, the extraction unit 18, and the deletion unit 19, respectively. And a process for executing a specific process, an extraction process, and a deletion process.

  As described above, the failure analysis apparatus 1 according to the embodiment specifies a dominant failure factor using the failure candidate wiring (first wiring) that is highly likely to have a failure included in the failure information 24. Furthermore, the failure analysis apparatus 1 deletes the failure candidate information (second wire) associated with the failure of the first wiring and the first wiring from the failure information, and specifies the failure factor again. Thereby, the failure analysis apparatus 1 can specify not only a failure factor due to the failure of the first wiring but also other failure factors.

  Therefore, the user can improve the yield of semiconductor devices by referring to a plurality of failure factors specified by the failure analysis apparatus 1 and designing with consideration of failure factors other than the dominant failure factors. .

11 to 13 are flowcharts showing processing for specifying a failure factor.
With reference to FIG. 11 to FIG. 13, a process in which the failure analysis apparatus 1 shown in FIG. 1 identifies a failure factor will be described.

This will be described with reference to FIG.
The dividing unit 13 divides the connection information 21 and generates a plurality of pieces of division information 25 (S101). For example, the division processing described with reference to FIG. 5 may be used for the processing of S101. Then, the processing unit 12 generates divided arrangement information 26 corresponding to each of the plurality of pieces of division information 25.

  The selection unit 14 selects failure candidate wirings one by one from the plurality of failure information 24 (S102).

  The calculation unit 15 calculates a first failure rate indicating the ratio of the selected plurality of failure candidate wirings for each of the plurality of pieces of division information 25 obtained by dividing the connection information 21 (S103).

  For each piece of division information 25, the calculation unit 15 uses the factor information 22 and the division arrangement information 26 to calculate a feature value indicating the degree of factor candidates included in each wiring stored in the division information 25. Each factor candidate stored in 22 is calculated (S104).

  The generation unit 16 generates a regression equation indicating the relationship between the calculated first failure rate and the value obtained by adding the contribution to the calculated feature value for each piece of the division information 25 (S105).

  The calculation unit 15 calculates the contribution corresponding to each factor candidate by performing regression analysis using the plurality of generated regression equations (S106).

  The calculation unit 15 calculates a determination coefficient indicating the correlation between the first failure rate and the second failure rate obtained using the calculated contribution (S107).

  In S201, which will be described later, the selection unit 14 determines whether or not the determination coefficient calculated in S107 is larger than the determination coefficient held until the previous time (S108). When the determination coefficient calculated in S107 is larger than the determination coefficient held until the previous time (Yes in S108), the selection unit 14 executes the process of S201. In addition, when the determination coefficient calculated in S107 is equal to or less than the determination coefficient held until the previous time (No in S108), the selection unit 14 executes the process of S202.

This will be described with reference to FIG.
The selection unit 14 holds the combination of failure candidate wirings selected in S102 or S203 described later and the determination coefficient immediately before (S201). At this time, the selection unit 14 may overwrite and update the combination of failure candidate wirings and the determination coefficient currently held with the combination of failure candidate wirings and the determination coefficient held so far. Accordingly, the selection unit 14 can search for a combination of failure candidate wirings that has a high determination coefficient calculated by regression analysis. The selection unit 14 may store the combination of failure candidate wirings and the determination coefficient in the storage unit 20 or may be stored in a cache area included in the control unit 10.

  The selection unit 14 determines whether or not all combinations of failure candidate wirings to be selected one by one from the plurality of pieces of failure information 24 have been selected (S202). The selection unit 14 selects one of the selected failure candidate wirings when not selecting all the combinations of failure candidate wirings to be selected one by one from the plurality of failure information 24 (No in S202). Change (S203) and execute the process of S103. For example, the selection unit 14 holds the combinations of failure candidate wirings selected up to the previous time, and in S203, the combination of failure candidate wirings selected up to the previous time is different from the combination of failure candidate wirings selected this time. In addition, one of the failure candidate wirings may be changed. In S203, the selection unit 14 may change one of the failure candidate wirings using an annealing method or a hill climbing method. In this case, in S202, the selection unit 14 predicts that the maximum determination coefficient is obtained even if all combinations are not selected for the combination of failure candidate wirings to be selected one by one. If obtained, the process of S204 described later may be executed.

  When the selection unit 14 selects all the combinations of failure candidate wirings that are selected one by one from the plurality of pieces of failure information 24 (Yes in S202), the specifying unit 17 determines that the determination coefficient held last is a predetermined value. It is determined whether it is larger than the threshold value (S204).

  When it is determined that the determination coefficient last retained by the specifying unit 17 is greater than the predetermined threshold (Yes in S204), the selection unit 14 generates a combination of failure candidate wirings related to the retained determination coefficient in S105. It is determined that the regression equation is fit. Then, the selection unit 14 selects each of the failure candidate wirings included in the combination of the guaranteed candidate wirings held last as the first wiring having a high possibility of failure (S205). The good fit of the regression equation means that the reliability of the contribution obtained from the result of the regression equation is high. Therefore, the specifying unit 17 can specify the failure factor with high accuracy in S206 in which the failure factor is specified using the contribution described later.

  The specifying unit 17 uses the first wiring to specify, as a failure factor, a factor candidate corresponding to a contribution value showing a high value among contribution factors corresponding to a plurality of factor candidates calculated by the regression analysis of S105. (S206).

  The identifying unit 17 outputs the identified failure factor (S207). Further, the specifying unit 17 stores the specified failure factor in the specified information 27 every time the failure factor is specified, and stores it in the specified information 27 when it is determined in S204 that the specification of the cause of the systematic failure is finished. It is also possible to output the determined failure factor.

This will be described with reference to FIG.
The extraction unit 18 searches the connection information 21 and extracts the second wiring having the same fault difference function as the fault difference function of the first wiring from the plurality of fault information 24 (S301). That is, the extraction unit 18 extracts, from the plurality of pieces of failure information 24, second wirings that make the output of the semiconductor device the same output as the output when the first wiring fails, when a failure occurs.

  The deletion unit 19 determines whether or not the second wiring is extracted in S301 (S302).

  When the second wiring is extracted in S301 (Yes in S302), the deletion unit 19 deletes the first wiring and the second wiring from the plurality of pieces of failure information 24 (S303).

  And the process part 12 updates each failure information 24 to the failure information 24 which deleted the 1st wiring and the 2nd wiring, and performs the process of S102 (S304).

  When the second wiring is not extracted in S301 (No in S302), the deletion unit 19 deletes the first wiring from the plurality of pieces of failure information 24 (S305).

  And the process part 12 updates each failure information 24 to the failure information 24 which deleted the 1st wiring, and performs the process of S102 (S306).

This will be described with reference to FIG.
In S204, when it is determined that the last stored determination coefficient is equal to or less than the predetermined threshold (No in S204), the specifying unit 17 generates the regression equation generated in S105 for the combination of failure candidate wirings related to the stored determination coefficient. It is determined that is not true. Then, the specifying unit 17 finishes specifying the cause of the systematic failure. Note that the poor fit of the regression equation means that the reliability of the contribution obtained from the result of the regression equation is low. Therefore, when the regression equation is not well applied, the specifying unit 17 cannot specify the cause of the failure with high accuracy in S206, and thus ends the specification of the cause of the systematic failure.

FIG. 14 is a block diagram illustrating an embodiment of a computer device.
With reference to FIG. 14, the structure of the failure analysis apparatus 1 will be described.

  14, a computer device 400 includes a control circuit 401, a storage device 402, a reading device 403, a recording medium 404, a communication interface 405 (communication I / F), and an input / output interface 406 (input / output I / F). ), A display device 407, and a network 408. Each component is connected by a bus 409.

  The control circuit 401 controls the entire computer device 400. The control circuit 401 is, for example, a CPU, a multi-core CPU, an FPGA (Field Programmable Gate Array), a PLD (Programmable Logic Device), or the like. For example, the control circuit 401 functions as the control unit 10 in FIG. Note that the connection information 21, the factor information 22, the arrangement information 23, the failure information 24, the division information 25, the division arrangement information 26, and the specific information 27 included in the storage unit 20 are, for example, CPU, FPGA. And may be stored in the PLD cache.

  The storage device 402 stores various data. The storage device 402 includes, for example, a memory such as a ROM (Read Only Memory) and a RAM (Random Access Memory), an HD (Hard Disk), and the like. For example, the storage device 402 functions as the storage unit 20 in FIG. The storage device 402 includes, for example, the connection information 21, the factor information 22, the arrangement information 23, the failure information 24, the division information 25, the division arrangement information 26, and the specific information 27 illustrated in FIG. You may remember.

  The ROM stores a program such as a boot program. The RAM is used as a work area for the control circuit 401. The HD stores an OS, an application program, a program such as firmware, and various data.

  For example, the storage device 402 stores a failure analysis program that causes the control circuit 401 to function as the control unit 10.

  When performing the failure analysis processing, the failure analysis device 1 reads the failure analysis program stored in the storage device 402 into the RAM. Then, the failure analysis apparatus 1 executes the failure analysis processing by executing the failure analysis program read into the RAM by the control circuit 401.

  Note that the failure analysis program may be stored in a storage device included in a server on the network 408 as long as the control circuit 401 can be accessed via the communication interface 405.

  The reading device 403 is controlled by the control circuit 401 to read / write data on the removable recording medium 404. The reading device 403 includes, for example, an FDD (Floppy Disk Drive), a CDD (Compact Disc Drive), a DVDD (Digital Versatile Disk Drive), a BDD (Blu-ray (registered trademark) Disc UsU) Etc.

  The recording medium 404 stores various data. The recording medium 404 stores a failure analysis program, for example. Further, the recording medium 404 stores the connection information 21, the factor information 22, the arrangement information 23, the failure information 24, the division information 25, the division arrangement information 26, and the specific information 27 shown in FIG. May be.

  The recording medium 404 is connected to the bus 409 via the reading device 403, and the control circuit 401 controls the reading device 403 so that data is read / written. The recording medium 404 is, for example, an FD (Floppy Disk), a CD (Compact Disc), a DVD (Digital Versatile Disk), a BD (Blu-ray (registered trademark) Disk), and a flash memory.

  The communication interface 405 connects the computer apparatus 400 and other apparatuses via the network 408 so that they can communicate with each other.

  The input / output interface 406 is connected to, for example, a keyboard, a mouse, a touch panel, and the like. When a signal indicating various information is input from the connected device, the input signal is output to the control circuit 401 via the bus 409. To do. When a signal indicating various information output from the control circuit 401 is input via the bus 409, the input / output interface 406 outputs the signal to various connected devices. For example, the input / output interface 406 functions as the input / output unit 30 in FIG.

  The display device 407 is connected to the input / output interface 406, for example, and displays various types of information. For example, the display device 407 displays the failure factor specified by the specifying unit 17.

  The network 408 is, for example, a LAN, wireless communication, the Internet, or the like, and connects the computer apparatus 400 and other apparatuses for communication.

  As described above, the failure analysis apparatus 1 according to the embodiment specifies the failure factor using the first wiring that is highly likely to be broken, and the second wiring associated with the failure of the first wiring and the first wiring. Is deleted from the failure information 24 and the cause of the failure is identified again. Thereby, the failure analysis apparatus 1 can specify a plurality of factors of the systematic failure. Therefore, the user can improve the yield of semiconductor devices by designing in consideration of failure factors other than dominant failure factors.

  When the failure analysis apparatus 1 according to the embodiment extracts the second wiring from the failure information 24, the failure analysis apparatus 1 extracts the failure candidate wiring having the same failure difference function as the failure difference function of the first wiring that has a high possibility of failure as the second wiring. Extract as As a result, when the first wiring fails, the failure analysis apparatus 1 can extract the second wiring that is determined to be accompanied by the failure by the logic diagnosis. Therefore, the failure analysis apparatus 1 analyzes the cause of the failure again using the failure information 24 in which the first wiring and the second wiring are deleted, thereby eliminating the influence of the second wiring accompanying the failure of the first wiring. Therefore, it is possible to improve the accuracy of identifying the cause of failure.

  The failure analysis apparatus 1 according to the embodiment ends the identification of the cause of the systematic failure when the determination coefficient obtained by the regression analysis is equal to or less than a predetermined threshold value. As a result, the failure analysis apparatus 1 analyzes the failure factor using a well-equipped regression equation, so that the accuracy of identifying the failure factor can be improved.

  In addition, this embodiment is not limited to embodiment described above, A various structure or embodiment can be taken in the range which does not deviate from the summary of this embodiment.

The following additional notes are further disclosed with respect to the embodiments including the examples described above. Note that the present invention is not limited to the following supplementary notes.
(Appendix 1)
Using the failure information indicating the failure candidate wiring that may have failed for each of the plurality of semiconductor devices and the factor information indicating the plurality of cause candidates that may cause systematic failure, the failure information is included in the failure information. The first wiring that is likely to be selected is selected for each of the semiconductor devices,
Among the contributions indicating the strength of the influence on the failure of the semiconductor device corresponding to the plurality of candidate factors of the systematic failure obtained by performing regression analysis using the selected first wiring, Identifying a factor candidate corresponding to a contribution indicating a value as a factor of the systematic failure,
From the failure information, for each semiconductor device, a failure simulation result when the first wiring is assumed to have failed and a second wiring that is the same failure simulation result when a failure is assumed are extracted for each semiconductor device;
Deleting the first wiring and the second wiring from the failure information;
Using the failure information of each semiconductor device from which the first wiring and the second wiring are deleted, execute the selection process, the specific process, the extraction process, and the deletion process on a computer Failure analysis program
(Appendix 2)
In the process of extracting the second wiring,
Search connection information indicating a connection relationship of a plurality of elements included in the semiconductor device,
The failure analysis program according to appendix 1, which causes a computer to execute a process of extracting the second wiring having a failure difference function that matches the failure difference function of the selected first wiring.
(Appendix 3)
In the process of identifying the cause of the systematic failure,
The failure analysis program according to appendix 1 or 2, which causes a computer to execute a process of ending the identification of the cause of the systematic failure when a determination coefficient obtained by the regression analysis is equal to or less than a predetermined threshold.
(Appendix 4)
In the process of selecting the first wiring,
Dividing connection information indicating a connection relation of a plurality of elements included in the semiconductor device;
Select one failure candidate wiring from each of the failure information of each semiconductor device,
For each of a plurality of pieces of division information obtained by dividing the connection information, a first failure rate indicating a ratio including a connection relationship corresponding to the selected plurality of failure candidate wirings is calculated,
For each of the pieces of division information, the division arrangement information indicating the arrangement of the wiring corresponding to the division information is used to indicate the degree to which the feature that causes the systematic failure is included in each wiring corresponding to the division information. A value is calculated for a plurality of candidate factors for the systematic failure;
A regression equation indicating a relationship between the calculated first failure rate and a value obtained by adding a contribution to the calculated feature value is generated for each of the division information,
By performing regression analysis using the generated plurality of regression equations, the degree of contribution corresponding to each factor candidate is calculated,
Calculating a determination coefficient indicating a correlation between the first failure rate and the second failure rate obtained using the calculated contribution,
Supplementary notes 1 to 1 for repeatedly executing the process of selecting the failure candidate wiring so that the calculated determination coefficient is high, and selecting the failure candidate wiring having the high determination coefficient as the first wiring. 4. The failure analysis program according to any one of 3.
(Appendix 5)
In the process of dividing the connection information,
Using the layout information indicating the layout of the wiring corresponding to the connection information, a feature value indicating the degree to which the feature that causes the systematic failure is included for each of the wirings of the semiconductor device. For multiple candidate factors,
The failure analysis program according to appendix 4, wherein the computer executes a process of dividing the connection information into the division information by combining a plurality of wirings in descending order of the characteristic value for each of the plurality of factor candidates of the systematic failure .
(Appendix 6)
The failure analysis program according to appendix 3, which causes a computer to execute a process of outputting the cause of the systematic failure when the cause of the systematic failure is specified.
(Appendix 7)
Using the failure information indicating the failure candidate wiring that may have failed for each of the plurality of semiconductor devices and the factor information indicating the plurality of cause candidates that may cause systematic failure, the failure information is included in the failure information. A selection unit that selects one of the first wirings that is highly likely to be performed for each semiconductor device;
Among the contributions indicating the strength of the influence on the failure of the semiconductor device corresponding to the plurality of factor candidates of the systematic failure obtained by performing regression analysis using the first wiring selected by the selection unit Then, a specific part that identifies a factor candidate corresponding to a contribution value showing a high value as a factor of the systematic failure, and
An extraction unit that extracts, for each semiconductor device, a second simulation wiring that has a failure simulation result when the first wiring is assumed to have failed and the same failure simulation result when the failure is assumed. When,
A deletion unit for deleting the first wiring and the second wiring from the failure information;
A processing unit that executes the selection process, the specifying process, the extracting process, and the deleting process using failure information of each semiconductor device from which the first wiring and the second wiring are deleted When,
A failure analysis apparatus comprising:
(Appendix 8)
A failure analysis method executed by a computer,
The computer
Using the failure information indicating the failure candidate wiring that may have failed for each of the plurality of semiconductor devices and the factor information indicating the plurality of cause candidates that may cause systematic failure, the failure information is included in the failure information. The first wiring that is likely to be selected is selected for each of the semiconductor devices,
Among the contributions indicating the strength of the influence on the failure of the semiconductor device corresponding to a plurality of factor candidates of the systematic failure obtained by performing regression analysis using the selected first wiring, Identifying a factor candidate corresponding to a contribution indicating a value as a factor of the systematic failure,
From the failure information, for each semiconductor device, a failure simulation result when the first wiring is assumed to have failed and a second wiring that is the same failure simulation result when a failure is assumed are extracted for each semiconductor device;
Deleting the first wiring and the second wiring from the failure information;
Failure to execute the selection process, the specific process, the extraction process, and the deletion process using the failure information of each semiconductor device from which the first wiring and the second wiring are deleted analysis method.

DESCRIPTION OF SYMBOLS 1 Failure analysis apparatus 2 Wafer 10 Control part 11 Acquisition part 12 Processing part 13 Dividing part 14 Selection part 15 Calculation part 16 Generation part 17 Fixed part 18 Extraction part 19 Deletion part 20 Storage part 21 Connection information 22 Factor information 23 Arrangement information 24 Each Failure information 24 Failure information 25 Each division information 25 Division information 26 Division arrangement information 27 Specific information 30 Input / output unit 31 Input unit 32 Output unit 300 Logic circuit 400 Computer device 401 Control circuit 402 Storage device 403 Reading device 404 Recording medium 405 Communication interface 406 I / O interface 407 Display device 408 Network 409 Bus

Claims (5)

Using the failure information indicating the failure candidate wiring that may have failed for each of the plurality of semiconductor devices and the factor information indicating the plurality of cause candidates that may cause systematic failure, the failure information is included in the failure information. The first wiring that is likely to be selected is selected for each of the semiconductor devices,
Among the contributions indicating the strength of the influence on the failure of the semiconductor device corresponding to a plurality of factor candidates of the systematic failure obtained by performing regression analysis using the selected first wiring, Identifying a factor candidate corresponding to a contribution indicating a value as a factor of the systematic failure,
From the failure information, for each semiconductor device, a failure simulation result when the first wiring is assumed to have failed and a second wiring that is the same failure simulation result when a failure is assumed are extracted for each semiconductor device;
Deleting the first wiring and the second wiring from the failure information;
Using the failure information of each semiconductor device from which the first wiring and the second wiring are deleted, execute the selection process, the specific process, the extraction process, and the deletion process on a computer Failure analysis program In the process of extracting the second wiring,
Search connection information indicating a connection relationship of a plurality of elements included in the semiconductor device,
The failure analysis program according to claim 1, wherein the computer executes a process of extracting the second wiring having a failure difference function that matches a failure difference function of the selected first wiring. In the process of identifying the cause of the systematic failure,
The failure analysis program according to claim 1 or 2, wherein when the determination coefficient obtained by the regression analysis is equal to or less than a predetermined threshold value, the computer executes a process of ending the identification of the cause of the systematic failure. Using the failure information indicating the failure candidate wiring that may have failed for each of the plurality of semiconductor devices and the factor information indicating the plurality of cause candidates that may cause systematic failure, the failure information is included in the failure information. A selection unit that selects one of the first wirings that is highly likely to be performed for each semiconductor device;
Among the contributions indicating the strength of the influence on the failure of the semiconductor device corresponding to the plurality of factor candidates of the systematic failure obtained by performing regression analysis using the first wiring selected by the selection unit Then, a specific part that identifies a factor candidate corresponding to a contribution value showing a high value as a factor of the systematic failure, and
An extraction unit that extracts, for each semiconductor device, a second simulation wiring that has a failure simulation result when the first wiring is assumed to have failed and the same failure simulation result when the failure is assumed. When,
A deletion unit for deleting the first wiring and the second wiring from the failure information;
A processing unit that executes the selection process, the specifying process, the extracting process, and the deleting process using failure information of each semiconductor device from which the first wiring and the second wiring are deleted When,
A failure analysis apparatus comprising: A failure analysis method executed by a computer,
The computer
Using the failure information indicating the failure candidate wiring that may have failed for each of the plurality of semiconductor devices and the factor information indicating the plurality of cause candidates that may cause systematic failure, the failure information is included in the failure information. The first wiring that is likely to be selected is selected for each of the semiconductor devices,
Among the contributions indicating the strength of the influence on the failure of the semiconductor device corresponding to a plurality of factor candidates of the systematic failure obtained by performing regression analysis using the selected first wiring, Identifying a factor candidate corresponding to a contribution indicating a value as a factor of the systematic failure,
From the failure information, for each semiconductor device, a failure simulation result when the first wiring is assumed to have failed and a second wiring that is the same failure simulation result when a failure is assumed are extracted for each semiconductor device;
Deleting the first wiring and the second wiring from the failure information;
Failure to execute the selection process, the specific process, the extraction process, and the deletion process using the failure information of each semiconductor device from which the first wiring and the second wiring are deleted analysis method.

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