JP2015169452A - Semiconductor appearance inspection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which in conjunction with fineness of a wafer of an inspection object, measures have to be taken by increasing the number of processor elements, and the semiconductor appearance inspection device which has to attain low costs by holding down non-inspection areas from image data to reduce position deviation processing loads of the processor elements and suppressing increase in image processing hardware quantity can be a high-costed device.SOLUTION: A semiconductor appearance inspection device 99 has: an image detection unit 8 that detects image data 12 on a wafer 2 from a sensor 5; an amount-of-characteristic calculation unit 13 that calculates an amount of characteristic of the detected image data 12; an image data cut-out unit 17 that sets an inspection area of the image data 12 on the basis of the calculated amount of characteristic; a transmission control unit 19 that transmits transmission data 23 including the set inspection area of the image data 12; and a processor element that uses the transmitted transmission data 23 to perform defect determination processing of the wafer 2.

Description

  The present invention relates to a semiconductor appearance inspection apparatus.

  As a background art of this technical field, there is Japanese Patent No. 4016472 (Patent Document 1). In Patent Document 1, as a problem, “by correcting a non-stationary misalignment existing in two images to be compared, and correcting a difference in brightness that occurs in a portion to be recognized as a normal portion, There is provided a visual inspection method and apparatus capable of detecting minute defects with high reliability without causing false detection, "and as a solution means," Patterns that should be essentially the same in two detected images to be compared " In other words, even if there is a light / dark difference in a portion having no defect, the light / dark correction is performed so that the light / dark difference is small enough to be recognized as a normal part. Is corrected so that the brightness of each of the corresponding areas is substantially equal. "

Japanese Patent No. 4016472

  The above-mentioned patent document 1 describes a mechanism for reducing the probability of false detection by correcting a difference in density and performing alignment according to the degree of distortion, thereby realizing a highly reliable inspection. It can be done ".

  However, the image processing apparatus disclosed in Patent Document 1 has to cope with improvement in reliability by increasing the number of processor elements as the wafer to be inspected is miniaturized. Therefore, for example, there has been a problem that the cost of the apparatus increases due to an increase in the number of processor elements.

  Therefore, the present invention provides a semiconductor appearance inspection apparatus including a feature amount calculation unit that calculates a feature amount from image data and an image data cutout unit that extracts an inspection region from image data using the feature amount. In addition, by suppressing non-inspection areas from image data, it is possible to reduce the processing load on misalignment of processor elements and to suppress the increase in the amount of image processing hardware, which is excellent in terms of cost reduction and low power consumption of semiconductor visual inspection equipment. A semiconductor visual inspection apparatus is provided.

  In order to solve the above problems, for example, the configuration described in the claims is adopted.

  According to the present invention, the non-inspection area is suppressed from the image data, thereby reducing the processing shift of the position shift of the processor element, suppressing the increase in the amount of image processing hardware, and realizing the cost reduction of the semiconductor appearance inspection apparatus.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

Configuration diagram of semiconductor visual inspection apparatus of embodiment 1 FIG. 3 is a configuration diagram of a feature amount calculation unit according to the first embodiment. Configuration diagram of misregistration detection unit of Embodiment 1 Flowchart for explaining the processing of the misalignment detection unit of the first embodiment. Schematic diagram illustrating the processing of the misalignment detection unit of the first embodiment. The schematic diagram which showed the image detection process in the semiconductor appearance inspection apparatus of Example 1 The schematic diagram which showed the process of the image data cutout part of Example 1 FIG. 3 is a diagram illustrating a transmission control unit according to the first embodiment. Flowchart of image processing of embodiment 1 FIG. 6 is a diagram for explaining the data flow of image distribution control and image processing according to the first embodiment. The figure which shows GUI2400 displayed on the central control part 33 of Example 1. FIG. Configuration diagram of conventional semiconductor visual inspection equipment The schematic diagram which showed the image detection process in the conventional semiconductor appearance inspection apparatus. The figure explaining the data flow of the image distribution control of the conventional semiconductor appearance inspection apparatus, and image processing In the conventional semiconductor visual inspection equipment, a diagram configured to prevent fatal errors as the equipment Configuration diagram of semiconductor appearance inspection apparatus of embodiment 2 FIG. 6 is a diagram illustrating a feature amount calculation unit corresponding to a second plurality of image sensors according to the second embodiment. FIG. 6 is a diagram illustrating a feature amount calculation unit corresponding to a plurality of image sensors according to the second embodiment. The figure explaining the position shift detection part of Example 2. Configuration diagram of a semiconductor visual inspection apparatus using a plurality of conventional image sensors Configuration diagram of semiconductor appearance inspection apparatus of embodiment 3 The figure explaining the feature-value calculation part of Example 3. FIG. 6 is a diagram illustrating a misalignment detection unit according to the third embodiment. 10 is a flowchart of processing for calculating a positional deviation amount in a positional deviation detection unit according to the third embodiment. Schematic diagram of misregistration amount calculation processing in the misregistration detection unit of Embodiment 3 Schematic diagram of image detection processing in the semiconductor appearance inspection apparatus of Example 3 Configuration diagram of semiconductor visual inspection apparatus of embodiment 4

  Hereinafter, examples will be described with reference to the drawings.

  In this embodiment, semiconductor non-inspection area is reduced from the image data, thereby reducing the processing load on the position of PE and suppressing the increase in the amount of image processing hardware, thereby reducing the cost of the semiconductor appearance inspection apparatus. An example of the apparatus will be described.

  FIG. 1 is an example of a configuration diagram of a semiconductor appearance inspection apparatus according to the present embodiment.

  The semiconductor appearance inspection apparatus 99 includes an XY stage 1, a wafer 2, an objective lens 4, an image sensor 5, an aggregating lens 6, a light source 7, an image detection unit 8, an A / D converter 11, a feature amount calculation unit 13, and image data extraction. Unit 17, transmission control unit 19, wafer coordinate table 22, image processing device 25, data distribution control unit 38, path switch 26, first processor element 27, second processor element 28, nth processor element 29, result An output unit 30, a central control unit 33, and a scan control unit 34 are included.

  The central control unit 33 includes a GUI (Graphical User Interface) (not shown) and has a function of controlling the entire apparatus in response to an operator instruction. As the GUI, a display monitor of a personal computer, input means such as a keyboard and a mouse are generally used. The GUI control target is necessary for, for example, controlling the inspection sequence, classifying the defect information after the inspection based on the feature quantity, confirming the detected defect, creating the inspection recipe, and operating the apparatus. There are utility controls, etc.

  The scan control unit 34 receives an instruction from the central control unit 33, generates two-dimensional coordinates for scanning the electron beam of the scanning electron microscope, and performs stage operation with the stage control signal 35 for the XY stage 1. In addition, the operation content of the on-wafer scan is transmitted to the data distribution control unit 38 by using the scan control signal 36.

  The configuration of the image detection unit 8 is as follows.

  The light source 7 outputs light (for example, UV light or DUV light). The collective lens 6 condenses the light output from the light source 7 in a slit shape and irradiates the wafer 2 through the objective lens. The XY stage 1 moves the wafer 2 in a predetermined direction. The objective lens 4 collects the light reflected from the circuit pattern formed on the wafer 2 and forms an image. The image sensor 5 is a TDI sensor or the like. The image sensor 5 captures an image of the formed circuit pattern and outputs analog image information 10.

  The A / D converter 11 converts the analog image information 10 output from the sensor 5 into image data 12. The feature amount calculation unit 13 receives the image data 12 and calculates a feature amount 14 and a calculated feature amount 15 from the image data 12.

  FIG. 2 is a diagram illustrating an example of the feature amount calculation unit 13.

  The feature amount calculation unit 13 includes a misregistration detection unit 200, a counter 203, and an information synthesis unit 204.

  FIG. 3 is an example of a diagram illustrating the misregistration detection unit 200.

  The positional deviation detection unit 200 includes a buffer 205, a calculation unit 207, and a peak value search unit 208.

  The misregistration detection unit 200 uses the input image data 12 and the matching image data 206 stored in the buffer 205 to calculate a feature amount in the calculation unit 207 and uses the correlation value map 210 to calculate the peak value. The search unit 208 searches for the peak value and outputs it as the feature amount 14 to the image data cutout unit 17.

  The counter 203 counts the amount of the input image data 12 as an increment value, and sends the count result value to the information composition unit 204.

  The information combining unit 204 combines the feature value 14 and the count result of the counter 203 and sends the result to the wafer coordinate table 22 as the calculated feature value 15.

  In the semiconductor appearance inspection apparatus 99 according to the present embodiment, the calculation unit 207 calculates a positional deviation amount using the input image data 12 and the corresponding adjacent chip as the feature quantity 14 to be calculated. A value obtained as a result of calculating the positional deviation amount in units of chips is sequentially output with respect to the input image data 12 such as calculating the positional deviation amount with the chip of the corresponding adjacent chip.

  The calculation unit 207 uses various methods for calculating the amount of misregistration, such as normalization cross-correlation between images, sum of shade differences between images, square sum of shade differences between images, and the like.

As an example of the calculation unit 207, an example in which normalized cross-correlation calculation is performed is shown here. The normalized cross-correlation coefficient R is defined as f _{avg as} the average value of the input image data 12 and g _{avg as} the average value of the matching image data 206.

It becomes. This normalized cross-correlation coefficient R combines the average value components of the image and normalizes the variance from the average value. The normalized cross-correlation coefficient R approaches 1.0 when the correlation between the two patterns is high, and approaches -1.0 when the correlation between the two patterns is high.

  FIG. 4 is a flowchart for explaining an example of a positional deviation amount calculation process in the positional deviation detection unit 200 according to this embodiment.

  When the misregistration detection process in the misregistration detection unit 200 is started (400), the image data 12 is input to the misregistration detection unit 200 (401). Of the input image data 12, the data for the chip area is stored in the buffer 205 (402).

  Next, the matching image 206 output from the image data 12 and the buffer 205 is input to the normalized correlation calculation unit 207 (403). The normalized correlation calculation unit 207 performs a normalized cross-correlation calculation process (404) and outputs a correlation value map 210 (405).

  The peak value search unit 208 searches for the peak value of the output correlation value map 210 (406), and outputs the peak value R (x, y) of the correlation value map 210 for which the search has been completed as the feature amount 14 (407). ).

  Thus, the completion of the misregistration detection process in the misregistration detection unit 200 is completed (408).

  FIG. 5 is a diagram showing an example of a schematic diagram of the flowchart shown in FIG. Each process will be described in detail with reference to FIG.

  The image of the chip area on the wafer to be inspected is set as the image data 12, and the corresponding chip area image on the wafer immediately before is set as the matching image 206. The image data 21 and the matching image 206 delayed by the chip area in the buffer are input to a normalized cross-correlation calculation unit 207 for detecting a positional deviation.

  The normalized cross-correlation calculation unit 207 calculates the correlation value when the two images are relatively shifted by −m to + m pixels in the x direction and −n to + n pixels in the y direction using [Equation 1]. Then, a correlation value map (similarity map) 210 is obtained.

  The maximum correlation value position of the correlation value map (similarity map) 210 is detected as a positional deviation amount between images, and the maximum position (peak value) R (x, y) is output as the feature amount 14.

  Although the example in which the misregistration detection unit 200 detects the misregistration amount based on the normalized cross-correlation value has been described here, the misregistration amount may be calculated by another method such as the sum of the density differences between images.

  FIG. 6 is a schematic diagram showing an example of processing when the flowchart shown in FIG. 4 is applied to image detection processing in the semiconductor appearance inspection apparatus.

  Chip (1) 300 and chip (2) 301 exist on the wafer.

  The sensor 302 acquires wafer image data. FIG. 6 shows an example in which chip image data is distributed to five PEs. Therefore, the sensor 302 continuously acquires PE distribution image data 303 to 307 from the chip (1) 300 and 308 to 312 from the chip (2) 301.

  Here, it is assumed that the chip (2) 301 exists at a position shifted from the original position. As a cause of this position shift, it is caused by a shift caused when a stepper forming a chip pattern on the wafer is shot, a wafer is rotated on the stage 1 from its original position, or it is caused by optical It may be caused by factors such as In optical semiconductor visual inspection equipment, the formation of a uniform wiring pattern over the entire surface of the wafer has become increasingly difficult due to the increased size of the wafer.

  The image of the chip area on the wafer to be inspected is set as the image data 12, and the chip area image on the corresponding wafer immediately before that is set as the matching image 206. The image data 21 and the matching image 206 delayed by the chip area in the buffer are input to a normalized cross-correlation calculation unit 207 for detecting a positional deviation.

  The in-chip wiring pattern 320 of the chip (1) 300 exists as the in-chip wiring pattern 321 in the chip (2) 301. The positional deviation of the chip (1) is assumed to be shifted by a in the x direction and b in the y direction.

  The maximum correlation value position of the correlation value map 210 is detected as a positional deviation amount between images, and the maximum position (peak value) is output as a feature value 14 as R (a, b).

  The image data cutout unit 17 in FIG. 1 cuts out the image data 12 using the feature amount 14 and generates cutout data 18.

  FIG. 7 is a schematic diagram showing an example of processing of the image data cutout unit 17 in FIG.

  Image data 12 is input to the image data cutout unit 17, and R (a, b) at the maximum correlation value position is shown as the feature amount 14.

  The image data cutout unit 17 sets a cutout region 326 having a non-inspection region around R (a, b). In the image data cutout unit 17 shown in this embodiment, the non-inspection area is 10 pixels. The image data 12 is cut out in accordance with the set cut-out area 326, a cut-out image 327 is obtained, and cut-out data 18 is generated.

  FIG. 8 is a diagram illustrating an example of the transmission control unit 19 according to the present embodiment.

  The transmission control unit 19 includes a counter 190, a data packetization unit 191, and a network interface 192.

  The counter 190 counts the amount of the input cut-out data 18 as an increment value, and sends the count result value as the image counter value 20 to the wafer coordinate table 22.

  The data packetization unit 191 receives the distribution destination information 21 returned from the wafer coordinate table 22, extracts the distribution destination PE number and the distribution destination address from the distribution destination information 21, and packetizes the extracted data 18 together with the network interface 192. To pass.

  The network interface 192 transmits the packet in which the distribution destination PE number, the distribution destination address, and the data are collected to the path switch 26 of the data processing unit 25 illustrated in FIG.

  The path switch 26 of the data processing unit 25 interprets the distribution destination PE number of the received data packet and distributes the data packet to desired processor elements 27 to 29.

  The processor elements 27 to 29 perform predetermined data processing using the received data packet.

  FIG. 9 shows a flowchart of an example of image processing performed by the processor elements 27 to 29.

  When image processing is started in the processor elements 27 to 29 (2700), inspection images are input to the respective processor elements (2701). The input inspection image is subjected to misalignment detection and / or correction processing (2702). In the present embodiment, the feature amount calculation unit 13 and the image data cutout unit 14 of the data distribution control unit 38 calculate feature amounts from the image data 12, and use the calculated feature amounts to suppress non-inspection areas from the image data 12. Since the cut-out data 18 cut out in this way is transmitted to the processor element, the load on the misalignment detection and / or correction processing in the processor element is reduced. For example, since the image data in which the displacement is detected is transmitted to the processor element, it is not necessary to detect the displacement in the processor element. Alternatively, since the cut-out data 18 is suppressed from the non-inspection area, the amount of image data used for detecting the displacement by the processor element is also reduced, and the image processing load is reduced.

  The inspection image subjected to the positional deviation detection process and / or the correction process is subjected to a threshold value calculation process (2703).

  The inspection image subjected to the threshold calculation processing is subjected to defect determination processing (2704), and image processing in the processor elements 27 to 29 is completed (2705).

  The result output unit 30 in FIG. 1 displays a result obtained by integrating the processing results performed by the processor elements 27 to 29 of the data processing unit 25 as a processing result for the user of the apparatus.

  The data processing unit control information 31 is status information on the status of data processing in the data processing unit 25 and is received by the central control unit 33.

  The data distribution control unit control information 32 is status information on the control status of the data distribution control unit 38 and is received by the central control unit 33.

  FIG. 10 is a diagram for explaining an example of image distribution control and image processing operations and data flow of the semiconductor visual inspection apparatus 99 according to the present embodiment.

  The image data 12 distributes the image 2115 of the first die (1) 2100 to the PE (0) 2110, and transfers the second image 2116 to the PE (1) 2111, and similarly to the PE (3) 2113. .

  Since the image data 12 is scanned on the wafer mechanically continuously, the first image 2120 of the next die (2) 2101 is set to PE (0) 2110, and the second image 2121 is set to PE (1). In the same manner, the data is sequentially transferred to the PE (3) 2113.

  In PE (0) 2110 to PE (3) 2113, the distributed data is subjected to image processing. For example, in the PE (1) 2111, after the image 2121 of the die (2) 2101 is distributed (2107), the image processing 2108 is performed.

  As described above, the semiconductor appearance inspection apparatus 99 performs predetermined image cutting in units of basic images in the data distribution control unit 38 for the image data 12 that is continuous digital image information, and assigns it to a plurality of PEs. Perform an inspection.

  FIG. 11 is a diagram illustrating an example of a GUI 2400 displayed on the central control unit 33.

  The GUI 2400 includes a statistical log 2402, a wafer image 2403, a chip image 2404, and a scanned image image 2405.

  The statistical log 2402 displays the feature value of the wafer coordinate table 22.

  The scanned image 2405 displays the (R (a, b)) coordinate position information, which is the feature value 14 of the correlation value maximum position, and the set non-inspection area together with the actually scanned wafer image.

  With the GUI 2400, it is possible to check the positional deviation on the wafer for the entire scan, and a function as process monitoring is realized.

  Here, for comparison between the present embodiment and a conventional semiconductor appearance inspection apparatus, a conventional semiconductor appearance inspection apparatus will be described with reference to FIG. FIG. 12 is a configuration diagram of a conventional semiconductor appearance inspection apparatus.

  A conventional semiconductor visual inspection apparatus 1099 includes an XY stage 1, a wafer 2, an objective lens 4, an image sensor 5, an aggregation lens 6, a light source 7, an A / D converter 11, a data distribution table 1022, a transmission control unit 19, and a path switch. 26, processor elements 27 to 29, a result output unit 30, and a central control unit 33.

  A difference from the configuration of the semiconductor appearance inspection apparatus 99 in FIG. 1 is that a data distribution table 1022 is provided instead of the feature amount calculation unit 13 and the wafer coordinate table 22 in FIG. Other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

  FIG. 13 is a schematic diagram showing an example of image detection processing in the semiconductor appearance inspection apparatus of FIG.

  Chip (1) 300 and chip (2) 301 exist on the wafer.

  The sensor 302 acquires image data of the wafer 399. FIG. 13 shows an example in which chip image data is distributed to five PEs.

  The sensor 302 continuously acquires PE distribution image data 303, 304, 305, 306, and 307 from the chip (1) 300, and 308, 309, 310, 311, and 312 from the chip (2) 301. Here, it is assumed that the chip (2) 301 exists at a position shifted from the original position.

  In FIG. 13, an image of a chip area on a wafer to be inspected is set as image data 12.

  In-chip wiring patterns 321 and 1124 exist in the chip (2) 301.

  The positional deviation of the chip (1) is assumed to be shifted by a in the x direction and b in the y direction.

  The transmission control unit 19 of the conventional semiconductor visual inspection apparatus 1099 scans the scan start position in order to transmit the in-chip wiring pattern 321 to the first processor element 27 even if there is a deviation a in the x direction and a deviation b in the y direction. A fixed value instructed by the central control unit 33 is added to 1122, a transmission area 1126 having a sufficient non-inspection area is set, and packetized transmission data 1127 is obtained.

  In addition, the transmission control unit 19 adds a fixed value instructed by the central control unit 33 to the scan start position 1123 to transmit the in-chip wiring pattern 1124 to the second processor element 28, thereby providing a sufficient non-inspection area. The transmission area 1128 is set and packetized to obtain transmission data 1129. Thereafter, transmission data is obtained repeatedly.

  FIG. 14 is a diagram for explaining an example of the operation and data flow of the conventional semiconductor appearance inspection apparatus 1099 when image distribution control and image processing according to this embodiment are performed.

  The image data 12 distributes the image 2115 of the first die (2) 2100 to the PE (0) 2110, and transfers the second image 2116 to the PE (1) 2111, and similarly to the PE (3) 2113. .

  Since the image data 12 is scanned on the wafer mechanically continuously, the first image 2120 of the next die (2) 2101 is set to PE (0) 2110, and the second image 2121 is set to PE (1). In the same manner, the data is sequentially transferred to the PE (3) 2113.

  In PE (0) 2110 to PE (3) 2113, the distributed data is subjected to image processing. For example, in the PE (1) 2111, after the image (5) 2121 of the die (2) 2101 is subjected to the distribution processing 1107, the image processing 1108 is performed.

  Here, the image processing 1108 takes a longer processing time than the image processing 2108 of the semiconductor appearance inspection apparatus 99 of the present embodiment. This is because the position shift detection / correction processing 1109 in PE (1) 2111 is added to the image processing 1108.

  The misregistration detection / correction processing 1109 uses various methods for calculating the misregistration amount, such as normalized cross-correlation between images, sum of shade differences between images, and sum of squares of shade differences between images. Is used. In the present embodiment, it is assumed that normalized cross-correlation calculation is performed, and the calculation formula executes [Equation 1].

  Here, if the misregistration detection / correction processing 1109 and the image processing 1108 are added, and the total image processing time in the PE (1) 2111 is about 20% and the calculation time is prolonged, the image data distribution processing 1107, A time period 1110 in which the previously performed image processing 1111 overlaps occurs.

  The time zone 1110 in which the image data distribution and the image processing overlap is a factor that reduces the calculation speed of the image processing, and the image processing time further increases. The distribution of the detection data 2105 to the PE does not stop because the scanning on the wafer is continuously performed, and the image processing speed does not catch up with the generation speed of the image data 12, so the balance of the speed is lost, and the network path switch This may cause a fatal error such as 26 buffer overflow.

  FIG. 15 is a diagram for explaining an example of a data flow for explaining operations of image distribution control and image processing, which are configured so as to prevent a fatal error from occurring in the conventional semiconductor appearance inspection apparatus 1099. The configuration example shown in FIG. 15 is different from FIG. 14 in that the number of PEs is increased by 1 to 5 PEs.

  The image data 12 distributes the image 2115 of the first die 2100 to the PE (0) 2110, and transfers the second image 2116 to the PE (1) 2111 and so on up to the PE (4) 2114.

  Since the image data 12 is mechanically continuously scanned on the wafer, the first image 2120 and the second image 2121 of the next die 2101 are changed to PE (0) 2110, PE (1) 2111, Similarly, the data is sequentially transferred to PE (4) 2114.

  From PE (0) 2110 to PE (4) 2114, the distributed data is subjected to image processing. For example, in the PE (0) 2110, after the image 2120 of the die (2) 2101 is distributed 1207, the image processing 1208 is performed.

  Here, the image processing 1208 shown in FIG. 15 has a shorter processing time than the image processing 1108 shown in FIG. This is because the size of the image data distribution 1207 is reduced by 20% compared to the image data distribution 1107 by increasing the number of PEs by one.

  Since the processing time of the image processing 1208 is shorter than that of the image processing 1108 shown in FIG. 14 due to the reduction in the size of the image data distribution 1207, the image processing time is increased by the misalignment detection / correction processing 1109. Even so, the occurrence of a time zone in which image data distribution and image processing overlap is suppressed.

  The conventional semiconductor appearance inspection apparatus 1099 having the configuration shown in FIG. 15 does not have a time zone in which image data distribution and image processing overlap, and no fatal error occurs as an apparatus. However, the number of PEs is increased by one compared with the image distribution control and image processing of the semiconductor visual inspection apparatus 99 according to the present embodiment shown in FIG. 10, and the cost of the image processing apparatus 25 is increased by 20%.

  The semiconductor visual inspection apparatus responds to the increase in the number of PEs due to the demand for increased inspection image data and the increase in inspection throughput due to the miniaturization of wafers and the increase in wafer size. There has been a problem that the cost of the image processing unit 25 and the semiconductor appearance inspection apparatus is increased due to the increase in the number.

  On the other hand, the semiconductor appearance inspection apparatus 99 according to the present embodiment includes a feature amount calculation unit 13 that calculates a feature amount from image data, and an image data cutout unit 14 that extracts an inspection region from the image data using the feature amount. By suppressing the non-inspection area from the image data, it is possible to reduce the load processing processing of the PE and suppress the increase in the amount of image processing hardware, thereby reducing the cost of the semiconductor visual inspection apparatus. From the above, it has become possible to realize a semiconductor appearance inspection apparatus in which the cost of the image processing apparatus 25 is reduced.

  The semiconductor outside inspection apparatus 99 according to the present embodiment performs image processing in response to a demand for an increase in inspection image data and an increase in inspection throughput due to wafer miniaturization and wafer size increase as shown in the conventional example of FIG. Since high-speed, large-capacity parallel image processing can be realized at low cost without increasing the number of PEs constituting the device 25, the device is excellent in terms of cost reduction and power consumption.

  In the present embodiment, in a semiconductor visual inspection apparatus using a plurality of image sensors 5, 1301, and 1302, a non-inspection area is suppressed from image data, thereby reducing the PE misalignment processing load and increasing the amount of image processing hardware. An example of a semiconductor visual inspection apparatus that realizes further cost reduction of the apparatus by suppressing the above will be described.

  FIG. 16 is a configuration diagram of an example of the semiconductor appearance inspection apparatus according to the present embodiment.

  The semiconductor appearance inspection apparatus 1300 includes a feature amount calculation section 1371 corresponding to a plurality of image sensors, instead of the feature amount calculation section 13 of the semiconductor appearance inspection apparatus 99 of FIG. Further, the second objective lens 1341, the nth objective lens 1342, the second image sensor 1301, the nth image sensor 1302, the second A / D converter 1005, the nth A / D converter 1006, the first Feature quantity calculation unit 1350 corresponding to the plurality of image sensors 2, feature quantity calculation unit 1351 corresponding to the nth plurality of image sensors, second image data extraction unit 1354, nth image data extraction unit 1355, second A transmission control unit 1358, an nth transmission control unit 1359, a second wafer coordinate table 1368, and an nth wafer coordinate table 1369 are added.

  Other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

  The second image sensor 1301 and the n-th image sensor 1302 are TDI sensors and the like, similar to the image sensor 5. An image of the formed circuit pattern is captured, and second analog image information 1331 and nth analog image 1332 are output, respectively.

  The second A / D converter 1005 converts the second analog image information 1331 into the second image data 1007, and the nth A / D converter 1006 converts the nth analog image information 1332 into the nth image data. Image data 1008.

  As described above, the image sensor 5, the second image sensor 1301, and the n-th image sensor 1302 perform the same operation, acquire images at the same XY position on the wafer 2 at the same timing, and the image data 12 The second image data 1007 and the nth image data 1008 are output.

  This is because the light source 7, the collective lens 6, the wafer 2, the XY stage 1, the scan control unit 34, and the stage control signal 35 are common to the image sensor 5, the second image sensor 1301, and the nth image sensor 1302. Because.

  The difference between the image sensor 5, the second image sensor 1301, and the n-th image sensor 1302 is the angle at which light reflected from the wafer 2 enters each sensor. As a result, three images of the circuit pattern to be formed are obtained, and more detailed circuit pattern analysis and defect pattern analysis are possible.

  Differences in configuration between the present embodiment and the first embodiment will be described in detail with reference to FIGS.

  FIG. 17 is an example for explaining an example of the feature quantity calculation unit 1350 corresponding to the second plurality of image sensors.

  The feature quantity calculation unit 1350 corresponding to the second plurality of image sensors includes a misregistration detection unit 200, a counter 203, and an information synthesis unit 204. The difference from the feature amount calculation unit 13 shown in FIG. 2 is that the feature amount calculation unit data 1370 is extracted from the input image data 12 and is output to another feature amount calculation unit. The image data 12 input to the feature quantity calculation unit 1350 corresponding to the second plurality of image sensors becomes the second feature quantity 1352 and the second calculated feature quantity 1360, which are the second image data cutout unit 1354 and the second feature quantity calculation unit 1360, respectively. Is output to the wafer coordinate table 1368.

  FIG. 18 is a diagram illustrating an example of a feature amount calculator 1371 corresponding to a plurality of image sensors and a feature amount calculator 1351 corresponding to an nth plurality of image sensors. As a representative example, an example of a feature amount calculation unit 1371 corresponding to a plurality of image sensors is shown.

  The feature amount calculation unit 1371 corresponding to a plurality of image sensors includes a misregistration detection unit 13712, a counter 203, and an information synthesis unit 204. The feature amount calculation unit 13 shown in FIG. 2 is obtained by adding a displacement detection unit 13712 in place of the displacement detection unit 200.

  FIG. 19 is a diagram illustrating an example of the misregistration detection unit 13712.

  The positional deviation detection unit 13712 includes a calculation unit 207 and a peak value search unit 208. A difference from the misregistration detection unit 200 shown in FIG. 3 is that data between feature quantity calculation units 1370 is input instead of the buffer 205.

  The second image data 1007 input to the feature quantity calculation unit 1350 corresponding to the second plurality of image sensors shown in FIG. 17 is on-wafer image data acquired by the second image sensor 1301.

  Image data 12 input to the feature quantity calculator 1371 corresponding to the plurality of image sensors shown in FIG. 18 is on-wafer image data acquired by the image sensor 5.

  The image data 12 and the second image data 1007 are data obtained by sensing the scattered light of the laser that has passed through the single light source 7 and the collective lens 6 with an image sensor and converted into digital data by an A / D converter. This is data obtained by sensing image data at the same position on the wafer.

  However, the image data 12 and the second image data 1007 may have different image sensor angles. The second objective lens 1341 and the second image sensor 1301 in the semiconductor appearance inspection apparatus 1300 according to the present embodiment sense laser light scattered in the direction perpendicular to the wafer 2. The second objective lens 1341 and the second image sensor 1301 are referred to as an upper detection system.

  In addition, the objective lens 4 and the image sensor 5 in the semiconductor appearance inspection apparatus 1300 according to the present embodiment sense laser light scattered in an oblique direction with respect to the wafer 2. The objective lens 4 and the image sensor 5 are called an oblique detection system. The nth objective lens 1342 and the nth image sensor 1302 are also oblique detection systems.

  In the semiconductor appearance inspection apparatus 1300 of the present embodiment, there may be a particularly large positional deviation between the image data by the upper detection system and the image data by the oblique detection system. This is caused by the deviation of the chipper on the wafer, which is caused by the deviation of the stepper that forms the chip pattern on the wafer, and the wafer is rotated from the original position on the stage 1. This is because misalignment of captured image data due to causes or optical factors, etc. occurs in different directions in the upper detection system and the oblique detection system.

  Further, in the semiconductor appearance inspection apparatus 1300 of the present embodiment, the reason why the positional deviation is particularly large between the image data by the upper detection system and the image data by the oblique detection system is that the upper detection system and the oblique detection system are This is because the image data is misaligned between the upper detection system and the oblique detection system even when the alignment for aligning the imaging positions does not necessarily coincide completely, because it is mechanically independent.

  For comparison, a conventional semiconductor appearance inspection apparatus using a plurality of image sensors 5, 1301, 1302 will be described.

  FIG. 20 is an example of a configuration diagram of a semiconductor visual inspection apparatus using a plurality of conventional image sensors.

  Compared with the semiconductor appearance inspection apparatus 1300 of the present embodiment, the conventional semiconductor appearance inspection apparatus 1700 has a feature amount calculation unit 1371 corresponding to a plurality of image sensors, a feature amount calculation unit 1350 corresponding to a second plurality of image sensors, n feature quantity calculation units 1351 corresponding to a plurality of image sensors, image data cutout unit 17, second image data cutout unit 1354, nth image data cutout unit 1355, wafer coordinate table 22, second wafer coordinate table 1368, The n-th wafer coordinate table 1369 has no configuration, and includes a wafer coordinate table 1701, a second wafer coordinate table 1702, and an n-th wafer coordinate table 1703.

  In the conventional semiconductor appearance inspection apparatus 1700, regarding the positional deviation generated in the image data between the upper detection system and the oblique detection system, in the processor elements 27 to 29 of the semiconductor appearance inspection apparatus 1700, the upper detection system and the oblique detection system. Image processing that detects and corrects misalignment between the detection systems has been performed.

  In the conventional semiconductor appearance inspection apparatus 1700, the processing time of PE of the semiconductor appearance inspection apparatus 1700 is lengthened by the detection and correction processing of the positional deviation of the image data between the upper detection system and the oblique detection system. The image processing speed cannot keep up with the generation speed of the second image data 1007 and the n-th image data 1008, the speed balance is lost, and a fatal error occurs as a device such as a buffer overflow of the network path switch 26.

  Therefore, in order to prevent a fatal error from occurring as an apparatus, it is necessary to increase the number of PEs, reduce the size of image data distributed to PEs, and shorten the image processing time. However, this does not cause a fatal error as a device. However, the increase in the number of PEs increases the cost of the image processing apparatus.

  That is, in the conventional semiconductor appearance inspection apparatus 1700, the image processing apparatus can cope with an increase in the number of PEs due to a demand for an increase in inspection image data and an increase in inspection throughput due to wafer miniaturization and wafer size increase. As a result of the increase in the number of PEs, there has been a problem that the cost of the image processing unit and the semiconductor appearance inspection apparatus is increased.

  On the other hand, the semiconductor visual inspection apparatus 1300 according to the present embodiment suppresses the non-inspection area from the image data, and detects and corrects the positional deviation between the upper detection system and the oblique detection system, thereby correcting the PE positional deviation processing. The load is reduced and the increase in the amount of image processing hardware is suppressed, and the cost reduction of the semiconductor visual inspection apparatus is realized. From the above, it has become possible to realize a semiconductor appearance inspection apparatus in which the cost of the image processing apparatus 25 is reduced.

  The outside-semiconductor inspection apparatus 1300 according to the present embodiment performs image processing in response to a demand for an increase in inspection image data and an increase in inspection throughput due to wafer miniaturization and wafer size increase as shown in the conventional example of FIG. Since high-speed, large-capacity parallel image processing can be realized at low cost without increasing the number of PEs constituting the device 25, the device is excellent in terms of cost reduction and power consumption.

  In the present embodiment, an example of a semiconductor visual inspection apparatus that realizes a process of suppressing a non-inspection area from image data with high speed and low power consumption by utilizing the feature of positional deviation of wafer image data will be described.

  FIG. 21 is a configuration diagram of an example of a semiconductor appearance inspection apparatus according to the present embodiment.

  The semiconductor appearance inspection device 1899 is obtained by adding a feature amount calculation unit 1813 different from the feature amount calculation unit 13 from the semiconductor appearance inspection device 99 of FIG. Other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

  Differences in configuration between the present embodiment and the first embodiment will be described in detail with reference to FIGS.

  FIG. 22 is a diagram for explaining an example of the feature amount calculation unit 1813. The feature amount calculation unit 1813 includes a misregistration detection unit 18200, a counter 203, and an information synthesis unit 204.

  A misregistration detection unit 18200 different from the misregistration detection unit 200 is added to the feature amount calculation unit 1399 in FIG.

  FIG. 23 is a diagram for explaining an example of the misregistration detection unit 18200. The positional deviation detection unit 18200 includes a buffer 205, matching image data 206, a calculation unit 18207, a correlation value map 210, and a peak value search unit 208.

  A calculation unit 18207 different from the calculation unit 207 is added to the misalignment detection unit 200 in FIG.

  The misregistration detection unit 18200 uses the input image data 12, the matching image data 206 stored in the buffer 205, and the reference feature amount 16 to calculate a feature amount using the calculation unit 18207, and the correlation value map 210. The peak value search unit 208 searches for the peak value and outputs it as the feature amount 14 to the image data cutout unit 17.

  In the semiconductor appearance inspection apparatus 99 according to the present embodiment, the calculation unit 18207 calculates the positional deviation amount using the input image data 12 and the corresponding adjacent chip as the feature quantity 14 to be calculated. A value obtained as a result of calculating the positional deviation amount in units of chips is sequentially output with respect to the input image data 12 such as calculating the positional deviation amount with the chip of the corresponding adjacent chip.

  The calculation unit 18207 uses various methods for calculating the amount of misregistration, such as normalized cross-correlation between images, the sum of shade differences between images, the sum of squares of shade differences between images, and the like.

  Here, as an example of the calculation unit 18207, an example in which normalized cross-correlation calculation is performed will be described.

The normalized cross-correlation coefficient R is given by [ _Equation 1] where the average value of the input image data 12 is f _avg and the average value of the matching image data 206 is g _avg . This normalized cross-correlation coefficient R combines the average value components of the image and normalizes the variance from the average value. The normalized cross-correlation coefficient R approaches 1.0 when the correlation between the two patterns is high, and approaches -1.0 when the correlation between the two patterns is high.

  FIG. 24 is an example of a flowchart for explaining processing for calculating the amount of misalignment in the misalignment detection unit 18200 according to this embodiment.

  When the misregistration detection process in the misregistration detection unit 18200 is started (2100), the image data 12 is input to the misregistration detection unit 18200 (2101).

  Of the input image data 12, the data for the chip area is stored in the buffer 205 (2102). When the image data 12 and the matching image 206 output from the buffer 205 and the reference feature 16 are input to the normalized correlation calculation unit 18207 (2103), the normalized correlation calculation unit 18207 performs the normalized cross-correlation calculation process. (2104).

  The normalized correlation calculation unit 18207 outputs the correlation value map 210 as a result of the calculation process (2105), and the peak value search unit 208 searches for the peak value of the correlation value map 210 (2106). The peak value search unit 208 outputs the peak value R (x, y) of the correlation value map 210 for which the search has been completed as the feature amount 14 (2107), and the position shift detection process in the position shift detection unit 18200 is completed ( 2108).

  FIG. 25 is a diagram showing the flowchart shown in FIG. 24 as an example of a schematic diagram.

  The image of the chip area on the wafer to be inspected is set as the image data 12, and the chip area image on the corresponding wafer immediately before that is set as the matching image 206. The image data 12, the matching image 206 delayed by the chip area in the buffer, and the reference feature quantity 16 that is the feature quantity of the immediately preceding chip area are input to the normalized cross-correlation calculation unit 207 for detecting misalignment. The

  The normalized cross-correlation calculation unit 18207 shifts the inspection target image in advance to R (x, y) indicated by the reference feature 16, and then uses the shifted inspection target image and two matching images, Correlation values are calculated by using [Equation 1] when relatively shifting by −m to + m pixels in the x direction and −n to + n pixels in the y direction, and a correlation value map (similarity map) 210 is obtained.

  The maximum correlation value position of the correlation value map (similarity map) 210 is detected as a positional deviation amount between images, and the maximum position (peak value) R (x, y) is output as the feature amount 14.

  Unlike the misregistration detection unit 200 of FIG. 3, the misregistration detection unit 18200 shifts the inspection target image in advance because the reference feature 16 is known. As a result, the amount by which the two images are relatively shifted (-m to + m pixels in the x direction and -n to + n pixels in the y direction) to obtain a correlation value calculated using [Equation 1] It is possible to make the range narrower than the position deviation detection unit 200 of FIG.

The misregistration detection unit 18200 detects misregistration in FIG. 3 by setting the amount by which the two images are relatively displaced (−m to + m pixels in the x direction and −n to + n pixels in the y direction) in a narrow range. FIG. 26 is a schematic diagram illustrating an example of an image detection process in the semiconductor appearance inspection apparatus. FIG. 26 illustrates the schematic diagram illustrated in FIG. 25.

  Chip (1) 300, chip (2) 301, chip (3) 320, and chip (4) 321 exist on wafer 399.

  Here, it is assumed that the chip (2) 301 exists at a position shifted from the original position. Similarly, it is assumed that the chip (3) 320 and the chip (4) 321 exist at positions shifted from the original positions. The positional deviation amount is the largest in the positional deviation 330, and the positional deviation amount decreases as the positional deviation 331 and the positional deviation 332 progress. Alternatively, there are cases where the positional deviation 330, the positional deviation 331, and the positional deviation 332 all have the same positional deviation amount.

  The cause of the change in the amount of misalignment is that the stepper that forms the chip pattern on the wafer forms the chip pattern continuously on the wafer, and the wafer rotates from its original position on the stage 1. It can be considered that it is caused by this or caused by optical factors.

  In FIG. 26, the positional deviation 330, the positional deviation 331, and the positional deviation 332 of the chip (2) 301, the chip (3) 320, and the chip (4) 321 do not occur at random, but the position of the previous chip. It is shown that it exists in relation to the amount of deviation.

  In the semiconductor appearance inspection apparatus 1899 in this embodiment, the image data 12 is shifted in the vicinity of R (x, y) indicated by the reference feature 16 that is the feature of the previous chip area in the calculation unit 18207. It is shown from FIG.

  Therefore, the positional deviation detection unit 18200 shifts the image to be inspected using the value of the reference feature 16 in advance, and the amount by which the two images of [Equation 1] are relatively shifted (−m to + m pixels in the x direction, 3 can be made narrower than the misregistration detection unit 200 in FIG. 3, processing can be performed at high speed, and low power consumption can be realized. .

  The semiconductor appearance inspection apparatus 1899 according to the present embodiment has a narrower search range of the misregistration detection unit 18200 without allowing the misregistration amount of the image included in the image detection unit 8 to be within the range. Since it can be within the range, the processing can be performed at high speed, and it is excellent in terms of low power consumption.

  In the present embodiment, an example of a semiconductor appearance inspection apparatus will be described in which a portion for suppressing a non-inspection area from image data is mounted on a card, and the cost reduction of the apparatus is realized more generally.

  FIG. 27 is a configuration diagram of an example of a semiconductor appearance inspection apparatus according to the present embodiment.

  The semiconductor appearance inspection apparatus 2500 includes an XY stage 1, a wafer 2, an objective lens 4, an image sensor 5, an aggregation lens 6, a light source 7, an A / D converter 11, a feature amount calculation unit 13, an image data cutout unit 17, and a transmission control unit. 19, wafer coordinate table 22, data distribution control unit 38, path switch 26, processor elements 27 to 29, result output unit 30, central control unit 33, scan control unit 34, PC card 2501, high-speed data input port 2502, high-speed data It has an output port 2503, a card edge connector 2504, communication data 2505 between the card and the PC, and a PC slot 2506.

  1 differs from the semiconductor visual inspection apparatus 99 in FIG. 1 in that a PC card 2501, a high-speed data input port 2502, a high-speed data output port 2503, a card edge connector 2504, and communication between the card and the PC are used instead of the data distribution control unit 38. Data 2505 and a PC slot 2506 are added. Other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

  The PC card 2501 is a general-purpose card-like board having a connector 2504 for insertion into a PC slot 2506 of a PC (Personal Computer).

  The high-speed data input port 2502 is an interface for inputting high-speed and large-capacity image data 12 to the PC card 2501. In this embodiment, the high-speed data input port 2502 is a general-purpose port standard interface called CX4 or SFP.

  The high-speed data output port 2503 is an interface for outputting high-speed and large-capacity data 23 from the PC card 2501. Like the high-speed data input port 2504, in this embodiment, a general-purpose port standard called CX4 or SFP is used. Interface.

  The card edge connector 2504 is a connector to be inserted into the PC slot 2506, and has a connector shape conforming to the PCI Express standard in this embodiment.

  The PC slot 2506 is a general-purpose port provided for connecting a PC card when the PC expands its performance and functions. In this embodiment, the PC slot 2506 has a port compliant with the PCI Express standard. Data is exchanged through the communication data 2505 between the card and the PC.

  The semiconductor appearance inspection apparatus 2500 according to the present embodiment includes a feature amount calculation unit 13 that calculates a feature amount from image data, and an image data cutout unit 14 that extracts an inspection region from the image data using the feature amount.

  Further, in order to add an image data cutout function for cutting out an inspection area from image data, the function can be realized only by inserting the PC card 2501 into the PC port 2506.

  Since the semiconductor visual inspection apparatus 2500 according to the present embodiment is configured with the card edge connector 2504 of the PC card 2501 in accordance with the general-purpose standard of the PC port 2506, the image data extraction function for extracting the inspection area from the image data can be realized at low cost. In addition, it is excellent in that it can be realized for general purposes.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files for realizing each function can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

  Further, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

99 Semiconductor visual inspection apparatus 1 XY stage, 2 wafer, 4 objective lens, 5 image sensor, 6 aggregating lens, 7 light source 10 analog image information, 11 A / D converter, 12 image data, 13 feature quantity calculation unit, 14 feature Amount, 15 calculated feature amount, 16 reference feature amount, 17 image data cutout unit, 18 cutout data, 19 transmission control unit 20 image counter value, 21 distribution destination information, 22 wafer coordinate table, 23 transmission data, 26 path switch, 27 First processor element, 28 Second processor element, 29 nth processor element 30 Result output unit, 31 Data processing unit control information, 32 Image transmission control unit control information, 33 Central control unit, 34 Scan control unit, 35 Stage control signal, 36 scan control signal, 38 data distribution control unit, 39 image detection unit control Information 1005 2nd A / D converter, 1006 nth A / D converter, 1007 2nd image data, 1008 nth image data 1301 2nd image sensor, 1302 nth image sensor 1331 2nd Analog image information, 1332 nth analog image information 1341, second objective lens, 1342 nth objective lens 1350, feature quantity calculator corresponding to second plurality of image sensors, 1351 corresponding to nth plurality of image sensors Feature amount calculation unit 1352 second feature amount, 1353 nth feature amount, 1354 second image data cutout unit, 1355 nth image data cutout unit, 1356 second cutout data, 1357 nth cutout data, 1358 2nd transmission control part, 1359 nth transmission control part 1360 2nd calculation feature-value, 1361 2nd reference feature-value , 1362 second image counter value, 1363 second distribution destination information,
1364 nth calculated feature, 1365 nth reference feature, 1366 nth image counter value, 1367 nth distribution destination information 1368 2nd wafer coordinate table, 1369 nth wafer coordinate table 1371 Multiple images Sensor-compatible feature value calculation unit, 1372 2nd transmission data, 1373 n-th transmission data 1813 feature value calculation unit, 18200 misalignment detection unit 2501 PC card, 2502 high-speed data input port, 2503 high-speed data output port, 2504 card Edge connector, 2505 communication data between card and PC, 2506 PC slot

Claims (6)

A semiconductor visual inspection device,
An image detection unit for detecting image data of the wafer from the sensor;
A feature amount calculation unit for calculating a feature amount of the detected image data;
An image data cutout unit that sets an inspection region of the image data based on the calculated feature amount;
A transmission control unit for transmitting transmission data including the set inspection region of the image data;
A processor element for performing defect determination processing of the wafer using the transmitted transmission data;
A semiconductor visual inspection apparatus. The semiconductor appearance inspection apparatus according to claim 1,
The feature amount calculation unit calculates a positional deviation amount between predetermined image data and image data to be inspected as a feature amount. The semiconductor inspection apparatus according to claim 2,
The transmission data is composed of the inspection area and a non-inspection area, and the non-inspection area is set based on the amount of displacement. The semiconductor inspection apparatus according to claim 2,
A semiconductor visual inspection apparatus, wherein normalized cross-correlation is used for the calculation of the positional deviation amount. The semiconductor inspection apparatus according to claim 2,
The image detection unit includes a first sensor and a second sensor,
A first feature amount calculation unit that calculates a feature amount of an image detected by the first sensor; a second feature amount calculation unit that calculates a feature amount of an image detected by the second sensor;
A semiconductor inspection apparatus comprising: The semiconductor inspection apparatus according to claim 5,
The first sensor is an upper detection system that senses laser light scattered in a direction perpendicular to the wafer, and the second sensor is an oblique direction that senses laser light scattered in an oblique direction with respect to the wafer. Detection system,
The first feature amount calculation unit is configured to generate a first feature amount based on the first image data detected by the first sensor and the second feature amount calculated by the second feature amount calculation unit. Calculate
The second feature amount calculation unit is configured to generate a second feature amount based on the second image data detected by the second sensor and the first feature amount calculated by the first feature amount calculation unit. Calculate
A semiconductor inspection apparatus.

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