JP2011158439A - Visual inspecting system using electron beam - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a visual inspecting system which can implement efficient inspection in a short time by speedily acquiring to inspect image data including only a desired part. <P>SOLUTION: In the visual inspecting system with an ROI inspection function, image data for forming reference image is cut out including an aligning margin from a scanning stripe image arranged on a semiconductor wafer, based on a region specifying condition set. The plurality of image data cut out are added to average to compose the reference image for the ROI inspection. Also, misdetermination is prevented by providing a predetermined prohibition condition when cutting out the image data for the reference image. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an inspection apparatus that uses a substrate on which a circuit pattern is formed, such as a semiconductor substrate of a semiconductor device or a deflection array substrate of a liquid crystal display, as an inspection sample, and inspects the substrate using an electron beam.

  When laminating a fine circuit pattern on a substrate such as a semiconductor substrate of a semiconductor device or a deflection array substrate of a liquid crystal display, a foreign substance or a circuit pattern on the substrate using an appearance inspection device in the formation process of each layer to be laminated Conventionally, it is inspected for the presence of the above defects. At the time of appearance inspection, image data of the inspection location is acquired using an imaging device such as an electron microscope or an optical microscope, and image comparison of the pattern before and after using the periodicity of the circuit pattern or an appropriate reference image is performed. Image comparison is performed, and a portion having a difference is extracted as a defect.

  In appearance inspection, an extremely high inspection speed (throughput) is required, which is approximately one hour per substrate, and therefore, an image processing apparatus that performs pixel calculation at the time of image comparison includes a plurality of processors. It is normal. Image data used for image comparison is continuously output from the imaging means, divided into an appropriate size, and sequentially transferred to a plurality of processors. Thereby, parallel processing is executed, and the inspection speed is increased.

  When image data is divided for image comparison, in general, in addition to the portion actually used for image comparison (hereinafter referred to as inspection image region), a margin for alignment is included around the inspection image region. Cut out. That is, the inspection image area is cut out from the continuously output image data so as to include areas that overlap each other. For example, in Patent Document 1, when continuous image data is distributed to a plurality of processors, the image data is cut out so as to include an overlap area before and after the cut out area, so that a non-inspectable area at the division boundary An invention for preventing the occurrence of the problem is disclosed.

  As described above, the appearance inspection basically detects a defect by a comparison calculation process between images. Therefore, the inspection speed of the appearance inspection apparatus is basically limited by the image acquisition speed, in other words, the size of the area that the imaging apparatus can image at a time. On the other hand, the throughput requirement for the visual inspection apparatus is very strict, about 1 hour per substrate. Therefore, various methods have been tried to reduce the inspection time or improve the inspection speed without degrading the inspection accuracy by appropriately thinning out the area of the substrate to be imaged. For example, Document 2 discloses an inspection apparatus having a function of automatically setting the number of scanning stripes set in a chip in accordance with the set value of the sampling rate when the sampling rate is set when setting the inspection region. . Here, the scanning stripe is an electron beam irradiation region formed in the case of an inspection method in which the sample stage is continuously moved. If an electron beam is scanned one-dimensionally in a direction orthogonal to the stage movement direction with respect to the inspection sample that is continuously moving, a strip-shaped irradiation region having the stage movement direction as the longitudinal direction is formed on the sample. .

  When thinning inspection is performed, the imaging area of the sample to be inspected is reduced compared to the full inspection. However, if sampling is performed with a statistically meaningful technique, the distribution of detected defect candidates or the defect candidate By detailed analysis, the defect distribution on the entire surface of the sample can be estimated almost correctly.

JP 2004-259228 A JP 2002-026093 A

  In the conventional thinning inspection, the thinned imaging region is adjusted in units of scanning stripes, but it is impossible to satisfy the inspection throughput requirement of about one hour per substrate. Therefore, the applicant is developing an inspection method capable of further increasing the thinning rate, and this method will be described below.

  It is empirically known that areas where defects frequently occur in appearance inspection are edges or boundaries of the periodic structure existing in the circuit pattern, such as chip edges and memory mat edges. Therefore, an image is acquired by irradiating only the end of the chip or the end of the memory mat with an electron beam. At this time, although the sample stage is continuously moved, the sample stage can be moved at a higher speed than in the prior art by an amount that does not irradiate the electron beam (a beam irradiation skip region). Hereinafter, such an inspection method is referred to as ROI (Region Of Interest) inspection.

  However, in ROI inspection, since an image is acquired specifically for the edge of a periodic structure such as a memory mat edge such as a chip edge, defect detection cannot be performed by comparison between the self-image and the preceding and following images. Therefore, an object of the present invention is to realize an appearance inspection apparatus capable of realizing defect detection by the ROI method.

  The present invention adopts a detection method based on a comparison operation with a reference image instead of a comparison operation between the self-image and the preceding and following images as a defect detection method in the ROI method, and forms a reference image at the stage of creating an inspection recipe, The above-mentioned problem is solved by storing it as a recipe. Here, the inspection recipe is set data of inspection conditions determined in advance, such as imaging conditions and image acquisition regions.

  The reference image is formed by acquiring a plurality of images of a defect-free region on the inspection sample, aligning them, and averaging them. Therefore, when acquiring the image data for forming the reference image, it is necessary to acquire it including a margin for alignment (alignment region) in addition to the region actually used for the comparison calculation. Typically, an image for a reference image is obtained by acquiring an image of one scanning stripe for a chip to be inspected at the time of creating a recipe, and cutting out and averaging a plurality of images at the edge of the memory mat and the edge of the chip. Get the data.

  Furthermore, a predetermined prohibition condition is provided when image data for reference images is cut out to prevent erroneous determination.

  According to the present invention, it is possible to provide an appearance inspection apparatus that can perform an efficient inspection in a short time by acquiring and inspecting image data of only a desired portion at high speed in ROI inspection.

It is a figure which shows the concept of a ROI inspection system. It is explanatory drawing of the high-speed stage movement in a ROI inspection system. It is a whole block diagram of the external appearance inspection apparatus of a present Example. It is a block diagram of the image distribution table with which a distribution control part is equipped. It is an internal block diagram of a processor element. It is a flowchart which shows the production | generation flow of the reference image in a ROI test | inspection. It is a figure which shows an example of the ROI area | region setting screen in a recipe setting screen. It is explanatory drawing which shows the prohibition conditions at the time of reference image formation.

  Examples of the present invention will be described below.

  First, the principle of ROI inspection will be described. FIG. 1A is a top view showing a state where the scanning stripes 103 are arranged on the semiconductor wafer 101. A plurality of chips 102, which are patterns processed in the manufacturing process, are arranged in a lattice pattern on a wafer 101, which is an object to be inspected, and an inspection image is obtained by forming a plurality of scanning stripes on the chips. is doing. An arrow 104 indicates the direction of continuous movement of the sample stage, and the primary charged particle beam is scanned one-dimensionally in a direction orthogonal to the arrow 104. After forming the scanning stripe for a certain chip row, the stage is moved (in the direction orthogonal to the arrow 104) to shift the beam irradiation position to the next chip row to form the scanning stripe on the entire wafer surface, thereby removing defects on the entire wafer 101 surface. To detect.

  FIG. 1B is a schematic diagram showing a state in which the scanning stripe 103 is formed on a certain chip row. In the conventional appearance inspection, for example, in order to inspect the nth chip, the nth chip. Are compared with the n−1 th chip image and the (n + 1) th chip image to detect a defect. A comparison inspection method for comparing chips with each other is called a die comparison inspection method, and is one of typical defect detection methods along with a cell comparison inspection method described later. In FIGS. 1A and 1B, the width of the scanning stripe is shown to be thicker than the actual width for emphasis, but the width of the stripe is actually about 100 to several hundreds μm. Is much narrower.

  FIG. 1C is an enlarged view of a part of the memory mat area 105 of a certain chip formed on the semiconductor wafer 101, and FIG. 1D is a part of the memory mat existing in the memory mat area. It is the figure which expanded further. In FIG. 1C, the square indicated by the alternate long and short dash line indicates the scanning stripe 103 having a substantially actual size. A plurality of repetitive pattern areas called memory mats are arranged in the memory mat area 105, and a large number of memory cells 106 are periodically arranged in the memory mat. In the above-described cell comparison inspection method, images of memory cells are cut out one by one from the image data of the scanning stripe 103, aligned, and then the previous and subsequent images are compared.

  As described above, it is empirically known that a defect-prone region of a semiconductor circuit pattern is an end portion of a memory mat. Therefore, in the ROI inspection method, images of only the quadrangular portions 107, 108, 309, and 110 at the edge of the memory mat that are considered to have many defects are acquired, and beam scanning is skipped for the region between the square portions. The above-described quadrangular portions 107, 108, 109, and 110 are referred to as ROI inspection regions. In addition, the moving speed of the sample stage is increased according to the ratio of the length of the skip region 111 and the length of the ROI scanning regions 107 to 110. Thereby, the defect distribution in the wafer can be monitored efficiently in a shorter time than the conventional cell comparison inspection method. As indicated by 112 and 113, the ROI inspection area may be set at all the both ends of the memory mat.

Next, the reason why the stage moving speed can be increased in the ROI inspection method will be described with reference to FIG. 2A and 2D show the relationship between the length L of the ROI scanning region and the time of the arrangement pitch P at a predetermined stage moving speed, and FIGS. 2B and 2E show the scanning on the actual wafer. FIGS. 2C and 2F are schematic views showing the positional relationship of the scanning lines in the visual field region having a size of M, with respect to the arrangement of the ROI scanning region on the stripe. 2A, 2B, and 2C show the same stage movement speed V ₀ as in the conventional case, while FIGS. 2D, 2E, and 2F show the conventional stage movement. This corresponds to the case where the stage moving speed is set to Vs faster than the speed V ₀ . As shown in FIG. 2B, it is assumed that a plurality of ROI scanning regions 202 are arranged at a pitch P on the scanning stripe 201, and n ROI scanning regions 202 are arranged in a direction parallel to the moving direction of the stage. The primary electron beam scanning line is assumed to be configured. For simplicity of explanation, the lengths of the ROI scanning regions are equally L, the width of the scanning stripe (the length in the direction perpendicular to the longitudinal direction of the stripe) is l, and the center of the scanning stripe 201 (see FIG. 2 (B) is the scanning deflection center of the primary electron beam.

In the above case, in order to acquire the entire image of the scanning stripe by the primary electron beam scanning, during the time required for scanning one scanning line, the length in the stage moving direction of one scanning line (that is, 1) It is only necessary to move the stage by the amount of pixels). The time required for the primary electron beam to scan one scanning line is equal to 1 / f, where f is the deflection frequency of the scanning deflector. Usually, since the secondary charged particle detector of the inspection apparatus outputs image data for one scanning line per 1 / f time, this 1 / f is referred to as one line image detection time. Therefore, the normal stage moving speed V ₀ means a speed at which the sample stage can move by one pixel size in a time corresponding to the image detection time for one line. In the present embodiment, this V ₀ may be expressed as a stage moving speed synchronized with the beam scanning.

As shown in FIG. 2B, assuming that a plurality of ROI scanning regions are arranged on the scanning stripe at a pitch P and the stage continuously moves at a speed V ₀ as shown in FIG. The first scanning line 203a and the nth scanning line 203b arranged in the ROI scanning region move within the field of view region M by a length corresponding to n pixels, that is, the actual distance L on the wafer. This is because the stage moving speed and the beam scanning speed are synchronized as described above.

On the other hand, when the sample stage is moved at Vs faster than the moving speed V _0, the irradiation position of the primary electron beam moves to the adjacent scanning line before the scanning of one line is completed, and imaging is performed on the actual wafer. Position loss occurs. That is, if the stage moving speed Vs is faster than the image detection speed, an image of the entire scanning stripe cannot be acquired. However, as shown in FIG. 2 (E), when only the image of the ROI scanning area set intermittently on the scanning stripe needs to be detected, the first scanning line as shown in FIG. 2 (F). When the position on the real wafer corresponding to the first pixel of 203c is carried into the visual field region M, irradiation of the primary electron beam to the first pixel is started, and the final pixel of the nth scanning line 203d is the visual field region. If the irradiation of the primary electron beam to the final pixel is completed at the time when the image is taken out from M, the entire ROI scanning region can be imaged without missing an image. Reference numeral 203e denotes the first scanning line of the next ROI scanning area. Hereinafter, beam scanning to a plurality of set ROI scanning areas is sequentially performed.

  Here, the size M of the visual field region is normally set to the maximum within the range of the maximum value of the visual field determined by the performance of the electron optical system. The electron optical system has a fixed visual field, and within the visual field, it is possible to detect an image having substantially the same effect such as aberration and distortion. The maximum value of the field of view is determined by the performance of the electron optical system, such as the deflection distance of the scanning deflector and the degree of field curvature, and the larger the field of view to be set, the larger the area of the sample that can be imaged at one time. High-speed inspection is possible.

  However, since the stage moving speed Vs and the beam scanning deflection frequency are asynchronous, if nothing is done, the beam irradiation position on the ROI scanning area is from the position of the scanning line to be irradiated to the stage moving direction. Will gradually shift. Therefore, in the inspection apparatus of the present embodiment, the synchronization deviation between the scanning deflection frequency of the beam and the stage moving speed is eliminated by beam deflection in the same direction as the stage moving direction. This beam deflection is sometimes called back deflection.

  However, the stage moving speed Vs cannot be increased without limit, and if the width of the ROI scanning area is increased, the stage moving speed needs to be reduced. Conversely, if the length of the scanning skip area is large, the moving speed of the stage can be increased. For this reason, the stage moving speed Vs is determined by the ratio between the width of the scanning area and the width of the skip area.

  Next, an overall configuration diagram of the appearance inspection apparatus of the present embodiment is shown in FIG. A wafer 303, which is an object to be inspected, is placed on a stage stored in a sample chamber 304, and the circuit pattern of the wafer 303 is irradiated from the irradiator 301 to the circuit pattern of the wafer 303 while moving the stage. The secondary electrons or reflected electrons 305 to be detected are detected by the detector 306. Although not shown, optical means for beam irradiation control, such as a scanning deflector and an objective lens, is provided between the irradiator 301 and the wafer 303. The irradiator 301, the optical means, or the stage described above constitutes an imaging means for acquiring a charged particle beam image. Each component of the imaging unit such as the optical unit and the stage is controlled by the imaging device control unit 319. The image signal detected by the detector 306 is digitized through the AD converter 307 and input to the image processing device 308. The input image data is sent to the transfer buffer 309 in the image processing device 308. Of the image data sent to the transfer buffer 309, only the image data of a desired portion set by the distribution control unit 310 is selected, and PEs (Processor Elements) 312, 313, and 3 constituting a parallel processor are selected via the path switch 311. This is distributed to 314, and defect detection processing is performed. The extracted defect image is stored in the image server 317 via the communication bus 316. The detected defect information is stored in the control computer 315, and the defect detection result is displayed on a display of an EW (Engineering Work-station) 318 via the communication bus 316, thereby completing the inspection. The EW 318 also serves as a user interface. A recipe setting screen for setting inspection conditions is displayed on a display provided in the EW 318, and the set recipe contents are also stored in an external storage device built in the EW 318. The The EW 318 also serves as a host control device that controls the entire apparatus in an integrated manner, and supplies control information necessary for inspection to the image processing device 308 and the imaging device control means 319.

  FIG. 4 is an internal explanatory diagram of the distribution control unit 310 in FIG. 3. The distribution processor 401 executes the cut-out process of the image data transferred from the transfer buffer 309 and the transfer process to each parallel processor PE, and the cut-out process. An image distribution table 402 describing the execution conditions for the transfer process is provided. The image distribution table 402 stores the coordinate information of the image data to be extracted from the transfer buffer 309, the capacity of the image data to be extracted, and PENo which is the number of the parallel processor PE as the transfer destination. Each parameter is preliminarily set by the control computer 315. Are set as inspection conditions.

  Here, the control computer 315 displays and analyzes the data of the defect detection result, and the image data to be processed by each parallel processor PE 312, 313, 314 from the inspection condition (recipe information) given by the operator before the inspection. It plays the role of calculating conditions such as location, size, processing method, etc., and setting each parameter of the image processing apparatus 308 via the communication bus 316 as various parameter information for image processing. The image processing device 308 inputs the input image data from the AD converter 307 to the transfer buffer 309. The distribution processor 401 of the distribution control unit 310 determines an image of a desired portion of image data continuously input according to the contents of the image distribution table 402 in the distribution control unit 310 set by the control computer 315 before the examination. Only data is selected and distributed to the parallel processors PE 312, 313, 314 via the path switch 311.

  FIG. 5 is a diagram illustrating an internal configuration example of the parallel processor PE 312. In FIG. 3, image data input via the input / output control unit 501 from the input / output control unit 501 and path switch 311 that controls the input / output of image data is stored in an image memory 503 and an image stored in the image memory 503. At least one or more processors 504, 505, and 506 that perform defect detection processing on the data are provided, and data access therebetween is arbitrated by the arbiter 502. Each processor 504, 505, 506 includes a communication bus 507 used for setting inspection conditions, reference images, transfer of defect information, and the like, and a communication bus 508 for transferring defect images and the like. The communication bus 507 is a control computer. The communication bus 508 communicates with the image server 117 and the EW 318 via the communication bus 316.

  FIG. 6 shows an example of an operation sequence in the ROI inspection of this embodiment. The left side of FIG. 6 shows the ROI recipe setting sequence, and the right side shows the ROI inspection execution flow based on the set recipe. First, the recipe setting sequence will be described. When recipe setting is started (step 601), the apparatus operator first calls a recipe setting screen on the display screen of the EW 318 to set a reference image acquisition area (step 602).

  FIG. 7 shows an example of a setting screen for the reference image acquisition area called on the recipe setting screen. An image display area 701 with a first magnification is arranged on the left side of the reference image acquisition area setting screen. In FIG. 7, an image with a field of view magnification that displays a part of the memory mat area is displayed. Yes. This magnification is such that the width of the scanning stripe (scanning width of the primary electron beam) is displayed in the field of view, but it is also possible to display the entire die or the entire wafer by reducing the magnification. In the right half of FIG. 7, an image display area 702 of the second magnification is arranged, and a part of one memory mat is enlarged and displayed. The apparatus operator manually sets the reference image acquisition area by operating the trimming tool 703 on the image display area 702 at the second magnification. Actually, since the image is cut out from the reference image acquisition region, the reference image acquisition region is set slightly larger than the visual field size of the actual reference image. FIG. 7 shows a state in which a reference image acquisition area is set by surrounding a part on the memory mat displaying the upper left corner with a trimming tool 703. Further, the apparatus operator appropriately scrolls the display image on the image display area 702 of the second magnification and surrounds a part of the other corners with the trimming tool 703, so that the four corners of the memory mat are operated. To set the reference image acquisition area.

  The position information of the reference image acquisition area set by the trimming tool 703 is developed on the memory mat in another chip by the EW 318, and the reference image acquisition area is set for all chips existing on the semiconductor wafer 101. Since all circuit patterns formed on the wafer have the same structure, it is possible in principle to inspect with only one reference image. However, the circuit pattern is formed due to uneven exposure. Since the size, shape, etc. are slightly different for each region on the wafer, it is actually better to set a reference image for each chip. A reference image may be set in units by dividing an appropriate area in the chip. Alternatively, the reference image may be acquired only from the specified region by appropriately specifying a chip or a region on the wafer from which the reference image is acquired.

  Next, based on the position information of the set reference image acquisition area, the stage and the imaging unit are operated to acquire image data of the scanning stripe (step 603). At this time, the stage may be moved asynchronously with the image detection speed as described above, or may be moved at a normal synchronous speed. The image signal output from the detector 306 is converted into a digital signal by the AD converter 307, and then the image data is taken into the transfer buffer 309 of the image processing device 308. The distribution control unit 310 sequentially extracts the image data of the reference image acquisition area from the image data of the scanning stripe fetched into the transfer buffer 309 using the deflection information of the scanning deflector and the stage drive control information, and the control computer 315. The image data is transferred to the image server 317 via the communication bus 316 (step 604). Here, when the stage is moved asynchronously, the scanning buffer image in a state where the scanning skip area 111 in FIG. 1D does not exist is captured in the transfer buffer 309. Therefore, when the number of chips for acquiring the reference image is large, moving the stage asynchronously is advantageous in terms of speeding up the inspection.

  Here, since the position information in the chip of the appearance inspection apparatus is a relative amount specified in units of pixels used for inspection from an appropriate chip origin such as the left corner of the chip, for example, as shown in FIG. If the position information of the reference image acquisition area specified on the actual image is developed on another chip, the reference image acquisition area may be slightly different from the actual memory cell pattern. This is because the size of the circuit pattern formed in the chip is not necessarily an integral multiple of the pixel size, and a deviation of several pixels may occur depending on the accumulation of errors. Generating a reference image using image data cut out in a shifted state not only causes a false alarm, but also shifts the defect center in the difference image between the reference image and the inspection image even for a defect that actually exists. Therefore, the defect position is erroneously determined. Therefore, in the overview inspection apparatus of the present embodiment, the following prohibition conditions are provided when extracting image data for reference images. Hereinafter, the prohibition condition will be described with reference to FIGS. 8A and 8B.

  As shown in FIG. 8A, the reference image is cut out by providing an alignment region 802 for alignment around a region 801 used for actual comparison calculation. Here, when the image data of the reference image acquisition areas 805 and 806 set from the image data of the memory mat 804 on the scanning stripe 803 is cut out, the actual memory cell pattern may be shifted. 8B is a diagram showing a type of deviation, in which a region 801 used for the actual comparison operation is shifted as in types 808 and 809, and only an alignment region is included in types 811 and 812. There may be deviation.

  Therefore, in the case of the types 808 and 809, the distribution control unit 310 does not extract the image data for the reference image, and does not adopt the image. In the case of the types 811 and 812, the image cutout is executed by shifting the cutout position by the amount protruding from the memory mat 804. Since the position information of the outline 807 of the memory mat can be calculated from the position information of the chip origin, the distribution control unit 310 compares the position information of the memory mat outline 807 with the position information of the set reference image acquisition area, The above determination process is executed. Further, the area calculation of the shift areas 816 and 817 in the case of the types 811 and 812 is also performed by comparing the position information of the memory mat outline 807 with the position information of the set reference image acquisition area. As shown at 112 and 113 in FIG. 1D, the same prohibition condition is applied even when the ROI inspection area is set at both ends of the memory mat. The prohibition conditions described above are stored in the nonvolatile memory in the distribution control unit 310 in the form of a microprogram or software, and are read and executed as necessary.

  When the required number of reference image image data is accumulated in the image server 317, the image server 317 outputs the image data to the EW 318, and the EW 318 adds and averages the received image data to generate a reference image. The generated reference image is stored as a part of the inspection recipe in the external storage device of the EW 318 together with the chip ID indicating the number of the chip formed on the wafer (step 605). When the generation unit of the reference image is specified in units of the internal area of the chip, the reference image is stored in association with the in-chip ID indicating the area information in the chip. When the reference image generation unit is specified in units of regions divided on the wafer, the same reference image is registered for a plurality of chip IDs. This completes the recipe setting (step 606).

  When the setting of the inspection recipe is completed, the ROI inspection based on the set recipe is executed as shown in the right side view of FIG. The apparatus operator reads the registered inspection recipe from the display screen of the EW 318 (step 607), and then sets the ROI area to be inspected (step 608). The ROI area setting screen is almost the same as the screen shown in FIG. 7, and is displayed when the operator clicks an “inspection” button shown on the lower side of FIG. The ROI area is set by surrounding a part of the memory mat displayed in the image display area 702 of the second magnification with the trimming tool 703 in the same manner as the setting of the reference image acquisition area. Alternatively, information such as “mat angle”, “four corners”, “10 μm”, and “golden” is input to the ROI condition setting unit displayed below the image display area 702 of the second magnification. These are information indicating the detailed conditions of ROI inspection, which means that all four corners of the memory mat are to be inspected, the image acquisition size is 10 μm, and inspection is performed by comparison inspection with the golden image. ing. When the ROI area is set by the trimming tool 703, detailed information corresponding to the area surrounded by the trimming tool 703 is displayed in the ROI condition setting unit.

  When the operator clicks the inspection start button, the main inspection is started (step 609), and image data of the inspection stripe is acquired from the designated area on the wafer by moving the stage and scanning the primary electron beam. At the same time, the reference image data stored in the EW 318 is transferred to the processors PE 312, 313, and 314 together with each information of the chip ID and the in-chip ID. The distribution control unit 310 cuts out only the image data of the memory mat quadrilateral portions 107, 108, 109, and 110 from the acquired image data of the scanning stripe and distributes it to each parallel processor PE 312, 313, 314 via the path switch 311. To do. Then, alignment processing between the cut-out image and the reference image is performed, and comparison calculation processing is performed to detect a defect. The detected defect image is stored in the image server 117 via the communication bus 316. Further, the position information of the defect (position information of the center of the visual field of the defect image) is transferred to the EW 318 via the control computer 315 and stored in the built-in external storage device. When the image data has been acquired for all the ROI regions, this inspection ends (step 610).

101 Semiconductor wafer 102 Chip 103, 201, 803 Scan stripe 104 Stage moving direction 105 Memory mat area 106 Memory cell 107, 108, 109, 110, 112, 113, 202 ROI scan area 111 Scan skip area 203a, 203b, 203c, 203d , 203e Scan line 301 Irradiator 302 Primary electron beam 303 Wafer 304 Sample chamber 305 Secondary electron or backscattered electron 306 Detector 307 AD converter 308 Image processing device 309 Transfer buffer 310 Distribution control unit 311 Path switch 312, 313, 314 Processor Element (PE)
315 Control computer 316, 507, 508 Communication bus 317 Image server 318 EW
319 Imaging device control means 401 Distribution processor 402 Image distribution table 501 Input / output control unit 502 Arbiter 503 Image memory 504, 505, 506 Processor 701 First magnification image display area 702 Second magnification image display area 703 Trimming tool 801 Area used for actual comparison operation of reference image 802 Alignment area 804 Memory mat 805, 806 Reference image acquisition area 807 Memory mat outlines 808, 809, 810, 811, 812, 813, 814, 815 Types 816, 817 region

Claims (9)

An inspection apparatus that detects a defect by scanning an electron beam on a sample to be inspected to detect a secondary signal, and performing comparison operation processing with a predetermined reference image on image data formed from the secondary signal In
A host controller on which a setting screen for setting inspection position information on the sample to be inspected and acquisition position information of the reference image is displayed;
Imaging means for acquiring image data of the sample to be inspected based on the inspection position information or the acquisition position information of the reference image;
Image processing means for performing comparison operation processing between the inspection image data output from the imaging means and the reference image, and detecting the defect;
The image processing means includes a distribution control unit that extracts image data for the reference image from the image data so that an alignment region for alignment is included around a region used for the comparison calculation. Characteristic inspection device. The inspection apparatus according to claim 1,
The distribution controller is
When the alignment region protrudes from an image data region formed from the secondary signal, the inspection is performed by shifting the protruding portion in a direction in which the image data exists. The inspection apparatus according to claim 2,
The distribution controller is
The inspection apparatus, wherein when the area used for the comparison operation protrudes from the area of the image data formed from the secondary signal, the image data for the reference image is not cut out. The inspection apparatus according to any one of claims 1 to 3,
An image server for storing an image of a defect determined as a defect by the comparison operation;
The inspection apparatus characterized in that the host control device synthesizes a reference image from a plurality of reference image image data accumulated in the image server and stores the reference image. The inspection apparatus according to any one of claims 1 to 4,
A sample stage for moving the sample to be inspected;
Stage control means for controlling the moving speed of the sample stage,
The host controller is
Using the inspection position information, calculate a scan area where the scan is performed and a scan skip area where the scan is not performed,
The stage control means includes
An electron beam apparatus, wherein the moving speed of the sample stage is controlled in accordance with a ratio of a length of the scanning area and a length of the scanning skip area with respect to the moving direction of the sample stage. A secondary signal is detected from a scanning stripe formed by continuously moving a sample to be inspected by a sample stage and scanning an electron beam in a direction crossing the moving direction of the sample stage. In an inspection apparatus for detecting defects by executing a comparison operation process with a predetermined reference image for image data to be formed,
A host controller on which a setting screen for setting the acquisition position information of the reference image and the inspection position information on the scanning stripe is displayed;
Imaging means for acquiring image data of the sample to be inspected based on the inspection position information or the acquisition position information of the reference image;
Image data of the sample to be inspected and a comparison calculation process of the reference image, and comprising image processing means for detecting the defect,
The host controller is
Using the inspection position information, a scan area in which the scan is performed and a scan skip area in which the scan is not performed are set on the scan stripe,
The image processing means includes
An inspection apparatus comprising: a distribution control unit that extracts the image data for the reference image from the image data so that an alignment region for alignment is included around a region used for the comparison calculation. The inspection apparatus according to claim 6, wherein
The distribution controller is
When the alignment region protrudes from the scanning region, the inspection is performed by shifting the protruding portion in a direction in which image data exists, and performing the extraction. The inspection apparatus according to claim 7,
The distribution controller is
The inspection apparatus, wherein when the area used for the comparison operation protrudes from the scanning area, the image data for the reference image is not cut out. The inspection apparatus according to any one of claims 6 to 8,
An image server for storing an image of a defect determined as a defect by the comparison operation;
The inspection apparatus characterized in that the host control device synthesizes a reference image from a plurality of reference image image data accumulated in the image server and stores the reference image.

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