JP2015167190A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To complete off-set trimming for a plurality of voltage regulator circuits in a short time.SOLUTION: A semiconductor device comprises: a plurality of differential amplifiers DEF each of which creates an output signal AOUT by comparing corresponding correction reference potential VRTRM with internal potential VINT appearing at power supply wiring 14; a plurality of output drives DRV each of which drives the power supply wiring 14 based on the corresponding output signal AOUT; and a voltage monitor circuit 60 which monitors in a state where any one of the plurality of output drivers DRV is activated and all the rest are inactivated, a plurality of output signals AOUT input to the inactivated plurality of output drivers DRV. According to the present embodiment, off-set trimming can be simultaneously performed for a plurality of voltage regulator circuits. Accordingly, regardless of the number of voltage regulator circuits, off-set trimming can be completed in a short time.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of voltage regulator circuits.

  Many semiconductor devices are provided with a voltage regulator circuit for generating an internal potential (see Patent Document 1). The internal potential generated by the voltage regulator circuit is supplied to various circuit blocks in the semiconductor device via the power supply wiring, and is used as the operating potential of these circuit blocks.

  A plurality of voltage regulator circuits may be connected to the same power supply wiring in order to prevent local voltage fluctuations of the power supply wiring. In this case, if there is a difference in the output potential between the voltage regulator circuits, the response speed to the load current is different for each voltage regulator circuit, so that the internal potential tends to fluctuate. For this reason, in the manufacturing stage of the semiconductor device, fine adjustment of the output potential of the voltage regulator circuit is performed by performing offset trimming.

JP2013-118769A

  In the conventional trimming method, the output potential is generally measured in a state where only the voltage regulator circuit to be trimmed is activated among a plurality of voltage regulator circuits connected to the same power supply wiring. In this case, since each of the voltage regulator circuits is activated and trimmed in order, not only the number of voltage regulator circuits need to be measured, but also after the output potential is switched until the potential stabilizes. It is necessary to make a measurement after waiting for the time. Therefore, a semiconductor device having a large number of voltage regulator circuits has a problem that it takes a long time for offset trimming.

  A semiconductor device according to an aspect of the present invention includes a power supply line, a first differential amplifier that generates a first output signal by comparing a potential appearing in the power supply line and a reference potential, and the first output. A first output driver that drives the power supply line based on a signal, a first calibration circuit that generates a first calibration reference potential from the reference potential based on first trimming data, and the power supply line appear A second differential amplifier that generates a second output signal by comparing a potential with the first calibration reference potential; and a second output that drives the power supply wiring based on the second output signal. A driver, and a first determination circuit that generates a first determination signal based on a level of the second output signal in a state where the second output driver is inactivated. To do.

  A semiconductor device according to another aspect of the present invention includes a power supply line, a plurality of differential amplifiers each generating an output signal by comparing a corresponding reference potential and a potential appearing in the power supply line, and a corresponding output A plurality of output drivers that drive the power supply line based on a signal and a plurality of the deactivated plurality of output drivers in a state where any one of the plurality of output drivers is activated and all the others are deactivated. And a voltage monitor circuit that monitors a plurality of output signals input to the output driver.

  According to the present invention, since the determination is performed with the output driver deactivated, it is possible to simultaneously perform offset trimming on a plurality of voltage regulator circuits. As a result, offset trimming can be completed in a short time regardless of the number of voltage regulator circuits. In addition, since there is no need to wait for the time until the output potential becomes stable, the output potential can be switched at high speed.

1 is a block diagram showing a configuration of a semiconductor device 10 according to an embodiment of the present invention. 2 is a block diagram showing a tester 16 connected to the semiconductor device 10. FIG. It is a block diagram for demonstrating the structure of the voltage regulator circuits 20-2N in 1st Embodiment. FIG. 3 is a circuit diagram of a first-stage voltage regulator circuit 20 in the first embodiment. 2 is a circuit diagram of voltage regulator circuits 21 to 2N in the first embodiment. FIG. FIG. 6 is a timing diagram for explaining an offset trimming operation in the first embodiment. It is a block diagram for demonstrating the structure of the voltage regulator circuits 20-2N in 2nd Embodiment. It is a circuit diagram of the voltage regulator circuit 20 of the first stage in 2nd Embodiment. It is a circuit diagram of the voltage regulator circuits 21-2N in 2nd Embodiment. FIG. 10 is a timing diagram for explaining an offset trimming operation in the second embodiment. It is a block diagram for demonstrating the structure of the voltage regulator circuits 20-2N in 3rd Embodiment. FIG. 10 is a circuit diagram of a first-stage voltage regulator circuit 20 in a third embodiment. It is a circuit diagram of the voltage regulator circuits 21-2N in 3rd Embodiment. It is a timing diagram for demonstrating the offset trimming operation | movement in 3rd Embodiment. It is a timing diagram for demonstrating the offset trimming operation | movement in 3rd Embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>
A first embodiment of the present invention will be described.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to each embodiment of the present invention.

  The semiconductor device 10 includes a main circuit 12 and a plurality of voltage regulator circuits 20 to 2N. The semiconductor device 10 includes, for example, DRAM (Dynamic Random Access Memory), Flash Memrmoy, ReRAM (Resistive Random Access Memory), PCM (Phace Change Memory), MRAM (Magnetroresistive Random Access Memory), STT-RAM (Spin Transfer Torque Memroy) Corresponds to a semiconductor chip including a memory system circuit such as a CPU, a logic system circuit such as a CPU or a DPS, or a semiconductor electronic device or a semiconductor system including the semiconductor chip.

  The main circuit 12 is a circuit for realizing the main function of the semiconductor device 10. Data read from the main circuit 12 or generated by the main circuit 12 is output to the outside from the data output terminal DQ by the output circuit 12a.

  Voltage regulator circuits 20-2N receive external potential VDD and ground potential VSS supplied from the outside, and generate internal potential VINT based on the external potential VDD and ground potential VSS.

  The power supply wiring 14 is connected to the main circuit 12, and the main circuit 12 operates using the internal potential VINT supplied via the power supply wiring 14 as a power supply. The internal potential VINT is generated by N + 1 voltage regulator circuits 20 to 2N connected in parallel to the power supply wiring 14.

  The output levels of the voltage regulator circuits 20 to 2N are all designed to coincide with the desired internal potential VINT. However, the output level actually obtained with respect to the desired internal potential VINT is affected by process variations and the like. Has an offset. Such an offset is calibrated by performing offset trimming in the manufacturing stage of the semiconductor device 10.

  FIG. 2 shows the tester 16 connected to the semiconductor device 10.

  Offset trimming of the voltage regulator circuits 20 to 2N is performed using the tester 16 shown in FIG. Although details will be described later, in the semiconductor device 10 according to the present embodiment, offset trimming can be performed in parallel on the plurality of voltage regulator circuits 21 to 2N.

  FIG. 3 is a block diagram for explaining the configuration of the voltage regulator circuits 20 to 2N according to the first embodiment.

  Among the N + 1 voltage regulator circuits 20 to 2N, N voltage regulator circuits 21 to 2N excluding the voltage regulator circuit 20 include corresponding trimming control circuits 31 to 3N and antifuse circuits (AF) 41 to 4N, respectively. . The antifuse circuits 41 to 4N are circuits that permanently store the corresponding trimming data TRM. Although not particularly limited, in the present embodiment, the value of the trimming data TRM can be set to X + 1 stages from “0” to “X”. When the trimming data TRM is set to the minimum value “0”, the output level of the voltage regulator circuits 21 to 2N is the highest, and the trimming data TRM is set to the maximum value “X”. If so, the output levels of the voltage regulator circuits 21 to 2N are the lowest.

  The trimming data TRM stored in the antifuse circuits 41 to 4N is read by the corresponding trimming control circuits 31 to 3N and temporarily held in the holding circuit 40 when the power is turned on. The trimming data TRM held in the holding circuit 40 is supplied to the corresponding voltage regulator circuits 21 to 2N. The voltage regulator circuits 21 to 2N generate a calibration reference potential VRTRM, which will be described later, based on the trimming data TRM, and generate an internal potential VINT having an output level finely adjusted based on the calibration reference potential VRTRM.

  The value of the trimming data TRM held in the holding circuit 40 in the trimming control circuits 31 to 3N is updated in response to the update signal GL. The update signal GL is a signal supplied from the tester 16 during the trimming operation. In addition, during the trimming operation, test signals TEST0 and TEST1 and a test clock signal TCLK are supplied from the tester 16 to the voltage regulator circuits 20 to 2N.

  The voltage regulator circuits 20 to 2N are cascade-connected to the data output terminal DQ. As a result, the test output signal TOUT output from the previous voltage regulator circuit is supplied to the subsequent voltage regulator circuit as the test input signal TIN. The test input signal TIN to the first-stage voltage regulator circuit 20 is fixed at a low level (VSS).

  FIG. 4 is a circuit diagram of the first-stage voltage regulator circuit 20 in the first embodiment.

  The voltage regulator circuit 20 in the first stage drives the power supply wiring 14 based on the output signal AOUT and the differential amplifier DEF that generates the output signal AOUT by comparing the internal potential VINT appearing in the power supply wiring 14 with the reference potential VR. An output driver DRV is provided. With this configuration, the output driver DRV included in the first-stage voltage regulator circuit 20 pulls up the power supply wiring 14 so that the internal potential VINT becomes the same potential as the reference potential VR.

  The voltage regulator circuit 20 includes a latch circuit LT. The latch circuit LT includes input nodes IN and D, an output node OUT, a selection node S, and a clock node CK. The selection node S is a node for switching an input node to be used, and is supplied with a test signal TEST0. As a result, the input node D is selected while the test signal TEST0 is at the low level, and the input node IN is selected while the test signal TEST0 is at the high level. In the first-stage voltage regulator circuit 20, the input nodes IN and D are fixed at a low level (VSS).

  When the input node IN is selected, the logic level of the signal supplied to the input node IN is latched in synchronization with the rising edge of the test clock signal TCLK supplied to the clock node CK. On the other hand, when the test signal TEST0 changes from the low level to the high level, the logic level of the signal supplied to the input node D is latched in response to the rising edge. The latch data latched by the latch circuit LT is output from the output node OUT as the test output signal TOUT. The test output signal TOUT output from the first stage voltage regulator circuit 20 is used as the test input signal TIN of the next stage voltage regulator circuit 21.

  FIG. 5 is a circuit diagram of the voltage regulator circuits 21 to 2N in the first embodiment.

  The voltage regulator circuits 21 to 2N include a calibration circuit OFT, a driver control circuit CNT, and an inverter circuit AD in addition to the configuration of the first-stage voltage regulator circuit 20 shown in FIG.

  The voltage monitor circuit 60 includes an inverter circuit AD and a latch circuit LT. The inverter circuit AD and the latch circuit LT calibrate the voltage monitor circuit 60 that monitors the output signal AOUT from the differential amplifier DEF.

  The calibration circuit OFT generates a calibration reference potential VRTRM from the reference potential VR based on the corresponding trimming data TRM. The calibration reference potential VRTRM is supplied to the differential amplifier DEF. Accordingly, the differential amplifier DEF generates the output signal AOUT by comparing the internal potential VINT appearing on the power supply wiring 14 with the calibration reference potential VRTRM. The output signal AOUT is supplied not only to the output driver DRV but also to the inverter circuit AD.

  The inverter circuit AD is a determination circuit that determines an output signal AOUT that is an analog level, and the determination result is output as a determination signal VDET that is a 1-bit digital signal. The determination signal VDET is supplied to the input node D of the latch circuit LT. In the voltage regulator circuits 21 to 2N, the test input signal TIN output from the previous voltage regulator circuit is supplied to the input node IN of the latch circuit LT.

  The driver control circuit CNT is a circuit that switches activation and deactivation of the output driver DRV, and the switching is performed by a test signal TEST1. Specifically, if the test signal TEST1 is at a low level, the output driver DRV is activated, and if the test signal TEST1 is at a high level, the output driver DRV is deactivated. During normal operation, test signal TEST1 is always at a low level, and therefore all voltage regulator circuits 20-2N are activated.

  FIG. 6 is a timing chart for explaining the offset trimming operation in the first embodiment.

  In the offset trimming period, the test signal TEST1 is set to the high level. As a result, all the output drivers DRV included in the voltage regulator circuits 21 to 2N are deactivated, so that the power supply wiring 14 is driven only by the voltage regulator circuit 20. Therefore, the differential amplifier DEF included in the voltage regulator circuits 21 to 2N compares the internal potential VINT generated only by the voltage regulator circuit 20 with the calibration reference potential VRTRM. The output signal AOUT obtained by the comparison is A / D converted by the inverter circuit AD and input to the latch circuit LT as the determination signal VDET.

  At the timing when TEST1 in the offset trimming period is at a high level, the initial value of the trimming data TRM, for example, “0” is set in the holding circuit 40 in the trimming control circuits 31 to 3N. Therefore, each of the voltage regulator circuits 21 to 2N generates the determination signal VDET using the calibration reference potential VRTRM calibrated by the trimming data TRM whose value is “0”. Although not shown, when the value of the trimming data TRM is “0”, for example, the determination signal VDET of the voltage regulator circuits 21 to 2N−1 is at a low level, and the determination signal VDET of the voltage regulator circuit 2N is at a high level. .

  At time t10, the test signal TEST0 is set to the high level. Thereby, the determination signal VDET is latched by the latch circuit LT in synchronization with the time t10, and the input node IN of the latch circuit LT is selected. Then, when the test clock signal TCLK is clocked, the determination signal VDET latched in the voltage regulator circuits 20 to 2N is transferred to the output circuit 12a and serially output from the data output terminal DQ. The determination signal VDET output from the data output terminal DQ is taken into the tester 16 and stored in the memory 18 in the tester 16. This completes the measurement when the value of the trimming data TRM is “0”, that is, “trimming setting 0” shown in FIG.

  At t11, the test signal TEST0 returns from the high level to the low level.

  When the update signal GL is input as a high-level one-shot pulse, the trimming data TRM held in the holding circuit 40 in the trimming control circuits 31 to 3N is counted up from “0” to “1”.

  Here, when the trimming data TRM is “1”, each of the voltage regulator circuits 21 to 2N uses the calibration reference potential VRTRM calibrated by the trimming data TRM whose value is “1”. Each of the voltage regulator circuits 21 to 2N generates a determination signal VDET when the trimming data TRM having a value “1” is used. Although not shown, when the value of the trimming data TRM is “1”, as an example, the determination signals VDET of the voltage regulator circuits 21 and 2N−1 are at a high level.

  At time t12, the test signal TEST0 is again set to the high level. Thereby, the determination signal VDET is latched by the latch circuit LT in synchronization with the time t12, and the input node IN of the latch circuit LT is selected. Then, when the test clock signal TCLK is clocked, the determination signal VDET latched in the voltage regulator circuits 20 to 2N is transferred to the output circuit 12a and serially output from the data output terminal DQ. The determination signal VDET output from the data output terminal DQ is taken into the tester 16 and stored in the memory 18 in the tester 16. This completes the measurement when the value of the trimming data TRM is “0”, that is, “trimming setting 1” shown in FIG.

  At t13, the test signal TEST0 returns from the high level to the low level.

  In the offset trimming operation, the above-described operation is repeated up to the maximum trim value “X”.

  By repeating the above-described operation, the determination signal VDET from when the trimming data TRM is the minimum value “0” to the maximum value “X” is obtained, and these are all stored in the memory 18 in the tester 16. The

  The optimum trimming data TRM is set in the holding circuit 40 in the trimming control circuits 31 to 3N based on the determination signal VDET stored in the memory 18, respectively. Setting of the trimming data TRM is executed by writing the trimming data TRM into the corresponding antifuse circuits 41 to 4N. In this way, a series of offset trimming operations are completed. Here, the optimum trimming data TRM to be written in the antifuse circuits 41 to 4N may be the trimming data TRM when the determination signal VDET corresponding to each of the voltage regulator circuits 21 to 2N changes to a high level.

  According to the present embodiment, offset trimming can be simultaneously performed on the plurality of voltage regulator circuits 21 to 2N. In addition, since all the output drivers DRV of the voltage regulator circuits 21 to 2N are deactivated, there is no need to wait for the stabilization of the potential that is changed by switching the trimming data TRM. Thereby, a series of trimming operations can be completed in a short time.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

  FIG. 7 is a block diagram for explaining the configuration of the voltage regulator circuits 20 to 2N in the second embodiment.

  The voltage regulator circuits 20 to 2N are not cascade-connected to the data output terminal DQ. Instead, NOR gate circuits 51 to 5N are added before the trimming control circuits 31 to 3N. Accordingly, the test clock signal TCLK and the test signal TEST0 are not used. Since the other points are the same as those of the first embodiment shown in FIG. 3, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The NOR gate circuits 51 to 5N receive the determination signals VDET (VDET1 to VDETN) and the update signal GL output from the corresponding voltage regulator circuits 21 to 2N, and supply the output signals to the trimming control circuits 31 to 3N, respectively. Therefore, the update signal GL is masked for the trimming control circuits 31 to 3N corresponding to the voltage regulator circuits 21 to 2N whose determination signal VDET has changed to the high level.

  FIG. 8 is a circuit diagram of the first-stage voltage regulator circuit 20 in the second embodiment. FIG. 9 is a circuit diagram of the voltage regulator circuits 21 to 2N in the second embodiment.

  Voltage regulator circuits 20-2N have the same circuit configuration as voltage regulator circuits 20-2N shown in FIGS. 4 and 5 in that latch circuit LT is eliminated. For this reason, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  FIG. 10 is a timing chart for explaining the offset trimming operation in the second embodiment.

  In the offset trimming operation in the second embodiment, as in the first embodiment, the update signal GL is periodically activated while the test signal TEST1 is fixed at a high level. In the present embodiment, the test signal TEST0 is not used.

  As the initial value of the trimming data TRM, a minimum value, for example, “0” is set in the holding circuit 40 in the trimming control circuits 31 to 3N. Then, in response to the activation of the update signal GL, the value of the trimming data TRM is counted up as “1”, “2”. In conjunction with this, in each of the voltage regulator circuits 21 to 2N, the calibration reference potential VRTRM gradually decreases, and when this falls below the internal potential VINT on the power supply wiring 14, the determination signal VDET changes to a high level.

  When the determination signal VDET changes to high level, the trimming control circuits 31 to 3N corresponding to the determination signal VDET mask the update signal GL. Thereafter, even if the update signal GL is activated, the value of the trimming data TRM changes. Disappear. Therefore, if the update signal GL is activated X times, the holding circuit 40 in the trimming control circuits 31 to 3N holds the trimming data TRM having the value immediately before the determination signal VDET changes to the high level. It will be.

  Thus, after the values of the trimming data TRM in the trimming control circuits 31 to 3N are determined, the offset trimming operation is completed by writing the trimming data TRM into the antifuse circuits 41 to 4N.

  In the second embodiment, since the optimum trimming data TRM is held in each of the trimming control circuits 31 to 3N, in addition to the effect of the first embodiment, the determination signal VDET is not output to the outside. A series of offset trimming operations can be completed.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

  FIG. 11 is a block diagram for explaining the configuration of the voltage regulator circuits 20 to 2N in the third embodiment.

  The two types of reference potentials VRa and VRb are supplied to the voltage regulator circuits 20 to 2N. Two sets of trimming control circuits 31a to 3Na and 31b to 3Nb and two sets of antifuse circuits 41a to 4Na and 41b to 4Nb are assigned to the respective voltage regulator circuits 21 to 2N. Since the other points are the same as those of the first embodiment shown in FIG. 3, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  The antifuse circuits 41a to 4Na are circuits that store corresponding trimming data TRMa, respectively. The trimming data TRMa stored in the antifuse circuits 41a to 4Na is read by the trimming control circuits 31a to 3Na and supplied to the corresponding voltage regulator circuits 21 to 2N. Similarly, the antifuse circuits 41b to 4Nb are circuits that store corresponding trimming data TRMb. The trimming data TRMb stored in the antifuse circuits 41b to 4Nb is read by the trimming control circuits 31b to 3Nb and supplied to the corresponding voltage regulator circuits 21 to 2N.

  FIG. 12 is a circuit diagram of the first-stage voltage regulator circuit 20 in the third embodiment.

  The voltage regulator circuit 20 includes two differential amplifiers DEFa and DEFb and two output drivers DRVa and DRVb. The differential amplifier DEFa compares the reference potential VRa with the internal potential VINT on the power supply wiring 14, and generates an output signal AOUTa based on the result. The output signal AOUTa is supplied to the output driver DRVa, whereby the power supply wiring 14 is pulled up. On the other hand, the differential amplifier DEFb compares the reference potential VRb with the internal potential VINT on the power supply wiring 14, and generates an output signal AOUTb based on the result. The output signal AOUTb is supplied to the output driver DRVb, whereby the power supply wiring 14 is pulled down.

  The first-stage voltage regulator circuit 20 includes driver control circuits CNTa and CNTb that control activation and deactivation of the output drivers DRVa and DRVb.

  The driver control circuit CNTa is controlled by a test signal TEST3, and the driver control circuit CNTb is controlled by a test signal TEST4. Other configurations are the same as those of the voltage regulator circuit 20 shown in FIG. During normal operation, the test signals TEST3 and TEST4 are always at a low level.

  FIG. 13 is a circuit diagram of the voltage regulator circuits 21 to 2N in the third embodiment.

  Similar to the voltage regulator circuit 20 in the first stage, the voltage regulator circuits 21 to 2N include two differential amplifiers DEFa and DEFb and two output drivers DRVa and DRVb.

  The differential amplifier DEFa compares the calibration reference potential VRTRMa calibrated by the calibration circuit OFTa with the internal potential VINT on the power supply wiring 14, and generates an output signal AOUTa based on the result. The output signal AOUTa is supplied to the output driver DRVa, whereby the power supply wiring 14 is pulled up. The calibration circuit OFTa is generated by calibrating the reference potential VRa based on the trimming data TRMa. Activation and deactivation of the output driver DRVa is controlled by the driver control circuit CNTa based on the test signal TEST1.

  The differential amplifier DEFb compares the calibration reference potential VRTRMb calibrated by the calibration circuit OFTb with the internal potential VINT on the power supply wiring 14, and generates an output signal AOUTb based on the result. The output signal AOUTb is supplied to the output driver DRVb, whereby the power supply wiring 14 is pulled down. The calibration circuit OFTb is generated by calibrating the reference potential VRb based on the trimming data TRMb. Activation and deactivation of the output driver DRVb is controlled by the driver control circuit CNTb based on the test signal TEST2.

  During normal operation, the test signals TEST1, TEST2 are always at a low level.

  The output signal AOUTa is supplied to the inverter circuit ADa, and the output of the determination signal VDETa is supplied to the input node D of the latch circuit LT via the selector 50. Similarly, the output signal AOUTb is supplied to the inverter circuit ADb, and the determination signal VDETb that is the output thereof is supplied to the input node D of the latch circuit LT via the selector 50. The selector 50 selects one of the determination signals VDETa and VDETb based on the test signal TEST1.

  As described above, since the pull-up side output driver DRVa and the pull-down side output driver DRVb are provided in this embodiment, when the internal potential VINT on the power supply wiring 14 is low, it is pulled up by the output driver DRVa. When the internal potential VINT on 14 is high, it is pulled down by the output driver DRVb. As a result, the internal potential VINT on the power supply wiring 14 can be further stabilized.

  14 and 15 are timing charts for explaining an offset trimming operation in the third embodiment.

  In the third embodiment, offset trimming on the pull-up side and offset trimming on the pull-down side are performed in this order.

  First, when performing offset trimming on the pull-up side, as shown in FIG. 14, the test signal TEST3 is set to a low level, and the test signals TEST1, TEST2, and TEST4 are set to a high level. Thereby, only the output driver DRVa in the voltage regulator circuit 20 is activated. Therefore, the power supply wiring 14 is driven only by the output driver DRVa in the voltage regulator circuit 20. In this state, as in the first embodiment, the test signal TEST0 and the update signal GL are changed, and the test clock signal TCLK is clocked. As a result, the determination signal VDETa corresponding to the pull-up side is stored in the memory 18 in the tester 16.

  Next, when performing offset trimming on the pull-down side, as shown in FIG. 15, the test signal TEST4 is set to the low level, and the test signals TEST1, TEST2, and TEST3 are set to the high level. Thereby, only the output driver DRVb in the voltage regulator circuit 20 is activated. Therefore, the power supply wiring 14 is driven only by the output driver DRVb in the voltage regulator circuit 20. In this state, as in the first embodiment, the test signal TEST0 and the update signal GL are changed, and the test clock signal TCLK is clocked. Thereby, the determination signal VDETb corresponding to the pull-down side is stored in the memory 18 in the tester 16.

  Based on the determination signal VDETa stored in the memory 18, optimum trimming data TRMa is set in the holding circuit 40 in each of the trimming control circuits 31 a to 3 Na. Further, based on the determination signal VDETb stored in the memory 18. The optimum trimming data TRMb is set for each of the holding circuits 40 in the trimming control circuits 31b to 3Nb. Finally, if the trimming data TRMa held in the holding circuit 40 is written to the antifuse circuits 41a to 4Na and the trimming data TRMb is written to the antifuse circuits 41b to 4Nb, a series of offset trimming operations are completed.

  As described above, according to the present embodiment, a series of offset trimming operations are performed even when the voltage regulator circuits 20 to 2N are provided with the pull-up output driver DRVa and the pull-down output driver DRVb. It can be completed in a short time.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the trimming data TRM is permanently stored using the antifuse circuit, but other nonvolatile memory circuits such as an optical fuse circuit and a ROM circuit are used instead of the antifuse circuit. You may use.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Main circuit 12a Output circuit 14 Power supply wiring 16 Tester 18 Memory 20-2N Voltage regulator circuit 31-3N, 31a-3Na, 31b-3Nb Trimming control circuit 40 Holding circuit 41-4N, 41a-4Na, 41b-4Nb Antifuse circuit 50 Selectors 51 to 5N NOR gate circuit 60 Voltage monitor circuit AD, ADa, ADb Inverter circuit (determination circuit)
CNT, CNTa, CNTb Driver control circuit DEF, DEFa, DEFb Differential amplifier DQ Data output terminal DRV, DRVa, DRVb Output driver LT Latch circuit OFT, OFTa, OFTb Calibration circuit TRM, TRMa, TRMb Trimming data VDETa, VDETa, VDETb Signal VINT Internal potential VR, VRa, VRb Reference potential VRTRM, VRTMa, VRTRMb Calibration reference potential

Claims (12)

Power wiring,
A first differential amplifier that generates a first output signal by comparing a potential appearing in the power supply wiring with a reference potential;
A first output driver for driving the power supply line based on the first output signal;
A first calibration circuit for generating a first calibration reference potential from the reference potential based on first trimming data;
A second differential amplifier that generates a second output signal by comparing a potential appearing in the power supply wiring with the first calibration reference potential;
A second output driver for driving the power supply line based on the second output signal;
And a first determination circuit that generates a first determination signal based on a level of the second output signal in a state where the second output driver is deactivated. . A second calibration circuit for generating a second calibration reference potential from the reference potential based on second trimming data;
A third differential amplifier that generates a third output signal by comparing the potential appearing in the power supply wiring with the second calibration reference potential;
A third output driver for driving the power supply line based on the third output signal;
A second determination circuit configured to generate a second determination signal based on a level of the third output signal in a state where the second and third output drivers are inactivated. The semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein each of the first to third output drivers is a driver circuit that pulls up the power supply wiring.   The first and second output drivers are both driver circuits that pull up the power supply wiring, and the third output drivers are driver circuits that pull down the power supply wiring. 2. The semiconductor device according to 2.   5. The semiconductor device according to claim 2, further comprising first and second trimming control circuits that temporarily hold the first and second trimming data, respectively. 6.   6. The semiconductor device according to claim 5, wherein the first and second trimming control circuits update the first and second trimming data in synchronization with an update signal, respectively.   The first and second trimming control circuits are respectively synchronized with the update signal in response to the first and second determination signals indicating a first logic level. The semiconductor device according to claim 6, wherein updating of the trimming data is stopped.   7. The semiconductor device according to claim 2, further comprising first and second nonvolatile memory circuits that permanently hold the first and second trimming data, respectively. An external terminal,
And first and second latch circuits for latching the first and second determination signals, respectively.
The semiconductor device according to claim 2, wherein the first and second latch circuits are cascade-connected to the external terminal. Power wiring,
A plurality of differential amplifiers each generating an output signal by comparing a corresponding reference potential and a potential appearing in the power supply wiring;
A plurality of output drivers for driving the power supply lines based on respective corresponding output signals;
A voltage monitor circuit that monitors a plurality of output signals input to the deactivated output drivers in a state where any one of the plurality of output drivers is activated and all the others are deactivated A semiconductor device comprising: The voltage monitor circuit includes a plurality of latch circuits that respectively latch the plurality of output signals,
The semiconductor device according to claim 10, wherein the plurality of latch circuits are cascade-connected.   The semiconductor device according to claim 10, further comprising a calibration circuit that changes a level of the reference potential.

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