JP2015158957A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test whether or not an input buffer and output buffer operate normally.SOLUTION: A semiconductor device includes: a data input/output terminal DQa; a data output circuit 63 whose output node is connected to the data input/output terminal DQa; a data input circuit 64 whose input node is connected to the data input/output terminal DQa ; a read/write bus RWBUS that supplies an input node of the data output circuit 63 with test read data tRD which is read from a memory cell array 60; and a data comparison circuit 65a that compares test write data tWD and test read data tRD which is output from an output node of the data input circuit 64, to generate a determination signal TCMP0. The data input circuit 64 transfers the test read data tRD to the data comparison circuit 65a in response to a test clock signal SCLK, and the data comparison circuit 65a outputs a determination signal TCMP0 in response to the test clock signal SCLK.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of performing an operation test on an input buffer and an output buffer.

  In recent years, it has been desired to further increase the data transfer rate between the semiconductor memory and the controller chip. In order to achieve this, various semiconductor memories have been devised in which the bit width of data input / output, that is, the number of input / output terminals is increased as compared with a conventional semiconductor memory. Examples of such a semiconductor memory include a high-bandwidth memory (High Band-width Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), and a wide I / O type DRAM (Wide-IO DRAM) ( Patent Document 1) is known.

  In such a semiconductor memory, since the number of external terminals including data input / output terminals is extremely larger than that of a normal DRAM, each terminal is constituted by microelectrodes called microbumps. Since a large number of micro bumps are arranged at a very narrow pitch, it is difficult to bring the tester probe into direct contact with the micro bumps during a test operation. For this reason, in such a semiconductor memory, a test pad electrode is provided separately from the microbump. During a test operation, a tester probe is brought into contact with the test pad electrode to input a signal. Output.

JP2012-243251A

  In an operation test using a pad electrode for a test, test data is usually input via a pad electrode for address input, and a determination signal indicating the test data or a test result is output via a pad electrode for data output. Is done. However, in this case, since the input buffer and the output buffer used in the normal operation mode are not used, there is a problem that it is impossible to test whether the input buffer and the output buffer operate normally.

  The above problem is not limited to the specific semiconductor memory described above, and is a problem that occurs in all semiconductor devices that do not use the input buffer and output buffer used in the normal operation mode during the operation test.

  A semiconductor device according to an aspect of the present invention includes a memory cell array, a first data output terminal, a first output circuit whose output node is connected to the first data input / output terminal, and an input node that is the first data output terminal. An input circuit connected to the data input / output terminal, a data wiring for supplying first data read from the memory cell array to an input node of the first output circuit, second data, and the input A data comparison circuit that generates a determination signal by comparing the first data output from an output node of the circuit, wherein the input circuit is responsive to a first clock signal, The first data output from one output circuit is transferred to the data comparison circuit, and the data comparison circuit outputs the determination signal in response to the first clock signal. .

  A semiconductor device according to another aspect of the present invention includes first and second terminals, a memory cell array, a first output circuit connected between the first terminal and the memory cell array, and a first input node. Connected in common to the first terminal and the output circuit, connected to the memory cell array at the first output node, connected to the input circuit including the second output node, and the second output node of the input circuit. And a second output circuit connected between the comparison circuit and the second terminal, wherein the first input circuit, the comparison circuit, and the second output circuit are the first A pipeline operation is executed in accordance with the clock signal.

  According to the present invention, since the test read data read from the memory cell array can be supplied to the data comparison circuit via the output circuit and the input circuit, the output buffer included in the output circuit and the input included in the input circuit. It is possible to determine whether or not the buffer is operating normally by an operation test. In addition, since both the input circuit and the data comparison circuit perform an operation in response to the test clock signal, it is possible to sequentially process the test read data even when the test read data is continuously read. Become.

1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a preferred first embodiment of the present invention. It is typical sectional drawing for demonstrating the structure of 10 A of semi-finished products. 3 is a plan view of a main surface 20F of the memory chip 20. FIG. 4 is a block diagram for explaining a circuit configuration of a memory chip 20. FIG. It is a block diagram for demonstrating the circuit structure of channel ChA. 3 is a circuit diagram of a test lead control circuit 70. FIG. 3 is a circuit diagram of a data output circuit 63 and a data input circuit 64. FIG. 3 is a circuit diagram of a three-input selector 110. FIG. It is a truth table which shows the logic level of the various control signals in each operation mode. 2 is a circuit diagram of an output circuit 120. FIG. It is a circuit diagram which shows the structure of the principal part of the data comparison circuit 65a. It is a circuit diagram which shows the structure of the principal part of the data comparison circuit 65b. 3 is a circuit diagram of a data output circuit 69. FIG. 4 is a timing chart for explaining a Loop Back Write operation of the semiconductor device 10. FIG. 4 is a timing chart for explaining a Loop Back Read operation of the semiconductor device 10. FIG. FIG. 5 is a timing diagram for explaining a Loop Back Read operation in synchronization with a test clock signal SCLK. It is a typical sectional view for explaining structure of semiconductor device 100 by a 2nd embodiment of the present invention. It is typical sectional drawing for demonstrating the structure of 100 A of semi-finished products. It is a schematic diagram for demonstrating the connection state of penetration electrode TSV1, TSV2. It is sectional drawing which shows the structure of penetration electrode TSV1. It is a typical sectional view for explaining the structure of semiconductor device 200 by a 3rd embodiment of the present invention. It is a typical sectional view for explaining structure of semiconductor device 300 by a 4th embodiment of the present invention. It is a schematic plan view for explaining the structure of a semiconductor device 400 according to a fifth embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a preferred first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device 10 according to the present embodiment has a configuration in which a memory chip 20 and a control chip 30 are stacked. The memory chip 20 is a so-called wide IO type DRAM, and a main surface 20F is provided with a plurality of surface micro bumps MFB (bump electrodes) and a plurality of test pads TP (pad electrodes). The main surface 20F is the surface on which circuit elements such as transistors are formed. In the example shown in FIG. 1, the main surface 20F of the memory chip 20 faces downward. That is, in the present embodiment, the memory chip 20 is stacked on the control chip 30 in a face-down manner.

  The control chip 30 is a semiconductor chip (SOC) that controls the operation of the memory chip 20, and is mounted on the circuit board 40 in a face-down manner. That is, the control chip 30 is mounted such that the main surface 30F faces the circuit board 40 side and the back surface 30B faces the memory chip 20 side. A plurality of front surface micro bumps CFB are formed on the main surface 30F of the control chip 30, and a plurality of back surface micro bumps CBB are formed on the back surface 30B of the control chip 30. The front surface microbump CFB is bonded to the substrate electrode 41 provided on the circuit board 40, and the back surface microbump CBB is bonded to the front surface microbump MFB provided on the memory chip 20. The internal circuit provided in the control chip 30 is connected to the front surface micro bump CFB and also connected to the back surface micro bump CBB through a through electrode TSV (Through Substrate Via) provided through the control chip 30. Has been.

  The circuit board 40 has a structure in which a substrate electrode 41 is provided on the upper surface side on which the memory chip 20 and the control chip 30 are mounted, and an external terminal 42 is provided on the lower surface side. The substrate electrode 41 and the external terminal 42 are connected to each other via a through-hole conductor (not shown) provided through the circuit substrate 40. Further, a sealing resin 50 is provided on the upper surface of the substrate electrode 41 so as to cover the memory chip 20 and the control chip 30, thereby providing the semiconductor device 10 as one package.

  With this configuration, a signal (address signal, command signal, clock signal, write data, etc.) input via the external terminal 42 is first input to the control chip 30, and after undergoing necessary signal processing by the control chip 30, the memory It is supplied to the chip 20. On the other hand, a signal (such as read data) output from the memory chip 20 is input to the control chip 30 and is output to the outside from the external terminal 42 through necessary signal processing by the control chip 30.

  In the manufacturing process of the semiconductor device 10, after mounting the control chip 30 and the memory chip 20 on the circuit board 40, these chips 20 and 30 may be sealed with a sealing resin 50, as shown in FIG. The semi-finished product 10A may be prepared and connected to the control chip 30 and the circuit board 40. The semi-finished product 10A shown in FIG. 2 includes a sealing resin 50 that covers each surface except the memory chip 20 and its main surface 20F. If such a semi-finished product 10A is used, it is possible to appropriately connect the control chips 30 that differ depending on the specifications and applications, so that versatility can be improved.

  FIG. 3 is a plan view of the main surface 20F of the memory chip 20.

  As shown in FIG. 3, the main surface 20F of the memory chip 20 is provided with four channels ChA to ChD arranged in a matrix in the X direction and the Y direction. Each of the channels ChA to ChD is a circuit block that can operate as a single DRAM. Therefore, the memory chip 20 has a configuration in which four independent DRAMs are integrated into one chip.

  The main surface 20F of the memory chip 20 is provided with a plurality of micro bumps MFBa to MFBd corresponding to the channels ChA to ChD. The number of data micro-bumps MFBa to MFBd assigned to each channel ChA to ChD, that is, the number of data input / output terminals is as large as 128, for example, and a large number of micro-bumps MFBa to MFBd for power supply are necessary. Therefore, for example, about 300 micro bumps MFBa to MFBd are provided for each of the channels ChA to ChD. For this reason, more than 1000 micro bumps MFB are used in the entire chip.

  These micro bumps MFB include test terminals called direct access terminals. However, since the size of the micro bump MFB is very small, it is difficult to bring the tester probe into contact with the direct access terminal. For this reason, each direct access terminal is assigned a test pad TP for contacting a tester probe. The test pad TP has a larger plane size than the micro bump MFB so that the tester probe can be easily brought into contact with the test pad TP. With this configuration, an operation test can be performed using the test pad TP on the memory chip 20 in a wafer state before stacking, for example, and after stacking on the control chip 30, the control chip 30 can be externally connected. The operation test of the memory chip 20 can be performed by accessing the micro bump MFB for direct access.

  FIG. 4 is a block diagram for explaining a circuit configuration of the memory chip 20.

  In FIG. 4, a double circle indicates a micro bump MFB (bump electrode), and a double square indicates a test pad TP (pad electrode). The signal having “DA” at the head of the signal name and the test signal TEST are signals that are input (or output) through the direct access terminal. As shown in FIG. 4, each direct access terminal is provided with a corresponding test pad TP. In addition, signals having “a” to “d” at the end of the signal names are signals corresponding to the channels ChA to ChD, respectively.

  For example, the signal SIGa shown in FIG. 4 is an input signal supplied to the channel ChA and includes an address signal ADDa, a command signal CMDa, a chip select signal CS0a, a clock signal CLKa, a clock enable signal CKE0a, and the like. The channel ChA receives these input signals SIGa and performs a read operation, a write operation, and the like. When the channel ChA performs a read operation, the read data DQa that has been read is output via the micro bump MFBa (first terminal). On the other hand, when the channel ChA performs a write operation, the write data DQa input via the micro bump MFBa is supplied to the channel ChA.

  The same applies to the other channels ChB to ChD, which respectively receive corresponding input signals SIGb to SIGd, and output read data DQb to DQd or input write data DQb to DQd.

  On the other hand, a signal input through the direct access terminal is input in common to the channels ChA to ChD. Signals input via the direct access terminal include an address signal DA_ADD, a command signal DA_CMD, a chip select signal DA_CS0, a clock signal DA_CLK, a clock enable signal DA_CKE0, a test signal TEST, and the like. Since these signals are commonly assigned to the channels ChA to ChD, the channels ChA to ChD operate in parallel during the test operation, and the determination signals DA_DQa to DA_DQd, which are test results, are respectively associated with the corresponding direct access. To the micro bump MFB or the test pad TP (second terminal).

  FIG. 4 shows an example in which each of the boundary scan signals BSCTL1 to BSCTL1 to 3 is supplied from the corresponding microbump MFB. However, the present invention is not limited to this configuration. For example, the boundary scan signals BSCTL1 to 3 are supplied from the outside of the memory lip 20 via the micro bumps, and the boundary scan signal generation circuit for generating the boundary scan signals BSCTL1 to 3 is mounted on the memory chip 20. You can also. In this case, the boundary scan signal generation circuit generates a boundary scan signal in accordance with at least a part of the signal input via the direct access terminal, for example.

  FIG. 5 is a block diagram for explaining the circuit configuration of the channel ChA. The other channels ChB to ChD also basically have the same circuit configuration as that of the channel ChA, and therefore redundant description is omitted.

  As shown in FIG. 5, the channel ChA includes a memory cell array 60 and an access control circuit 61 that performs an access operation to the memory cell array 60. The access control circuit 61 performs an access operation to the memory cell array 60 based on an input signal SIG including an address signal ADD, a command signal CMD, a chip select signal CS, a clock signal CLK, and a clock enable signal CKE. The input signal SIG is supplied from the input switching circuit 62. The input switching circuit 62 receives the input signal SIGa for normal operation and the input signal DA_SIG for test operation, and outputs one selected based on the test signal TEST to the access control circuit 61 as the input signal SIG. Thus, the normal operation input signal SIGa is supplied to the access control circuit 61 during the normal operation, and the test operation input signal DA_SIG is supplied to the access control circuit 61 during the test operation.

  When the write operation is executed during the normal operation, the write data DQa input from the outside via n + 1 micro bumps MFBa is transferred to the memory cell array 60 via the data input circuit 64 and the read / write bus RWBUS (data wiring). To be supplied. On the other hand, when the write operation is executed during the loopback test operation (first test operation), the test write data tWD0 held in the test data register 66 is inverted by the inversion circuit 67 and the data output circuit 63 (first output). Circuit) is transferred (looped back) to the data input circuit 64 as test write data tWD. The data input circuit 64 supplies test write data tWD (second data) to the memory cell array 60. The test write data tWD is the same as or at least one bit inverted from the test write data tWD0, and has an n + 1 bit configuration composed of W0 to Wn. The test data register 66 is activated by the enable signal TPen and plays a role of temporarily holding the test write data tWD0 input via the address direct access terminal.

  Further, in both the normal operation and the test operation, when the read operation is executed, the read data DQa read from the memory cell array 60 is supplied to the data output circuit 63 via the read / write bus RWBUS. The read data DQa has an n + 1 bit configuration including DQa0 to DQan.

  Then, the read data DQa read in the normal operation is output to the outside from the n + 1 micro bumps MFBa. On the other hand, in the loopback test operation (first test), the read data DQa (first data) is transferred (loopback) to the data input circuit 64 via the data output circuit 63. The data input circuit 64 transfers the read data DQa as test read data tRD to the data comparison circuit 65a. Similarly to the read data DQa, the test read data tRD has an n + 1 bit configuration including R0 to Rn. Details of the loopback test operation will be described later.

  During the loopback test operation, test write data tWD is supplied to the data comparison circuit 65. Then, the data comparison circuit 65a compares the test read data tRD with the test write data tWD. The data comparison circuit 65a compares them in response to the enable signal CMPen0, and outputs a determination signal TCMP0 generated according to the result to the data output circuit 69.

  The test write data tWD is also supplied to the data comparison circuit 65b. The data comparison circuit 65b is a circuit that compares the bypass signal tO output from the data output circuit 63 with the test write data tWD. The bypass signal tO has an n + 1 bit configuration including O0 to On, and is data that bypasses the output buffer included in the data output circuit 63. The data comparison circuit 65b compares these signals in response to the enable signal CMPen1, and outputs a determination signal TCMP1 generated according to the result to the data output circuit 69.

  The enable signals TPen, CMPen0, and CMPen1 are generated by the test mode control circuit 68. The test mode control circuit 68 generates enable signals TPen, CMPen0, and CMPen1 based on the address signal ADD and the command signal CMD during a test operation, and also generates a selection signal SWC, an enable signal DAOBUFen, a test mode signal TESTL, and the like.

  The test mode signal TESTL is supplied to the test read control circuit 70 and the test clock generation circuit 71. The test read control circuit 70 receives the read signal RCOM and the enable signal OBUFen supplied from the access control circuit 61 in addition to the test mode signal TESTL, and generates loopback signals TLOOP_RD0, TLOOP_RD1, and TLOOP_WR based on them. The read signal RCOM is a signal that is activated when the command signal CMD indicates a read command. The enable signal OBUFen is a signal that is activated after a predetermined period of time has elapsed when the command signal CMD indicates a read command.

  The loopback signal TLOOP_RD0 is supplied to the selector 73 via the OR gate circuit 72. The loopback signal TLOOP_RD1 and the loopback signal TLOOP_WR are supplied to the data output circuits 69 and 63, respectively.

  The test clock generation circuit 71 receives the boundary scan clock signal SCK and the chip select signal DA_CS0 in addition to the test mode signal TESTL, and generates the test clock signal SCLK based on these. When the test mode signal TESTL is activated, the test clock generation circuit 71 outputs the loopback test clock signal as a test clock signal (first clock signal). Here, the loopback test clock signal is a signal input from the outside via the test pad TP of the chip select signal DA_CS0. At this time, the chip select signal CS output from the input switching circuit 62 is held at an active level by the input switching circuit. On the other hand, when the test mode signal TESTL is inactivated, the test clock generation circuit 71 outputs the boundary scan clock signal SCK as the test clock signal SCK. The test clock signal SCLK is supplied to the data comparison circuit 65a and the selector 73.

  The above-described loopback signal TLOOP_RD0 and the boundary scan signal BSCTL3 are input to the OR gate circuit 72. Then, the output signal of the OR gate circuit 72 is supplied to the selector 73, and based on this, one of the clock signal CLK (second clock signal) and the test clock signal SCLK is selected. Specifically, the clock signal CLK is selected when the output signal of the OR gate circuit 72 is at a low level, and the test clock signal SCLK is selected when the output signal of the OR gate circuit 72 is at a high level. . The selected signal is supplied to the data input circuit 64 and the data output circuit 69 as the read clock signal SCLK1.

  The boundary scan signals BSCTL1 to 3 are internal control signals used during the boundary scan test operation (second test operation). Among these, the boundary scan signal BSCTL 1 is supplied to the data input circuit 64, and the boundary scan signal BSCTL 2 is supplied to the data output circuit 63. As described above, the boundary scan signal BSCTL3 is supplied to the OR gate circuit 72.

  FIG. 6 is a circuit diagram of the test lead control circuit 70.

  As shown in FIG. 6, the test lead control circuit 70 includes a plurality of cascaded latch circuits LT10 to LT1m and a plurality of cascaded latch circuits LT20 and LT21. These latch circuits LT10 to LT1m, LT20, and LT21 are all circuits that perform a latch operation in synchronization with the clock signal CLK.

  Among the cascaded latch circuits LT10 to LT1m, the output signal of the AND gate circuit 81 is input to the leading latch circuit LT10. A read signal RCOM and a test mode signal TESTL are input to the AND gate circuit 81. As described above, the read signal RCOM is a signal that is activated in response to a read command. Therefore, when a read command is input during the loopback test operation, a high level signal is latched in the leading latch circuit LT10. The high level signal latched in the latch circuit LT10 is shifted to the latch circuits LT11 to LT1m in the subsequent stage every time the clock signal CLK is clocked.

  As shown in FIG. 6, the output signals of the AND gate circuit 81 and the latch circuits LT <b> 10 to LT <b> 1 m are all input to the OR gate circuit 83. For this reason, after the output signal of the AND gate circuit 81 changes to a high level, the output signal of the OR gate circuit 83 becomes a high level for a period until it passes through the final stage latch circuit LT1m. The output signal of the OR gate circuit 83 is input to one input node of the NOR gate circuit 84 and one input node of the AND gate circuit 85.

  The test mode signal TESTL inverted by the inverter 86 is input to the other input node of the NOR gate circuit 84. The test mode signal TESTL is input to the other input node of the AND gate circuit 85. During the loopback test operation, the test mode signal TESTL becomes the active high level. Thus, when a read command is issued, the loopback signal TLOOP_RD0 is activated to a high level for a certain period defined by the number of stages of the latch circuits LT10 to LT1m. During this time, the loopback signal TLOOP_WR is at a low level. On the other hand, other than during the loopback test operation, for example, during the normal operation or the boundary scan test operation, the test mode signal TESTL becomes an inactive low level. As a result, the loopback signal TLOOP_RD0 and the loopback signal TLOOP_WR are fixed to the low level of the inactive level.

  On the other hand, the output signal of the AND gate circuit 82 is input to the first latch circuit LT20 among the cascaded latch circuits LT20 and LT21. An enable signal OBUFen and a test mode signal TESTL are input to the AND gate circuit 82. As described above, the enable signal OBUFen is a signal that is activated after a certain period of time has elapsed after the read command is input. For this reason, when a read command is input during the loopback test operation, a high level signal shifts the latch circuits LT20 and LT21 in response to the clock signal CLK after a certain period of time has passed, and is used as the loopback signal TLOOP_RD1. Is output. On the other hand, other than during the loopback test operation, for example, during the normal operation or the boundary scan test operation, the test mode signal TESTL becomes an inactive low level. As a result, the loopback signal loopback signal TLOOP_RD1 is fixed to the low level of the inactive level.

  Thus, when a read command is issued during the loopback test operation, the loopback signal TLOOP_RD1 is activated to a high level after a certain period of time has elapsed.

  Thus, the test read control circuit 70 is a circuit that generates a signal for controlling the read operation during the loopback operation. The signal generated by the test read control circuit 70 is deactivated during an operation other than the loopback test operation.

  FIG. 7 is a circuit diagram of the data output circuit 63 and the data input circuit 64.

  As shown in FIG. 7, the data output circuit 63 includes n + 1 unit output circuits OBU, and the data input circuit 64 includes n + 1 unit input circuits IBU. The unit output circuit OBU and the unit input circuit IBU are assigned to the corresponding bits of the input / output data DQa. That is, the plurality of unit output circuits OBU are connected corresponding to each of the plurality of read / write wirings constituting the read / write bus RWBUS. Similarly, the plurality of unit input circuits IBU are connected corresponding to each of the plurality of read / write wirings.

  More specifically, the unit output circuit OBU includes a three-input selector 110 and an output circuit 120. The three-input selector 110 has three data input nodes I1 to I3, two selection nodes S2 and S3, and a data output node O. Based on the logic level of the signals input to the selection nodes S2 and S3, the data input Any one of the nodes I1 to I3 is connected to the data output node O. The loopback signal TLOOP_WR and the boundary scan signal BSCTL2 are input to the selection nodes S2 and S3 of the 3-input selector 110, respectively.

  The output circuit 120 includes an enable node EN, a data input node D, a control node I1, a clock node C, a data output node DQ, and a bypass output node O. As will be described later, the output circuit 120 includes an output buffer OB, and read data driven by the output buffer OB is output from the data output node DQ. An enable signal OBUFen is supplied to the enable node EN of the output circuit 120. The control node I1 is supplied with an output signal of an OR gate circuit 75 that receives the loopback signal TLOOP_WR and the boundary scan signal BSCTL2.

  The unit input circuit IBU includes an input buffer IB, a three-input selector 210, a latch circuit 220, and a tristate buffer 230. The input data of the input buffer IB is supplied with write data DQa input from the outside via the micro bump MFBa or test write data tWD and test read data tRD transferred (looped back) from the unit output circuit OBU. The

  The three-input selector 210 has three data input nodes I1 to I3, two selection nodes S2 and S3, and a data output node O. Based on the logic level of the signal input to the selection nodes S2 and S3, the data input node Any one of the nodes I1 to I3 is connected to the data output node O. The data input node I1 of the 3-input selector 210 is connected to the output node of the input buffer IB. Boundary scan signal BSCTL1 and selection signal SWC are input to selection nodes S2 and S3 of 3-input selector 210, respectively.

  The latch circuit 220 (first latch circuit) has a data input node D, a clock node C, and a data output node Q, and is synchronized with the read clock signal SCLK1 supplied to the clock node C to the data input node D. The supplied data is latched and output from the data output node Q. The data input node D of the latch circuit 220 is connected to the data output node O of the 3-input selector 210. A signal output from the data output node Q of the latch circuit 220 is output to the read / write bus RWBUS via the tristate buffer 230 and is also used as test read data tRD. The tristate buffer 230 is activated when the write signal WCTL supplied from the access control circuit 61 is at a high level, and is in a high impedance state in other cases. The write signal WCTL is a signal that is activated to a high level when a write command is issued.

  The read / write bus RWBUS is also connected to the input node I1 of the three-input selector 210 included in the unit output circuit OBU. The input node I2 of the three-input selector 210 is connected to the data output node Q of the latch circuit 220 included in the unit input circuit IBU. Further, test write data tWD is supplied to the input node I3 of the three-input selector 210.

  FIG. 8 is a circuit diagram of the 3-input selector 110. The three-input selector 210 has the same circuit configuration.

  As shown in FIG. 8, the 3-input selector 110 includes 2-input selectors 111 and 112 and an OR gate circuit 113. The OR gate circuit 113 receives signals supplied to the selection nodes S2 and S3 and supplies an output signal to the 2-input selector 112. The 2-input selector 111 selects a signal supplied to the data input nodes I2 and I3 based on the signal supplied to the selection node S3, and outputs the selected signal to the 2-input selector 112. The 2-input selector 112 selects a signal supplied to the data input node I1 or a signal output from the 2-input selector 111 based on the output signal of the OR gate circuit 113, and supplies the selected signal to the data output node O. To do.

  FIG. 9 is a truth table showing the logic levels of various control signals in each operation mode.

  Normal Read and Normal Write shown in FIG. 9 indicate a read operation and a write operation in the normal operation mode, respectively. In the normal operation mode, since the boundary scan signal BSCTL3 and the loopback signal TLOOP_RD0 are both at the low level, the normal clock signal CLK is used as the read clock signal SCLK1. Since the boundary scan signals BSCTL1 and BSCTL2, the selection signal SWC, and the loopback signal TLOOP_WR are also at a low level, the data output node O of the three-input selectors 110 and 210 is connected to the data input node I1. As a result, read data read via the read / write bus RWBUS is taken into the data output circuit 63 during the read operation, and externally input write data is transferred to the read / write bus RWBUS during the write operation. The

  All other operations shown in FIG. 9 are operations in the test mode. Among these, Loop Back Write indicates a write operation during a loop back test operation. Specifically, the test write data tWD is transferred (looped back) from the data output circuit 63 to the data input circuit 64 and written to the memory cell array 60. In the Loop Back Write operation, since the loop back signal TLOOP_WR becomes high level, the output node O of the 3-input selector 110 included in the unit output circuit OBU is connected to the data input node I3. As a result, the test write data tWD is transferred to the data input circuit 64 via the data output circuit 63.

  Loop Back Read indicates a read operation during a loop back test operation. Specifically, the read data DQa read from the memory cell array 60 is transferred (looped back) from the data output circuit 63 to the data input circuit 64, and the test read data tRD latched by the data input / output circuit 64 is transferred to the data comparison circuit. 65 is an operation to supply to 65. In the Loop Back Read operation, since the loop back signal TLOOP_RD0 is at a high level, the test clock signal SCLK is selected as the read clock signal SCLK1.

  Test Write shown in FIG. 9 indicates a write operation during a test operation (third test operation) other than the loopback test operation and the boundary scan test operation described later. Specifically, this is an operation of writing the test write data tWD into the memory cell array 60 without going through a loopback path passing through the output buffer OB and the input buffer IB. In the Test Write operation, since the selection signal SWC is at a high level, the output node O of the 3-input selector 210 included in the unit input circuit IBU is connected to the data input node I3. As a result, the test write data tWD is directly supplied to the data input circuit 64 without going through the output buffer OB and the input buffer IB.

  Similarly, Test Read indicates a read operation during a test operation other than a loopback test operation and a boundary scan test operation described later. Specifically, the read data DQa read from the memory cell array 60 to the data output circuit 63 is supplied to the data comparison circuit 65b as test read data tO. The Test Read operation is the same as the read operation in the normal operation mode, and the normal clock signal CLK is selected as the read clock signal SCLK1.

  Boundary Scan Serial In shown in FIG. 9 is an operation for inputting test data serially in the boundary scan test. In the Boundary Scan Serial In operation, since the boundary scan signal BSCTL1 becomes high level, the output node O of the three-input selector 210 included in the unit input circuit IBU is connected to the data input node I2. As a result, the test data output from the unit input circuit IBU at the previous stage is transferred to the unit input circuit IBU at the next stage. Therefore, the test data is serialized to the unit input circuit IBU at the first stage in synchronization with the test clock signal SCLK. N + 1 bit test data can be set in the latch circuit 220.

  Boundary Scan Parallel In is an operation of setting the test write data DQa input from the micro bump MFBa in the latch circuit 220. The Boundary Scan Parallel In operation is the same as the write operation in the normal operation mode except that the test clock signal SCLK is used as the read clock signal SCLK1.

  Boundary Scan Parallel Out is an operation for outputting n + 1-bit test data set in the latch circuit 220 from the output circuit 63 in the Boundary Scan Serial In or Boundary Scan Parallel In operation. In the Boundary Scan Parallel Out operation, since the boundary scan signal BSCTL2 becomes high level, the output node O of the three-input selector 110 included in the unit output circuit OBU is connected to the data input node I2. As a result, the test data output from the data input circuit 64 is transferred to the data output circuit 63 as it is.

  FIG. 10 is a circuit diagram of the output circuit 120.

  As shown in FIG. 10, the output circuit 120 includes a pull-up transistor PU that pulls up the data output node DQ, a pull-down transistor PD that pulls down the data output node DQ, and a NAND gate circuit 121 that controls the pull-up transistor PU. And a NOR gate circuit 122 for controlling the pull-down transistor PD. The pull-up transistor PU is a P-channel MOS transistor, and the pull-down transistor PD is an N-channel MOS transistor. The pull-up transistor PU and the pull-down transistor PD constitute an output buffer OB and have a driving capability sufficient to output read data to the outside via the micro bump MFB.

  The NAND gate circuit 121 receives signals supplied to the data input node D and the enable node EN. As shown in FIG. 7, the output signal from the three-input selector 110 is supplied to the data input node D, and the enable signal OBUFen is supplied to the enable node EN. As a result, when the output signal from the 3-input selector 110 and the enable signal OBUFen both become high level, the output signal of the NAND gate circuit 121 becomes low level.

  The output signal of the NAND gate circuit 121 is supplied to the gate electrode of the pull-up transistor PU via the transfer gate TGP1, the latch circuit LTP1, the transfer gate TGP2, and the latch circuit LTP2. The transfer gate TGP1 is controlled by clock signals CLK1_T and CLK1_B generated by the clock generation circuit 123. The transfer gate TGP2 is controlled by clock signals CLK2_T and CLK2_B generated by the clock generation circuit 124.

  The clock generation circuits 123 and 124 are activated when the signal input to the control node I1 is at a low level, and the clock signals CLK1_T and CLK1_B and the clock are based on the signal (clock signal CLK) input to the clock node C. Signals CLK2_T and CLK2_B are generated. When the signal input to the control node I1 is at a high level, the clock signals CLK1_T and CLK1_B are fixed at a low level and a high level, respectively, and the clock signals CLK2_T and CLK2_B are fixed at a high level and a low level, respectively. A signal input to the control node I1 is an output signal of the OR gate circuit 75 shown in FIG.

  On the other hand, the NOR gate circuit 122 receives a signal supplied to the data input node D and an inverted signal of the signal supplied to the enable node EN. Thus, when the output signal from the three-input selector 110 is at a low level and the enable signal OBUFen is at a high level, the output signal of the NOR gate circuit 122 is at a high level.

  The output signal of the NOR gate circuit 122 is supplied to the gate electrode of the pull-down transistor PD via the transfer gate TGN1, the latch circuit LTN1, the transfer gate TGN2, and the latch circuit LTN2. The transfer gate TGN1 is controlled by clock signals CLK1_T and CLK1_B, and the transfer gate TGP2 is controlled by clock signals CLK2_T and CLK2_B.

  With this configuration, pull-up is performed based on the logic level of the signal supplied to the data input node D on condition that the enable signal OBUFen is at high level and the signal input to the control node I1 is at low level. Either the transistor PU or the pull-down transistor PD is turned on. Specifically, if the signal supplied to the data input node D is at a high level, the pull-up transistor PU is turned on and the data output node DQ is driven to a high level. On the other hand, if the signal supplied to the data input node D is at a low level, the pull-down transistor PD is turned on, and the data output node DQ is driven to a low level. The timing at which the data output node DQ is switched is synchronized with the timing at which the clock signal CLK becomes high level. When both the enable signal OBUFen and the signal input to the control node I1 are at the high level, the logic level of the signal supplied to the data input node D is output to the data output node DQ regardless of the clock signal CLK. . When the enable signal OBUFen is at a low level, both the pull-up transistor PU / pull-down transistor PD are turned off, and the output node DQ becomes Hi-Z.

  Further, the signal latched by the latch circuit LTN 2 is output to the bypass output node O via the buffer circuit 125. The logic level of the signal output from bypass output node O is the same as the logic level of the signal output from data output node DQ. The drive capability of the buffer circuit 125 is significantly smaller than the drive capability of the output buffer OB.

  FIG. 11 is a circuit diagram showing a configuration of a main part of the data comparison circuit 65a.

  As shown in FIG. 11, the data comparison circuit 65a exclusively compares each bit of the test write data tWD consisting of a plurality of bits W0 to Wn and each bit of the test read data tRD consisting of a plurality of bits R0 to Rn. Non-OR circuits ENOR0 to ENORn are provided. The output signals of these exclusive OR circuits ENOR0 to ENORn are input to an AND gate circuit 76, and the output signal is latched in a latch circuit 77 (second latch circuit). The latch circuit 77 performs a latch operation based on the test clock signal SCLK, and its output signal is used as the determination signal TCMP0. With this configuration, when all the bits of the test write data tWD and the test read data tRD match, the determination signal TCMP0 becomes high level (pass), and even if the test write data tWD and the test read data tRD do not match even one bit. In this case, the determination signal TCMP0 becomes low level (fail). The determination signal TCMP0 is supplied to the data output circuit 69 shown in FIG.

  FIG. 12 is a circuit diagram showing a configuration of a main part of the data comparison circuit 65b.

  As shown in FIG. 12, the data comparison circuit 65b compares each bit of the test write data tWD consisting of a plurality of bits W0 to Wn with each bit of the bypass signal tO consisting of a plurality of bits O0 to On. OR circuits ENOR0 to ENORn are provided. The output signals of these exclusive OR circuits ENOR0 to ENORn are input to the AND gate circuit 78, and the output signal is used as the determination signal TCMP1. With this configuration, when all the bits of the test write data tWD and the bypass signal tO match, the determination signal TCMP1 becomes high level (pass), and even when the test write data tWD and the bypass signal tO do not match even one bit. The determination signal TCMP1 becomes a low level (fail). The determination signal TCMP1 is supplied to the data output circuit 69 shown in FIG.

  FIG. 13 is a circuit diagram of the data output circuit 69.

  As shown in FIG. 13, the data output circuit 69 includes logic circuits 51 and 52 that receive an enable signal DAOBUFen, a loopback signal TLOOP_RD1, and determination signals TCMP0 and TCMP1.

  The logic circuit 51 sets the output signal to a low level when both the loopback signal TLOOP_RD1 and the determination signal TCMP0 are at a high level, or when both the enable signal DAOBUFen and the determination signal TCMP1 are at a high level. The output signal of the logic circuit 51 is latched by the latch circuit 53 (third latch circuit) in synchronization with the read clock signal SCLK1, and then supplied to the gate electrode of the pull-up transistor PU_DA.

  When the loopback signal TLOOP_RD1 is at a high level and the determination signal TCMP0 is at a low level, or the enable signal DAOBUFen is at a high level and the determination signal TCMP1 is at a low level, the logic circuit 52 The output signal is set to high level. The output signal of the logic circuit 52 is latched by the latch circuit 54 in synchronization with the read clock signal SCLK1, and then supplied to the gate electrode of the pull-down transistor PD_DA.

  The pull-up transistor PU_DA is a P-channel type MOS transistor, and the pull-down transistor PD_DA is an N-channel type MOS transistor. The pull-up transistor PU_DA and the pull-down transistor PD_DA constitute an output buffer OB_DA, and have sufficient drive capability to output the determination signal DA_DQa to the outside through the micro bump MFB and the test pad TP.

  Next, the test operation of the semiconductor device 10 according to the present embodiment will be explained.

  FIG. 14 is a timing chart for explaining the Loop Back Write operation of the semiconductor device 10 according to the present embodiment. In FIGS. 14 and 15, the portion shown in gray is don't care.

  As shown in FIG. 14, in the Loop Back Write operation, the clock signal DA_CLK is input via the test pad TP, and the active command ACT, the write register write command WRW, and the write command WRT are synchronized with the test signal TP. It inputs in this order via TP. Although not shown, when an active command ACT is input, an address signal DA_ADD (row address) is input via the test pad TP. As a result, a predetermined row address is selected in the memory cell array 60.

  The write register write command WRW is a command for writing the test write data tWD to the test data register 66. Although not shown, when a write register write command WRW is input, test write data tWD is input via the test pad TP. As a result, test write data tWD is stored in the test data register 66.

  In this state, when a write command WRT is input and an address signal DA_ADD (column address) is input, a write operation is performed on a selected memory cell in the memory cell array 60.

  As described with reference to FIG. 9, since the loopback signal TLOOP_WR is at the high level in the Loop Back Write operation, the output node O of the 3-input selector 110 included in the unit output circuit OBU is connected to the data input node I3. It is connected. As a result, the test write data tWD read from the test data register 66 is looped back to the data input circuit 64 via the data output circuit 63. That is, the test write data tWD in the test data register 66 is supplied to the memory cell array 60 via the output buffer OB in the data output circuit 63, the input buffer IB in the data input circuit 64, and the read / write bus RWBUS. Are written into the memory cell. Therefore, the write operation using the output buffer OB and the input buffer IB can be performed without actually using the micro bumps MFBa for the data DQa0 to DQan which are data input / output terminals.

  Here, the logic level of the test write data tWD output from the test data register 66 can be inverted by the inversion circuit 67. As shown in FIG. 5, a 1-bit inversion control signal TDINV (inversion control signal) is supplied to the inversion circuit 67. When this is activated, the inversion circuit 67 inverts and outputs the test write data tWD. The inversion control signal TDINV is generated by the inversion control circuit 74. The inversion control circuit 74 outputs the clock enable signal DA_CKE0 input through the test pad TP as the inversion control signal TDINV when the test signal TEST is activated. Therefore, during the test operation, whether or not the test write data tWD is inverted can be controlled by the logic level of the clock enable signal DA_CKE0 input via the test pad TP.

  In the example shown in FIG. 14, four consecutive write operations are executed in response to the write command WRT, and the presence or absence of inversion can be controlled using the clock enable signal DA_CKE0 each time. Therefore, it is possible to write not only one pattern of test write data tWD stored in the test data register 66 but also a pattern obtained by inverting this pattern at an arbitrary address. In FIG. 14, patterns of test write data tWD written for the first time to the fourth time are denoted as D1 to D4.

  When the precharge command PRE is finally input, the initial state before the active command ACT is input is restored.

  As described above, when the loop back write operation of the present embodiment is used, the write operation using the output buffer OB and the input buffer IB can be performed without actually using the micro bumps MFBa for the data DQa0 to DQan. Therefore, it is possible to test whether these circuits function normally. In addition, since the test write data tWD stored in the test data register 66 can be inverted at an arbitrary timing, two patterns of test write data tWD can be written at an arbitrary address.

  The signal input from the outside in order to invert the test write data tWD is not limited to the clock enable signal DA_CKE0, and other signals such as a predetermined bit of the address signal DA_ADD may be used. Further, inversion of the test write data tWD may be performed for the entire 128 bits constituting the test write data tWD, or partial inversion may be enabled by using an inversion control signal TDINV of 2 bits or more.

  The test write data tWD written in the memory cell array 60 in this way is read as test read data tRD by the Loop Back Read operation, and is compared with the test write data tWD.

  FIG. 15 is a timing chart for explaining the Loop Back Read operation of the semiconductor device 10 according to the present embodiment.

  As shown in FIG. 15, in the Loop Back Read operation, the clock signal DA_CLK is input via the test pad TP, and the active command ACT, the write register write command WRW, and the read command RD are synchronized with the test signal TP. It inputs in this order via TP. As described above, when the active command ACT is input, the address signal DA_ADD (row address) is input via the test pad TP. As a result, a predetermined row address is selected in the memory cell array 60.

  Next, when the write register write command WRW is input, the same test write data tWD as the expected value is written in the test data register 66. When the test write data tWD that is the same as the expected value is already stored in the test data register 66, it is not necessary to input the write register write command WRW.

  In this state, when a read command RD is input and an address signal DA_ADD (column address) is input, test read data tRD is read from a selected memory cell in the memory cell array 60.

  Specifically, when a read command RD is input, the read signal RCOM is activated in response thereto. Since the read signal RCOM is supplied to the test read control circuit 70 shown in FIG. 6, when the read signal RCOM is activated, the loopback signal TLOOP_RD0 becomes a high level over a certain period, and the loopback signal TLOOP_WR becomes a certain period. It goes low level. Further, when a predetermined time elapses after activation of the read signal RCOM, the enable signal OBUFen is activated. The enable signal OBUFen is also supplied to the test read control circuit 70, and the loopback signal TLOOP_RD1 is activated with a delay of two clock cycles.

  Therefore, the read data read from the memory cell array 60 is transferred to the data input circuit 64 via the read / write bus RWBUS and the data output circuit 63, and becomes the test read data tRD.

  In the example shown in FIG. 15, four consecutive read operations are executed in response to the read command RD, and the pattern of the test read data tRD read out for the first time to the fourth time is denoted as D1 to D4. Yes. Then, every time the test read data tRD is transferred to the data input circuit 64, the chip select signal DA_CS0 is clocked through the test pad TP. As a result, the test clock generation circuit 71 shown in FIG. 5 generates a test clock signal SCLK having the same waveform as the chip select signal DA_CS0. The generated test clock signal SCLK is supplied to the data input circuit 64, the data comparison circuit 65a, and the data output circuit 69 via the selector 73 or directly. In clocking the chip select signal DA_CS0 (that is, the test clock signal SCLK), it is necessary to generate at least 6 rising edges (= 4 times + 2 times). In FIG. 15, rising edges appear at times t1 to t6.

  FIG. 16 is a timing chart for explaining a Loop Back Read operation synchronized with the test clock signal SCLK.

  A symbol A illustrated in FIG. 16 indicates data patterns D1 to D4 latched by the latch circuit 220 included in the data input circuit 64. Symbol B indicates the determination signal TCMP0 latched in the latch circuit 77 included in the data comparison circuit 65a. Further, the symbol C indicates the determination signal DA_DQa output from the data output circuit 69.

  First, at time t1, the data pattern D1 (first data bit) of the test read data tRD read first is latched by the latch circuit 220. As a result, the data pattern D1 is transferred to the data comparison circuit 65a.

  Next, at time t2, the data pattern D2 (second data bit) of the second read test read data tRD is latched by the latch circuit 220, and the data pattern D1 is stored in the data comparison circuit 65a. The determination signal TCMP0 corresponding to is latched in the latch circuit 77. Thereby, the determination signal TCMP0 corresponding to the data pattern D1 is supplied to the data output circuit 69, and the next data pattern D2 is transferred to the data comparison circuit 65a.

  Next, at time t3, the data pattern D3 of the third read test read data tRD (fourth data bit) is latched by the latch circuit 220, and the data pattern D2 is stored in the data comparison circuit 65a. The determination signal TCMP0 corresponding to is latched in the latch circuit 77. Further, the determination signal DA_DQa corresponding to the data pattern D1 is output to the outside via the test pad TP. Thereby, the determination signal TCMP0 corresponding to the data pattern D2 is supplied to the data output circuit 69, and the next data pattern D3 is transferred to the data comparison circuit 65a.

  By sequentially performing such an operation, the data patterns D1 to D4 are sequentially transferred to the data comparison circuit 65a, the determination signal TCMP0 corresponding to them is generated, and the determination signal DA_DQa is further sent to the outside by the data output circuit 69. Is output. Thereby, even if it is a case where several data patterns D1-D4 are read continuously, it becomes possible to determine about all these data patterns D1-D4.

  As described above, the tetrate data tWD output from the test data register 66 can be inverted using the clock enable signal DA_CKE0. Also in the example shown in FIG. 15, it is possible to designate whether or not the corresponding test write data tWD is inverted each time in synchronization with the read operation performed four times.

  Specifically, for the test read data tRD obtained by reading the test write data tWD written without being inverted, the clock enable signal DA_CKE0 is used for comparison with the test write data tWD that has not been inverted. Non-inversion may be used. Conversely, if the test read data tRD obtained by reading the test write data tWD written in an inverted manner is inverted using the clock enable signal DA_CKE0 so that it is compared with the inverted test write data tWD. Good.

  When the precharge command PRE is finally input, the initial state before the active command ACT is input is restored.

  Thus, in the loop back read operation of this embodiment, the latch operation in the data input circuit 64, the latch operation in the data comparison circuit 65a, and the output operation in the data output circuit 69 are all performed in synchronization with the same test clock signal SCLK. ing. For this reason, even when a plurality of data patterns are continuously read from the memory cell array 60, it is possible to make a determination for all these data patterns.

  On the other hand, when the test is performed without performing the loopback, the test write data tWD may be written to the memory cell array 60 by the Test Write operation and read from the memory cell array 60 by the Test Read operation. In this case, the read data is output from the data output circuit 63 as a bypass signal tO. The bypass signal tO is compared with the test write data tWD by the data comparison circuit 65b, and the determination signal TCMP1 is generated based on the result. The determination signal TCMP1 is supplied to the data output circuit 69 and output to the outside in response to the enable signal DAOBUFen.

  As described above, in the present embodiment, the test read data tRD is supplied to the data comparison circuit 65a via the output buffer OB included in the data output circuit 63 and the input buffer IB included in the data input circuit 64. Since the route is provided, it is possible to evaluate whether not only the memory cell array 60 and the access control circuit 61 but also the data output circuit 63 and the data input circuit 64 operate normally. As a result, it is possible to test whether or not these circuit blocks operate normally using the micro bump MFB or the test pad TP for direct access.

  Moreover, in the present embodiment, since the above-described operation test is performed using the circuits provided in the data output circuit 63 and the data input circuit 64 in advance for the boundary scan test, the data output circuit 63 and the data The circuit configuration of the input circuit 64 is not complicated.

  Furthermore, in this embodiment, since the logic level of the test write data tWD can be inverted using the inverting circuit 67, a plurality of test write data having different data patterns can be obtained without rewriting the contents of the test data register 66. Data tWD can be written into the memory cell array 60.

  Further, in the loop back read operation of the present embodiment, a plurality of data patterns continuously read from the memory cell array 60 are processed in a pipeline manner in synchronization with the test clock signal SCLK. It becomes possible to determine pass / fail for the pattern.

  Next, a second embodiment of the present invention will be described.

  FIG. 17 is a schematic cross-sectional view for explaining the structure of the semiconductor device 100 according to the second embodiment of the present invention.

  As shown in FIG. 17, the semiconductor device 100 according to the present embodiment has a configuration in which four memory chips 21 to 24 are stacked on a control chip 30. The memory chips 21 to 24 are chips having the same circuit configuration as the memory chip 20 described above. The main surfaces 21F to 24F of the memory chips 21 to 24 are provided with a plurality of front surface micro bumps MFB and a plurality of test pads TP, and the back surfaces 21B to 23B of the memory chips 21 to 23 are provided with a plurality of back surface micro bumps MBB. ing. The back surface micro-bump MBB is not provided on the back surface 24B of the memory chip 24 located in the uppermost layer.

  The memory chips 21 to 23 are provided with through electrodes TSV that connect the front surface micro bumps MFB and the back surface micro bumps MBB. The back surface micro bump MBB of the control chip 30 or the memory chips 21 to 23 located in the lower layer and the front surface micro bump MFB of the memory chips 21 to 24 located in the upper layer are joined to each other.

  The reason why the back micro bump MBB and the through silicon via TSV are not provided in the memory chip 24 is that the memory chip 24 is a chip located at the uppermost stage of the semiconductor device 100, so that the signal supplied to the memory chip 24 is further transferred to another chip. This is because there is no need to transfer. As described above, when the through silicon via TSV and the back surface micro bump MBB are not formed in the memory chip 24, the memory chip 24 can be made thicker than the other memory chips 21 to 23 as illustrated in FIG. As a result, it is possible to suppress chip deformation due to thermal stress (thermal stress generated when the memory chips 21 to 24 are stacked) when the semiconductor device 100 is manufactured. However, as a matter of course, a chip having the same structure as the memory chips 21 to 23 may be used as the memory chip 24.

  In the manufacturing process of the semiconductor device 100, after mounting the control chip 30 and the memory chips 21 to 24 on the circuit board 40, these chips 21 to 24 and 30 may be sealed with a sealing resin 50. A semi-finished product 100A shown in FIG. 18 may be prepared and connected to the control chip 30 and the circuit board 40. The semi-finished product 100A shown in FIG. 18 includes a sealing resin 50 that covers the memory chips 21 to 24 so that the main surface 21F of the memory chip 21 is exposed. If such a semi-finished product 100A is used, it becomes possible to appropriately connect the control chips 30 that differ depending on the specifications and applications.

  The through silicon vias TSV provided in the memory chips 21 to 23 include a first type through silicon via TSV1 and a second type through silicon via TSV2.

  FIGS. 19A and 19B are schematic views for explaining the connection state of the through silicon vias TSV1 and TSV2, respectively.

  The through silicon via TSV1 shown in FIG. 19A is short-circuited with the other through silicon via TSV1 provided in the same plane position in a plan view seen from the stacking direction, that is, when seen from the arrow A shown in FIG. ing. That is, as shown in FIG. 19A, the upper and lower through electrodes TSV1 provided at the same position in plan view are short-circuited, and one signal path is configured by these through electrodes TSV1. This signal path is connected to the internal circuit 2 of each of the memory chips 21 to 24. Therefore, input signals (command signal, address signal, clock signal, write data, etc.) supplied from the control chip 30 via the main surface 21F of the memory chip 21 to this signal path are transmitted to the memory chips 21 to 24, respectively. It is input to the internal circuit 2 in common. In addition, an output signal (read data or the like) supplied from the internal circuit 2 of each memory chip 21 to 24 to this signal path is wired-ORed and output from the main surface 21F of the memory chip 21 to the control chip 30.

  FIG. 20 is a cross-sectional view showing the structure of the through silicon via TSV1.

  As shown in FIG. 20, the through silicon via TSV1 is provided through the semiconductor substrate 90 and the interlayer insulating film 91 on the surface thereof. An insulating film 92 is provided between the through silicon via TSV1 and the semiconductor substrate 90, thereby ensuring insulation between the through silicon via TSV1 and the semiconductor substrate 90.

  The lower end of the through-hole electrode TSV1 is provided on the main surface of the memory chips 21 to 23 via the pads P0 to P3 provided in the wiring layers L0 to L3 and the plurality of through-hole electrodes TH1 to TH3 connecting the pads. Are connected to the surface micro-bump MFB. On the other hand, the upper end of the through silicon via TSV1 is connected to the backside micro bumps MBB of the memory chips 21-23. The back surface micro bumps MBB are connected to the front surface micro bumps MFB provided in the upper memory chips 22 to 24. Thereby, two penetration electrode TSV1 provided in the same position by planar view will be in the state where it mutually short-circuited. Connection to the internal circuit 2 shown in FIG. 19A is performed via internal wiring (not shown) drawn from the pads P0 to P3 provided in the wiring layers L0 to L3.

  The through silicon via TSV2 shown in FIG. 19B is short-circuited with the through silicon via TSV2 of another memory chip provided at a different position in plan view. Specifically, each of the memory chips 21 to 23 is provided with four through electrodes TSV2 at the same position in plan view, and the N (N = 1 to 3) th through hole provided in the lower memory chip. The electrode TSV2 is connected to the (N + 1) th through electrode TSV2 provided in the upper memory chip. The fourth through electrode TSV2 (the rightmost through electrode TSV2 in FIG. 19B) provided in the lower memory chip is the first through electrode TSV2 (FIG. 19B) provided in the upper memory chip. Then, it is connected to the leftmost through silicon via TSV2). Such a cyclic connection forms four independent signal paths.

  Of the four through electrodes TSV2, the through electrode TSV2 (the leftmost through electrode TSV2 in FIG. 19B) provided at a predetermined position in plan view is an internal circuit in the memory chips 21 to 23. 3 is connected. The internal circuit 3 included in the uppermost memory chip 24 is connected to the rightmost through silicon via TSV <b> 2 included in the memory chip 23.

  With this configuration, the signals S1 to S4 shown in FIG. 19B are selectively input to the internal circuits 3 of the memory chips 21 to 24, respectively. Examples of such signals include a chip select signal CS and a clock enable signal CKE.

  As described above, the semiconductor device according to the present invention can be applied to the stacked semiconductor device 100 in which the plurality of memory chips 21 to 24 are stacked.

  After the semi-finished product 100A shown in FIG. 18 is formed by stacking a plurality of memory chips 21 to 24, the test pads TP of the memory chips 22 to 24 are covered with the sealing resin 50. However, it is possible to perform an operation test on each of the memory chips 21 to 24 through the through silicon via TSV by bringing a tester probe into contact with the test pad TP of the memory chip 21 in the lowermost layer. is there. In addition, after the semiconductor device 100 shown in FIG. 17 is configured, the operation test of each of the memory chips 21 to 24 can be performed from the control chip 30 through the direct access micro bumps MFB and MBB and the through silicon via TSV. .

  Next, a third embodiment of the present invention will be described.

  FIG. 21 is a schematic cross-sectional view for explaining the structure of a semiconductor device 200 according to the third embodiment of the present invention.

  As shown in FIG. 21, the semiconductor device 200 according to the third embodiment of the present invention has the second embodiment shown in FIG. 17 in that the control chip 30 is mounted on the circuit board 40 in a face-up manner. This is different from the semiconductor device 100 according to the form. The stacked structure of the memory chips 21 to 24 is the same as that of the semiconductor device 100 according to the second embodiment. In the present embodiment, the connection between the control chip 30 and the circuit board 40 is performed using the bonding wire BW. For this reason, it is not necessary to form the through silicon via TSV in the control chip 30.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 22 is a schematic cross-sectional view for explaining the structure of a semiconductor device 300 according to the fourth embodiment of the present invention.

  As shown in FIG. 22, in the semiconductor device 300 according to the fourth embodiment of the present invention, the memory chips 21 to 24 and the control chip 30 are mounted on different planes on the silicon interposer SI, and the silicon interposer SI is a circuit. The semiconductor device 100 is different from the semiconductor device 100 according to the second embodiment shown in FIG. The stacked structure of the memory chips 21 to 24 is the same as that of the semiconductor device 100 according to the second embodiment.

  The silicon interposer SI has a front surface microbump SFB, a back surface microbump SBB, and a through silicon via TSV connecting them. The front surface microbump SFB is connected to the front surface microbump MFB of the memory chip 21 and the front surface microbump CFB of the control chip 30, and the back surface microbump SBB is connected to the substrate electrode 41 provided on the circuit board 40. With this configuration, it is not necessary to form the through silicon via TSV in the control chip 30 also in the present embodiment.

  As described above, various connection methods can be used as the connection method between the memory chip 20 (21 to 24) and the control chip 30, and in the present invention, these connection methods are not limited to specific connection methods. .

  Next, a fifth embodiment of the present invention will be described.

  FIG. 23 is a schematic plan view for explaining the structure of a semiconductor device 400 according to the fifth embodiment of the present invention.

  As shown in FIG. 23, the semiconductor device 400 according to the present embodiment is an embedded chip in which a memory macro 410 and control circuits 421 to 424 having different functions from the memory macro 410 are integrated on a single semiconductor substrate. . The memory macro 410 has the same circuit configuration and the same function as the memory chip 20 in the first embodiment. The control circuits 421 to 424 are circuit blocks having functions different from those of the memory macro 410 and are not particularly limited, but include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), and the like. A logic system circuit, an analog system circuit such as a sensor, and a power system circuit such as a DC / DC converter can be arbitrarily selected.

  As described above, the present invention can also be applied to an embedded semiconductor device.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

2, 3 Internal circuit 10 Semiconductor device 10A Semi-finished product 20-24 Memory chip 20F-24F Main surface 21B-24B Back surface 30 Control chip 30B Back surface 30F Main surface 40 Circuit board 41 Substrate electrode 42 External terminal 50 Sealing resin 51, 52 Logic Circuits 53 and 54 latch circuit 60 memory cell array 61 access control circuit 62 input switching circuit 63 data output circuit 64 data input circuits 65a and 65b data comparison circuit 66 test data register 67 inversion circuit 68 test mode control circuit 69 data output circuit 70 test read Control circuit 71 Test clock generation circuit 72 OR gate circuit 73 Selector 74 Inversion control circuit 75 OR gate circuit 76 AND gate circuit 77 Latch circuit 78 AND gate circuits 81, 82, 85 AND gate circuit 83 OR gate circuit 4 NOR gate circuit 86 Inverter 90 Semiconductor substrate 91 Interlayer insulating film 92 Insulating film 100 Semiconductor device 100A Semi-finished product 110, 210 3-input selector 111, 112 2-input selector 113 OR gate circuit 120 Output circuit 121 NAND gate circuit 122 NOR gate circuit 123 , 124 Clock generation circuit 125 Buffer circuit 200 Semiconductor device 220 Latch circuit 230 Tristate buffer 300 Semiconductor device 400 Semiconductor device 410 Memory macro 421 to 424 Control circuit BW Bonding wire CBB Back surface micro bump CFB Front surface micro bump ChA to ChD Channel DQa Data input Output terminal IB Input buffer IBU Unit input circuits L0 to L3 Wiring layers LT10 to LT1m, LT20, LT21 Latch circuits LTN1, LTN , LTP1, LTP2 Latch circuit MBB Back surface micro bump MFB Front surface micro bump OB Output buffer OBU Unit output circuit OB_DA Output buffer P0 to P3 Pad PD, PD_DA Pull-down transistor PU, PU_DA Pull-up transistor RWBUS Read / write bus SBB Back surface micro bump SI Silicon interposer SFB Surface micro bump TGN1, TGN2, TGP1, TGP2 Transfer gate TH1-TH3 Through-hole electrode TP Test pad TSV, TSV1, TSV2 Through-electrode

Claims (20)

A memory cell array;
A first data output terminal;
A first output circuit having an output node connected to the first data input / output terminal;
An input circuit having an input node connected to the first data input / output terminal;
Data wiring for supplying first data read from the memory cell array to an input node of the first output circuit;
A data comparison circuit that generates a determination signal by comparing the second data and the first data output from the output node of the input circuit;
The input circuit, in response to a first clock signal, transfers the first data output from the first output circuit to the data comparison circuit;
The semiconductor device according to claim 1, wherein the data comparison circuit outputs the determination signal in response to the first clock signal. The input circuit, in response to a first edge of the first clock signal, transfers the first data output from the first output circuit to the data comparison circuit;
The semiconductor device according to claim 1, wherein the data comparison circuit outputs the determination signal in response to a second edge subsequent to the first edge of the first clock signal. The first data includes at least first and second data bits;
The second data includes at least a third data bit;
The input circuit transfers the first data bit output from the first output circuit to the data comparison circuit in response to the first edge of the first clock signal. In response to the second edge of the clock signal, the second data bit output from the first output circuit is transferred to the data comparison circuit;
The data comparison circuit outputs the determination signal obtained by comparing the first data bit and the third data bit in response to the second edge of the first clock signal. The semiconductor device according to claim 2. A second data input / output terminal;
A second output circuit that outputs the determination signal to the second data input / output terminal;
The semiconductor device according to claim 3, wherein the second output circuit outputs the determination signal to the second data input / output terminal in response to the first clock signal. The first data further includes a fourth data bit;
The second data further includes a fifth data bit;
The input circuit outputs the fourth data bit output from the first output circuit to the data comparison circuit in response to the third edge following the second edge of the first clock signal. Forward,
The data comparison circuit receives the determination signal obtained by comparing the second data bit and the fifth data bit in response to the third edge of the first clock signal. Forward to the second output circuit,
The second output circuit responds to the third edge of the first clock signal with the determination signal obtained by comparing the first data bit with the third data bit. 5. The semiconductor device according to claim 4, wherein the data is output to the second data input / output terminal. A register that is provided independently of the memory cell array and that holds the second data;
6. The data comparison circuit according to claim 1, wherein the data comparison circuit compares the second data held in the register with the first data output from an output node of the input circuit. The semiconductor device according to one item.   The semiconductor device according to claim 6, further comprising an inversion circuit that inverts a logic level of the second data output from the register. Further provided with a signal input terminal for inputting a control signal from the outside,
8. The semiconductor device according to claim 7, wherein the inverting circuit inverts the logic level of the first write data in response to the control signal indicating a first logic level.   The first output circuit transfers the second data held in the register or the second data inverted by the inversion circuit to the input circuit in response to activation of an enable signal. The semiconductor device according to claim 8. An address terminal for inputting a plurality of address signals for designating any of a plurality of memory cells included in the memory cell array;
10. The semiconductor device according to claim 8, wherein the second data is supplied to the register through the plurality of address terminals.   The semiconductor device according to claim 10, wherein the signal input terminal is a terminal different from the plurality of address terminals.   The semiconductor device according to claim 10, wherein the signal input terminal is one of the plurality of address terminals.   13. The semiconductor device according to claim 1, wherein the first data input / output terminal has a smaller planar size than the second data input / output terminal.   The semiconductor device according to claim 13, further comprising a third data input / output terminal connected in parallel to the second data input / output terminal and having the same planar size as the first data input / output terminal. . First and second terminals;
A memory cell array;
A first output circuit connected between the first terminal and the memory cell array;
An input circuit connected in common to the first terminal and the output circuit at a first input node, connected to the memory cell array at a first output node, and including a second output node;
A comparison circuit connected to the second output node of the input circuit;
A second output circuit connected between the comparison circuit and the second terminal;
The semiconductor device, wherein the first input circuit, the comparison circuit, and the second output circuit execute a pipeline operation in accordance with a first clock signal. The input circuit is connected to the first input node at its own input node, is commonly connected to the first and second output nodes at its own output node, and operates according to the first clock signal Including a first latch circuit;
The comparison circuit is connected to the comparison logic circuit connected to the second output node of the input circuit at one input node of the comparison circuit, and to the comparison logic circuit at the input terminal of the comparison circuit, A second latch circuit that operates in response.
The second output circuit includes a third latch circuit that is connected to the second latch circuit at an input node of the second output circuit and operates in accordance with the first clock signal. Item 16. The semiconductor device according to Item 15.   17. The semiconductor device according to claim 16, further comprising a register circuit connected to the other input node of the comparison logic circuit.   18. An inverting circuit connected between the other input node of the comparison circuit and the register circuit and inverting the logic level of the output of the register according to a first control signal. A semiconductor device according to 1.   The semiconductor device according to claim 15, wherein the first output circuit operates in accordance with a second clock signal.   The semiconductor device according to claim 15, wherein the first terminal is a bump electrode, and the second terminal is a pad electrode.