JP2015158943A5 - - Google Patents

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Publication number
JP2015158943A5
JP2015158943A5 JP2015092810A JP2015092810A JP2015158943A5 JP 2015158943 A5 JP2015158943 A5 JP 2015158943A5 JP 2015092810 A JP2015092810 A JP 2015092810A JP 2015092810 A JP2015092810 A JP 2015092810A JP 2015158943 A5 JP2015158943 A5 JP 2015158943A5
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JP
Japan
Prior art keywords
memory
request
requests
address
stream
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JP2015092810A
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English (en)
Japanese (ja)
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JP2015158943A (ja
JP5951844B2 (ja
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Priority claimed from US13/315,370 external-priority patent/US8782356B2/en
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Publication of JP2015158943A publication Critical patent/JP2015158943A/ja
Publication of JP2015158943A5 publication Critical patent/JP2015158943A5/ja
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Publication of JP5951844B2 publication Critical patent/JP5951844B2/ja
Expired - Fee Related legal-status Critical Current
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JP2015092810A 2011-12-09 2015-04-30 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け Expired - Fee Related JP5951844B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/315,370 2011-12-09
US13/315,370 US8782356B2 (en) 2011-12-09 2011-12-09 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2014546181A Division JP5745191B2 (ja) 2011-12-09 2012-12-10 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2016114191A Division JP6408514B2 (ja) 2011-12-09 2016-06-08 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Publications (3)

Publication Number Publication Date
JP2015158943A JP2015158943A (ja) 2015-09-03
JP2015158943A5 true JP2015158943A5 (cg-RX-API-DMAC7.html) 2016-06-16
JP5951844B2 JP5951844B2 (ja) 2016-07-13

Family

ID=47472053

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2014546181A Expired - Fee Related JP5745191B2 (ja) 2011-12-09 2012-12-10 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け
JP2015092810A Expired - Fee Related JP5951844B2 (ja) 2011-12-09 2015-04-30 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け
JP2016114191A Expired - Fee Related JP6408514B2 (ja) 2011-12-09 2016-06-08 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2014546181A Expired - Fee Related JP5745191B2 (ja) 2011-12-09 2012-12-10 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2016114191A Expired - Fee Related JP6408514B2 (ja) 2011-12-09 2016-06-08 複数のメモリ領域にわたる強順序付けされたデバイス、および排他的トランザクションの自動順序付け

Country Status (7)

Country Link
US (1) US8782356B2 (cg-RX-API-DMAC7.html)
EP (1) EP2788882B1 (cg-RX-API-DMAC7.html)
JP (3) JP5745191B2 (cg-RX-API-DMAC7.html)
KR (1) KR101445826B1 (cg-RX-API-DMAC7.html)
CN (1) CN103975314B (cg-RX-API-DMAC7.html)
IN (1) IN2014CN04025A (cg-RX-API-DMAC7.html)
WO (1) WO2013086529A1 (cg-RX-API-DMAC7.html)

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WO2014018912A1 (en) 2012-07-27 2014-01-30 Huawei Technologies Co., Ltd. The handling of barrier commands for computing systems
US9411542B2 (en) * 2014-02-21 2016-08-09 Analog Devices Global Interruptible store exclusive
US9594713B2 (en) 2014-09-12 2017-03-14 Qualcomm Incorporated Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media
CN106886504B (zh) * 2017-04-05 2020-12-04 上海弘矽半导体有限公司 基于ahb总线的多核soc中实现原子操作系统及方法
CN112840574B (zh) * 2018-09-28 2024-10-01 苹果公司 第五代(5g)新无线电(nr)中的波束故障恢复和无线电链路故障关联
US11321248B2 (en) * 2019-05-24 2022-05-03 Texas Instruments Incorporated Multiple-requestor memory access pipeline and arbiter
US11252108B2 (en) 2019-06-19 2022-02-15 Nxp Usa, Inc. Controller for ordering out-of-order transactions in SoC
US20220405221A1 (en) * 2019-07-03 2022-12-22 Huaxia General Processor Technologies Inc. System and architecture of pure functional neural network accelerator
KR102300798B1 (ko) 2019-07-31 2021-09-13 주식회사 태성이엔지 젓갈용 해산물 선별장치
US10860333B1 (en) * 2019-10-14 2020-12-08 Western Digital Technologies, Inc. Interleaved host reset and next re-initialization operations
US11775467B2 (en) 2021-01-14 2023-10-03 Nxp Usa, Inc. System and method for ordering transactions in system-on-chips
KR102856424B1 (ko) 2022-12-27 2025-09-09 주식회사 포엠 양식 패류 분리 및 선별장치
US12332811B1 (en) * 2024-03-19 2025-06-17 Qualcomm Incorporated Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
US5832304A (en) 1995-03-15 1998-11-03 Unisys Corporation Memory queue with adjustable priority and conflict detection
US6038646A (en) 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US6275914B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc Apparatus for preserving memory request ordering across multiple memory controllers
US6275913B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc. Method for preserving memory request ordering across multiple memory controllers
US6549985B1 (en) 2000-03-30 2003-04-15 I P - First, Llc Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor
US6754751B1 (en) 2001-03-30 2004-06-22 Intel Corporation Method and apparatus for handling ordered transactions
US6801976B2 (en) * 2001-08-27 2004-10-05 Intel Corporation Mechanism for preserving producer-consumer ordering across an unordered interface
AU2003900733A0 (en) * 2003-02-19 2003-03-06 Canon Kabushiki Kaisha Dynamic Reordering of Memory Requests
US20050289306A1 (en) 2004-06-28 2005-12-29 Sridhar Muthrasanallur Memory read requests passing memory writes
US9026744B2 (en) * 2005-03-23 2015-05-05 Qualcomm Incorporated Enforcing strongly-ordered requests in a weakly-ordered processing
US7500045B2 (en) 2005-03-23 2009-03-03 Qualcomm Incorporated Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
US9292436B2 (en) * 2007-06-25 2016-03-22 Sonics, Inc. Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary
JP2010170609A (ja) * 2009-01-22 2010-08-05 Toshiba Corp 不揮発性半導体記憶装置
US8352682B2 (en) * 2009-05-26 2013-01-08 Qualcomm Incorporated Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
JP2010287058A (ja) * 2009-06-11 2010-12-24 Canon Inc メモリシステム

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