KR101445826B1 - 다수의 메모리 영역들에 걸친 강하게 순서화된 디바이스 및 배타적인 트랜잭션들의 자동-순서화 - Google Patents

다수의 메모리 영역들에 걸친 강하게 순서화된 디바이스 및 배타적인 트랜잭션들의 자동-순서화 Download PDF

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KR101445826B1
KR101445826B1 KR1020147018823A KR20147018823A KR101445826B1 KR 101445826 B1 KR101445826 B1 KR 101445826B1 KR 1020147018823 A KR1020147018823 A KR 1020147018823A KR 20147018823 A KR20147018823 A KR 20147018823A KR 101445826 B1 KR101445826 B1 KR 101445826B1
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memory
requests
request
stream
address
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KR20140102732A (ko
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제이슨 로렌스 파나비치
제임스 노리스 다이펜더퍼
토마스 앤드류 사토리우스
토마스 필립 스피어
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
KR1020147018823A 2011-12-09 2012-12-10 다수의 메모리 영역들에 걸친 강하게 순서화된 디바이스 및 배타적인 트랜잭션들의 자동-순서화 Expired - Fee Related KR101445826B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/315,370 2011-12-09
US13/315,370 US8782356B2 (en) 2011-12-09 2011-12-09 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions
PCT/US2012/068820 WO2013086529A1 (en) 2011-12-09 2012-12-10 Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions

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KR20140102732A KR20140102732A (ko) 2014-08-22
KR101445826B1 true KR101445826B1 (ko) 2014-09-29

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KR1020147018823A Expired - Fee Related KR101445826B1 (ko) 2011-12-09 2012-12-10 다수의 메모리 영역들에 걸친 강하게 순서화된 디바이스 및 배타적인 트랜잭션들의 자동-순서화

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US (1) US8782356B2 (cg-RX-API-DMAC7.html)
EP (1) EP2788882B1 (cg-RX-API-DMAC7.html)
JP (3) JP5745191B2 (cg-RX-API-DMAC7.html)
KR (1) KR101445826B1 (cg-RX-API-DMAC7.html)
CN (1) CN103975314B (cg-RX-API-DMAC7.html)
IN (1) IN2014CN04025A (cg-RX-API-DMAC7.html)
WO (1) WO2013086529A1 (cg-RX-API-DMAC7.html)

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WO2014018912A1 (en) 2012-07-27 2014-01-30 Huawei Technologies Co., Ltd. The handling of barrier commands for computing systems
US9411542B2 (en) * 2014-02-21 2016-08-09 Analog Devices Global Interruptible store exclusive
US9594713B2 (en) 2014-09-12 2017-03-14 Qualcomm Incorporated Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media
CN106886504B (zh) * 2017-04-05 2020-12-04 上海弘矽半导体有限公司 基于ahb总线的多核soc中实现原子操作系统及方法
CN112840574B (zh) * 2018-09-28 2024-10-01 苹果公司 第五代(5g)新无线电(nr)中的波束故障恢复和无线电链路故障关联
US11321248B2 (en) * 2019-05-24 2022-05-03 Texas Instruments Incorporated Multiple-requestor memory access pipeline and arbiter
US11252108B2 (en) 2019-06-19 2022-02-15 Nxp Usa, Inc. Controller for ordering out-of-order transactions in SoC
US20220405221A1 (en) * 2019-07-03 2022-12-22 Huaxia General Processor Technologies Inc. System and architecture of pure functional neural network accelerator
KR102300798B1 (ko) 2019-07-31 2021-09-13 주식회사 태성이엔지 젓갈용 해산물 선별장치
US10860333B1 (en) * 2019-10-14 2020-12-08 Western Digital Technologies, Inc. Interleaved host reset and next re-initialization operations
US11775467B2 (en) 2021-01-14 2023-10-03 Nxp Usa, Inc. System and method for ordering transactions in system-on-chips
KR102856424B1 (ko) 2022-12-27 2025-09-09 주식회사 포엠 양식 패류 분리 및 선별장치
US12332811B1 (en) * 2024-03-19 2025-06-17 Qualcomm Incorporated Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management

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US5832304A (en) 1995-03-15 1998-11-03 Unisys Corporation Memory queue with adjustable priority and conflict detection
US6038646A (en) 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US6275914B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc Apparatus for preserving memory request ordering across multiple memory controllers
US6275913B1 (en) 1999-10-15 2001-08-14 Micron Technology, Inc. Method for preserving memory request ordering across multiple memory controllers
US6549985B1 (en) 2000-03-30 2003-04-15 I P - First, Llc Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor
US6754751B1 (en) 2001-03-30 2004-06-22 Intel Corporation Method and apparatus for handling ordered transactions
US6801976B2 (en) * 2001-08-27 2004-10-05 Intel Corporation Mechanism for preserving producer-consumer ordering across an unordered interface
AU2003900733A0 (en) * 2003-02-19 2003-03-06 Canon Kabushiki Kaisha Dynamic Reordering of Memory Requests
US20050289306A1 (en) 2004-06-28 2005-12-29 Sridhar Muthrasanallur Memory read requests passing memory writes
US9026744B2 (en) * 2005-03-23 2015-05-05 Qualcomm Incorporated Enforcing strongly-ordered requests in a weakly-ordered processing
US7500045B2 (en) 2005-03-23 2009-03-03 Qualcomm Incorporated Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
US9292436B2 (en) * 2007-06-25 2016-03-22 Sonics, Inc. Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary
JP2010170609A (ja) * 2009-01-22 2010-08-05 Toshiba Corp 不揮発性半導体記憶装置
US8352682B2 (en) * 2009-05-26 2013-01-08 Qualcomm Incorporated Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
JP2010287058A (ja) * 2009-06-11 2010-12-24 Canon Inc メモリシステム

Also Published As

Publication number Publication date
US8782356B2 (en) 2014-07-15
US20130151799A1 (en) 2013-06-13
IN2014CN04025A (cg-RX-API-DMAC7.html) 2015-07-10
EP2788882B1 (en) 2016-04-13
WO2013086529A1 (en) 2013-06-13
JP2016157490A (ja) 2016-09-01
CN103975314B (zh) 2015-09-16
JP5745191B2 (ja) 2015-07-08
JP2015158943A (ja) 2015-09-03
JP6408514B2 (ja) 2018-10-17
CN103975314A (zh) 2014-08-06
KR20140102732A (ko) 2014-08-22
JP2015500536A (ja) 2015-01-05
EP2788882A1 (en) 2014-10-15
JP5951844B2 (ja) 2016-07-13

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