JP2015155839A - Infrared detector and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an infrared detector and a manufacturing method thereof capable of further reducing the size and achieving higher precision with an identical area of a first active layer and a second active layer.

SOLUTION: An infrared detector includes: a first electrode layer 31; a first active layer 32 disposed over the first electrode layer 31; an intermediate electrode layer 33 disposed over the first active layer 32; a second active layer 34 disposed over the intermediate electrode layer 33; and a second electrode layer 35 disposed over the second active layer 34. Each pixel of the infrared detector is separated from each other by: a first separation groove 41a formed with a depth from the upper side of the second electrode layer 35 to the first electrode layer 31 and extending in a first direction; a second separation groove 41b formed with a depth from the upper side of the second electrode layer 35 to an intermediate electrode layer 33 and extending in a second direction; and a third separation groove 41c formed with a depth from the lower side of the first electrode layer 31 to an intermediate electrode layer 33.

COPYRIGHT: (C)2015,JPO&INPIT

Description

  The present invention relates to an infrared detector and a method for manufacturing the same.

  Quantum Well Infrared Photo-detector is a high-performance infrared detector that can be used to measure the surface temperature of objects from a distance or to observe the movement of objects in the dark. : QWIP) has been developed. The quantum well infrared detector has an active layer in which two or more types of semiconductor layers having different band gaps are alternately stacked, and a pair of electrode layers arranged with the active layer interposed therebetween.

  An infrared detector (hereinafter referred to as “two-wavelength infrared detector”) that simultaneously detects infrared rays having two different wavelengths has also been developed. The two-wavelength infrared detector has a structure in which a first electrode layer, a first active layer, an intermediate electrode layer, a second active layer, and a second electrode layer are stacked in this order from the bottom. The first active layer and the second active layer have different wavelengths of infrared rays to be detected.

JP 2012-69801 A JP-A-9-107121

  An object of the present invention is to provide an infrared detector that has the same area as the first active layer and the second active layer, and that can cope with further miniaturization and high definition, and a manufacturing method thereof.

  According to one aspect of the disclosed technology, a first electrode layer, a first active layer disposed on the first electrode layer, and an intermediate electrode disposed on the first active layer A second active layer disposed on the intermediate electrode layer, a second electrode layer disposed on the second active layer, and the second electrode layer from above the second electrode layer. A first separation groove formed at a depth reaching one electrode layer and extending in a first direction when viewed from above; and a depth reaching the intermediate electrode layer from above the second electrode layer A second separation groove extending in a second direction intersecting the first direction and a depth reaching the intermediate electrode layer from a lower side of the first electrode layer, An infrared detector is provided having a third separation groove extending in two directions.

  According to another aspect of the disclosed technology, a first electrode layer, a first active layer, an intermediate electrode layer, a second active layer, and a second electrode layer are sequentially formed on a first substrate. A first separating groove that reaches the first electrode layer from above the second electrode layer and extends in the first direction when viewed from above, and an upper side of the second electrode layer. Forming a second separation groove extending in a second direction that reaches the intermediate electrode layer and intersects the first direction; and removing the first substrate to form the first electrode layer A method of manufacturing an infrared detector, comprising: exposing a surface of the first electrode layer; and forming a third separation groove extending from the surface of the first electrode layer to the intermediate electrode layer and extending in the second direction. Is done.

  In the infrared detector according to the above aspect, the areas of the first active layer and the second active layer are the same, so that it is possible to cope with further miniaturization and high definition. In addition, according to the method for manufacturing an infrared detector according to the above aspect, the first active layer and the second active layer have the same area, and can be further reduced in size and increased in definition. Can be manufactured.

FIG. 1 is a schematic cross-sectional view showing an example of a quantum well type two-wavelength infrared detector. FIG. 2 is a schematic cross-sectional view showing another example of a quantum well type two-wavelength infrared detector. FIG. 3A is a top view illustrating an example of an infrared detector according to the embodiment, and FIG. 3B is a bottom view of the same. 4A is a cross-sectional view taken along the line II of FIG. 3A, and FIG. 4B is a cross-sectional view taken along the line II-II of FIG. FIG. 5 is a diagram illustrating a method of driving the infrared detector according to the embodiment. FIG. 6 is a diagram illustrating the state of each switch when a signal is extracted from the far-infrared detector of the pixel in the second row and the second column. FIG. 7 is a diagram illustrating the state of each switch when a signal is extracted from the mid-infrared detector of the pixel in the second row and second column. Drawing 8 is a figure (the 1) showing a manufacturing method of an infrared detector concerning an embodiment. FIG. 9 is a diagram (part 2) illustrating the method of manufacturing the infrared detector according to the embodiment. Drawing 10 is a figure (the 3) showing a manufacturing method of an infrared detector concerning an embodiment. Drawing 11 is a figure (the 4) showing a manufacturing method of an infrared detector concerning an embodiment. Drawing 12 is a figure (the 5) showing a manufacturing method of an infrared detector concerning an embodiment. FIG. 13 is a view (No. 6) illustrating the method for manufacturing the infrared detector according to the embodiment.

  Hereinafter, before describing the embodiment, a preliminary matter for facilitating understanding of the embodiment will be described.

  FIG. 1 is a schematic cross-sectional view showing an example of a quantum well type two-wavelength infrared detector.

  In the infrared detector 10 shown in FIG. 1, a lower electrode layer 12, a lower active layer 13, an intermediate electrode layer 14, an upper active layer 15 and an upper electrode layer 16 are stacked in this order from below on a non-doped GaAs substrate 11. Has the structure. Light (infrared rays) enters the infrared detector 10 from the GaAs substrate 11 side.

  The lower electrode layer 12, the intermediate electrode layer 14, and the upper electrode layer 16 are all formed of n-type GaAs. Each of the lower active layer 13 and the upper active layer 16 has a structure in which two or more types of semiconductor layers having different band gaps are alternately stacked.

  A grating coupler 17 and a metal film 18 are formed on the upper electrode layer 16. The quantum well infrared detector cannot detect infrared rays incident on the active layers 13 and 15 perpendicularly. Therefore, the infrared rays incident perpendicularly to the active layers 13 and 15 are scattered obliquely by the grating coupler 17 and the metal film 18 to increase the components parallel to the active layers 13 and 15.

  Although FIG. 1 shows one pixel of the infrared detector, in an actual infrared detector, a large number of pixels are arranged in a two-dimensional direction, and each pixel is divided by a groove. The top and side surfaces of each pixel are covered with an insulating film 19, and bump electrodes for connecting to a signal processing circuit (Readout Integrated Circuit: ROIC) are arranged on the insulating film 19.

  In the two-wavelength infrared detector 10 shown in FIG. 1, three bump electrodes 21a, 21b, and 21c are provided for each pixel. The bump electrode 21 a is electrically connected to the lower electrode layer 12 through an opening provided in the extraction electrode 22 a and the insulating film 19, and the bump electrode 21 b is an opening provided in the extraction electrode 22 b and the insulating film 19. Is electrically connected to the intermediate electrode layer 14. Further, the bump electrode 21 c is electrically connected to the metal film 18 and the upper electrode layer 16 through an opening formed in the insulating film 19.

  In recent years, miniaturization and high performance of various electric devices have been promoted, and accordingly, a small and high-definition infrared detector is demanded. However, the infrared detector 10 illustrated in FIG. 1 requires three bump electrodes 21a, 21b, and 21c for each pixel, and it is difficult to achieve high definition while reducing the size.

  FIG. 2 is a schematic cross-sectional view showing another example of a quantum well type two-wavelength infrared detector. In FIG. 2, the same components as those in FIG.

  In this quantum well infrared detector 20, the lower electrode layer 12 is common to each pixel. Further, the upper electrode layer 16 of each pixel is also electrically connected to each other by the wiring 22c. This eliminates the need for the bump electrodes 21a and 21c in FIG. 1, and enables a smaller size and higher definition than the quantum well infrared detector 10 in FIG.

  However, in the two-wavelength infrared detectors 10 and 20 of FIGS. 1 and 2, it is necessary to form an extraction electrode 22b that electrically connects the intermediate electrode layer 14 and the bump electrode 21b. The part is notched. Therefore, the area of the upper active layer 15 (the area when viewed from above: the same applies hereinafter) is smaller than the area of the lower active layer 13, and the sensitivity of the upper active layer 15 is lower than that of the lower active layer 13. In addition, the in-plane sensitivity distribution of the upper active layer 15 also deteriorates due to the notches.

  When the pixel size is large, the difference in area between the lower active layer 13 and the upper active layer 15 is not a big problem. However, when the pixel size is reduced, the lower active layer 13 may have sufficient sensitivity, but the upper active layer 15 may have insufficient sensitivity.

  In the following embodiments, an infrared detector that has the same area as the lower active layer and the upper active layer, and can cope with further miniaturization and higher definition, and a manufacturing method thereof will be described.

(Embodiment)
FIG. 3A is a top view illustrating an example of an infrared detector according to the embodiment, and FIG. 3B is a bottom view of the same. 4 (a) is a cross-sectional view taken along the line II of FIG. 3 (a), and FIG. 4 (b) is a cross-sectional view taken along the line II-II of FIG. 3 (a). In the embodiment, an example applied to a quantum well type two-wavelength infrared detector is shown.

  As shown in FIGS. 4A and 4B, the infrared detector 30 according to this embodiment includes a lower electrode layer 31, a lower active layer 32, an intermediate electrode layer 33, an upper active layer 34, and an upper portion. The electrode layer 35 is stacked in this order from the bottom. Light (infrared rays) enters the infrared detector 30 from the lower electrode layer 31 side. The lower electrode layer 31 and the upper electrode layer 35 are examples of the first electrode layer and the second electrode layer, respectively, and the lower active layer 32 and the upper active layer 34 are respectively the first active layer and the second active layer. It is an example.

  The lower electrode layer 31, the intermediate electrode layer 33, and the upper electrode layer 35 are all made of n-type GaAs. Each of the lower active layer 32 and the upper active layer 34 has a quantum well structure in which two or more types of semiconductor layers having different band gaps are alternately stacked.

  As shown in FIGS. 3A and 3B, each pixel 40 is divided by a separation groove 41a extending in the X direction and separation grooves 41b and 41c extending in the Y direction.

  The separation groove 41 a is formed so as to reach the upper surface of the lower electrode layer 31 from the upper side of the upper electrode layer 35, and the separation groove 41 b reaches the upper surface of the intermediate electrode layer 33 from the upper side of the upper electrode layer 35. It is formed to do. The separation groove 41 c is formed so as to reach the lower surface of the intermediate electrode layer 33 from the lower side of the lower electrode layer 31.

  The lower electrode layers 31 are formed in a strip shape extending in the Y direction, and are arranged at a constant pitch in the X direction. Each lower electrode layer 31 is an electrode common to a plurality of pixels 40 arranged in the Y direction. The lower electrode layers 31 are separated by a separation groove 41c.

  The lower active layer 32 is disposed on the lower electrode layer 31 as described above. The lower active layer 32 is divided for each pixel 40 by a separation groove 41a and a separation groove 41c.

  The intermediate electrode layer 33 is disposed on the lower active layer 32. The intermediate electrode layer 33 is formed in a strip shape extending in the X direction, and is arranged at a constant pitch in the Y direction. Each intermediate electrode layer 33 is an electrode common to a plurality of pixels 40 arranged in the X direction. The intermediate electrode layer 33 is separated by a separation groove 41a.

  The upper active layer 34 is disposed on the intermediate electrode layer 33. The upper active layer 34 is also divided for each pixel 40 by the separation groove 41a and the separation groove 41b.

  The upper electrode layer 35 is disposed on the upper active layer 34. Similarly to the upper active layer 34, the upper electrode layer 35 is also divided for each pixel 40 by separation grooves 41a and 41b.

  A grating coupler 36 and a metal film 37 are formed on the upper electrode layer 35. The upper side of the metal film 37 and the side and bottom surfaces of the separation grooves 41 a and 41 b are covered with an insulating film 38.

  A bump electrode 39 is disposed on the insulating film 38. The bump electrode 39 is electrically connected to the metal film 37 and the upper electrode layer 35 through an opening formed in the insulating film 38.

  Hereinafter, a driving method of the infrared detector 30 according to the present embodiment will be described with reference to FIG. In FIG. 5, the signal processing circuit (ROIC) is shown outside the broken line.

  In the infrared detector 30 according to the present embodiment, each pixel 40 has a mid-infrared detector that detects mid-infrared light having a wavelength of about 2.5 μm to 5 μm and a far-infrared light that detects far infrared light having a wavelength of about 8 μm to 12 μm. And a detection unit. The mid-infrared detector is composed of the lower active layer 32, the intermediate electrode layer 33, and the lower electrode layer 31. The far-infrared detector is composed of the upper active layer 34, the intermediate electrode layer 33, and the upper electrode layer 35.

  In FIG. 5, the mid-infrared detector is represented by MWxy (x and y are numbers indicating pixel positions (rows, columns)), and the far-infrared detector is represented by LWxy. Further, only the pixel 40 in the second row and the second column surrounds the mid-infrared detector MW22 and the far-infrared detector LW22 with a one-dot chain line.

  As shown in FIG. 5, the lower electrode layer 31 of each pixel 40 in the yth column is connected to a switch SWBy of the signal processing circuit. In addition, the intermediate electrode layer 33 of each pixel 40 in the xth row is connected to the switch SWMx of the signal processing circuit. Further, the upper electrode layer 35 of the pixel 40 at the xy position is connected to the switch SWxy of the signal processing circuit.

  The switch SWBy is connected to the terminal By. The signal processing circuit supplies a bias voltage to the lower electrode layer 31 of the pixel 40 in the y-th column via the switch SWBy when taking out a signal from the mid-infrared detector MWxy.

  The switch SWxy is connected to the terminal Txy of the signal processing circuit. The signal processing circuit supplies a bias voltage to the upper electrode layer 35 of the pixel 40 at the xy position via the switch Txy when taking out a signal from the far-infrared detector LWxy.

  The switch SWMx is connected to the terminal Mx. When a signal is taken out from the mid-infrared detector MWxy or the far-infrared detector LWxy, a signal is taken from the terminal Mx into the signal processor of the signal processing circuit.

  In the example shown in FIG. 5, Cx between the terminal Mx and the ground is a storage capacitor for storing a signal. The signal processing circuit reads the voltage of the storage capacitor Cx and performs signal processing (imaging processing).

  FIG. 6 is a diagram illustrating the state of each switch when a signal is extracted from the far-infrared detector LW22 of the pixel 40 in the second row and second column.

  As shown in FIG. 6, when a signal is extracted from the far-infrared detector LW22, the switch SW22 is turned on and the other switches SWxy are turned off. Also, SWM2 is turned on and the other switches SWMx are turned off. Further, all the switches SWBy are turned off. Furthermore, a bias voltage is supplied from the terminal T22 to the upper electrode layer 35 of the pixel 40 in the second row and second column via the switch SW22.

  Accordingly, a signal corresponding to the intensity of the far infrared ray detected by the far infrared ray detection unit LW22 is output from the far infrared ray detection unit LW22 to the terminal M2.

  FIG. 7 is a diagram illustrating the state of each switch when a signal is extracted from the mid-infrared detector MW22 of the pixel 40 in the second row and second column.

  As shown in FIG. 7, when a signal is extracted from the mid-infrared detector MW2, all the switches SWxy are turned off. Further, the switch SWM2 is turned on and the other switches SWMx are turned off. Further, the switch SWB2 is turned on and the other switches SWBy are turned off. Furthermore, a bias voltage is supplied from the terminal B2 to the lower electrode layer 31 of the pixel 40 in the second column via the switch SWB2.

  Thereby, the signal according to the intensity | strength of the mid-infrared detected by the mid-infrared detector MW22 is output from the mid-infrared detector MW22 to the terminal M2.

  As described above, in the infrared detector 30 according to the present embodiment, signals are transmitted from the mid-infrared detector and the far-infrared detector of any pixel 40 by appropriately turning on and off each switch in the signal processing circuit (ROIC). Can be taken out.

  Hereinafter, the sensitivity of the infrared detector 30 according to the present embodiment will be described in comparison with the infrared detector 10 of FIG.

  Here, the size of one pixel (when viewed from above) is 20 μm × 20 μm. Further, in the infrared detector 10 of FIG. 1, in order to form the extraction electrode 22 b, a notch having a size of 5 μm × 5 μm is formed in the upper electrode layer 15 when viewed from above.

Then, in the infrared detector 30 of the present embodiment, the area of the upper active layer 34 is 400 μm ² , whereas in the infrared detector 10 shown in FIG. 1, the area of the upper active layer 15 is 375 μm ² . That is, in the infrared detector 30 of the present embodiment, the area of the upper active layer is expanded by about 7% compared to the infrared detector 10 shown in FIG. Therefore, it can be said that the infrared detector 30 of this embodiment has a sensitivity of about 7% higher than that of the infrared detector 10 shown in FIG.

  Further, in the infrared detector 30 according to the present embodiment, the upper active layer 34 is not provided with a notch, unlike the infrared detector 10 shown in FIG. For this reason, the in-plane sensitivity distribution of the upper active layer 34 is good.

  Actually, since the active layer is damaged when forming the groove or notch, a region where infrared rays cannot be detected is generated in the vicinity of the groove or notch. For this reason, it is considered that the difference in sensitivity between the infrared detector 30 according to the present embodiment and the infrared detector 10 shown in FIG. 1 is larger than the above value.

  Hereinafter, the manufacturing method of the infrared detector 30 according to the present embodiment will be described. 8-13 is a figure which shows the manufacturing method of the infrared detector 30 which concerns on this embodiment in order of a process.

  First, steps required until a structure shown in FIG.

  A non-doped GaAs substrate 51 is prepared, and a lower electrode layer 31, a lower active layer 32, an intermediate electrode layer 33, an upper active layer 34, an upper electrode layer 45, and a grating coupler layer 52 are sequentially formed on the GaAs substrate 51. To do. These lower electrode layer 31, lower active layer 32, intermediate electrode layer 33, upper active layer 34, upper electrode layer 45, and grating coupler layer 52 are formed by molecular beam epitaxy (MBE) or metal organic vapor phase epitaxy (OMVPE). It can be formed by a method or the like. The GaAs substrate 51 is an example of a first substrate.

The lower electrode layer 31, the intermediate electrode layer 33, and the upper electrode layer 35 are made of, for example, n-type GaAs doped with Si at a concentration of 1 × 10 ¹⁸ cm ⁻³ or more. The lower active layer 32 is formed by alternately laminating AlGaAs and GaAs, for example, about 10 to 50 layers. At this time, the sensitivity wavelength of the lower active layer 32 is determined by the thickness of each layer and the composition of AlGaAsAl.

  The upper active layer 34 is formed by alternately laminating, for example, about 10 to 50 layers of InGaAs, GaAs, and AlGaAs. The sensitivity wavelength of the upper active layer 34 is determined by the thickness of each layer and the composition of InGaAs and AlGaAs. If necessary, Si may be doped into the InGaAs layer.

  The thickness of the lower electrode layer 31 is 1.5 μm, for example, and the thickness of the lower active layer 32 is 0.3 μm to 2.0 μm, for example. The thickness of the intermediate electrode layer 33 is, for example, 1.5 μm, and the thickness of the upper active layer 34 is, for example, 0.3 μm to 2.0 μm. Furthermore, the thickness of the upper electrode layer 35 is, for example, 0.5 μm to 1.5 μm, and the thickness of the grating coupler layer 52 is, for example, 0.5 μm to 1.0 μm.

  Next, steps required until a structure shown in FIG.

  After the grating coupler layer 52 is formed by the above-described process, a resist film (not shown) having a predetermined pattern is formed on the grating coupler layer 52 by photolithography. Then, the grating coupler layer 52 is etched using the resist film as a mask to form the grating coupler 36. Etching may be performed by dry etching using a gas such as chlorine or argon, or may be performed by wet etching using a chemical solution containing phosphoric acid as a main component.

  Next, a metal film 37 of Au or the like is formed on the entire upper surface of the GaAs substrate 51 using a vacuum deposition method or a vacuum sputtering method. Then, a resist film (not shown) provided with a predetermined pattern is formed on the metal film 37 by photolithography, and the metal film 37 is etched using this resist film as a mask. By this etching, the metal film 37 is divided for each pixel region. After the etching of the metal film 37 is completed, the resist film is removed.

  Next, steps required until a structure shown in FIGS. 10A shows a cross section at a position corresponding to FIG. 4A, and FIG. 10B shows a cross section at a position corresponding to FIG. 4B.

  After forming the metal film 37 in the above-described process, the isolation grooves 41a and 41b are formed by using a photolithography method and an etching method. When the separation groove 41a is formed, a photosensitive resist film (not shown) is formed on the entire upper surface of the GaAs substrate 51, and then exposure and development processes are performed to open portions corresponding to the separation groove 41a. Forming part. Then, the upper electrode layer 35, the upper active layer 34, the intermediate electrode layer 33, and the lower active layer 32 are sequentially etched using the resist film as a mask. Etching may be performed by dry etching using a gas such as chlorine or argon, for example, or may be performed by wet etching using a chemical solution containing phosphoric acid as a main component. After the separation groove 41a is formed, the resist film is removed.

  Further, when forming the separation groove 41b, a photosensitive resist film (not shown) is formed on the entire upper surface of the GaAs substrate 51, and then exposure and development processes are carried out so as to correspond to the separation groove 41b. An opening is formed in Then, the upper electrode layer 35 and the upper active layer 34 are sequentially etched using the resist film as a mask. After the separation groove 41b is formed, the resist film is removed.

  After forming the isolation grooves 41a and 41b in this way, a SiON film of 0.2 μm to 0.5 μm is formed as an insulating film 38 on the entire upper surface of the GaAs substrate 51 by using, for example, a CVD (Chemical Vapor Deposition) method. Form to thickness. The insulating film 38 covers the top of the metal film 37 and the wall surfaces and bottom surfaces of the separation grooves 41a and 41b.

  Next, steps required until a structure shown in FIGS. 11A shows a cross section at a position corresponding to FIG. 4A, and FIG. 11B shows a cross section at a position corresponding to FIG. 4B.

  After forming the insulating film 38 in the above-described process, a resist film (not shown) having an opening provided at a position corresponding to the bump electrode 39 is formed on the insulating film 38. Then, the insulating film 38 is etched using this resist film as a mask to form a contact hole in which the metal film 37 is exposed. Thereafter, the resist film is removed.

  Next, a mask (not shown) provided with an opening having a predetermined pattern is disposed on the insulating film 38, and In (indium) is vacuum-deposited or sputtered from the upper side of the GaAs substrate 51 to form the bump electrode 39. Form. After the bump electrode 39 is formed, the resist film is removed together with In deposited thereon.

  Next, steps required until a structure shown in FIGS. 12A shows a cross section at a position corresponding to FIG. 4A, and FIG. 12B shows a cross section at a position corresponding to FIG. 4B.

  After the bump electrode 39 is formed in the above-described process, the GaAs substrate 51 and the structure thereon are divided for each chip using a dicing apparatus. Hereinafter, the GaAs substrate 51 divided on a chip basis and the structure thereon are referred to as a sensor chip 50.

  On the other hand, a signal processing circuit (ROIC) 55 is formed using a known semiconductor manufacturing technique. Bump electrodes (not shown) for joining to the sensor chip 50 are formed on the signal processing circuit 55. The signal processing circuit 55 is an example of a second substrate.

  Thereafter, the sensor chip 50 is flip-chip bonded on the signal processing circuit 55. At this time, the sensor chip 50 faces down the surface on which the bump electrode 39 is formed. In the flip chip bonding, the bump electrode 39 on the sensor chip 50 side and the bump electrode on the silicon substrate 55 side are melted and integrated. In FIGS. 12A and 12B, the bump electrode after being integrated is also denoted by reference numeral 39.

  Next, steps required until a structure shown in FIGS. 13A shows a cross section at a position corresponding to FIG. 4A, and FIG. 13B shows a cross section at a position corresponding to FIG. 4B.

  After the sensor chip 50 is bonded on the signal processing circuit 55 in the above-described process, the GaAs substrate 51 is removed by etching to expose the lower electrode layer 31. Etching may be performed by dry etching using a gas such as chlorine or argon, for example, or may be performed by wet etching using a chemical solution containing phosphoric acid as a main component.

  Next, a resist film (not shown) having an opening provided in a portion corresponding to the separation groove 41 c is formed on the lower electrode layer 31. Then, using this resist film as a mask, the lower electrode layer 31 and the lower active layer 32 are etched to form a separation groove 41c reaching the intermediate electrode layer 33. After forming the separation groove 41c, the resist film is removed. In this way, the infrared detector 30 according to the present embodiment is completed.

  In the above-described method, the separation grooves 41a, 41b, and 41c are formed by etching. However, the separation grooves 41a, 41b, and 41c may be formed by laser processing.

  In the above-described method, the separation groove 41 c is formed in the sensor chip 50 after the sensor chip 50 is bonded on the signal processing circuit 55. However, the sensor chip 50 may be bonded onto the signal processing circuit 55 after the separation groove 41 c is formed in the sensor chip 50. However, it is preferable to form the separation groove 41c after bonding the sensor chip 50 on the signal processing circuit 55 in order to avoid the possibility that the sensor chip 50 is damaged during bonding.

  Further, in the above-described embodiment, a quantum well infrared detector in which the lower active layer 31 and the upper active layer 34 have a quantum well structure is described. However, the disclosed technique can also be applied to a quantum dot infrared detector in which the lower active layer 31 and the upper active layer 34 have a quantum dot structure.

  The following additional notes are disclosed with respect to the above embodiments.

(Appendix 1) a first electrode layer;
A first active layer disposed on the first electrode layer;
An intermediate electrode layer disposed on the first active layer;
A second active layer disposed on the intermediate electrode layer;
A second electrode layer disposed on the second active layer;
A first separation groove formed at a depth reaching the first electrode layer from above the second electrode layer and extending in a first direction when viewed from above;
A second separation groove formed in a depth reaching the intermediate electrode layer from above the second electrode layer and extending in a second direction intersecting the first direction;
An infrared detector, comprising: a third separation groove formed at a depth reaching the intermediate electrode layer from below the first electrode layer and extending in the second direction.

  (Supplementary note 2) The infrared detector according to supplementary note 1, wherein the first active layer and the second active layer have a quantum well structure or a quantum dot structure.

  (Supplementary Note 3) The first electrode layer, the first active layer, the intermediate electrode layer, the second active layer, and the second electrode layer, the first separation groove, the second electrode layer. A plurality of pixels separated from each other by the separation groove and the third separation groove are arranged in the first direction and the second direction, and the infrared rays according to appendix 1 or 2, Detector.

  (Additional remark 4) Only one bump electrode is provided on the said 1 pixel, The said bump electrode is electrically connected with the said 2nd electrode layer, Additional remark 3 characterized by the above-mentioned. The described infrared detector.

  (Supplementary note 5) The infrared detector according to supplementary note 4, further comprising a semiconductor substrate provided with an electronic circuit, wherein the semiconductor substrate and the bump electrode are connected.

  (Appendix 6) The infrared ray according to any one of appendices 1 to 5, wherein an infrared wavelength detected by the first active layer is different from an infrared wavelength detected by the second active layer. Detector.

(Supplementary Note 7) A step of sequentially forming a first electrode layer, a first active layer, an intermediate electrode layer, a second active layer, and a second electrode layer on a first substrate;
A first separation groove that reaches the first electrode layer from above the second electrode layer and extends in a first direction when viewed from above; and the intermediate electrode from above the second electrode layer Forming a second separation groove reaching a layer and extending in a second direction intersecting the first direction;
Removing the first substrate to expose the first electrode layer;
Forming a third separation groove extending from the surface of the first electrode layer to the intermediate electrode layer and extending in the second direction.

  (Additional remark 8) The said 1st active layer and said 2nd active layer have a quantum well structure or a quantum dot structure, The manufacturing method of the infrared detector of Additional remark 7 characterized by the above-mentioned.

(Supplementary Note 9) An insulating film is formed between the step of forming the second separation groove and the step of removing the first substrate to cover the wall surfaces of the first separation groove and the second separation groove. And a process of
The method for producing an infrared detector according to appendix 7 or 8, further comprising: forming a bump electrode on the upper side of the insulating film.

  (Additional remark 10) Furthermore, it has the process of joining the said 1st board | substrate on the 2nd board | substrate with which the electronic circuit was provided, the surface in which the said bump electrode was provided below, and said 1st board | substrate after that The method for manufacturing an infrared detector according to appendix 9, wherein the step of removing the substrate is performed.

  10, 20, 30 ... infrared detectors, 11, 51 ... GaAs substrate, 12, 31 ... lower electrode layer, 13, 32 ... lower active layer, 14, 33 ... intermediate electrode layer, 15, 34 ... upper active layer, 16 35 ... Upper electrode layer 17, 36 ... Grating coupler, 18, 37 ... Metal film, 19, 38 ... Insulating film, 21a, 21b, 21c, 39 ... Bump electrode, 40 ... Pixel, 41a, 41b, 41c ... Isolation Groove, 50 ... sensor chip, 52 ... grating coupler layer, 55 ... silicon substrate.

Claims (6)

A first electrode layer;
A first active layer disposed on the first electrode layer;
An intermediate electrode layer disposed on the first active layer;
A second active layer disposed on the intermediate electrode layer;
A second electrode layer disposed on the second active layer;
A first separation groove formed at a depth reaching the first electrode layer from above the second electrode layer and extending in a first direction when viewed from above;
A second separation groove formed in a depth reaching the intermediate electrode layer from above the second electrode layer and extending in a second direction intersecting the first direction;
An infrared detector, comprising: a third separation groove formed at a depth reaching the intermediate electrode layer from below the first electrode layer and extending in the second direction.   The infrared detector according to claim 1, wherein the first active layer and the second active layer have a quantum well structure or a quantum dot structure.   The first electrode layer, the first active layer, the intermediate electrode layer, the second active layer, and the second electrode layer are constituted by the first separation groove, the second separation groove, and The infrared detector according to claim 1, wherein a plurality of pixels separated from each other by the third separation groove are arranged in the first direction and the second direction.   4. The infrared ray according to claim 3, wherein only one bump electrode is provided on one pixel, and the bump electrode is electrically connected to the second electrode layer. 5. Detector.   The infrared detector according to claim 4, further comprising a semiconductor substrate provided with an electronic circuit, wherein the semiconductor substrate and the bump electrode are connected. Sequentially forming a first electrode layer, a first active layer, an intermediate electrode layer, a second active layer, and a second electrode layer on a first substrate;
A first separation groove that reaches the first electrode layer from above the second electrode layer and extends in a first direction when viewed from above; and the intermediate electrode from above the second electrode layer Forming a second separation groove reaching a layer and extending in a second direction intersecting the first direction;
Removing the first substrate to expose the first electrode layer;
Forming a third separation groove extending from the surface of the first electrode layer to the intermediate electrode layer and extending in the second direction.

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