JP2015135650A - Design method, design device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a clock path that is excellent in resistance properties with respect to power source noise.SOLUTION: A design device 1 is configured to: preferentially select a small coefficient within a range satisfying a design condition from a coefficient group (coefficent library 5) showing delay increase when a voltage falls for each combination of clock buffers 11a, 11b and 11c different in a parameter and wiring loads 12a, 12b and 12c connected to the clock buffers 11a, 11b and 11c; select the clock buffer and wiring load that have a parameter associated with the selected coefficient out of the clock buffers 11a, 11b and 11c and wiring loads 12a, 12b and 12c, and design a clock path 10.

Description

  The present invention relates to a design method, a design apparatus, and a program.

  In recent years, the amount of power supply noise tends to increase due to an increase in current density accompanying miniaturization of a semiconductor integrated circuit, and an increase in power due to higher speed and higher integration. In addition, the power supply noise resistance of the circuit is lowered due to the lower voltage for power consumption reduction. For this reason, for example, a design in consideration of power supply noise is performed such as moving a noise source away from the periphery of an element that is easily affected by noise.

JP 2011-151100 A JP 2011-8410 A JP 2006-195754 A JP 2005-4268 A

  In the clock path of the synchronous circuit, delay variation may occur due to power supply noise, and timing constraints may not be satisfied. For this reason, for example, it is possible to use a clock buffer that operates at high speed in the clock path or shorten the wiring load to minimize the delay generated in the clock path and make it less susceptible to power supply noise. .

  However, even with such a clock path, the delay time increases when it is affected by power supply noise, and timing constraints may not be satisfied. Therefore, it cannot be said that the clock path is highly resistant to power supply noise.

  According to one aspect of the invention, the design apparatus has a coefficient representing an increase in delay at the time of a voltage drop for each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers. A clock buffer and a wiring having the parameters associated with the selected coefficient out of the plurality of clock buffers and the plurality of wiring loads, with priority being selected from a group within a range satisfying a design condition. A design method is provided for selecting a load and designing a clock path.

  Further, according to one aspect of the invention, the design apparatus may reduce delay time and voltage drop for each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers. The delay increase amount with respect to the magnitude is calculated, and the delay increase amount with respect to the voltage drop is divided by the delay time to calculate a coefficient group representing the delay increase at the time of the voltage drop. A small coefficient is preferentially selected within a range that satisfies a condition, and a clock buffer and a wiring load having the parameter associated with the selected coefficient are selected from the plurality of clock buffers and the plurality of wiring loads. Thus, a design method for designing a clock path is provided.

  According to the disclosed design method, design apparatus, and program, it is possible to design a clock path highly resistant to power supply noise.

It is a figure which shows an example of the design method of 1st Embodiment, and a design apparatus. It is a figure which shows the example of calculation of noise amount. It is a figure which shows an example of the correlation with the simulation result with respect to the maximum value of the delay variation of a clock path, and the calculated value of Formula (1). It is a figure which shows an example of the design apparatus of 2nd Embodiment. 1 is a diagram illustrating an example of a semiconductor integrated circuit including a design target clock path. FIG. It is a flowchart explaining the flow of an example of the design method of 2nd Embodiment. It is a figure which shows an example of the relationship between the delay increase amount and the magnitude | size of a voltage drop. It is a figure which shows an example of a coefficient library. It is a figure which shows an example of a coefficient group. It is a figure which shows the mode of an example of the fluctuation | variation of the path delay at the time of the noise generation | occurrence | production in the clock path using multiple types of clock buffers and wiring load. It is a figure which shows an example of the relationship between the noise generation time and the variation | change_quantity of a path delay in the clock path using multiple types of clock buffers and wiring loads. It is a figure which shows the mode of an example of the fluctuation | variation of the path delay at the time of the noise generation in the clock path using the same kind of clock buffer and wiring load. It is a figure which shows an example of the relationship between the noise generation time in the clock path | route using the same kind of clock buffer and wiring load, and the variation | change_quantity of path delay. It is a figure which shows the example of the magnitude | size of the delay time according to a parameter.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a design method and a design apparatus according to the first embodiment.

The design apparatus 1 includes a processor 2 and a storage unit 3. The processor 2 executes the following design method based on data and programs stored in the storage unit 3.
The storage unit 3 stores programs executed by the processor 2 and various data. For example, the storage unit 3 stores a coefficient library 5 described later.

The design method according to the present embodiment is designed to design a clock path with a small delay variation with respect to power supply noise, that is, a clock path with high resistance to power supply noise.
First, the processor 2 calculates a coefficient group representing a delay increase at the time of a voltage drop for each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers (step S1). ).

The parameters of the clock buffer include the size of the clock buffer (the transistor size included in the clock buffer), the threshold voltage of the transistor, and the like.
The wiring load parameters include the wiring width, the wiring length, the wiring interval between adjacent wirings, the type of wiring layer used by the wiring (for example, the first metal layer, the second layer,...).

  An example of the clock path 10 is shown in FIG. In the clock path 10, a combination of the clock buffer 11 a and the wiring load 12 a connected to the clock buffer 11 a is used as one stage cell, and the cells are connected in a plurality of stages according to the length of the clock path 10.

  In the example of the present embodiment, the coefficient is expressed as voltage sensitivity (Ds) / delay time (D). Here, the voltage sensitivity is expressed as Ds = ΔD / ΔV. D indicates the delay time (cell delay time) for one stage of the above combination at the ideal power supply voltage Vdd, and ΔD indicates an increase in delay with respect to the voltage drop of ΔV. Since D and ΔD may vary depending on the parameters as described above, the coefficient is calculated using, for example, circuit simulation for each combination of a plurality of clock buffers and a plurality of wiring loads having different parameters. Is done.

FIG. 1 shows combinations A, B, and C of a plurality of clock buffers 11a, 11b, and 11c and a plurality of wiring loads 12a, 12b, and 12c having different parameters.
The wiring loads 12a, 12b and 12c have wiring resistances R1, R2, R3, R4, R5 and R6, wiring capacitances C1, C2, C3, C4, C5 and C6. These values vary depending on the parameters. The clock buffers 11a, 11b, and 11c have different sizes. Thus, in the combinations A, B, and C of the clock buffers 11a, 11b, and 11c and the wiring loads 12a, 12b, and 12c having different parameters, D and ΔD may also change.

  Therefore, in the example of FIG. 1, the coefficient is calculated for each combination A, B, and C of the clock buffers 11a, 11b, and 11c and the wiring loads 12a, 12b, and 12c having different parameters.

The calculated coefficient group is stored in the storage unit 3 as the coefficient library 5, for example.
Next, the processor 2 preferentially selects a small coefficient within a range satisfying the design condition from the coefficient group (step S2).

  The design conditions include clock path wiring length, clock path timing conditions (timing constraints), cell type, wiring conditions (wiring layer, wiring width, wiring spacing), and the like. For example, in the process of step S2, the coefficient corresponding to the type of clock buffer not used in the design and the parameter of the wiring condition is not selected. Then, among the coefficients corresponding to the condition parameters used in the design, a smaller coefficient is preferentially selected (for example, the smallest coefficient is selected).

  The inventors of the present application can approximate the maximum value of the delay variation of the clock path by the following formula in a clock path created by repeatedly connecting a combination of a clock buffer and a wiring load of a certain parameter uniformly in a plurality of stages. I got the knowledge.

Max (ΔD _path ) = (Ds / D) × S (1)
In Expression (1), Max (ΔD _path ) is the maximum value of the delay variation ΔD _path of the clock path, (Ds / D) is the coefficient described above, and S is the amount of noise received by the clock path.

The amount of noise is obtained as follows.
FIG. 2 is a diagram illustrating a calculation example of the noise amount.
The horizontal axis indicates time, and the vertical axis indicates voltage. In the example of FIG. 2, it is shown that the power line of the clock path receives noise between the timing T0 and the timing T1, and the voltage drops from the ideal power supply voltage Vdd. The noise amount (S) is obtained by integrating the magnitude ΔV of the voltage drop from the power supply voltage Vdd with the time (T0 to T1) when the noise is received.

And Max determined in equation (1) (ΔD _path), showing the relationship between the Max ([Delta] D _path) obtained in circuit simulation below.
FIG. 3 is a diagram showing an example of the correlation between the simulation result for the maximum delay variation of the clock path and the calculated value of Equation (1).

  The horizontal axis indicates the simulation value of the maximum value of the delay variation, and the vertical axis indicates the calculated value obtained by Expression (1). The correlation between the simulation value for the clock path in which 21 stages of the same combination of the clock buffer and the wiring load with the changed parameters and the wiring load are connected and the calculated value by the equation (1) is shown.

  Although the maximum value of the delay variation is changed by changing the parameter, as shown in FIG. 3, the calculated value of the maximum value of the delay variation is in good agreement with the simulation value. Therefore, it can be seen that the maximum value of the variable delay of the clock path can be approximated by Equation (1).

As can be seen from equation (1), by minimizing the coefficient (Ds / D), the maximum value of the delay variation of the clock path due to noise can be reduced.
However, as will be described later, if the coefficient is reduced, the delay time is increased. Therefore, in the process of step S2, a smaller coefficient is preferentially selected within a range that satisfies the timing constraint, which is one of the design conditions. An example of timing constraint determination will be described in the second embodiment.

  When the process of step S2 as described above is completed, the processor 2 performs the process of step S3. In the process of step S3, the processor 2 selects a clock buffer and a wiring load having a parameter associated with the coefficient selected in the process of step S2 among a plurality of clock buffers and a plurality of wiring loads having different parameters. Design the clock path.

  As described above, the coefficient represents an increase in delay when the voltage drops. Therefore, by selecting a small coefficient preferentially within a range that satisfies the design condition, and designing the clock path using the clock buffer and wiring load of the parameters associated with the coefficient, the delay increases due to the voltage drop due to power supply noise. A small clock path can be designed. That is, it is possible to design a clock path in which delay variation due to power supply noise hardly occurs (high resistance to power supply noise).

  In addition, a clock path that is highly resistant to power supply noise can be designed at the design stage, so the delay variation of the clock path is verified with a circuit simulator after the placement / routing process, and the return to the placement / routing process is corrected according to the result. The occurrence of reworking can be suppressed.

  In the above example, the design apparatus 1 has been described as generating the coefficient library 5, but the present invention is not limited to this. For example, the design device 1 acquires the coefficient library 5 generated by another device and stores it in the storage unit 3 so that the processor 2 reads it from the storage unit 3 and uses it when designing the clock path. It may be.

(Second Embodiment)
Hereinafter, an example of the design method and design apparatus of the second embodiment will be described.
FIG. 4 is a diagram illustrating an example of a design apparatus according to the second embodiment.

  The design apparatus is, for example, a computer 20, and the entire apparatus is controlled by a processor 21. The processor 21 is connected to a RAM (Random Access Memory) 22 and a plurality of peripheral devices via a bus 29. The processor 21 may be a multiprocessor. The processor 21 is, for example, a central processing unit (CPU), a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a programmable logic device (PLD). The processor 21 may be a combination of two or more elements among CPU, MPU, DSP, ASIC, and PLD.

  The RAM 22 is used as a main storage device of the computer 20. The RAM 22 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the processor 21. The RAM 22 stores various data necessary for processing by the processor 21.

  Peripheral devices connected to the bus 29 include an HDD (Hard Disk Drive) 23, a graphic processing device 24, an input interface 25, an optical drive device 26, a device connection interface 27, and a network interface 28.

  The HDD 23 magnetically writes and reads data to and from the built-in disk. The HDD 23 is used as an auxiliary storage device of the computer 20. The HDD 23 stores an OS program, application programs, and various data. Note that a semiconductor storage device such as a flash memory can also be used as the auxiliary storage device.

  A monitor 24 a is connected to the graphic processing device 24. The graphic processing device 24 displays an image on the screen of the monitor 24a in accordance with an instruction from the processor 21. Examples of the monitor 24a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 25 a and a mouse 25 b are connected to the input interface 25. The input interface 25 transmits a signal sent from the keyboard 25a and the mouse 25b to the processor 21. The mouse 25b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 26 reads data recorded on the optical disc 26a using a laser beam or the like. The optical disk 26a is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 26a includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The device connection interface 27 is a communication interface for connecting peripheral devices to the computer 20. For example, the device connection interface 27 can be connected to a memory device 27a and a memory reader / writer 27b. The memory device 27 a is a recording medium equipped with a communication function with the device connection interface 27. The memory reader / writer 27b is a device that writes data to the memory card 27c or reads data from the memory card 27c. The memory card 27c is a card-type recording medium.

  The network interface 28 is connected to the network 28a. The network interface 28 transmits / receives data to / from other computers or communication devices via the network 28a.

  With the hardware configuration described above, the processing functions of the second embodiment can be realized. The design apparatus 1 according to the first embodiment shown in FIG. 1 can also be realized by the same hardware as the computer 20 shown in FIG.

  The computer 20 implements the processing functions of the second embodiment by executing a program recorded on a computer-readable recording medium, for example. A program describing the processing contents to be executed by the computer 20 can be recorded in various recording media. For example, a program to be executed by the computer 20 can be stored in the HDD 23. The processor 21 loads at least a part of the program in the HDD 23 into the RAM 22 and executes the program. A program to be executed by the computer 20 can also be recorded on a portable recording medium such as the optical disk 26a, the memory device 27a, and the memory card 27c. The program stored in the portable recording medium becomes executable after being installed in the HDD 23 under the control of the processor 21, for example. The processor 21 can also read and execute the program directly from the portable recording medium.

(Example of design object)
FIG. 5 is a diagram illustrating an example of a semiconductor integrated circuit including a clock path to be designed.
The semiconductor integrated circuit 30 includes a circuit unit 31, a PLL (Phase Locked Loop) 32, a clock path 33, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) 34, and an I / O (Input / Output) 35. .

  The circuit unit 31 serves as a power source noise generation source. In the example of FIG. 5, the circuit unit 31 is a synchronous circuit having flip-flops 31a, 31b, 31c, and 31d. The flip-flops 31a, 31b, 31c, and 31d operate based on the power supply voltage Vdd and a clock that is input via the clock buffers 31e and 31f. For example, power supply noise is generated by the operation of these flip-flops 31a, 31b, 31c, and 31d.

The PLL 32 generates a clock having a predetermined frequency.
The clock path 33 has clock buffers 33a1 to 33an and wiring loads 33b1 to 33bn connected thereto, and propagates a clock generated by the PLL32.

The DDR SDRAM 34 is shown as an example of a synchronization circuit, and performs a predetermined operation in synchronization with a clock input via the clock path 33.
The I / O 35 outputs data read from the DDR SDRAM 34 or supplies data input from the outside to the DDR SDRAM 34. The I / O 35 may output the clock generated by the PLL 32 via the clock path 33 and the DDR SDRAM 34.

  In such a semiconductor integrated circuit 30, when power supply noise occurs in the circuit unit 31, the clock path 33 is affected by this, and there is a possibility that the path delay increases. The design method described below is to design a clock path 33 that is less susceptible to delay fluctuations due to power supply noise, that is, has high power noise resistance.

(Example of design method)
FIG. 6 is a flowchart for explaining the flow of an example of the design method according to the second embodiment.
The following processing is performed under the control of the processor 21 in the computer 20 shown in FIG. In the design method of the second embodiment, the coefficient library as described in the first embodiment is generated in advance and is described as being stored in the HDD 23, for example.

First, each processing step will be briefly described.
For example, first, the amount of power supply noise in the semiconductor integrated circuit is calculated (step S10), and the calculated noise amount 40 is stored in the HDD 23, for example.

  Thereafter, a clock path is designed (step S11). The process of step S11 includes, for example, the following processes of steps S111, S112, S113, S114, and S115.

In the process of step S111, the minimum coefficient is selected from the coefficient library 41 within a range that satisfies the design condition.
In the process of step S112, a one-stage clock buffer and wiring load corresponding to the selected coefficient are selected.

  In the process of step S113, the number of cell stages depending on the clock buffer and the wiring load included in the clock path is determined based on the selection result of the clock buffer and the wiring load and the wiring length of the clock path included in the design condition 42.

In the process of step S114, clock path information 43 (including the number of clock path stages) is output. The clock path information 43 is stored in the HDD 23, for example.
The process of step S115 is performed when it is determined in the timing constraint check described later that the timing constraint is not satisfied, and the clock buffer and the wiring load are changed. For example, the next smaller coefficient than the coefficient selected in step S111 is selected and changed to a one-stage clock buffer and wiring load having parameters corresponding to the coefficient.

  After the process of step S11, the timing constraint is confirmed (step S12). In the process of step S12, it is determined whether or not the designed clock path satisfies the timing constraint. When the timing constraint is not satisfied, the process of step S115 is performed.

  When the timing constraint is satisfied, the maximum value of the delay variation is calculated (step S13). The maximum value of the delay variation amount is obtained by the above-described equation (1) based on the noise amount 40 and the coefficient 44 selected in the process of step S111 or step S115.

  Thereafter, it is confirmed whether or not the maximum value of the delay variation calculated in the process of step S13 satisfies the constraint of the synchronous circuit to which the clock path is connected (step S14). When the constraint is not satisfied, the noise amount 40 is reviewed (step S15). In the process of step S15, for example, the noise amount 40 is recalculated, the noise amount 40 is updated, and then the process from step S13 is repeated. In addition, after redesigning to reduce the noise amount 40, the processing from step S10 may be repeated.

If it is determined in step S14 that the maximum delay variation amount satisfies the constraint, the design process shown in FIG. 6 ends.
Note that the processing order of each step is not limited to the above. For example, the noise amount calculation process of step S10 may be performed immediately before the process of calculating the maximum delay fluctuation amount of step S13.

Hereinafter, an example of the processing of steps S10, S11, and S12 will be described.
(Noise amount calculation process (step S10))
In the noise amount calculation process, for example, the noise amount is calculated from a DvD (Dynamic voltage Drop) analysis result of a previously designed semiconductor integrated circuit, clock latency, DvD peak constraint, and the like. For example, the processor 21 acquires the DvD analysis result and the power supply waveform of the clock path, and integrates the voltage drop from the power supply voltage Vdd with the time (T0 to T1) when receiving noise as shown in FIG. As a result, the amount of noise is calculated.

(Clock path design (step S11))
In the clock path design process, for example, the processor 21 acquires the coefficient library 41 and the design condition 42 stored in the HDD 23 and performs the processes of steps S111 to S115. The design conditions 42 include, for example, clock path timing constraints and delay variation constraints, clock path wiring length, clock buffer type (transistor size, transistor threshold voltage, and the like are different), and wiring conditions.

The wiring conditions include, for example, usable wiring layers, wiring lengths, wiring widths, and intervals between adjacent wirings, and are determined by process technology.
As described above, the coefficient managed by the coefficient library 41 is expressed by voltage sensitivity (Ds) / delay time (D) in a cell based on a combination of a clock buffer having a certain parameter and a wiring load. Ds is expressed as Ds = ΔD / ΔV using the delay increase amount (ΔD) and the magnitude of the voltage drop (ΔV).

The relationship between the delay increase amount and the voltage drop is, for example, as follows.
FIG. 7 is a diagram illustrating an example of the relationship between the delay increase amount and the magnitude of the voltage drop.
The horizontal axis indicates the magnitude of voltage drop (ΔV), and the vertical axis indicates the delay fluctuation amount (ΔD).

  The relationship between the delay increase amount and the magnitude of the voltage drop is non-linear as shown in FIG. 7, and the delay increase amount increases rapidly as the voltage drop increases. In the present embodiment, the processor 21 calculates the voltage sensitivity from the voltage drop magnitude ΔV1 in a region that can be regarded as relatively linear and the delay increase amount ΔD1 at that time.

  Note that the delay time (D) and ΔD1 when the voltage drop occurs by ΔV1 are obtained for each combination of the clock buffer and wiring load parameters, for example, by circuit simulation. Then, for example, the following coefficient library 41 is obtained from the coefficient group calculated based on these values.

FIG. 8 is a diagram illustrating an example of a coefficient library.
For example, the coefficient library 41 includes a plurality of tables a11, b11, c11 to axk, bxk, cxk, and a coefficient for each combination of a plurality of parameters is managed.

  In the table a11, the wiring interval (d1, d2,... Dn) and the wiring length (l1, l2,...) When the type of the clock buffer is “BFa”, the used wiring layer is “M1”, and the wiring width is “W1”. , Lm) is managed. Then, the types of clock buffers are changed to “BFb” and “BFc”, and coefficient groups when other parameters are the same are managed in the tables b11 and c11.

Similarly, tables a11, b11, c11 to axk, bxk, and cxk manage the coefficient groups when the used wiring layer is changed in the range of M1 to Mx and the wiring width in the range of W1 to Wk.
Note that the types of clock buffers are not limited to three types, and may be four or more types or two types.

  In the process of step S111, for example, a table that satisfies the design condition 42 is selected from the coefficient library 41 as described above, and the minimum coefficient is selected from the coefficient group managed in the table.

FIG. 9 is a diagram illustrating an example of a coefficient group.
FIG. 9 shows an example of the coefficient group of the table a11 shown in FIG. A coefficient group is shown when the wiring interval is changed in the range of d1 to d6 and the wiring length is changed in the range of l1 to l16. As for the wiring interval, “d1” is the narrowest and “d6” is the widest. As for the wiring length, “l1” is the shortest and “l16” is the longest. In the example of FIG. 9, the coefficient when the wiring interval is “d1” and the wiring length is “l15” is minimum.

Therefore, when the table a11 as shown in FIG. 9 is selected in the process of step S111 and “d1” and “l15” satisfy the design condition, the coefficient at this time is selected.
In the process of step S112, a clock buffer and a wiring load having parameters corresponding to the selected coefficient are selected. In the above example, the clock buffer whose type is “BFa” is selected. In addition, a wiring load having a wiring layer of “M1”, a wiring width of “W1”, a wiring interval of “d1”, and a wiring length of “l15” is selected.

  Based on the clock buffer selected as described above, the wiring load, and the wiring length of the clock path included in the design condition 42, the number of cell stages depending on the clock buffer included in the clock path and the wiring load is determined (step S113). Is output (step S114).

In the present embodiment, it is assumed that the clock path is designed by repeating the clock buffer selected in step S112 and the cell due to the wiring load uniformly in multiple stages.
The reason will be described below.

FIG. 10 is a diagram showing an example of a variation in path delay when noise occurs in a clock path using a plurality of types of clock buffers and wiring loads.
FIG. 11 is a diagram showing an example of the relationship between noise generation time and path delay variation in a clock path using a plurality of types of clock buffers and wiring loads. In FIG. 11, the horizontal axis indicates the noise occurrence time, and the vertical axis indicates the path delay variation.

  As shown in FIG. 10, the clock path 50 has a plurality of types of clock buffers 51a, 52a, 53a, 54a, and wiring loads 51b, 52b, 53b, 54b. In the example of FIG. 10, the state of path delay variation when the occurrence time of noise having a certain period is scanned in the direction of the arrow is shown. For example, if noise occurs near the clock reaching the clock buffer 52a, the delay time varies by ΔDa. On the other hand, if noise occurs near the clock reaching the clock buffer 53a, the amount of variation in the delay time becomes ΔDb. Due to the difference in the fluctuation amount of the delay time in each stage, the fluctuation amount of the path delay also varies such as ΔDp1 or ΔDp2.

That is, if the clock buffers and the wiring loads at each stage are not uniform, the path delay variation amount varies according to the noise generation time, for example, as shown in FIG.
FIG. 12 is a diagram showing an example of path delay variation when noise occurs in a clock path using the same type of clock buffer and wiring load.

  FIG. 13 is a diagram showing an example of the relationship between noise generation time and path delay variation in clock paths using the same type of clock buffer and wiring load. In FIG. 13, the horizontal axis indicates the noise occurrence time, and the vertical axis indicates the path delay variation.

  As shown in FIG. 12, the clock path 60 includes clock buffers 61a, 62a, 63a, and 64a of the same type (having the same parameters) and wiring loads 61b, 62b, 63b, and 64b. FIG. 12 shows how the path delay fluctuates when the occurrence time of noise having a certain period is scanned in the direction of the arrow.

  In the example of FIG. 12, the clock buffers 61a, 62a, 63a, 64a and the wiring loads 61b, 62b, 63b, 64b of the respective stages are of the same type. Therefore, regardless of the noise occurrence time, the delay variation amount at each stage is ΔDc, and the path delay variation amount is also a constant value (ΔDp3).

That is, if the clock buffer and the wiring load at each stage are uniform, variation in path delay variation can be suppressed as shown in FIG. Therefore, jitter can be suppressed.
The reason for designing a clock path by repeating a plurality of cells uniformly by the clock buffer and wiring load selected in the process of step S112 is as described above.

  The process of step S115 is performed when it is determined in the timing constraint check described later that the timing constraint is not satisfied, and the clock buffer and the wiring load are changed. For example, the next smaller coefficient than the coefficient selected in step S111 is selected, and the one-stage clock buffer and wiring load corresponding to the coefficient are selected. In the example shown in FIG. 9, since the next smallest coefficient after “1.00” is “1.01”, the wiring length “l16” and the wiring interval “d1” associated with this coefficient are used as parameters. A wiring load is selected.

(Confirmation of timing constraints (step S12))
When the minimum coefficient is selected in the process of step S111, the noise resistance of the clock path created using the clock buffer having the parameter associated with the coefficient and the wiring load is increased. However, as the coefficient decreases, the delay time tends to increase.

FIG. 14 is a diagram illustrating an example of the magnitude of the delay time according to the parameter.
The table a11d shown in FIG. 14 shows an example of the delay time when the parameters are the same as those in the table a11 shown in FIG.

  As described above, in the table a11 shown in FIG. 9, the coefficient is the minimum when the wiring length is “l15” and the wiring interval is “d1”, but in the table a11d shown in FIG. "When the wiring interval is" d1 ", the delay time is relatively large. Therefore, there is a possibility that a clock path in which cells having such parameters are connected repeatedly in a plurality of stages may not satisfy the timing constraint.

Therefore, in the process of step S12, it is confirmed whether or not the clock path designed in the process of step S11 satisfies the timing constraint included in the design condition 42.
The processor 21 can confirm whether or not the clock path satisfies the timing constraint by executing STA (Static Timing Analysis) analysis. The clock path timing constraints include whether or not the clock pulse width is sufficient and clock latency (clock delay) constraints. These constraint conditions are determined by the specifications of the chip to be developed. The input in the STA analysis includes, for example, a cell delay library and clock path information 43 (information on the number of clock path stages).

  When the timing constraint is not satisfied, the process of step S115 is performed, and when the timing constraint is satisfied, the process of step S13 is performed. If a small coefficient is used, the delay time is not large. Therefore, it is possible to prevent the timing constraint from being satisfied by performing the processing in steps S12 and S115.

  As described above, according to the design method of the present embodiment, a coefficient as small as possible is selected within the range satisfying the design condition 42, and the clock path is determined by the clock buffer having the parameter associated with the coefficient and the wiring load. Designed. The coefficient represents an increase in delay when the voltage drops. Therefore, it is possible to design a clock path in which a delay increase with respect to a voltage drop due to power supply noise is small. That is, it is possible to design a clock path in which delay variation due to power supply noise hardly occurs (high resistance to power supply noise).

  In addition, a clock path that is highly resistant to power supply noise can be designed at the design stage, so the delay variation of the clock path is verified with a circuit simulator after the placement / routing process, and the return to the placement / routing process is corrected according to the result. The occurrence of reworking can be suppressed.

  In the second embodiment, the coefficient library 41 has been described as being created in advance. However, as in the design method of the first embodiment, a design apparatus (computer) that performs the processing shown in FIG. 20) may create the coefficient library 41. Further, the design apparatus may acquire the coefficient library 41 created by another apparatus and perform the processing as shown in FIG.

  In the processing of S111, the minimum coefficient is selected from the coefficient library 41 within the range that satisfies the design condition 42. However, the minimum coefficient is not necessarily selected, and a small coefficient is preferentially selected. For example, a clock path with high noise resistance can be designed.

  In the above description, a single cell is a combination of a clock buffer and a wiring load connected to its output side, but may be a combination of a clock buffer and a wiring load connected to its input side.

  As described above, one aspect of the design method, the design apparatus, and the program according to the present invention has been described based on the embodiments, but these are only examples and are not limited to the above description.

DESCRIPTION OF SYMBOLS 1 Design apparatus 2 Processor 3 Memory | storage part 5 Coefficient library 10 Clock path 11a, 11b, 11c Clock buffer 12a, 12b, 12c Wiring load R1-R6 Wiring resistance C1-C6 Wiring capacity D Delay time Ds Voltage sensitivity ΔD Delay increase ΔV Voltage Size of drop Vdd Power supply voltage

Claims (10)

Design equipment
A small coefficient within a range satisfying the design condition is selected from a group of coefficients representing an increase in delay at the time of voltage drop for each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers. Select preferentially,
A clock path is designed by selecting a clock buffer and a wiring load having the parameter associated with the selected coefficient among the plurality of clock buffers and the plurality of wiring loads.
A design method characterized by that.   The design method according to claim 1, wherein the design apparatus repeatedly arranges the selected clock buffer and the wiring load on the clock path based on a length of the clock path.   The coefficient is a value obtained by dividing a delay increase amount with respect to a magnitude of a voltage drop by a delay time in a combination of one clock buffer and one wiring load. The design method described in 1.   For each combination of the plurality of clock buffers and the plurality of wiring loads having different parameters, a delay increase amount with respect to the magnitude of the voltage drop and a delay time are calculated, and the delay increase amount with respect to the voltage drop is calculated as The design method according to claim 1, wherein the coefficient is calculated by dividing a delay time.   5. The design condition according to claim 1, wherein the design condition includes a timing condition of the clock path, and a minimum coefficient is selected from the coefficient group within a range that satisfies the timing condition. The design method described. Design equipment
For each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers, a delay time and a delay increase amount with respect to the magnitude of the voltage drop are calculated, and the voltage drop By dividing the amount of increase in delay by the delay time, a coefficient group representing an increase in delay at the time of voltage drop is calculated,
From the coefficient group, a small coefficient is preferentially selected within a range that satisfies a design condition,
A clock path is designed by selecting a clock buffer and a wiring load having the parameter associated with the selected coefficient among the plurality of clock buffers and the plurality of wiring loads.
A design method characterized by that. Have a processor,
The processor is
A small coefficient within a range satisfying the design condition is selected from a group of coefficients representing an increase in delay at the time of voltage drop for each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers. Select preferentially,
A clock path is designed by selecting a clock buffer and a wiring load having the parameter associated with the selected coefficient among the plurality of clock buffers and the plurality of wiring loads.
A design device characterized by that. Have a processor,
The processor is
For each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers, a delay time and a delay increase amount with respect to the magnitude of the voltage drop are calculated, and the voltage drop By dividing the amount of increase in delay by the delay time, a coefficient group representing an increase in delay at the time of voltage drop is calculated,
From the coefficient group, a small coefficient is preferentially selected within a range that satisfies a design condition,
A clock path is designed by selecting a clock buffer and a wiring load having the parameter associated with the selected coefficient among the plurality of clock buffers and the plurality of wiring loads.
A design device characterized by that. A small coefficient within a range satisfying the design condition is selected from a group of coefficients representing an increase in delay at the time of voltage drop for each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers. Select preferentially,
A clock path is designed by selecting a clock buffer and a wiring load having the parameter associated with the selected coefficient among the plurality of clock buffers and the plurality of wiring loads.
A program that causes a computer to execute processing. For each combination of a plurality of clock buffers having different parameters and a plurality of wiring loads connected to the plurality of clock buffers, a delay time and a delay increase amount with respect to the magnitude of the voltage drop are calculated, and the voltage drop By dividing the amount of increase in delay by the delay time, a coefficient group representing an increase in delay at the time of voltage drop is calculated,
From the coefficient group, a small coefficient is preferentially selected within a range that satisfies a design condition,
A clock path is designed by selecting a clock buffer and a wiring load having the parameter associated with the selected coefficient among the plurality of clock buffers and the plurality of wiring loads.
A program that causes a computer to execute processing.

Images