JP6070100B2 - Circuit design method, circuit design program, and circuit design apparatus - Google Patents

Description

  The present invention relates to a circuit design method, a circuit design program, and a circuit design apparatus. For example, the present invention relates to a circuit design method, a circuit design program, and a circuit design apparatus for arranging flip-flops.

  In a highly integrated circuit, a plurality of flip-flops (FF) that operate at a plurality of clock frequencies are used. The FF is reset by a reset signal. It is known that FFs are arranged in a plurality of groups (for example, Patent Documents 1 to 3).

JP-A-3-43811 JP 2005-182378 A JP-A-7-142963

  If the reset signal is distributed to a plurality of FFs supplied with different clock frequencies, clock skew may occur. For example, if the clock skew exceeds the clock period, the FF does not operate normally. In this way, the FFs are arranged on the integrated circuit so that the clock skew does not exceed the clock period. However, it may be difficult to arrange the FFs so that the clock skew is within a predetermined range.

  The circuit design method, the circuit design program, and the circuit design apparatus are intended to easily arrange the FFs.

Grouping a plurality of first flip-flops into a plurality of first groups for each clock frequency, and a second flip-flop supplying a reset signal to the plurality of first flip-flops for each of the plurality of first groups And when the delay time of the reset signal from the second flop flip to the plurality of first flip-flops included in the corresponding first group does not satisfy a desired value, the corresponding first group is A circuit design method, a circuit design program, and a circuit design apparatus , comprising: grouping into a plurality of second groups; and arranging the second flip-flop for each of the plurality of second groups. Is used.

  According to the present circuit design method, circuit design program, and circuit design apparatus, FFs can be easily arranged.

FIG. 1 is a diagram illustrating a clock tree. FIG. 2 is a diagram illustrating a synchronous reset circuit. FIG. 3 is a block diagram of a computer that functions as the circuit design apparatus according to the first embodiment. FIG. 4 is a flowchart showing a design flow of an integrated circuit in which the first embodiment is used. FIG. 5 is a flowchart illustrating the circuit design method according to the first embodiment. FIG. 6 is a diagram illustrating the FF synchronous reset circuit arranged by the circuit design method according to the first embodiment. FIG. 7 is a flowchart illustrating the circuit design method according to the second embodiment. FIG. 8A to FIG. 8F are diagrams showing data structures. FIG. 9A to FIG. 9C are diagrams showing the arrangement of FFs. FIG. 10 is a diagram for explaining the margin time. FIG. 11 is a flowchart showing the circuit design method in step S42 of FIG. FIG. 12A to FIG. 12C are diagrams showing the arrangement of FFs. FIG. 13 is a diagram illustrating a data structure. FIG. 14 is a flowchart showing the circuit design method in step S60 of FIG. Fig.15 (a) to FIG.15 (c) is a figure which shows arrangement | positioning of FF. FIG. 16 is a diagram illustrating a data structure.

FIG. 1 is a diagram illustrating a clock tree. Referring to FIG. 1, for example, tens of thousands to millions of first FFs 31 and 32 are arranged in one integrated circuit 100. PLL (Phase
An oscillator 39 such as “Locked Loop” outputs a clock. The FF 34 is an FF that supplies the high-frequency clock signal CKH to the first FF 31. A clock is input to the clock terminal CK of the FF 34. A signal output from the output terminal Q of the FF 34 is input to the data terminal D of the FF 34 via the inverter 37. As a result, the FF 34 divides the output signal of the oscillator 39 once and outputs it. The output of the FF 34 is input to the clock terminal CK of each first FF 31. The FF 35 is an FF that supplies the low-frequency clock signal CKL to the first FF 32. The output of the FF 34 is input to the clock terminal CK of the FF 35. The signal output from the output terminal Q of the FF 35 is input to the data terminal D of the FF 35 via the inverter 37. Thereby, the FF 35 divides the output signal of the FF 34 once and outputs it. The output of the FF 35 is input to the clock terminal CK of each first FF 32. The buffer 38 improves the driving capability of the clock signal.

  As described above, the high-frequency clock signal CKH having a frequency half that of the oscillation frequency of the oscillator 39 is input to the first FF 31. A low-frequency clock signal CKL that is ¼ of the oscillation frequency of the oscillator 39 is input to the first FF 32. In the integrated circuit 100, a clock signal having a frequency of 3 or more such as 1/8 or 1/16 of the oscillation frequency of the oscillator 39 may be used. However, for the sake of simplicity, in the following embodiments, the case of two clock frequencies will be described as an example.

  FIG. 2 is a diagram illustrating a synchronous reset circuit. As described in FIG. 1, the first FFs 31 and 32 have different clock frequencies. Referring to FIG. 2, the first FF 31 operates with the high frequency clock signal CKH, and the first FF 32 operates with the low frequency clock signal CKL. The second FF 33 receives the high frequency clock signal CKH at the clock terminal CK and supplies the reset signal Reset to the reset terminals R of the first FFs 31 and 32. The reset signal Reset is a synchronous reset signal for synchronizing reset between FFs. The buffer 35 improves the driving capability of the reset signal Reset.

  As shown in FIG. 1, clock signals having different frequencies are generated at different locations. Further, the number of first FFs 31 and 32 to be driven is different. The low frequency clock signal CKL is generated from the high frequency clock signal CKH. As a result, clock skew easily occurs between clock signals having different frequencies. This makes it difficult to converge the timing of the clock signal when the FF is arranged in the integrated circuit. For example, it becomes difficult to arrange the FFs so that the timing of the clock signal is within a specified range. Further, the convergence of the reset signal becomes difficult. For example, it becomes difficult to arrange the FFs so that the timing of the reset signal falls within a specified range. Therefore, it becomes difficult to arrange the FF on the integrated circuit.

  In the following, an embodiment for facilitating the arrangement of FFs on an integrated circuit will be described.

FIG. 3 is a block diagram of a computer that functions as the circuit design apparatus according to the first embodiment. The computer 10 executes a circuit design method and a circuit design program. The computer 10 is a CPU (Central
Processing Unit) 11, display device 12, input device 13, and output device 14. The computer 10 further includes a main storage device 15, a hard disk drive (HDD) 16, a storage medium drive 17, a communication interface 18, and an internal bus 19. The display device 12 includes a display panel such as a liquid crystal panel, for example, and displays processing results and the like. The input device 13 is, for example, a keyboard, a mouse, and a touch panel, and inputs processing data and the like. The output device 14 is a printer, for example, and outputs a processing result or the like. The main storage device 15 is, for example, a DRAM (Dynamic
It is a volatile memory such as Random Access Memory, and stores data being processed. The HDD 16 stores, for example, data during or after processing. The storage medium drive 17 is used when a program stored in the storage medium 21 is installed. Alternatively, the processed data is stored in the storage medium 21. The communication interface 18 is connected to another computer 20 and transmits / receives data to / from the other computer 20. The internal bus 19 connects each device in the computer 10. The computer 10 functions as a first unit and a second unit in cooperation with software.

A portable storage medium can be used as the storage medium 21 readable by the computer 10 storing the program. As a portable storage medium, for example, a CD-ROM (Compact
Disc Read Only Memory (DVD) disc, DVD (Digital Video Disc) disc, Blu-ray Disc or USB (Universal
Serial Bus) memory or the like can be used. As the storage medium 21, a flash memory or an HDD may be used.

FIG. 4 is a flowchart showing a design flow of an integrated circuit in which the first embodiment is used. Referring to FIG. 4, an SDC (Synopsys) including a netlist indicating the FF network and the clock frequency and position information of the FF.
The initial FF placement is performed using Design Constraints) (step S10). For example, the floor plan is used to verify the position of the hard macro, and all the cells on the net list are arranged on the frame. Next, CTS (Clock
The FF arrangement before Tree Synthesys is optimized (step S12). For example, if the clock signal skew is 0 in a register and a hard macro synchronized with the clock, the DRC (Design
Rule Check) error correction, timing optimization, area reduction and power consumption reduction. Next, a clock tree is created (step S14). For example, a clock signal buffer or the like is arranged.

  Next, the data after CTS is optimized (step S16). The skew of the clock signal is an actual value. In this state, DRC error correction, timing optimization, area reduction, and power consumption reduction are performed. Next, a wiring process is performed on the data (step S18). For example, the wiring process is performed for the digital signal terminals of each cell and each hard macro while considering the timing. Thereby, each cell and each hard macro are connected by physical wiring on software.

  Examples 1 and 2 are used, for example, in timing optimization in steps S12 and / or S16.

  FIG. 5 is a flowchart illustrating the circuit design method according to the first embodiment. FIG. 6 is a diagram illustrating the FF synchronous reset circuit arranged by the circuit design method according to the first embodiment. A plurality of first FFs 31 are arranged. As shown in FIGS. 5 and 6, the first unit groups the plurality of arranged first FFs 31 and 32 into first groups 41 and 42 for each clock frequency (step S20). For example, the first FF 31 in the first group 41 is an FF that operates at a high frequency clock, and the first FF 32 in the first group 42 is an FF that operates at a low frequency clock. The second unit arranges the second FFs 33a to 33c that supply the reset signal Reset to the plurality of first FFs 31 and 32 for each of the first groups 41 and 42 (step S22). For example, the first group 41 is further divided into second groups 43 and 44. The first FF 31 in the second group 43 receives the reset signal Reset from the output terminal of the second FF 33a. The first FF 31 in the second group 44 receives the reset signal Reset from the output terminal of the second FF 33b. The first FF 32 in the first group 42 is supplied with the reset signal Reset from the output terminal of the second FF 33c.

  According to the first embodiment, the second FFs 33a to 33c that supply the reset signal Reset to the plurality of first FFs 31 and 32 are arranged for each clock frequency. This facilitates the convergence of the reset signal timing. Therefore, the arrangement of the second FFs 33a to 33c is facilitated.

  The second embodiment is a specific example of the first embodiment. The computer functioning as the second embodiment is the same as that of the first embodiment shown in FIG. The flowchart showing the design flow of the integrated circuit in which the second embodiment is used is the same as that of FIG.

  FIG. 7 is a flowchart illustrating the circuit design method according to the second embodiment. FIG. 8A to FIG. 8F are diagrams showing data structures. FIG. 9A to FIG. 9C are diagrams showing the arrangement of FFs. Referring to FIG. 7, the computer 10 performs the following flow using a netlist, SDC, DEF (Definition), and Lib (Library). The DEF includes information on cell arrangement coordinates, power supply wiring, and signal wiring. The Lib includes cell delay time, standard values such as setup and hold, and power information. The computer 10 arranges the first FFs 31 and 32 and the second FF 33 (step S30). For example, as shown in FIG. 8A, the computer 10 extracts the reset of the entire integrated circuit and the first FF with preset. In the example of FIG. 8A, the first FF 31 is Reg1 to Reg4, and the respective clock frequencies are 270 MHz, 270 MHz, 60 MHz, and 60 MHz. The position information indicates the coordinates at which each first FF 31 is arranged, for example, the X coordinate and the Y coordinate. The computer 10 stores the first FF, frequency, and position information in, for example, a database in the HDD 16. As shown in FIG. 8B, the second FF 33 that supplies the reset signal to the first FF 31 is extracted. The second FF 33 is Reg01 and the clock frequency is 270 MHz. The computer 10 stores the second FF, frequency, and position information in a database. As shown to Fig.9 (a), 1st FF31 and 2nd FF33 are arrange | positioned. The FF preceding the second FF 33 is a third FF 50.

  The computer 10 predicts the delay time after the buffer 36 is arranged from the position information of the first FF 31 and the second FF 33 and the fanout (F / O) number. FIG. 8C is an example of a table for predicting the delay time. As shown in FIG. 8C, the total wiring length of the wiring connecting the second FF 33 to the first FF 31, the fan-out number of the second FF 33, and the delay time of the reset signal Reset are associated with each other. The table in FIG. 8C is stored as a database in the HDD 16, for example. Thereby, if the total wiring length and fan-out number connected to the second FF 33 are determined, the delay time can be predicted. Note that the table in FIG. 8C is, for example, after the buffer 36 is arranged. As shown in FIG. 8D, the delay time of the reset signal from Reg01, which is the second FF33, to Reg4, which is the first FF31, is expected to be 8 ns. The computer 10 stores the delay time in a database.

  Referring to FIG. 7, the computer 10 determines whether or not the delay time in each first FF 31 satisfies a desired value (step S32). For example, the computer 10 determines whether the predicted delay time of each predicted first FF 31 violates the timing constraint. If it violates, it is judged as No. If there is no violation, it is determined as Yes. Here, the timing constraint defines an allowable timing range such as a reset signal in each FF. If yes, end. In No, the computer 10 arrange | positions 2nd FF33 again (step S34).

  For example, the computer 10 acquires a margin time of the timing of the second FF 33 and the third FF 50. FIG. 10 is a diagram for explaining the margin time. As shown in FIG. 10, the signal from the output terminal Q of the third FF 50 in the previous stage is input to the data terminal D of the second FF 33 that supplies the reset signal Reset to the first FF 31. The computer 10 calculates a signal delay time from the wiring length T1 connecting the third FF 50 and the second FF 33. The computer 10 calculates a margin time with the timing allowed for the second FF 33. The margin time indicates that the signal from the third FF 50 to the second FF 33 is not allowed if the signal is further delayed by the margin time or more. As shown in FIG. 10, when there are a plurality of paths from the third FF 50 to the second FF 33, the time with the smallest margin time is set as the margin time. As shown in FIG. 8E, the margin time of Reg01 which is the second FF 33 is, for example, 1.2 ns. The computer 10 stores the spare time in the database.

  As shown in FIG. 9B, the computer 10 arranges the second FF 33 at the average coordinate 55 of the first FF 31. For example, the average of the X coordinate and Y coordinate of the first FF 31 is set as the average coordinate 55. As shown in FIG. 8F, the position information of the second FF 33 is the average coordinates of Reg1 to Reg4 which are the first FF31. The computer 10 calculates a margin time. In FIG. 9B, the distance between the second FF 33 and the third FF 50 is longer than in FIG. 9A. Therefore, the margin time is shorter in FIG. 8F than in FIG. The computer 10 stores the spare time in the database.

  Referring to FIG. 7, the computer 10 determines whether the margin time satisfies the desired value (step S36). That is, the computer 10 determines whether the delay time from the third FF 50 to the second FF 33 satisfies a desired value. For example, the computer 10 determines No when the surplus time violates the timing constraint. If there is no violation, it is determined as Yes. In the case of Yes, it progresses to step S40. In No, the computer 10 moves 2nd FF33 (step S38). The process returns to step S36. As shown in FIG. 9C, for example, the computer 10 moves the second FF 33 by a predetermined distance so that the margin time is improved. For example, the minimum grid is moved. As a result, the second FF 33 approaches the third FF 50 until the margin time satisfies the desired value. The length of the wiring connected from the third FF 50 to the second FF 33 is shortened. As shown in FIG. 9C, the coordinates of the second FF 33 move from the average coordinates 55 to the coordinates 56. If the margin time does not satisfy the desired value even after step S38 is executed a plurality of times, the process may return to the position of the second FF 33 in FIG. 9B.

  In step S40, the computer 10 determines whether the delay time in each first FF 31 satisfies a desired value. For example, the computer 10 predicts the delay time of each first FF 31 from the total wiring length in which the second FF 33 connects the first FF 31 and the fan-out number of the second FF 33. The computer 10 determines whether the predicted delay time of each predicted first FF 31 violates the timing constraint. If it violates, it is judged as No. If there is no violation, it is determined as Yes. If yes, end. In No, it progresses to Step S42.

  In step S42, the computer 10 arranges the second FF 33 for each clock frequency. Then exit.

  FIG. 11 is a flowchart showing the circuit design method in step S42 of FIG. FIG. 12A to FIG. 12C are diagrams showing the arrangement of FFs. FIG. 13 is a diagram illustrating a data structure. Referring to FIG. 11, the computer 10 divides the first FF into a first group for each clock frequency (step S50). For example, as shown in FIG. 12A, an FF 31 that operates with a high-frequency clock and an FF 32 that operates with a low-frequency clock are arranged as the first FF. The first FFs 31 and 32 are supplied with a reset signal from the same second FF 33. The computer 10 divides the first FF into a first group 41 including the FF 31 and a first group 42 including the FF 32.

  Referring to FIG. 11, steps S52 to S60 are performed for each first group. In the following description, first groups 41 and 42 will be described together. Although the case where the number of first groups is two will be described as an example, the number of first groups may be three or more. The computer 10 arranges the second FFs 33a and 33c (step S52). As illustrated in FIG. 12B, the computer 10 arranges the second FF 33 a corresponding to the first group 41 and arranges the second FF 33 c corresponding to the first group 42. The second FF 33c is a clone of the second FF 33a. For example, the second FF 33c is an FF having the same specifications as the second FF 33a. The second FFs 33a and 33c supply reset signals to the first FFs 31 and 32, respectively. The computer 10 arranges the second FFs 33a and 33c at, for example, the average coordinates 57 and 58 of the first FFs 31 and 32, respectively. The computer 10 calculates a margin time for the second FFs 33a and 33c.

  Referring to FIG. 11, computer 10 determines whether the margin time satisfies a desired value (step S54). That is, it is determined whether the delay time from the third FF 50 to the second FFs 33a and 33c satisfies a desired value. For example, the computer 10 determines No when the surplus time violates the timing constraint. If there is no violation, it is determined as Yes. In the case of Yes, it progresses to step S58. In No, the computer 10 moves 2nd FF33a and 33c (step S56). The process returns to step S54. As shown in FIG. 12C, for example, the computer 10 moves the second FFs 33a and 33c by a predetermined distance so as to improve the margin time. For example, the minimum grid is moved. Thereby, 2nd FF33a and 33c approach 3rd FF50 to such an extent that margin time satisfies desired value. As shown in FIG. 12C, the coordinates of the second FFs 33a and 33c move from the average coordinates 57 and 58 to the coordinates 59 and 60, respectively. If the margin time does not satisfy the desired value even after step S56 is executed a plurality of times, the process may return to the positions of the second FFs 33a and 33c in FIG.

  In step S58, the computer 10 determines whether the delay time in each of the first FFs 31 and 32 satisfies a desired value. For example, the computer 10 predicts the delay time of each first FF 31 and 32 from the total wiring length in which each second FF 33a and 33c connects each first FF 31 and 32 and the fanout number of each second FF 33a and 33c. The computer 10 determines whether the predicted delay time of each predicted first FF 31 and 32 violates the timing constraint. If it violates, it is judged as No. If there is no violation, it is determined as Yes. In the case of Yes, it progresses to step S62. In No, it progresses to Step S60.

  In step S60, the computer 10 divides the first groups 41 and 42 into the second groups, and arranges the second FF for each second group. Thereafter, the process proceeds to step S62.

  In step S62, the computer 10 determines whether it is the last first group. For example, when the arrangement of the second FFs of all the first groups (clock frequencies) is completed, it is determined as Yes. In the case of Yes, it ends and returns to FIG. In No, it is set as the following 1st group (step S64). For example, the computer 10 executes steps S52 to S60 for the first group of the next clock frequency.

  As shown in FIG. 13, Reg01 which is a second FF 33a for supplying a reset signal from Reg1 to Reg3 having a clock frequency of 270 MHz is provided. Furthermore, Reg02 for supplying a reset signal from Reg4 to 6 having a clock frequency of 66 MHz is provided. Reg1 to Reg3 are the first FF31, and Reg4 to Reg6 are the first FF32. Reg01 is the second FF 33a, and Reg02 is the second FF 33c. The computer 10 stores the position information of the second FFs 33a and 33c, the margin time, and the delay time of each first FF in the database.

  FIG. 14 is a flowchart showing the circuit design method in step S60 of FIG. Fig.15 (a) to FIG.15 (c) is a figure which shows arrangement | positioning of FF. FIG. 16 is a diagram illustrating a data structure. In FIG. 15A to FIG. 15C and FIG. 16, the description of the first FF 32 of the first group 42 is omitted. Referring to FIG. 14, the computer 10 divides the first FF 31 into a plurality of second groups 43 and 44 based on the coordinates (step S70). For example, as shown in FIG. 15A, a plurality of first FFs 31 and one second FF 33 that supplies a reset signal to the plurality of first FFs 31 are arranged. The computer 10 divides the first group 41 including the first FF 31 into a plurality of second groups 43 and 44 based on the coordinates of the first FF 31. For example, the computer 10 calculates the average coordinates (Xa, Ya) of the first FF 31. The computer 10 sets the first FF 31 whose Y coordinate is larger than Ya as the second group 43 and the first FF 31 whose Y coordinate is smaller than Ya as the second group 44.

  Referring to FIG. 14, steps S72 to S80 are performed for each of the second groups 43 and 44. In the following description, the second groups 43 and 44 will be described together. Moreover, although the case where the number of 2nd groups is two is demonstrated, the number of 2nd groups may be 3 or more. The computer 10 arranges the second FFs 33a and 33b (step S72). As shown in FIG. 15B, the second FF 33 a is arranged corresponding to the second group 43, and the second FF 33 b is arranged corresponding to the second group 44. The second FF 33b is a clone of the second FF 33a. For example, the second FF 33b is an FF having the same specifications as the second FF 33a. The computer 10 arranges the second FFs 33a and 33b at, for example, the average coordinates 62 and 63 of the first FF 31 included in the second groups 43 and 44, respectively. The computer 10 calculates a margin time.

  Referring to FIG. 14, the computer 10 determines whether the margin time satisfies a desired value (step S74). That is, it is determined whether the delay time from the third FF 50 to the second FFs 33a and 33b satisfies a desired value. For example, the computer 10 determines No when the surplus time violates the timing constraint. If there is no violation, it is determined as Yes. In the case of Yes, it progresses to step S78. In No, the computer 10 moves 2nd FF33a and 33b (step S76). The process returns to step S74. As shown in FIG. 15C, for example, the computer 10 moves the second FFs 33a and 33b by a predetermined distance so as to improve the margin time. For example, the minimum grid is moved. Thereby, 2nd FF33a and 33b approach 3rd FF50 to such an extent that margin time satisfies desired value. As shown in FIG. 15C, the coordinates of the second FFs 33a and 33b move from the average coordinates 62 and 63 to the coordinates 64 and 65, respectively. If the margin time does not satisfy the desired value even after step S76 is executed a plurality of times, the process may return to the positions of the second FFs 33a and 33b in FIG.

  In step S78, the computer 10 determines whether the delay time in each first FF 31 satisfies a desired value. For example, the computer 10 predicts the delay time of each first FF 31 from the total wiring length in which each second FF 33a and 33b connects each first FF 31 and the fan-out number of each second FF 33a and 33b. The computer 10 determines whether the predicted delay time of each predicted first FF 31 violates the timing constraint. If it violates, it is judged as No. If there is no violation, it is determined as Yes. In the case of Yes, it progresses to step S82. In No, it progresses to Step S80.

  In step S80, the computer 10 reports that it is difficult to arrange the FFs and recommends reviewing the floor plan or the like. Then, the process ends.

  In step S82, the computer 10 determines whether it is the last second group. For example, when the arrangement of the second FFs of all the second groups is completed, it is determined as Yes. In the case of Yes, it ends and returns to FIG. In the case of No, it is set as the next second group (step S84). For example, the computer 10 executes steps S52 to S60 for the next second group.

  As shown in FIG. 16, Reg1 to Reg4 having a clock frequency of 270 MHz included in the first group 41 are divided into second groups 43 and 44. The second group 43 is provided with Reg03, and the second group 44 is provided with Reg04. Reg1 to Reg4 are the first FF31, Reg03 is the second FF33a, and Reg04 is the second FF33b. The computer 10 stores the position information of the second FFs 33a and 33b, the margin time, the delay time of each first FF, and the group in the database.

  According to the second embodiment, the plurality of first FFs 31 and 32 arranged as in step S50 of FIG. 11 are grouped into a plurality of first groups 41 and 42 for each clock frequency. As in step S52, second FFs 33a and 33c for supplying a reset signal to the plurality of first FFs 31 and 32 are arranged for each of the plurality of first groups 41 and 42. As a result, as in the first embodiment, the timing of the reset signal is easily converged for each clock frequency.

  12B, second FFs 33a and 33c corresponding to the first groups 41 and 42 are arranged based on the coordinates of the plurality of first FFs 31 and 32 included in the first groups 41 and 42, respectively. Note that the second FF 33a or 33c may be arranged based on the first FF 31 or 32 for at least one first group 41 or 42 of the plurality of first groups. Thereby, the delay time of the reset signal from the second FF to the first FF can be shortened. For example, the second FFs 33a or 33c corresponding to the at least one first group 41 or 42 are arranged at the average coordinates of the plurality of first FFs 31 or 32 included in the at least one first group 41 or 42.

  Further, as shown in FIG. 12C, when the delay time of the reset signal from the third FF 50 to the second FFs 33a and 33c does not satisfy the desired value, the arrangement positions of the second FFs 33a and 33c are brought closer to the third FF 50. Thereby, the delay time of the reset signal from the third FF 50 to the second FFs 33a and 33c can be shortened.

  Furthermore, when the delay time of the reset signal from the second FF 33 to the plurality of first FFs 31 included in the first group 41 does not satisfy the desired value as in step S70 of FIG. 14, the first group 41 is changed to the plurality of second groups. Grouped into 43 and 44. Thereby, the delay time of the reset signal from the second FF 33 to the first FF 41 can be further shortened. For example, the plurality of second groups 43 and 44 are grouped based on the coordinates of the plurality of first FFs 31 included in the corresponding first group 41. The grouping of the second groups 43 and 44 can be performed based on the average coordinates of the first FF 31, for example.

  Further, as shown in FIG. 15B, the second FFs 33a and 33b are arranged for the second groups 43 and 44, respectively. Thereby, the delay time of the reset signal from the second FF to the first FF can be shortened. For example, based on the coordinates of the plurality of first FFs 31 included in the plurality of second groups 43 and 44, the second FFs 33a or 33b corresponding to the second groups 43 and 44, respectively, are arranged. Note that the second FF 33a or 33b may be arranged based on the coordinates of the first FF 31 for at least one first group 43 or 44 of the plurality of second groups. For example, the second FFs 33a or 33b corresponding to the at least one second group 43 or 44 are arranged at the average coordinates of the plurality of first FFs 31 included in the at least one second group 43 or 44.

  Further, as shown in FIG. 15C, when the delay time of the reset signal from the third FF 50 to the second FFs 33a and 33b does not satisfy the desired value, the arrangement positions of the second FFs 33a and 33b are brought closer to the third FF 50. As a result, the delay time of the reset signal from the third FF to the second FF can be shortened.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Supplementary Note 1): A circuit design method executed by a computer, the step of grouping a plurality of first flip-flops into a plurality of first groups for each clock frequency, and for each of the plurality of first groups, Disposing a second flip-flop for supplying a reset signal to a plurality of first flip-flops.
(Supplementary Note 2): The step of disposing the second flip-flop includes the at least one first flip-flop based on the coordinates of the plurality of first flip-flops included in at least one first group of the plurality of first groups. The circuit design method according to claim 1, further comprising the step of arranging the second flip-flops corresponding to one group.
(Supplementary Note 3): In the step of arranging the second flip-flop, the average coordinate of the plurality of first flip-flops included in the at least one first group is the first coordinate corresponding to the at least one first group. The circuit design method according to appendix 2, further comprising a step of arranging two flip-flops.
(Supplementary Note 4): When the delay time of the reset signal from the third flip-flop supplying the reset signal to the second flip-flop to the second flip-flop does not satisfy a desired value, the arrangement of the second flip-flop 4. The circuit design method according to claim 2 or 3, further comprising a step of bringing a position closer to the third flip-flop.
(Supplementary Note 5): When the delay time of the reset signal from the second flop flip to the plurality of first flip-flops included in the corresponding first group does not satisfy a desired value, the plurality of the corresponding first groups The circuit according to any one of appendices 1 to 4, further comprising a step of grouping the second flip-flop into a second group and a step of arranging the second flip-flop for each of the plurality of second groups. Design method.
(Supplementary Note 6): The step of grouping the corresponding first group into a plurality of second groups is based on the coordinates of the plurality of first flip-flops included in the corresponding first group. The circuit design method according to appendix 5, which includes a step of grouping into groups.
(Supplementary Note 7): The step of arranging the second flip-flop for each of the plurality of second groups includes the step of arranging the plurality of first flip-flops included in at least one second group of the plurality of second groups. 7. The circuit design method according to appendix 5 or 6, further comprising the step of arranging the second flip-flop corresponding to the at least one second group based on coordinates.
(Supplementary Note 8): A computer causes a plurality of first flip-flops to be grouped into a plurality of first groups for each clock frequency, and a reset signal is sent to the plurality of first flip-flops for each of the plurality of first groups. A circuit design program comprising a second flip-flop to be supplied.
(Supplementary Note 9): A first unit that groups a plurality of first flip-flops into a plurality of first groups for each clock frequency, and a reset signal to the plurality of first flip-flops for each of the plurality of first groups. And a second unit for disposing a second flip-flop for supplying the circuit.

10 Computer 31, 32 1st FF
33 2nd FF
41, 42 1st group 43, 44 2nd group 50 3rd FF

Claims (6)

A circuit design method executed by a computer,
Grouping a plurality of first flip-flops into a plurality of first groups for each clock frequency;
Disposing a second flip-flop for supplying a reset signal to the plurality of first flip-flops for each of the plurality of first groups;
When the delay time of the reset signal from the second flop flip to the plurality of first flip-flops included in the corresponding first group does not satisfy a desired value, the corresponding first group is changed to a plurality of second groups. The step of grouping,
Disposing the second flip-flop for each of the plurality of second groups;
A circuit design method comprising:   The step of arranging the second flip-flops corresponds to the at least one first group based on coordinates of the plurality of first flip-flops included in at least one first group of the plurality of first groups. 2. The circuit design method according to claim 1, further comprising the step of arranging the second flip-flop.   The step of disposing the second flip-flop includes disposing the second flip-flop corresponding to the at least one first group at an average coordinate of the plurality of first flip-flops included in the at least one first group. 3. The circuit design method according to claim 2, further comprising the step of:   When the delay time of the reset signal from the third flip-flop supplying the reset signal to the second flip-flop does not satisfy a desired value, the arrangement position of the second flip-flop is set to the third flip-flop. 4. The circuit design method according to claim 2, further comprising a step of approaching the flip-flop. On the computer,
Grouping a plurality of first flip-flops into a plurality of first groups for each clock frequency;
For each of the plurality of first groups, a second flip-flop that supplies a reset signal to the plurality of first flip-flops is disposed .
When the delay time of the reset signal from the second flop flip to the plurality of first flip-flops included in the corresponding first group does not satisfy a desired value, the corresponding first group is changed to a plurality of second groups. Let them group,
Wherein for each of the plurality of the second group, the circuit design program characterized Rukoto is disposed the second flip-flop. A first unit that groups a plurality of first flip-flops into a plurality of first groups for each clock frequency;
A second unit in which a second flip-flop that supplies a reset signal to the plurality of first flip-flops is disposed for each of the plurality of first groups;
When the delay time of the reset signal from the second flop flip to the plurality of first flip-flops included in the corresponding first group does not satisfy a desired value, the corresponding first group is changed to a plurality of second groups. A third unit to group,
A fourth unit for disposing the second flip-flop for each of the plurality of second groups;
A circuit design apparatus comprising:

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