JP2010211550A - Circuit design program, circuit design method, and circuit design device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and reliably extract a synchronizing reset signal. <P>SOLUTION: A domain extraction means 2 extracts a domain of a signal as a candidate of a synchronizing reset signal of a sequential circuit to be designed. For example, in a circuit 5 shown in a Fig.1, the signal is back traced from an enable terminal of a D flip flop 6, and reaches an external input terminal. The signal (Clear) of the terminal is extracted as a domain. A measurement means 3 measures a signal value to be input to the sequential circuit by changing the logic of the extracted domain signal. In the circuit 5 shown in the Fig.1, a signal value to be input to the D flip flop 6 is measured by changing the logic of the signal (Clear). A synchronizing reset determination means 4 determines whether or not there exists a synchronizing reset signal on the basis of the signal value measured by the measurement means 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit design program, a circuit design method, and a circuit design apparatus.

  A reset signal is mainly known that is used to initialize a sequential circuit such as a D flip-flop when it is generated internally when an abnormality is detected in the circuit or is input from the outside.

  There are two reset signals, a synchronous reset signal and an asynchronous reset signal. The synchronous reset signal initializes the flip-flop in synchronization with the clock. The asynchronous reset signal initializes the flip-flop when the reset signal is turned on regardless of the clock signal.

  The synchronization reset signal is manually set as necessary at present, but there are many setting locations, there is a setting omission, and it is easy to make an error in setting a fixed value to be in a reset state.

Japanese Patent Laid-Open No. 10-340289

  An asynchronous reset input terminal is provided in a flip-flop that inputs an asynchronous reset signal, and the asynchronous reset signal is directly input to this input terminal. Thus, the asynchronous reset signal does not affect the logic that generates the data input of the flip-flop.

  On the other hand, the synchronous reset signal affects the logic that generates the data input of the flip-flop. For example, an asynchronous structure check for checking whether a problem such as a malfunction occurs when transferring data between circuits operating with different clocks is known. In this check, it is checked whether the synchronization circuit (synchronizer or the like) inserted to prevent the occurrence of meta-stable is inserted based on a preset rule. During this check, a pseudo error (a situation where the tool outputs an error report for an operation or event that cannot actually occur) may occur due to the influence of the synchronous reset signal. When this pseudo error occurs, the designer needs to review the circuit.

In logic synthesis, a circuit that does not require resetting may be generated due to optimization, and an error will still occur, requiring the designer to review the circuit.
The present invention has been made in view of the above points, and an object thereof is to provide a circuit design program, a circuit design method, and a circuit design apparatus capable of easily and reliably extracting a synchronous reset signal.

  In order to achieve the above object, a disclosed circuit design program is provided. The circuit design program causes the computer to function as a domain extraction unit, a measurement unit, and a synchronization reset determination unit.

The domain extracting means extracts a domain of a signal that is a candidate for a synchronous reset signal of a sequential circuit.
The measuring means changes the logic of the extracted domain signal and measures the signal value input to the sequential circuit.

  The synchronization reset determination unit determines whether or not there is a synchronization reset signal based on the signal value measured by the measurement unit.

  According to the disclosed circuit design program, the synchronous reset signal can be easily and reliably extracted.

It is a figure which shows the outline | summary of the circuit design apparatus of embodiment. It is a figure which shows the hardware structural example of a circuit design apparatus. It is a block diagram which shows the structure of a circuit design apparatus. It is a block diagram which shows the function of a synchronous reset extraction part. It is a figure which shows the process of the domain extraction part in case an enable terminal exists in D flip-flop. It is a figure which shows the process of the domain extraction part when an enable terminal does not exist in D flip-flop. It is a figure explaining the process of a synchronous reset determination part. It is a flowchart which shows the whole process of a synchronous reset extraction part. It is a flowchart which shows the process of the domain extraction part in case an enable terminal exists in D flip-flop. It is a flowchart which shows the process of the domain extraction part when an enable terminal does not exist in D flip-flop. It is a flowchart which shows a determination process. It is a figure which shows the specific example of a synchronous reset extraction process. It is a figure which shows the specific example of a synchronous reset extraction process. It is a figure which shows the specific example of a synchronous reset extraction process. It is a figure which shows the specific example of a synchronous reset extraction process. It is a figure which shows the processing flow in the case of applying the extracted synchronous reset to circuit design. It is a figure which shows an example when a report is read into an asynchronous structure check part. It is a flowchart which shows the process of an asynchronous structure check part. It is a figure which shows an example when a logic synthetic | combination part reads a report.

Hereinafter, embodiments will be described in detail with reference to the drawings.
First, a circuit design apparatus according to an embodiment will be described, and then the embodiment will be described more specifically.

FIG. 1 is a diagram illustrating an outline of a circuit design apparatus according to an embodiment.
The circuit design program according to the embodiment causes a computer (circuit design apparatus) 1 to function as the domain extraction unit 2, the measurement unit 3, and the synchronization reset determination unit 4.

The domain extraction unit 2 extracts a domain of a signal that is a candidate for a synchronous reset signal of a sequential circuit in a circuit to be designed.
Specifically, when the enable terminal is present in the sequential circuit, the domain extracting unit 2 backtraces from the enable terminal and extracts the signal of the terminal that has reached the external input terminal, another sequential circuit, or the black box as a domain. Is preferred. Thereby, a domain can be extracted easily and reliably.

  For example, in the circuit 5 shown in FIG. 1, back tracing is performed from the enable terminal of the D flip-flop 6, and the external input terminal is reached via the inverter 7 and the AND circuit 8. Then, the signal (Clear) of the terminal is extracted as a domain.

  Although not shown in FIG. 1, when there is no enable terminal in the sequential circuit, the domain extracting means 2 preferably extracts a domain of a signal to which a condition related to the logic of the output signal of the sequential circuit belongs. . As a result, the flip-flop domain can be easily and reliably extracted.

  The measuring means 3 changes the logic of the extracted domain signal and measures the signal value input to the sequential circuit. In the circuit 5 shown in FIG. 1, the signal value input to the D flip-flop 6 is measured by changing the logic of the signal (Clear).

  The synchronization reset determination unit 4 determines whether or not a synchronization reset signal exists based on the signal value measured by the measurement unit. Specifically, when the signal values input to the sequential circuit are constants and the constants are all the same, it is preferable to determine that a synchronous reset signal exists. Thereby, it can be determined reliably whether a reset signal exists.

  According to such a circuit design device 1, the domain extraction unit 2 extracts the domain, and the synchronization reset determination unit 4 determines whether or not the synchronization reset signal exists, thereby easily and reliably generating the synchronization reset signal. Can be extracted.

Hereinafter, the embodiment will be described more specifically.
FIG. 2 is a diagram illustrating a hardware configuration example of the circuit design apparatus.
The entire circuit design apparatus 10 is controlled by a CPU (Central Processing Unit) 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, an external auxiliary storage device 106, and a communication interface 107 are connected to the CPU 101 via a bus 108. Yes.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. A program file is stored in the HDD 103.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits a signal transmitted from the keyboard 105 a and the mouse 105 b to the CPU 101 via the bus 108.

  The external auxiliary storage device 106 reads information written on the recording medium and writes information on the recording medium. Examples of the recording medium that can be read and written by the external auxiliary storage device 106 include a magnetic recording device, an optical disc, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include an HDD, a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  The communication interface 107 is connected to the network 30. The communication interface 107 transmits and receives data to and from other computers via the network 30.

  With the hardware configuration as described above, the processing functions of the present embodiment can be realized. The following functions are provided in the circuit design device 10 having such a hardware configuration.

FIG. 3 is a block diagram showing the configuration of the circuit design apparatus.
The circuit design device 10 includes an HDL description storage unit 11, a library storage unit 12, a synchronization reset extraction unit 13, and a synchronization reset storage unit 14.

  The HDL description storage unit 11 stores an HDL description expressed in hardware description language (HDL) related to a circuit to be designed such as RTL (Register Transfer Level) or a netlist.

The library storage unit 12 stores a library that matches the component information and pin assignment of the netlist.
The synchronous reset extraction unit 13 takes out the flip-flop description part of the hardware description language, and extracts the synchronous reset description part in a different manner depending on the presence / absence of the enable terminal of the flip-flop (hereinafter simply referred to as “extract synchronous reset”). )

The synchronization reset storage unit 14 stores the signal name and reset value of the synchronization reset extracted by the synchronization reset extraction unit 13.
Next, the function of the synchronous reset extraction unit 13 will be described.

FIG. 4 is a block diagram illustrating the function of the synchronous reset extraction unit.
The synchronization reset extraction unit 13 includes a domain extraction unit 131, a domain list storage unit 132, a constant propagation unit 133, and a synchronization reset determination unit 134.

  The domain extraction unit 131 extracts a domain by a different extraction method depending on whether an enable terminal exists in the D flip-flop. Here, the enable terminal covers all the conditions for determining the output data of the D flip-flop by simple synthesis after reading the RTL description, performing parsing (checking for grammatical violations), and elaborating (checking the module hierarchy). If not, the terminal is generated as a condition not covered.

First, the processing of the domain extraction unit 131 when the D flip-flop has an enable terminal will be described.
The domain extraction unit 131 backtraces the combinational logic from the enable terminal of the D flip-flop, and extracts a net signal to which the external input terminal, the D flip-flop output terminal, or the terminal reaching the black box belongs as a domain. The extracted domain is stored in the domain list storage unit 132. Here, the black box means an RTL description that does not have an HDL description or does not conform to a synthesis style such as PLL and I / O.

FIG. 5 is a diagram illustrating processing of the domain extraction unit when the D flip-flop has an enable terminal.
The circuit 20 shown in FIG. 5 includes a D flip-flop 21 including a selector Sel1 and a register Reg1, an AND circuit AND1 and an AND circuit AND2 that supply a Clear signal to the D flip-flop 21, and inverters Inv1 to Inv3. Yes.

A clock signal (clk) is supplied to the register Reg1.
In the example illustrated in FIG. 5, the domain extraction unit 131 starts backtrace from the enable terminal E. Then, it reaches the AND circuit AND2 via the inverter Inv1.

  Since the AND circuit AND2 does not correspond to any of the external input terminal, the D flip-flop output terminal, and the black box, the back trace is started again from the input side of the AND circuit AND2. Then, the net signal (Clear) reached via the inverter Inv2 is extracted.

  Next, the domain extraction unit 131 starts backtrace from the enable terminal E again. Then, it reaches the AND circuit AND2 via the inverter Inv1. Back tracing is started again from the input side of the AND circuit AND2. Then, the net signal (InCtrl) reached via the inverter Inv3 is extracted.

Next, processing of the domain extraction unit 131 when there is no enable terminal in the D flip-flop will be described.
FIG. 6 is a diagram illustrating processing of the domain extraction unit when there is no enable terminal in the D flip-flop.

  The domain extraction unit 131 reads the RTL description, and after parsing and elaborating, creates a CDFG (Control Data Flow Graph) indicating the control of the description and the data flow. Then, a net signal to which a condition (control) related to the logic of the signal to be the D flip-flop belongs is extracted as a domain. The extracted domain is stored in the domain list storage unit 132.

In the example shown in FIG. 6, the CDFG 32 created by reading the RTL description 31 is illustrated.
A branch condition such as an “if” statement or a “Case” statement becomes a control portion (a triangular portion in FIG. 6). Further, the assignment statement becomes a data portion (square portion in FIG. 6).

  The domain extraction unit 131 extracts, from the CDFG 32, net signals (Clear and InCtrl) to which a condition relating to the logic of the signal (Outdata) serving as the D flip-flop belongs.

  The constant propagation unit 133 sets constants of all patterns (powers of 2) in the extracted domain. And a constant is propagated by simulation. Specifically, “0” and “1” are given to the extracted net signal of the domain. Further, logic “X” is given to other net signals.

Then, constant propagation by simulation is performed for all the patterns of the domain, and the net signal value of the D flip-flop input is observed.
Referring to the constant propagation observation process using the circuit 20 shown in FIG. 5, “0” and “1” are given to the extracted net signals (Clear and InCtrl) of the domain, respectively. Further, logic “X” is given to the other net signals (InData). Then, a simulation is performed for the total number of domain patterns 2 ² = 4 to propagate the constants, and the net signal value at the input terminal D of the D flip-flop 21 is observed.

  The synchronization reset determination unit 134 performs the synchronization reset when the D flip-flop input at the observation point may be a constant (0 or 1) and all the constant values are the same in the simulation result of all patterns of the domain. It is determined that the signal exists in the extracted domain.

  When the synchronization reset determination unit 134 determines that there is a synchronization reset signal, the input pattern of the domain in which the D flip-flop input is a constant is AND logic, and a logical expression is generated as the OR logic for the number of patterns that are constant. To do. Then, logical optimization of the logical expression is performed. Then, the signal remaining in the logical expression that is logically optimized is extracted as a synchronous reset signal, and the reset value is extracted as “1” and “0” when the logical expression signal is affirmative / negative.

FIG. 7 is a diagram for explaining the processing of the synchronization reset determination unit.
A table 41 shown in FIG. 7 is a table (table) showing observation results.
The table 41 includes columns of domain net signals, non-domain net signals, and DFF input to be observed, and pieces of information arranged in the horizontal direction are associated with each other.

  In the domain net signal column, a domain name for identifying the extracted domain is set. In the lower part, the logic pattern given to the net signal of the domain in the observation process is set.

  In the column of net signals other than the domain, signal names for identifying net signals other than the domain are set. In the lower part, logic patterns that can be taken by the signal names are set.

The value observed at the input terminal of the D flip-flop when the logic pattern set in the domain net signal field is input is set in the DFF input field.
In the example shown in FIG. 7, the logic of the input terminal of the D flip-flop at the observation location is “0” in the third and fourth patterns of the table 41. For this reason, the input of the D flip-flop at the observation point may be a constant (0 or 1), and the condition that the values of the constants are all the same is satisfied. Therefore, the synchronization reset determination unit 134 determines that a synchronization reset signal exists.

  Then, the logic pattern of the domain in which the logic of the input terminal of the D flip-flop is a constant (the third and fourth patterns in FIG. 7) is AND logic, and the logical expression is OR logic for the number of patterns that are constant. Generate. Then, the net signal (Clear) remaining in the logical expression (Clear) that has been optimized from the generated logical expression (Clear & ~ InCtrl + Clear & InCtrl) is extracted as a synchronous reset signal.

Next, the whole process of the synchronous reset extraction part 13 is demonstrated.
FIG. 8 is a flowchart showing the overall processing of the synchronous reset extraction unit.
First, the D flip-flop from which synchronous reset is extracted is extracted (step S1).

Next, the domain extraction unit 131 extracts the domain of the extracted D flip-flop (step S2).
Next, the constant propagation unit 133 observes constant propagation (step S3). That is, a constant value is set in the domain, and “X” is set in the domain, and the logic of the input terminal of the D flip-flop after the simulation is observed.

Next, the synchronous reset determination unit 134 performs determination processing (step S4).
This is the end of the description of the entire process.
Next, the processing of the domain extraction unit 131 of the D flip-flop having the enable terminal will be described.

FIG. 9 is a flowchart showing the processing of the domain extraction unit when the D flip-flop has an enable terminal.
First, back tracing is performed from the enable terminal of the D flip-flop (step S11).

Next, it is determined whether or not the backtrace is finished (step S12).
When the backtrace is finished (Yes in step S12), the domain extraction process is finished.

On the other hand, if the backtrace has not ended (No in step S12), the reached point is checked (step S13).
Then, it is determined whether the reached point is an external input, a flip-flop, or a black box (step S14).

  When the point is not one of the external output, the flip-flop, and the black box, back tracing is performed from the input side of the reached point (step S15). Thereafter, the process proceeds to step S12, and the processing after step S12 is continued.

  On the other hand, when the point is any one of an external output, a flip-flop, and a black box (Yes in step S14), the reached net signal is stored (added) in the domain list storage unit 132 as a domain (step S16). Thereafter, the process proceeds to step S12, and the processing after step S12 is continued.

Above, description of the process of the domain extraction part 131 is complete | finished.
Next, processing of the domain extraction unit 131 of the D flip-flop having no enable terminal will be described.

FIG. 10 is a flowchart showing the processing of the domain extracting unit when there is no enable terminal in the D flip-flop.
First, a condition signal for the D flip-flop is extracted from CDFG (step S21).

Next, it is determined whether or not the extraction of the condition signal of the D flip-flop has been completed (step S22).
When the extraction is finished (Yes in step S22), the process is finished.

On the other hand, if the extraction has not ended (No in step S22), the control of the D flip-flop signal is extracted (step S23).
Then, the extracted condition signal is stored (added) as a domain in the domain list storage unit 132 (step S24). Thereafter, the process proceeds to step S22, and the processes after step S22 are continued.

This is the end of the description of the processing of the domain extraction unit.
Next, the determination process in step S4 will be described.
FIG. 11 is a flowchart showing the determination process.

First, the table 41 indicating the observation result is read (step S31).
Next, it is determined whether or not the signal value of the DFF input of a certain bit in the table 41 is a constant value (step S32).

When the observed value of the DFF input is not a constant value (No in step S32), the process proceeds to step S35.
On the other hand, if the observed value of the DFF input is a constant value (Yes in step S32), AND logic is generated from the pattern set in the domain (step S33).

Next, the generated AND logic is added to the OR logic (step S34).
Next, it is determined whether or not logical expressions for all patterns have been generated (step S35).
When the logical expressions of all the patterns have not been generated (No in Step S35), the process proceeds to Step S32, and the processing after Step S32 is continued for the observation value of the DFF input of the next bit.

  On the other hand, when the logical expressions of all patterns are generated (Yes in step S35), the generated logical expressions are optimized (step S36). Then, the signal remaining in the logical expression is extracted as a synchronous reset signal.

This is the end of the description of the determination process. The determination process is performed for each bit of the flip-flop.
Next, a specific example of the synchronous reset extraction process will be described.

<Specific example 1>
FIG. 12 is a diagram illustrating a specific example of the synchronous reset extraction process.
In the RTL description 31a shown in FIG. 12A, constants are substituted into the output. That is, although there is no input signal, “0” and “1” of the flip-flop are changed by the control signal. Specifically, it is 1 when InCtrl1. It becomes “0” in the case of Inctr2.

The domain extraction unit 131 extracts net signals (InCtrl1 and InCtrl2) from the RTL description 31a as domains.
Then, the synchronous reset determination unit 134 refers to the table 41a shown in FIG. 12B obtained by the constant propagation unit 133 performing the constant propagation observation process. Then, although the logic of the input terminal of the D flip-flop may become a constant, it is determined that there is no synchronous reset because the values of the constants are not the same.

<Specific example 2>
FIG. 13 is a diagram illustrating a specific example of the synchronous reset extraction process.
The domain extraction unit 131 extracts net signals (Clear, Init, and InCtrl) as domains from the RTL description 31b illustrated in FIG.

  Then, the synchronization reset determination unit 134 refers to the table 41b obtained by the constant propagation unit 133 performing the constant propagation observation process illustrated in FIG. Then, the logic of the input terminal of the D flip-flop is the same constant “0” in the third to eighth patterns.

  Therefore, the logical pattern of the domain that becomes a constant is AND logic, and a logical expression (~ Clear & Init & ~ InCtrl + ~ Clear & Init & InCtrl + Clear & ~ Init & ~ InCtrl + Clear & ~ Init & InCtrl + Clear & Init & ~ InCtrl + Clear & Init & InCtrl Extract as a signal. Both reset values are “1”.

<Specific example 3>
FIG. 14 is a diagram illustrating a specific example of the synchronous reset extraction process.
The domain extracting unit 131 extracts net signals (Clear, Init, and InCtrl) as domains from the RTL description 31c illustrated in FIG.

  Then, the synchronization reset determination unit 134 refers to the table 41c obtained by the constant propagation unit 133 performing the constant propagation observation process illustrated in FIG. Then, the logic of the input terminal of the D flip-flop is “0” in both the seventh and eighth patterns.

  For this reason, the logic pattern of the domain that becomes a constant is AND logic, and the logic is optimized from a logical expression (Clear & Init & ~ InCtrl + Clear & Init & InCtrl) that is generated as OR logic for the number of constant patterns. The net signal (Clear, Init) remaining in the logical expression (Clear & Init) is extracted as a synchronous reset signal. Both reset values are “1”.

<Specific Example 4>
FIG. 15 is a diagram illustrating a specific example of the synchronous reset extraction process.
The domain extraction unit 131 extracts net signals (Clear and InCtrl) as domains from the RTL description 31d illustrated in FIG.

  Then, the synchronization reset determination unit 134 refers to the table 41d obtained by the constant propagation unit 133 performing the constant propagation observation process illustrated in FIG. Then, since the logic of the input terminal of the D flip-flop does not become a constant, it is determined that there is no synchronous reset.

  As described above, according to the circuit design device 10, the synchronous reset extraction unit 13 extracts the synchronous reset. Thereby, for example, by inputting the extracted synchronous reset signal and its value with respect to a pseudo error, the error of the designer is not notified to the designer, so that the trouble of the designer can be saved.

  In addition, by designating a synchronous reset signal, it is possible to prevent the occurrence of an error by performing logic synthesis without generating logic that does not need to be reset before data input to the flip-flop. This will be described below using a specific example.

FIG. 16 is a diagram showing a processing flow when the extracted synchronous reset is applied to circuit design.
The circuit design device 10 further includes a design specification storage unit 51, an RTL design unit 52, a description style check unit 53, an asynchronous structure check unit 54, a logic synthesis unit 55, and a netlist storage unit 56. ing.

In FIG. 16, the library storage unit 12 and the synchronous reset extraction unit 13 are not shown.
The RTL design unit 52 designs an RTL from the design specifications stored in the design specification storage unit 51. The designed HDL of the RTL design description is stored in the HDL description storage unit 11.

The description style check unit 53 checks a syntax error in the RTL design description and a problem that does not cause a syntax error.
The asynchronous structure check unit 54 has a problem such as malfunction when transferring data between circuits operating with different clocks based on the signal name and reset value of the synchronous reset stored in the synchronous reset storage unit 14. Check whether or not.

  The logic synthesis unit 55 performs logic synthesis based on the signal name and reset value of the synchronization reset stored in the synchronization reset storage unit 14, and generates a gate level netlist from the RTL.

FIG. 17 is a diagram illustrating an example when a report is read by the asynchronous structure check unit.
When data is transferred using a clock signal (Tclk) and a clock signal (Rclk) having different frequencies, a meta stable may occur. In order to prevent this, a synchronizer 61 is provided which receives two D flip-flops 21 and 21a side by side with a clock Rclk (reception side clock). As shown in FIG. 17, an AND circuit AND3 for inserting a synchronous reset may be arranged between the D flip-flops 21 and 21a.

  In order to avoid meta-stable, it is not preferable that there is logic between the D flip-flops 21 and 21a. Therefore, the asynchronous structure check unit 54 detects an error. However, the route from the net signal (Clear) to the AND circuit AND1 and the AND circuit AND3 has no effect on the circuit 60 unless it is cleared, but the synchronizer 61 has logic due to the influence of the synchronous reset. This is because a pseudo error occurs.

  According to the circuit design device 10, it is extracted that the Clear signal input to the AND circuit AND1 and the AND circuit AND3 is a synchronous reset signal, and the asynchronous structure check unit 54 reads the report so that the AND circuit AND1 and The AND circuit AND3 can be ignored, and the error of the designer can be saved by not reporting the error to the designer.

Next, the processing of the asynchronous structure check unit 54 will be described in detail.
FIG. 18 is a flowchart showing the processing of the asynchronous structure check unit.
First, a constant is propagated by setting a value that does not turn on synchronous reset (opposite of the extracted reset value) to the net (step S41).

Next, an asynchronous path is extracted (step S42).
Next, it is determined whether or not logic exists before and after the asynchronous path (step S43).
If there is no logic before and after the asynchronous path (No in step S43), the process proceeds to step S46.

On the other hand, if logic exists before and after the asynchronous path (Yes in step S43), it is determined whether or not there are constants other than one input with multiple inputs (step S44).
If there are multiple inputs and there is no constant other than one input (No in step S44), the process proceeds to step S46.

On the other hand, if there are multiple inputs and a constant other than 1 input (Yes in step S44), the logic is marked (step S45).
Next, it is determined whether all asynchronous paths have been extracted (step S46).

If not all have been extracted (No in step S46), the process proceeds to step S42, and the processes after step S42 are continued.
On the other hand, if all of them are extracted (Yes in step S46), the marked logic is ignored and an asynchronous structure check is performed (step S47). Thereafter, the process ends.

This is the end of the description of the processing of the asynchronous structure check unit 54.
Next, processing when the logic synthesis unit 55 reads a report will be described.
FIG. 19 is a diagram illustrating an example when a report is read by the logic synthesis unit.

If a synchronous reset exists, the flip-flop is not reset due to the effect of optimization options (reducing area and timing).
As shown in FIG. 19A, if logic synthesis is performed in which AND-OR logic including a synchronous reset exists in the previous stage of the selector Sel2, the logic of the signal output from the selector Sel2 becomes “X”, and the D flip-flop The reset for the group 21b does not last forever. This is because if the control signal of the selector contains an indefinite X, the selector outputs “X”.

  On the other hand, in the circuit design device 10, since it can be extracted that the signal (Clear) input to the AND circuit AND4 and the AND circuit AND5 is a synchronous reset signal, logic synthesis can be performed without using the signal.

  That is, as shown in FIG. 19B, by configuring the circuit with AND-OR logic including a synchronous reset signal after the selector Sel2, the select signal is “0” when Clear = 0 input to the AND circuit AND6. Thus, errors can be avoided.

  In the present embodiment, the asynchronous reset check unit 54 or the logic synthesis unit 55 reads the synchronous reset report stored in the synchronous reset storage unit 14. However, the present invention is not limited to this, and the asynchronous structure check unit 54 and the logic synthesis unit 55 may each have a function corresponding to the function of the synchronous reset extraction unit 13.

  Further, the processing performed by the circuit design device 10 may be distributedly processed by a plurality of devices. For example, one device may perform RTL generation processing to generate an RTL, and another device may extract a reset signal using the RTL.

  The circuit design program, the circuit design method, and the circuit design apparatus of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each part has the same function. Can be replaced with any structure having Moreover, other arbitrary structures and processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions of the circuit design device 10 is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  A computer that executes a circuit design program stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

DESCRIPTION OF SYMBOLS 1, 10 Circuit design apparatus 2 Domain extraction means 3 Measurement means 4 Synchronization reset determination means 5, 20, 60 Circuit 6, 21, 21a, 21b D flip-flop 7, Inv1, Inv2, Inv3 Inverter 8, AND1-AND6 AND circuit 11 HDL description storage unit 12 Library storage unit 13 Synchronization reset extraction unit 14 Synchronization reset storage unit 31-31d RTL description 32 CDFG
41 to 41d Table 51 Design specification storage unit 52 RTL design unit 53 Description style check unit 54 Asynchronous structure check unit 55 Logic synthesis unit 56 Netlist storage unit 61 Synchronizer 131 Domain extraction unit 132 Domain list storage unit 133 Constant propagation unit 134 Synchronous reset Judgment part Reg1 register Sel1, Sel2 selector

Claims (8)

Computer
Domain extraction means for extracting a domain of a signal that is a candidate for a synchronous reset signal of a sequential circuit;
Measuring means for measuring a signal value input to the sequential circuit by changing logic of the extracted signal of the domain;
Synchronization reset determination means for determining whether a synchronization reset signal exists based on the signal value measured by the measurement means;
A circuit design program characterized by functioning as   When an enable terminal is present in the sequential circuit, the domain extracting unit backtraces from the enable terminal and extracts a signal domain of an external input terminal, another sequential circuit, or a terminal reaching a black box. The circuit design program according to claim 1.   2. The circuit design program according to claim 1, wherein when there is no enable terminal in the sequential circuit, the domain extracting unit extracts a domain of a signal to which a condition related to a logic of an output signal of the sequential circuit belongs. .   The circuit design program according to claim 1, wherein the measurement unit measures the signal value by applying indefinite logic to the extracted net signal other than the domain.   2. The circuit according to claim 1, wherein the synchronization reset determination unit determines that a synchronization reset signal is present when a signal value input to the sequential circuit is a constant and the constants are all the same. Design program.   2. The computer according to claim 1, wherein the computer further functions as a logic optimization unit that optimizes the logic of the net signal of the domain that is determined by the synchronization reset determination unit to include a synchronization reset signal. Circuit design program. The computer runs,
Domain extraction means extracts a domain of a signal that is a candidate for a synchronous reset signal of a sequential circuit,
The measuring means changes the logic of the extracted signal of the domain and measures the signal value input to the sequential circuit,
The synchronization reset determination means determines whether a synchronization reset signal exists based on the signal value measured by the measurement means;
A circuit design method characterized by the above. A domain extraction unit for extracting a domain of a signal that is a candidate for a synchronous reset signal of a sequential circuit;
A measurement unit that changes a logic of the extracted signal of the domain and measures a signal value input to the sequential circuit;
A synchronization reset determination unit that determines whether a synchronization reset signal exists based on a signal value measured by the measurement unit;
A circuit design apparatus comprising:

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