JP2010181984A - Program and device for supporting circuit design - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To verify whether or not failure occurs in a path when operating a product during scan test. <P>SOLUTION: A circuit design support device 1 functions as a first storage means 2, a second storage means 3, and a circuit arrangement means 4 by this circuit design support program. The first storage means 2 stores circuit design information (e.g. a net list) having a plurality of order circuits. The second circuit storage means 3 stores information between the order circuits having a condition causing timing restriction violation by inserting a failure-detecting clock (a scan clock) of the circuit design information. The circuit arrangement means 4 virtually arranges a circuit outputting an output signal of a tip order circuit to a subsequent-stage order circuit between the order circuits of the information stored by the second storage means 3 of the circuit design information only when logic of a signal input to the tip order circuit between the order circuits and a signal output by the tip order circuit does not change. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit design support program and a circuit design support apparatus.

In recent years, the number of gates that can be mounted on an LSI (Large Scale Integration) has increased, and the number of clocks inside the LSI has become more and more complex.
For this reason, in order to confirm that a physical defect does not occur in the manufacturing process, a test before shipment is generally performed. Specifically, for example, a scan design is performed on the circuit design information, and a test pattern is generated by an ATPG (Auto Test Pattern Generation) process to detect a failure of the internal node.

  In the scan design, a clock input terminal for operating a flip-flop (sequential circuit) is required. If possible, I want to use the same clock input terminal as the clock input terminal used to operate the product. However, in recent designs, there are many cases where the output signal of PLL (Phase Lock Loop) or the division signal is used as the clock. To do. In that case, a separate scan clock input terminal is required for the scan test.

FIG. 10 is a diagram illustrating an example in which scan clock input terminals are arranged for a scan test.
In the circuit 90 shown in FIG. 10, the clock CLK input to the PLL circuit 92 from the input terminal 91 for inputting the clock CLK is frequency-divided by the frequency dividing circuits 93 and 94 and supplied to the D flip-flops FF91 to FF94.

  In this circuit 90, at the time of a scan test, an input terminal 95 for inserting the scan clock SCAN_CK1 and an input terminal 96 for inserting the scan clock SCAN_CK2 are provided for the scan test.

  Further, a selector 97 for selecting the scan clock SCAN_CK1 and a selector 98 for selecting the scan clock SCAN_CK2 are provided for the scan test at the subsequent stage of the frequency dividing circuits 93 and 94, respectively.

  As the number of scan clock input terminals in the design increases, the number of test patterns generated increases and the test time also increases. For this reason, clocks are grouped together during scan design. Therefore, the “clock for operating the product” may not match the “clock for scan test”.

  Further, in order to reduce the number of test patterns to be generated, there are cases where a plurality of scan clock terminals are grouped as one group and are handled synchronously. In this case, even a path between clocks that was originally asynchronous is handled as a synchronization only during a scan test.

  If the clock path for operating the product differs from the clock path for the scan test, a hold timing error may occur during the scan test even if there is no timing error when operating the product.

  One of the factors that cause a hold timing error is that a setup time margin cannot be secured. If the setup time margin cannot be ensured, the route is designated as a failure detection target (hereinafter referred to as “NOATG”).

JP 2002-131387 A

  However, if a route is designated as NOATG, failure detection between the routes cannot be performed. For this reason, there is a problem in that it is impossible to verify whether or not a failure occurs in the path when the product is operated during the scan test.

  The present invention has been made in view of such points, and a circuit design support program and a circuit capable of verifying whether or not a failure occurs in the path when operating a product during a scan test. An object is to provide a design support apparatus.

  In order to achieve the above object, a circuit design support program for detecting a failure between sequential circuits operating with an asynchronous clock is provided. This circuit design support program causes a computer to function as first storage means, second storage means, and circuit arrangement means.

The first storage means stores circuit design information including a plurality of sequential circuits.
The second storage means stores information between sequential circuits having a condition that causes a timing constraint violation by inserting a failure detection clock in the circuit design information.

  The circuit arrangement means includes a signal input to a sequential circuit at the front end between the sequential circuits and a signal output from the sequential circuit at the front end between the sequential circuits of information stored by the second storage means for circuit design information. Only when the logic does not change, a circuit that outputs the output signal of the leading sequential circuit to the subsequent sequential circuit is virtually arranged.

  According to such a circuit design support program, this sequential circuit is arranged between the sequential circuits of the information stored in the second storage means by the circuit placement means in the circuit design information stored in the first storage means. A circuit that outputs the output signal of the leading sequential circuit to the subsequent sequential circuit is virtually arranged only when the logic of the signal input to the leading sequential circuit and the signal output by the leading sequential circuit does not change. The

  According to the disclosed circuit design support program, it is possible to generate a test pattern capable of detecting a failure under a condition that does not cause a timing constraint violation.

It is a figure which shows the outline | summary of the circuit design support apparatus of embodiment. It is a figure which shows the hardware structural example of a circuit design support apparatus. It is a block diagram which shows the function of a circuit design support apparatus. It is a block diagram which shows the function of an ATPG process part. It is a flowchart which shows the process of a circuit design support apparatus. It is a flowchart which shows an ATPG process. It is a figure which shows the specific example of an ATPG process. It is a figure which shows the circuit which has arrange | positioned the net list correction circuit. It is a figure which shows an example of a failure table. It is a figure which shows the example which has arrange | positioned the scan clock input terminal for a scan test.

Hereinafter, embodiments will be described in detail with reference to the drawings.
First, an outline of the circuit design support apparatus of the embodiment will be described, and then the embodiment will be described more specifically.

FIG. 1 is a diagram illustrating an outline of a circuit design support apparatus according to an embodiment.
The circuit design support apparatus (computer) 1 is an apparatus capable of executing a circuit design support program for detecting a failure between sequential circuits operating with an asynchronous clock.

The circuit design support device 1 functions as a first storage unit 2, a second storage unit 3, and a circuit placement unit 4 by a circuit design support program.
The first storage unit 2 stores circuit design information (for example, a net list) including a plurality of sequential circuits.

  In FIG. 1, as an example of circuit design information, a selector 7 is inserted on the input side of the D flip-flop FF1 to which the system clock # 1 is input. A selector 8 is inserted on the input side of the D flip-flop FF2 to which the system clock # 2 is input. A circuit configuration that satisfies the scan design rule is formed by switching this to a failure detection clock using a failure detection signal.

Further, a combinational circuit (a circuit having no register / flip-flop) 5 is provided between the D flip-flop FF1 and the D flip-flop FF2.
The second storage means 3 stores information between sequential circuits having a condition that violates a timing constraint by inserting a failure detection clock (scan clock) in the circuit design information.

  In FIG. 1, as an example, the combinational circuit 5 arranged between these flip-flops is associated with the D flip-flop FF1 and the D flip-flop FF2 that have a condition that causes a timing constraint violation by inserting a failure detection clock. Stored.

  The circuit arrangement means 4 outputs a signal inputted to the sequential circuit at the front end between the sequential circuits and the output from the sequential circuit at the front end between the sequential circuits of the information stored by the second storage means 3 of the circuit design information. Only when the logic of the signal to be changed does not change, a circuit for outputting the output signal of the sequential circuit at the front end to the subsequent sequential circuit is virtually arranged.

  In FIG. 1, a circuit 6 for outputting the output signal of the D flip-flop FF1 to the D flip-flop FF2 is arranged only when the logic of the signal input to the D flip-flop FF1 and the signal output from the D flip-flop FF1 does not change. ing.

  According to such a circuit design support device 1, only when the logic of the signal input to the D flip-flop FF1 and the signal output from the D flip-flop FF1 does not change, the output signal of the D flip-flop FF1 is changed to the D flip-flop FF2. Output to. That is, the output signal of the D flip-flop FF1 is output to the D flip-flop FF2 only when there is no timing constraint violation between the D flip-flops FF1 and FF2. As a result, it is possible to provide circuit information capable of detecting a failure when the timing constraint is not violated.

  In addition, when the logic of the signal input to the D flip-flop FF1 and the signal output from the D flip-flop FF1 change, the circuit 6 preferably outputs indefinite logic to the subsequent sequential circuit. As a result, since it is not necessary to exclude the target of failure detection, it is possible to provide circuit information capable of detecting a failure between the D flip-flop FF1 and the D flip-flop FF2.

Hereinafter, the embodiment will be described more specifically.
FIG. 2 is a diagram illustrating a hardware configuration example of the circuit design support apparatus.
The entire circuit design support apparatus 100 is controlled by a CPU (Central Processing Unit) 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, an external auxiliary storage device 106, and a communication interface 107 are connected to the CPU 101 via a bus 108. Yes.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. A program file is stored in the HDD 103.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits a signal transmitted from the keyboard 105 a and the mouse 105 b to the CPU 101 via the bus 108.

  The external auxiliary storage device 106 reads information written on the recording medium and writes information on the recording medium. Examples of the recording medium that can be read and written by the external auxiliary storage device 106 include a magnetic recording device, an optical disc, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include an HDD, a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  The communication interface 107 is connected to the network 30. The communication interface 107 transmits and receives data to and from other computers via the network 30.

  With the hardware configuration as described above, the processing functions of the present embodiment can be realized. In order to perform circuit design support in a system having such a hardware configuration, the following functions are provided in the circuit design support apparatus 100.

FIG. 3 is a block diagram illustrating functions of the circuit design support apparatus.
The circuit design support apparatus 100 includes a netlist storage unit 110, a DFT (Design For Test) insertion unit 120, a layout processing execution unit 130, a timing constraint storage unit 140, an SDF (Standard Delay Format) storage unit 150, Timing analysis unit 160, scan PIPO (Primary In Primary Out) mode timing constraint storage unit 170, error list storage unit 180, ATPG (Automatic Test Pattern Generator) processing unit 190, failure table storage unit 200, test pattern A storage unit 210 and a simulation execution unit 220 are included.

  The net list storage unit 110 stores a net list of an electronic circuit (for example, an electronic circuit to be a product). The net list is referred to by each unit included in the circuit design support apparatus 100, processed, and updated.

  The DFT insertion unit 120 inserts a test pattern design into the netlist stored in the netlist storage unit 110. Specifically, the scan flip-flop is replaced with a scan flip-flop to create a scan chain, or a scan test clock is set. As a result, a new netlist is created. The DFT insertion unit 120 stores the created new netlist in the netlist storage unit 110.

  The layout processing execution unit 130 executes layout processing on the netlist stored in the netlist storage unit 110 based on the timing constraint information stored in the timing constraint storage unit 140. Specifically, placement and wiring, clock tree insertion, timing optimization, and the like are performed.

  Examples of timing constraint information include timing constraints during product operation, timing constraints during scan shift, and the like. Note that the timing constraint information of the scan PIPO mode is not included here.

  As a result, a new netlist and SDF information (delay information) are created. The layout process execution unit 130 stores the created new netlist in the netlist storage unit 110. Further, the created SDF information is stored in the SDF storage unit 150.

  The timing analysis unit 160 refers to the timing constraint information stored in the timing constraint storage unit 140, the SDF information stored in the SDF storage unit 150, and the netlist stored in the netlist storage unit 110. Then, the static timing (setup timing, hold timing, etc.) of the netlist stored in the netlist storage unit 110 is analyzed to determine whether there is a timing error.

  If there is no timing error, the scan PIPO mode timing constraint information stored in the scan PIPO mode timing constraint storage unit 170 is referred to. Then, a list of hold timings (error list) violating the scan PIPO mode timing constraint information is generated and stored in the error list storage unit 180.

  In this error list, for example, a start side (front end side) flip-flop, an end side flip-flop, and a combinational circuit arranged between these flip-flops are described.

  The ATPG processing unit 190 generates a test pattern and a failure table based on the net list stored in the net list storage unit 110 and the error list stored in the error list storage unit 180. Here, the test pattern is a pattern for propagating a failure signal to the external output terminal.

Then, the generated failure table is stored in the failure table storage unit 200. The generated test pattern is stored in the test pattern storage unit 210.
The simulation execution unit 220 executes a simulation based on the net list stored in the net list storage unit 110 and the test pattern stored in the test pattern storage unit 210.

Next, the function of the ATPG processing unit 190 will be described in detail.
FIG. 4 is a block diagram illustrating functions of the ATPG processing unit.
The ATPG processing unit 190 includes a net list correction unit 191, an ATPG net list storage unit 192, an ATPG process execution unit 193, a failure table temporary storage unit 194, and a correction process execution unit 195.

  The net list correction unit 191 corrects the net list based on the net list stored in the net list storage unit 110 and the error list stored in the error list storage unit 180, and stores the net list in the ATPG net list storage unit 192. Store. The correction method will be described in detail later.

  The ATPG processing execution unit 193 executes ATPG processing based on the net list stored in the ATPG net list storage unit 192, and generates a test pattern and a failure table for activating one target failure.

Here, activating the failure means that the value of the signal line where the failure exists is different between when the target failure exists and when it does not exist.
The generated test pattern is stored in the test pattern storage unit 210, and the generated failure table is stored in the failure table temporary storage unit 194.

This failure table stores information indicating whether or not a failure has been detected for each logic circuit included in the net list.
The correction processing execution unit 195 corrects the net list corrected by the net list correction unit 191 from the failure table stored in the failure table temporary storage unit 194 to the original net list, and stores the corrected net list in the failure table storage unit 200.

Next, processing of the circuit design support apparatus 100 will be described.
FIG. 5 is a flowchart showing processing of the circuit design support apparatus.
First, the DFT insertion unit 120 inserts a DFT based on the net list stored in the net list storage unit 110 (step S1). Then, the net list with the DFT inserted is stored in the net list storage unit 110.

  Next, the layout process execution unit 130 executes a layout process for the net list stored in the net list storage unit 110 (step S2). Then, the net list generated by the layout process is stored in the net list storage unit 110. In addition, the SDF information generated by the layout process is stored in the SDF storage unit 150.

  Next, the timing analysis unit 160 analyzes the timing of the netlist stored in the netlist storage unit 110 based on the timing constraint condition stored in the timing constraint storage unit 140 (step S3).

As a result of analyzing the timing, it is determined whether or not a timing error exists (step S4).
When there is a timing error (Yes in step S4), the process proceeds to step S2, and the processes after step S2 are continued.

  On the other hand, when there is no timing error, that is, when timing constraint conditions other than the timing constraint conditions of the scan PIPO mode are cleared (No in step S4), the timing constraint conditions stored in the scan PIPO mode timing constraint storage unit 170 Based on the above, the timing of the net list stored in the net list storage unit 110 is analyzed (step S5). Then, the obtained error list is stored in the error list storage unit 180.

  Next, the ATPG processing unit 190 performs ATPG processing on the net list stored in the net list storage unit 110 based on the error list stored in the error list storage unit 180 (step S6). Then, the obtained test pattern is stored in the test pattern storage unit 210, and the obtained failure table is stored in the failure table storage unit 200.

Next, the simulation execution unit 220 executes a simulation using the test pattern stored in the test pattern storage unit 210 (step S7).
Above, description of the process of the circuit design support apparatus 100 is complete | finished.

Next, the ATPG process in step S6 will be described in detail.
FIG. 6 is a flowchart showing ATPG processing.
First, the net list correction unit 191 corrects the net list based on the net list stored in the net list storage unit 110 and the error list stored in the error list storage unit 180, and stores it in the ATPG net list storage unit 192. Store (step S11).

  Next, the ATPG process execution unit 193 executes the ATPG process based on the net list stored in the ATPG net list storage unit 192 to create a test pattern and a failure table. Then, the created test pattern is stored in the test pattern storage unit 210, and the created failure table is stored in the failure table temporary storage unit 194 (step S12).

  Next, the correction processing execution unit 195 corrects the net list corrected by the net list correction unit 191 from the failure table stored in the failure table temporary storage unit 194 to the original net list, and stores it in the failure table storage unit 200. Store (step S13).

Next, a specific example of ATPG processing will be described.
FIG. 7 is a diagram illustrating a specific example of ATPG processing.
The circuit 10 shown in FIG. 7 is a circuit that is realized by circuit information included in a netlist that has been subjected to layout processing by the layout processing execution unit 130, and that satisfies timing constraints other than the scan PIPO mode. It is.

The circuit 10 includes a start-side flip-flop FF 11, an end-side flip-flop FF 12, and combinational circuits 11 and 12.
The combinational circuit 11 outputs a signal to the flip-flop FF11. In some cases, the output signal of the flip-flop FF11 is received.

The combinational circuit 12 receives the output signal of the flip-flop FF11. In addition, a signal is output to the flip-flop FF12.
The circuit 10 is provided with a selector 13, a selector 14, a scan test signal output circuit 15, and a scan flip-flop 16 inserted by the DFT insertion unit 120.

  The selector 13 selects either the system clock # 1 or the scan clock and outputs it to the flip-flop FF11 during the scan test. The selector 14 selects either the system clock # 2 or the scan clock and outputs it to the flip-flop FF12.

  The scan test signal output circuit 15 outputs a select signal for scan test to the selector 13 and the selector 14. The select signal output from the scan test signal output circuit 15 is a signal having a fixed value of logic “1” or logic “0” during the scan test.

Further, the output signal of the flip-flop FF11 is guided to the scan flip-flop 16 by the scan path.
As a result of performing a scan test in this circuit 10, it is assumed that a hold timing violation occurs in the start flip-flop FF11 and the end flip-flop FF12 only during the scan test.

The net list correction unit 191 extracts the start-side flip-flop FF11 and the end-side flip-flop FF12 of the circuit 10.
Then, a net list correction circuit is arranged between the extracted flip-flop FF11 and the end flip-flop FF12.

  Note that the path returning to the same clock domain (in FIG. 7, the path from the flip-flop FF11 to the combinational circuit 11) is the same as the operation at the time of product operation, and is therefore designed not to cause a hold timing violation.

Further, if a hold timing violation does not occur between different clocks, it is not necessary to add a net list correction circuit.
FIG. 8 is a diagram showing a circuit in which a net list correction circuit is arranged.

  The circuit 10 a is a circuit in which a net list correction circuit 20 is arranged with respect to the circuit 10. In this circuit 10 a, the connection between the flip-flop FF 11 and the combinational circuit 12 is disconnected, and the output side of the flip-flop FF11 is connected to the input side of the combinational circuit 12 via the net list correction circuit 20.

The netlist correction circuit 20 includes a logic X generation circuit 21 that generates a logic “X”, an XOR circuit 22, and a selector 23.
One input terminal of the XOR circuit 22 is connected to the input terminal of the flip-flop FF11, and the other input terminal is connected to the output terminal of the flip-flop FF11.

  The selector 23 selects either the output signal of the logic X generation circuit 21 or the output signal of the flip-flop FF11 according to the logic of the signal output from the XOR circuit 22. Then, the selected signal is output to the combinational circuit 12.

  Specifically, if the logic of the signal output from the XOR circuit 22 is “0”, the output signal of the flip-flop FF11 is selected. If the logic of the output signal is “1”, the logic X generation circuit 21 is selected. Select the output signal.

  As a result, the netlist correction circuit 20 combines the signal output from the Q terminal when the logic of the signal input to the D terminal of the flip-flop FF11 matches the logic of the signal output from the Q terminal. Output to.

  In other words, indefinite (X) is output to the combinational circuit 12 under a condition that causes a hold timing violation (a condition in which the Q of the flip-flop FF11 changes) in the path from the flip-flop FF11 to the flip-flop FF12. On the other hand, under a condition that does not cause a hold timing violation (a condition in which the Q of the flip-flop FF11 does not change), a signal having the same logic as the output signal of the flip-flop FF11 is output to the combinational circuit 12.

As a result, it is possible to provide circuit information capable of detecting a failure under a condition that does not cause a timing constraint violation.
Further, even if the condition is a timing constraint violation, it is not necessary to designate the failure detection target, so that a failure between the flip-flop FF11 and the flip-flop FF12 can be detected.

The ATPG processing execution unit 193 reads this circuit and generates a test pattern that can detect a failure of the flip-flop FF12 from the flip-flop FF11.
The configuration of the logic X generation circuit 21 is not limited to that shown in the figure.

Next, a specific example of the process in step S13 will be described.
FIG. 9 is a diagram illustrating an example of a failure table.
The failure table 194a (before correction) stored in the failure table temporary storage unit 194 includes identification information (for example, instance names of logic circuits) of all circuit data stored in the net list storage unit 110, and The test result of the scan test for each input / output terminal name of the logic circuit is described.

  Hereinafter, it is assumed that the instance name of the flip-flop FF11 is “AAAA”. Further, it is assumed that the instance name of the netlist correction circuit 20 is “DUMMY1”. Further, it is assumed that the instance name of the selector 23 is “MUX”. Further, it is assumed that the instance name of the XOR circuit 22 is “EOR”. Further, it is assumed that the instance name of the D flip-flop of the logic X generation circuit 21 is “FF”.

  In FIG. 9, “◯” indicating that a failure has been detected (detected) for each logic of signals input to and output from the D terminal, CK terminal, and Q terminal of the flip-flop FF11, or no failure has been detected ( undetected) is set.

  In addition, for each logic of signals input to the A terminal, the B terminal, and the S terminal of the selector 23 of the netlist correction circuit 20, “◯” indicating that a failure has been detected, or that no failure has been detected. “X” shown is set. For each logic of the signals input to the A terminal and B terminal of the XOR circuit 22, “◯” indicating that a failure has been detected or “X” indicating that no failure has been detected is set. In addition, “Δ” indicating that a failure of the D terminal, CK terminal, and Q terminal of “FF” of the logic X generation circuit 21 cannot be detected (undetectable) is set.

  In the correction processing, the correction processing execution unit 195 performs correction to delete the part corresponding to the net list correction circuit 20 in the failure table 194a, that is, the column whose instance name is “DUMMY1”.

  As a result, the information on the virtually arranged netlist correction circuit 20 is excluded from the failure table 194a, so the failure table stored in the failure table storage unit 200 is information indicating the failure rate of the product.

  As described above, according to the circuit design support apparatus 100, during the ATPG processing, the netlist correction circuit 20 is virtually arranged, and the scan test is performed using the test pattern to which this circuit is added. That is, the scan test is performed by adding a circuit (not mounted on the product) only during the scan test. Thereby, since an unnecessary circuit is not mounted on the product, it is possible to suppress an increase in the number of gates and power consumption of the product.

  Also, if the clock path is different between the system operation mode and the SCAN test mode, and both timings cannot be satisfied, the path had previously been designated as not subject to failure detection (NOATG), but the circuit design According to the support device 100, such designation is unnecessary, and failure detection of the path becomes possible. As a result, it is possible to improve quality by improving the failure detection rate.

  In addition, for example, the timing analysis process can be omitted as compared with the case where the timing analysis violation is repeated until the timing constraint violation that occurs by inserting the failure detection clock is eliminated. Can be shortened.

  In addition, since the virtually added netlist correction circuit 20 does not exist, the netlist correction circuit 20 is deleted from the failure table 194 a and stored in the failure table storage unit 200. By obtaining the failure detection rate using the failure table stored in the failure table storage unit 200, the product failure detection rate can be easily obtained.

  Note that the processing performed by the circuit design support device 100 may be distributed by a plurality of devices. For example, one device may perform a process up to ATPG processing to generate a test pattern, and another device may perform simulation using the test pattern.

  The circuit design support program and the circuit design support apparatus of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit has the same function. Any configuration can be substituted. Moreover, other arbitrary structures and processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions of the circuit design support apparatus 100 is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include an HDD, a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD, a DVD-RAM, a CD-ROM, and a CD-R / RW. Examples of the magneto-optical recording medium include MO.

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  A computer that executes a circuit design support program stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

DESCRIPTION OF SYMBOLS 1,100 Circuit design support apparatus 2 1st storage means 3 2nd storage means 4 Circuit arrangement means 5, 11, 12 Combination circuit 6 Circuit 7, 8, 13, 14, 23 Selector 10, 10a Circuit 15 Scan test signal Output circuit 16 Scan flip-flop 20 Netlist modification circuit 21 Logic X generation circuit 22 XOR circuit 110 Netlist storage unit 120 DFT insertion unit 130 Layout processing execution unit 140 Timing constraint storage unit 150 SDF storage unit 160 Timing analysis unit 170 Scan PIPO mode Timing constraint storage unit 180 Error list storage unit 190 ATPG processing unit 191 Netlist modification unit 192 ATPG netlist storage unit 193 ATPG processing execution unit 194 Failure table temporary storage unit 194a Failure table 195 Execution of correction processing Unit 200 failure table storage unit 210 test pattern storage unit 220 simulation execution unit FF1, FF2 D flip-flop FF11, FF12 flip-flop

Claims (6)

In a circuit design support program for detecting a failure between sequential circuits operating with an asynchronous clock,
Computer
First storage means for storing circuit design information comprising a plurality of sequential circuits;
Second storage means for storing information between the sequential circuits having a condition that causes a timing constraint violation by inserting a failure detection clock in the circuit design information;
Between the sequential circuits of the information stored by the second storage means of the circuit design information, the logic of the signal input to the sequential circuit at the leading end between the sequential circuits and the signal output from the sequential circuit at the leading end are Circuit arrangement means for virtually arranging a circuit that outputs an output signal of the sequential circuit at the leading end to a subsequent sequential circuit only when it does not change,
Circuit design support program characterized by functioning as   2. The circuit design support program according to claim 1, further causing the computer to function as test pattern generation means for generating a test pattern from the circuit design information including the circuit arranged by the circuit arrangement means. The test pattern generation means further generates information indicating whether a failure is detected for each logic circuit included in the circuit design information,
The circuit design support program according to claim 2, further causing the computer to function as a deletion unit that deletes the logic circuit related to the virtually arranged circuit among the generated information.   The virtually arranged circuit has an indefinite logic in the succeeding sequential circuit under the condition that the logic of the signal input to the leading sequential circuit between the sequential circuits and the signal output from the leading sequential circuit changes. The circuit design support program according to claim 1, wherein the circuit design support program is output.   2. The circuit design information stored in the first storage means satisfies a timing constraint condition other than a condition causing a timing constraint violation by inserting a failure detection clock. Circuit design support program. In a circuit design support device for detecting a failure between sequential circuits operating with an asynchronous clock,
A first storage unit that stores circuit design information including a plurality of sequential circuits;
A second storage unit for storing information between the sequential circuits having a condition that causes a timing constraint violation by inserting a failure detection clock in the circuit design information;
Between the sequential circuits of the information stored by the second storage unit of the circuit design information, the logic of the signal input to the sequential circuit at the leading end between the sequential circuits and the signal output from the sequential circuit at the leading end are A circuit arrangement unit that virtually arranges a circuit that outputs an output signal of the sequential circuit at the front end to a sequential circuit at a subsequent stage only when it does not change;
A circuit design support apparatus comprising:

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